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Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_373( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_117 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_33( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_86 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_92 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_37 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_50 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_51 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_51; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_52 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_58 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_64 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_70 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_53 = _source_ok_T_52 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_59 = _source_ok_T_58 == 5'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_65 = _source_ok_T_64 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_71 = _source_ok_T_70 == 5'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_76 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_82 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_88 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_77 = _source_ok_T_76 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_81; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_83 = _source_ok_T_82 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_87 = _source_ok_T_85; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_87; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_89 = _source_ok_T_88 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_93 = _source_ok_T_91; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_94; // @[Parameters.scala:1138:31] wire _source_ok_T_95 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_101 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1266 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1266; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1266; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1339 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1339; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1339; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1339; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1192 = _T_1266 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1192 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1192 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1192 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1192 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1192 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1238 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1238 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1207 = _T_1339 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1207 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1207 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1207 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1310 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1310 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1292 = _T_1339 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1292 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1292 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1292 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_78( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_78 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first | last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first | last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB || !io.status.bits.blockB) assert (!io.status.bits.nestC || !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe || !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid || io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid || io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty || request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) | Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid || meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U || !(request.opcode === PutFullData || request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r || p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c || m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read || clean release can lead to this state eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_D, true) // MMIO write || dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done | probe_bit probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst || last_probe w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst || last_probe w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U) w_pprobeack := w_pprobeack || set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U || io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f || p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read || clean release can lead to this state bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_D, true) // MMIO write || dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid || (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT || new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
module MSHR_19( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_166( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_176 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File NoC.scala: package constellation.noc import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody} import freechips.rocketchip.util.ElaborationArtefacts import freechips.rocketchip.prci._ import constellation.router._ import constellation.channel._ import constellation.routing.{RoutingRelation, ChannelRoutingInfo} import constellation.topology.{PhysicalTopology, UnidirectionalLine} class NoCTerminalIO( val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle { val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) }) val egress = MixedVec(egressParams.map { u => new EgressChannel(u) }) } class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule { override def shouldBeInlined = nocParams.inlineNoC val internalParams = InternalNoCParams(nocParams) val allChannelParams = internalParams.channelParams val allIngressParams = internalParams.ingressParams val allEgressParams = internalParams.egressParams val allRouterParams = internalParams.routerParams val iP = p.alterPartial({ case InternalNoCKey => internalParams }) val nNodes = nocParams.topology.nNodes val nocName = nocParams.nocName val skipValidationChecks = nocParams.skipValidationChecks val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) } val router_sink_domains = Seq.tabulate(nNodes) { i => val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters( name = Some(s"${nocName}_router_$i") ))) router_sink_domain.clockNode := clockSourceNodes(i) router_sink_domain } val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) { val inParams = allChannelParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val outParams = allChannelParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val ingressParams = allIngressParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val egressParams = allEgressParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val noIn = inParams.size + ingressParams.size == 0 val noOut = outParams.size + egressParams.size == 0 if (noIn || noOut) { println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated") None } else { Some(LazyModule(new Router( routerParams = allRouterParams(i), preDiplomaticInParams = inParams, preDiplomaticIngressParams = ingressParams, outDests = outParams.map(_.destId), egressIds = egressParams.map(_.egressId) )(iP))) } }}.flatten val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) } val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) } // Generate channels between routers diplomatically Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) { val routerI = routers.find(_.nodeId == i) val routerJ = routers.find(_.nodeId == j) if (routerI.isDefined && routerJ.isDefined) { val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j) val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i) require (sourceNodes.size == destNodes.size) (sourceNodes zip destNodes).foreach { case (src, dst) => val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get router_sink_domains(j) { implicit val p: Parameters = iP (dst := ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits) := channelParam.channelGen(p)(src) ) } } } }} // Generate terminal channels diplomatically routers.foreach { dst => router_sink_domains(dst.nodeId) { implicit val p: Parameters = iP dst.ingressNodes.foreach(n => { val ingressId = n.destParams.ingressId require(dst.payloadBits <= allIngressParams(ingressId).payloadBits) (n := IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits) := ingressNodes(ingressId) ) }) dst.egressNodes.foreach(n => { val egressId = n.egressId require(dst.payloadBits <= allEgressParams(egressId).payloadBits) (egressNodes(egressId) := EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits) := n ) }) }} val debugNodes = routers.map { r => val sink = BundleBridgeSink[DebugBundle]() sink := r.debugNode sink } val ctrlNodes = if (nocParams.hasCtrl) { (0 until nNodes).map { i => routers.find(_.nodeId == i).map { r => val sink = BundleBridgeSink[RouterCtrlBundle]() sink := r.ctrlNode.get sink } } } else { Nil } println(s"Constellation: $nocName Finished parameter validation") lazy val module = new Impl class Impl extends LazyModuleImp(this) { println(s"Constellation: $nocName Starting NoC RTL generation") val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) { val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters()))) val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil }) (io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l } (io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r } (io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r } if (nocParams.hasCtrl) { ctrlNodes.zipWithIndex.map { case (c,i) => if (c.isDefined) { io.router_ctrl(i) <> c.get.in(0)._1 } else { io.router_ctrl(i) <> DontCare } } } // TODO: These assume a single clock-domain across the entire noc val debug_va_stall_ctr = RegInit(0.U(64.W)) val debug_sa_stall_ctr = RegInit(0.U(64.W)) val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_) debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_) dontTouch(debug_va_stall_ctr) dontTouch(debug_sa_stall_ctr) dontTouch(debug_any_stall_ctr) def prepend(s: String) = Seq(nocName, s).mkString(".") ElaborationArtefacts.add(prepend("noc.graphml"), graphML) val adjList = routers.map { r => val outs = r.outParams.map(o => s"${o.destId}").mkString(" ") val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ") val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}") (Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.adjlist"), adjList) val xys = routers.map(r => { val n = r.nodeId val ids = (Seq(r.nodeId.toString) ++ r.egressParams.map(e => s"e${e.egressId}") ++ r.ingressParams.map(i => s"i${i.ingressId}") ) val plotter = nocParams.topology.plotter val coords = (Seq(plotter.node(r.nodeId)) ++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) } ++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) } ) (ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n") }).mkString("\n") ElaborationArtefacts.add(prepend("noc.xy"), xys) val edgeProps = routers.map { r => val outs = r.outParams.map { o => (Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val egresses = r.egressParams.map { e => (Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val ingresses = r.ingressParams.map { i => (Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } (outs ++ egresses ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps) println(s"Constellation: $nocName Finished NoC RTL generation") } }
module TLNoC_router_4ClockSinkDomain( // @[ClockDomain.scala:14:9] output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_4 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3), .auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready), .auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid), .auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head), .auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail), .auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload), .auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready), .auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid), .auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head), .auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail), .auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload), .auto_ingress_nodes_in_2_flit_ready (auto_routers_ingress_nodes_in_2_flit_ready), .auto_ingress_nodes_in_2_flit_valid (auto_routers_ingress_nodes_in_2_flit_valid), .auto_ingress_nodes_in_2_flit_bits_head (auto_routers_ingress_nodes_in_2_flit_bits_head), .auto_ingress_nodes_in_2_flit_bits_payload (auto_routers_ingress_nodes_in_2_flit_bits_payload), .auto_ingress_nodes_in_2_flit_bits_egress_id (auto_routers_ingress_nodes_in_2_flit_bits_egress_id), .auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head), .auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail), .auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload), .auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id), .auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready), .auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid), .auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head), .auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload), .auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id), .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File SingleVCAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.random.{LFSR} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{ChannelRoutingInfo, FlowRoutingBundle} // Allocates 1 VC per cycle abstract class SingleVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) extends VCAllocator(vP)(p) { // get single input val mask = RegInit(0.U(allInParams.size.W)) val in_arb_reqs = Wire(Vec(allInParams.size, MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))) val in_arb_vals = Wire(Vec(allInParams.size, Bool())) val in_arb_filter = PriorityEncoderOH(Cat(in_arb_vals.asUInt, in_arb_vals.asUInt & ~mask)) val in_arb_sel = (in_arb_filter(allInParams.size-1,0) | (in_arb_filter >> allInParams.size)) when (in_arb_vals.orR) { mask := Mux1H(in_arb_sel, (0 until allInParams.size).map { w => ~(0.U((w+1).W)) }) } for (i <- 0 until allInParams.size) { (0 until allOutParams.size).map { m => (0 until allOutParams(m).nVirtualChannels).map { n => in_arb_reqs(i)(m)(n) := io.req(i).bits.vc_sel(m)(n) && !io.channel_status(m)(n).occupied } } in_arb_vals(i) := io.req(i).valid && in_arb_reqs(i).map(_.orR).toSeq.orR } // Input arbitration io.req.foreach(_.ready := false.B) val in_alloc = Wire(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val in_flow = Mux1H(in_arb_sel, io.req.map(_.bits.flow).toSeq) val in_vc = Mux1H(in_arb_sel, io.req.map(_.bits.in_vc).toSeq) val in_vc_sel = Mux1H(in_arb_sel, in_arb_reqs) in_alloc := Mux(in_arb_vals.orR, inputAllocPolicy(in_flow, in_vc_sel, OHToUInt(in_arb_sel), in_vc, io.req.map(_.fire).toSeq.orR), 0.U.asTypeOf(in_alloc)) // send allocation to inputunits for (i <- 0 until allInParams.size) { io.req(i).ready := in_arb_sel(i) for (m <- 0 until allOutParams.size) { (0 until allOutParams(m).nVirtualChannels).map { n => io.resp(i).vc_sel(m)(n) := in_alloc(m)(n) } } assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U) } // send allocation to output units for (i <- 0 until allOutParams.size) { (0 until allOutParams(i).nVirtualChannels).map { j => io.out_allocs(i)(j).alloc := in_alloc(i)(j) io.out_allocs(i)(j).flow := in_flow } } } File VCAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import freechips.rocketchip.rocket.{DecodeLogic} import constellation.channel._ import constellation.noc.{HasNoCParams} import constellation.routing.{FlowRoutingBundle, FlowRoutingInfo, ChannelRoutingInfo} class VCAllocReq( val inParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams with HasNoCParams { val flow = new FlowRoutingBundle val in_vc = UInt(log2Ceil(inParam.nVirtualChannels).W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } class VCAllocResp(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } case class VCAllocatorParams( routerParams: RouterParams, inParams: Seq[ChannelParams], outParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], egressParams: Seq[EgressChannelParams]) abstract class VCAllocator(val vP: VCAllocatorParams)(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams with HasNoCParams { val routerParams = vP.routerParams val inParams = vP.inParams val outParams = vP.outParams val ingressParams = vP.ingressParams val egressParams = vP.egressParams val io = IO(new Bundle { val req = MixedVec(allInParams.map { u => Flipped(Decoupled(new VCAllocReq(u, outParams, egressParams))) }) val resp = MixedVec(allInParams.map { u => Output(new VCAllocResp(outParams, egressParams)) }) val channel_status = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Input(new OutputChannelStatus)) }) val out_allocs = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputChannelAlloc)) }) }) val nOutChannels = allOutParams.map(_.nVirtualChannels).sum def inputAllocPolicy( flow: FlowRoutingBundle, vc_sel: MixedVec[Vec[Bool]], inId: UInt, inVId: UInt, fire: Bool): MixedVec[Vec[Bool]] def outputAllocPolicy( out: ChannelRoutingInfo, flows: Seq[FlowRoutingBundle], reqs: Seq[Bool], fire: Bool): Vec[Bool] } File ISLIP.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.random.{LFSR} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{ChannelRoutingInfo, FlowRoutingBundle} trait ISLIP { this: VCAllocator => def islip(in: UInt, fire: Bool): UInt = { val w = in.getWidth if (w > 1) { val mask = RegInit(0.U(w.W)) val full = Cat(in, in & ~mask) val oh = PriorityEncoderOH(full) val sel = (oh(w-1,0) | (oh >> w)) when (fire) { mask := MuxCase(0.U, (0 until w).map { i => sel(i) -> ~(0.U((i+1).W)) }) } sel } else { in } } def inputAllocPolicy(flow: FlowRoutingBundle, vc_sel: MixedVec[Vec[Bool]], inId: UInt, inVId: UInt, fire: Bool) = { islip(vc_sel.asUInt, fire).asTypeOf(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool())})) } def outputAllocPolicy(channel: ChannelRoutingInfo, flows: Seq[FlowRoutingBundle], reqs: Seq[Bool], fire: Bool) = { islip(VecInit(reqs).asUInt, fire).asTypeOf(Vec(allInParams.size, Bool())) } } class ISLIPMultiVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) extends MultiVCAllocator(vP)(p) with ISLIP class RotatingSingleVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) extends SingleVCAllocator(vP)(p) with ISLIP
module RotatingSingleVCAllocator_11( // @[ISLIP.scala:43:7] input clock, // @[ISLIP.scala:43:7] input reset, // @[ISLIP.scala:43:7] output io_req_3_ready, // @[VCAllocator.scala:49:14] input io_req_3_valid, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_req_2_ready, // @[VCAllocator.scala:49:14] input io_req_2_valid, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_req_1_ready, // @[VCAllocator.scala:49:14] input io_req_1_valid, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_req_0_ready, // @[VCAllocator.scala:49:14] input io_req_0_valid, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_2_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_2_2, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_2, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_2_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_2_2, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_2, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_channel_status_3_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_2_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_0_occupied, // @[VCAllocator.scala:49:14] output io_out_allocs_3_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_2_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_0_alloc // @[VCAllocator.scala:49:14] ); wire in_arb_vals_3; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39] reg [3:0] mask; // @[SingleVCAllocator.scala:16:21] wire [3:0] _in_arb_filter_T_3 = {in_arb_vals_3, in_arb_vals_2, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39] wire [7:0] in_arb_filter = _in_arb_filter_T_3[0] ? 8'h1 : _in_arb_filter_T_3[1] ? 8'h2 : _in_arb_filter_T_3[2] ? 8'h4 : _in_arb_filter_T_3[3] ? 8'h8 : in_arb_vals_0 ? 8'h10 : in_arb_vals_1 ? 8'h20 : in_arb_vals_2 ? 8'h40 : {in_arb_vals_3, 7'h0}; // @[OneHot.scala:85:71] wire [3:0] in_arb_sel = in_arb_filter[3:0] | in_arb_filter[7:4]; // @[Mux.scala:50:70] wire _GEN = in_arb_vals_0 | in_arb_vals_1 | in_arb_vals_2 | in_arb_vals_3; // @[package.scala:81:59] wire in_arb_reqs_0_0_0 = io_req_0_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_1 = io_req_0_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_2 = io_req_0_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_3_0 = io_req_0_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_0_0 | io_req_0_bits_vc_sel_0_1 | io_req_0_bits_vc_sel_0_2 | io_req_0_bits_vc_sel_1_0 | in_arb_reqs_0_1_1 | in_arb_reqs_0_1_2 | in_arb_reqs_0_2_0 | io_req_0_bits_vc_sel_2_1 | io_req_0_bits_vc_sel_2_2 | in_arb_reqs_0_3_0); // @[package.scala:81:59] wire in_arb_reqs_1_0_0 = io_req_1_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_1 = io_req_1_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_2 = io_req_1_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_3_0 = io_req_1_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_1 = io_req_1_valid & (in_arb_reqs_1_0_0 | io_req_1_bits_vc_sel_0_1 | io_req_1_bits_vc_sel_0_2 | io_req_1_bits_vc_sel_1_0 | in_arb_reqs_1_1_1 | in_arb_reqs_1_1_2 | in_arb_reqs_1_2_0 | io_req_1_bits_vc_sel_2_1 | io_req_1_bits_vc_sel_2_2 | in_arb_reqs_1_3_0); // @[package.scala:81:59] wire in_arb_reqs_2_0_0 = io_req_2_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_1 = io_req_2_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_2 = io_req_2_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_2_0 = io_req_2_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_3_0 = io_req_2_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_2 = io_req_2_valid & (in_arb_reqs_2_0_0 | io_req_2_bits_vc_sel_0_1 | io_req_2_bits_vc_sel_0_2 | io_req_2_bits_vc_sel_1_0 | in_arb_reqs_2_1_1 | in_arb_reqs_2_1_2 | in_arb_reqs_2_2_0 | io_req_2_bits_vc_sel_2_1 | io_req_2_bits_vc_sel_2_2 | in_arb_reqs_2_3_0); // @[package.scala:81:59] wire in_arb_reqs_3_0_0 = io_req_3_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_1_1 = io_req_3_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_1_2 = io_req_3_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_2_0 = io_req_3_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_3_0 = io_req_3_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_3 = io_req_3_valid & (in_arb_reqs_3_0_0 | io_req_3_bits_vc_sel_0_1 | io_req_3_bits_vc_sel_0_2 | io_req_3_bits_vc_sel_1_0 | in_arb_reqs_3_1_1 | in_arb_reqs_3_1_2 | in_arb_reqs_3_2_0 | io_req_3_bits_vc_sel_2_1 | io_req_3_bits_vc_sel_2_2 | in_arb_reqs_3_3_0); // @[package.scala:81:59] wire _in_vc_sel_T_10 = in_arb_sel[0] & in_arb_reqs_0_0_0 | in_arb_sel[1] & in_arb_reqs_1_0_0 | in_arb_sel[2] & in_arb_reqs_2_0_0 | in_arb_sel[3] & in_arb_reqs_3_0_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_17 = in_arb_sel[0] & io_req_0_bits_vc_sel_0_1 | in_arb_sel[1] & io_req_1_bits_vc_sel_0_1 | in_arb_sel[2] & io_req_2_bits_vc_sel_0_1 | in_arb_sel[3] & io_req_3_bits_vc_sel_0_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_24 = in_arb_sel[0] & io_req_0_bits_vc_sel_0_2 | in_arb_sel[1] & io_req_1_bits_vc_sel_0_2 | in_arb_sel[2] & io_req_2_bits_vc_sel_0_2 | in_arb_sel[3] & io_req_3_bits_vc_sel_0_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_31 = in_arb_sel[0] & io_req_0_bits_vc_sel_1_0 | in_arb_sel[1] & io_req_1_bits_vc_sel_1_0 | in_arb_sel[2] & io_req_2_bits_vc_sel_1_0 | in_arb_sel[3] & io_req_3_bits_vc_sel_1_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_38 = in_arb_sel[0] & in_arb_reqs_0_1_1 | in_arb_sel[1] & in_arb_reqs_1_1_1 | in_arb_sel[2] & in_arb_reqs_2_1_1 | in_arb_sel[3] & in_arb_reqs_3_1_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_45 = in_arb_sel[0] & in_arb_reqs_0_1_2 | in_arb_sel[1] & in_arb_reqs_1_1_2 | in_arb_sel[2] & in_arb_reqs_2_1_2 | in_arb_sel[3] & in_arb_reqs_3_1_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_52 = in_arb_sel[0] & in_arb_reqs_0_2_0 | in_arb_sel[1] & in_arb_reqs_1_2_0 | in_arb_sel[2] & in_arb_reqs_2_2_0 | in_arb_sel[3] & in_arb_reqs_3_2_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_59 = in_arb_sel[0] & io_req_0_bits_vc_sel_2_1 | in_arb_sel[1] & io_req_1_bits_vc_sel_2_1 | in_arb_sel[2] & io_req_2_bits_vc_sel_2_1 | in_arb_sel[3] & io_req_3_bits_vc_sel_2_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_66 = in_arb_sel[0] & io_req_0_bits_vc_sel_2_2 | in_arb_sel[1] & io_req_1_bits_vc_sel_2_2 | in_arb_sel[2] & io_req_2_bits_vc_sel_2_2 | in_arb_sel[3] & io_req_3_bits_vc_sel_2_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_73 = in_arb_sel[0] & in_arb_reqs_0_3_0 | in_arb_sel[1] & in_arb_reqs_1_3_0 | in_arb_sel[2] & in_arb_reqs_2_3_0 | in_arb_sel[3] & in_arb_reqs_3_3_0; // @[Mux.scala:30:73, :32:36] reg [9:0] mask_1; // @[ISLIP.scala:17:25] wire [9:0] _full_T_1 = {_in_vc_sel_T_73, _in_vc_sel_T_66, _in_vc_sel_T_59, _in_vc_sel_T_52, _in_vc_sel_T_45, _in_vc_sel_T_38, _in_vc_sel_T_31, _in_vc_sel_T_24, _in_vc_sel_T_17, _in_vc_sel_T_10} & ~mask_1; // @[Mux.scala:30:73] wire [19:0] oh = _full_T_1[0] ? 20'h1 : _full_T_1[1] ? 20'h2 : _full_T_1[2] ? 20'h4 : _full_T_1[3] ? 20'h8 : _full_T_1[4] ? 20'h10 : _full_T_1[5] ? 20'h20 : _full_T_1[6] ? 20'h40 : _full_T_1[7] ? 20'h80 : _full_T_1[8] ? 20'h100 : _full_T_1[9] ? 20'h200 : _in_vc_sel_T_10 ? 20'h400 : _in_vc_sel_T_17 ? 20'h800 : _in_vc_sel_T_24 ? 20'h1000 : _in_vc_sel_T_31 ? 20'h2000 : _in_vc_sel_T_38 ? 20'h4000 : _in_vc_sel_T_45 ? 20'h8000 : _in_vc_sel_T_52 ? 20'h10000 : _in_vc_sel_T_59 ? 20'h20000 : _in_vc_sel_T_66 ? 20'h40000 : {_in_vc_sel_T_73, 19'h0}; // @[OneHot.scala:85:71] wire [9:0] sel = oh[9:0] | oh[19:10]; // @[Mux.scala:50:70] wire in_alloc_3_0 = _GEN & sel[9]; // @[package.scala:81:59] wire in_alloc_2_0 = _GEN & sel[6]; // @[package.scala:81:59] wire in_alloc_2_1 = _GEN & sel[7]; // @[package.scala:81:59] wire in_alloc_2_2 = _GEN & sel[8]; // @[package.scala:81:59] wire in_alloc_1_0 = _GEN & sel[3]; // @[package.scala:81:59] wire in_alloc_1_1 = _GEN & sel[4]; // @[package.scala:81:59] wire in_alloc_1_2 = _GEN & sel[5]; // @[package.scala:81:59] wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59] wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59] wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59]
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }
module dataMems_206( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_TLBEntryData_119( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module IntSyncSyncCrossingSink_n1x2_6( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] input auto_in_sync_1, // @[LazyModuleImp.scala:107:25] output auto_out_0, // @[LazyModuleImp.scala:107:25] output auto_out_1 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire auto_in_sync_1_0 = auto_in_sync_1; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeIn_sync_1 = auto_in_sync_1_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire nodeOut_1; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] wire auto_out_1_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_1 = nodeIn_sync_1; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_1_0 = nodeOut_1; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] assign auto_out_1 = auto_out_1_0; // @[Crossing.scala:96:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File SingleVCAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.random.{LFSR} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{ChannelRoutingInfo, FlowRoutingBundle} // Allocates 1 VC per cycle abstract class SingleVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) extends VCAllocator(vP)(p) { // get single input val mask = RegInit(0.U(allInParams.size.W)) val in_arb_reqs = Wire(Vec(allInParams.size, MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))) val in_arb_vals = Wire(Vec(allInParams.size, Bool())) val in_arb_filter = PriorityEncoderOH(Cat(in_arb_vals.asUInt, in_arb_vals.asUInt & ~mask)) val in_arb_sel = (in_arb_filter(allInParams.size-1,0) | (in_arb_filter >> allInParams.size)) when (in_arb_vals.orR) { mask := Mux1H(in_arb_sel, (0 until allInParams.size).map { w => ~(0.U((w+1).W)) }) } for (i <- 0 until allInParams.size) { (0 until allOutParams.size).map { m => (0 until allOutParams(m).nVirtualChannels).map { n => in_arb_reqs(i)(m)(n) := io.req(i).bits.vc_sel(m)(n) && !io.channel_status(m)(n).occupied } } in_arb_vals(i) := io.req(i).valid && in_arb_reqs(i).map(_.orR).toSeq.orR } // Input arbitration io.req.foreach(_.ready := false.B) val in_alloc = Wire(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val in_flow = Mux1H(in_arb_sel, io.req.map(_.bits.flow).toSeq) val in_vc = Mux1H(in_arb_sel, io.req.map(_.bits.in_vc).toSeq) val in_vc_sel = Mux1H(in_arb_sel, in_arb_reqs) in_alloc := Mux(in_arb_vals.orR, inputAllocPolicy(in_flow, in_vc_sel, OHToUInt(in_arb_sel), in_vc, io.req.map(_.fire).toSeq.orR), 0.U.asTypeOf(in_alloc)) // send allocation to inputunits for (i <- 0 until allInParams.size) { io.req(i).ready := in_arb_sel(i) for (m <- 0 until allOutParams.size) { (0 until allOutParams(m).nVirtualChannels).map { n => io.resp(i).vc_sel(m)(n) := in_alloc(m)(n) } } assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U) } // send allocation to output units for (i <- 0 until allOutParams.size) { (0 until allOutParams(i).nVirtualChannels).map { j => io.out_allocs(i)(j).alloc := in_alloc(i)(j) io.out_allocs(i)(j).flow := in_flow } } } File VCAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import freechips.rocketchip.rocket.{DecodeLogic} import constellation.channel._ import constellation.noc.{HasNoCParams} import constellation.routing.{FlowRoutingBundle, FlowRoutingInfo, ChannelRoutingInfo} class VCAllocReq( val inParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams with HasNoCParams { val flow = new FlowRoutingBundle val in_vc = UInt(log2Ceil(inParam.nVirtualChannels).W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } class VCAllocResp(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } case class VCAllocatorParams( routerParams: RouterParams, inParams: Seq[ChannelParams], outParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], egressParams: Seq[EgressChannelParams]) abstract class VCAllocator(val vP: VCAllocatorParams)(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams with HasNoCParams { val routerParams = vP.routerParams val inParams = vP.inParams val outParams = vP.outParams val ingressParams = vP.ingressParams val egressParams = vP.egressParams val io = IO(new Bundle { val req = MixedVec(allInParams.map { u => Flipped(Decoupled(new VCAllocReq(u, outParams, egressParams))) }) val resp = MixedVec(allInParams.map { u => Output(new VCAllocResp(outParams, egressParams)) }) val channel_status = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Input(new OutputChannelStatus)) }) val out_allocs = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputChannelAlloc)) }) }) val nOutChannels = allOutParams.map(_.nVirtualChannels).sum def inputAllocPolicy( flow: FlowRoutingBundle, vc_sel: MixedVec[Vec[Bool]], inId: UInt, inVId: UInt, fire: Bool): MixedVec[Vec[Bool]] def outputAllocPolicy( out: ChannelRoutingInfo, flows: Seq[FlowRoutingBundle], reqs: Seq[Bool], fire: Bool): Vec[Bool] } File ISLIP.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.random.{LFSR} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{ChannelRoutingInfo, FlowRoutingBundle} trait ISLIP { this: VCAllocator => def islip(in: UInt, fire: Bool): UInt = { val w = in.getWidth if (w > 1) { val mask = RegInit(0.U(w.W)) val full = Cat(in, in & ~mask) val oh = PriorityEncoderOH(full) val sel = (oh(w-1,0) | (oh >> w)) when (fire) { mask := MuxCase(0.U, (0 until w).map { i => sel(i) -> ~(0.U((i+1).W)) }) } sel } else { in } } def inputAllocPolicy(flow: FlowRoutingBundle, vc_sel: MixedVec[Vec[Bool]], inId: UInt, inVId: UInt, fire: Bool) = { islip(vc_sel.asUInt, fire).asTypeOf(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool())})) } def outputAllocPolicy(channel: ChannelRoutingInfo, flows: Seq[FlowRoutingBundle], reqs: Seq[Bool], fire: Bool) = { islip(VecInit(reqs).asUInt, fire).asTypeOf(Vec(allInParams.size, Bool())) } } class ISLIPMultiVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) extends MultiVCAllocator(vP)(p) with ISLIP class RotatingSingleVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) extends SingleVCAllocator(vP)(p) with ISLIP
module RotatingSingleVCAllocator( // @[ISLIP.scala:43:7] input clock, // @[ISLIP.scala:43:7] input reset, // @[ISLIP.scala:43:7] output io_req_3_ready, // @[VCAllocator.scala:49:14] input io_req_3_valid, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_6, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_7, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_8, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_9, // @[VCAllocator.scala:49:14] output io_req_2_ready, // @[VCAllocator.scala:49:14] input io_req_2_valid, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_6, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_7, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_8, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_9, // @[VCAllocator.scala:49:14] output io_req_1_ready, // @[VCAllocator.scala:49:14] input io_req_1_valid, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_6, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_7, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_8, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_9, // @[VCAllocator.scala:49:14] output io_req_0_ready, // @[VCAllocator.scala:49:14] input io_req_0_valid, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_6, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_7, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_8, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_9, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_3, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_4, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_5, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_6, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_7, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_8, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_9, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_3, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_4, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_5, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_6, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_7, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_8, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_9, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_3, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_4, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_5, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_6, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_7, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_8, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_9, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_0_3, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_0_4, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_0_5, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_0_6, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_0_7, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_0_8, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_0_9, // @[VCAllocator.scala:49:14] input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_2_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_3_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_4_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_5_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_6_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_7_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_8_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_9_occupied, // @[VCAllocator.scala:49:14] output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_2_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_3_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_4_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_5_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_6_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_7_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_8_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_9_alloc // @[VCAllocator.scala:49:14] ); wire in_arb_vals_3; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39] reg [3:0] mask; // @[SingleVCAllocator.scala:16:21] wire [3:0] _in_arb_filter_T_3 = {in_arb_vals_3, in_arb_vals_2, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39] wire [7:0] in_arb_filter = _in_arb_filter_T_3[0] ? 8'h1 : _in_arb_filter_T_3[1] ? 8'h2 : _in_arb_filter_T_3[2] ? 8'h4 : _in_arb_filter_T_3[3] ? 8'h8 : in_arb_vals_0 ? 8'h10 : in_arb_vals_1 ? 8'h20 : in_arb_vals_2 ? 8'h40 : {in_arb_vals_3, 7'h0}; // @[OneHot.scala:85:71] wire [3:0] in_arb_sel = in_arb_filter[3:0] | in_arb_filter[7:4]; // @[Mux.scala:50:70] wire _GEN = in_arb_vals_0 | in_arb_vals_1 | in_arb_vals_2 | in_arb_vals_3; // @[package.scala:81:59] wire in_arb_reqs_0_0_0 = io_req_0_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_0_1 = io_req_0_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_0_2 = io_req_0_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_0_3 = io_req_0_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_0_4 = io_req_0_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_0_5 = io_req_0_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_0_6 = io_req_0_bits_vc_sel_0_6 & ~io_channel_status_0_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_0_7 = io_req_0_bits_vc_sel_0_7 & ~io_channel_status_0_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_0_8 = io_req_0_bits_vc_sel_0_8 & ~io_channel_status_0_8_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_0_9 = io_req_0_bits_vc_sel_0_9 & ~io_channel_status_0_9_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_0_0 | in_arb_reqs_0_0_1 | in_arb_reqs_0_0_2 | in_arb_reqs_0_0_3 | in_arb_reqs_0_0_4 | in_arb_reqs_0_0_5 | in_arb_reqs_0_0_6 | in_arb_reqs_0_0_7 | in_arb_reqs_0_0_8 | in_arb_reqs_0_0_9 | in_arb_reqs_0_1_0 | in_arb_reqs_0_2_0); // @[package.scala:81:59] wire in_arb_reqs_1_0_0 = io_req_1_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_1 = io_req_1_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_2 = io_req_1_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_3 = io_req_1_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_4 = io_req_1_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_5 = io_req_1_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_6 = io_req_1_bits_vc_sel_0_6 & ~io_channel_status_0_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_7 = io_req_1_bits_vc_sel_0_7 & ~io_channel_status_0_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_8 = io_req_1_bits_vc_sel_0_8 & ~io_channel_status_0_8_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_9 = io_req_1_bits_vc_sel_0_9 & ~io_channel_status_0_9_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_0 = io_req_1_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_1 = io_req_1_valid & (in_arb_reqs_1_0_0 | in_arb_reqs_1_0_1 | in_arb_reqs_1_0_2 | in_arb_reqs_1_0_3 | in_arb_reqs_1_0_4 | in_arb_reqs_1_0_5 | in_arb_reqs_1_0_6 | in_arb_reqs_1_0_7 | in_arb_reqs_1_0_8 | in_arb_reqs_1_0_9 | in_arb_reqs_1_1_0 | in_arb_reqs_1_2_0); // @[package.scala:81:59] wire in_arb_reqs_2_0_0 = io_req_2_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_1 = io_req_2_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_2 = io_req_2_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_3 = io_req_2_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_4 = io_req_2_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_5 = io_req_2_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_6 = io_req_2_bits_vc_sel_0_6 & ~io_channel_status_0_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_7 = io_req_2_bits_vc_sel_0_7 & ~io_channel_status_0_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_8 = io_req_2_bits_vc_sel_0_8 & ~io_channel_status_0_8_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_9 = io_req_2_bits_vc_sel_0_9 & ~io_channel_status_0_9_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_0 = io_req_2_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_2_0 = io_req_2_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_2 = io_req_2_valid & (in_arb_reqs_2_0_0 | in_arb_reqs_2_0_1 | in_arb_reqs_2_0_2 | in_arb_reqs_2_0_3 | in_arb_reqs_2_0_4 | in_arb_reqs_2_0_5 | in_arb_reqs_2_0_6 | in_arb_reqs_2_0_7 | in_arb_reqs_2_0_8 | in_arb_reqs_2_0_9 | in_arb_reqs_2_1_0 | in_arb_reqs_2_2_0); // @[package.scala:81:59] wire in_arb_reqs_3_0_0 = io_req_3_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_0_1 = io_req_3_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_0_2 = io_req_3_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_0_3 = io_req_3_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_0_4 = io_req_3_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_0_5 = io_req_3_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_0_6 = io_req_3_bits_vc_sel_0_6 & ~io_channel_status_0_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_0_7 = io_req_3_bits_vc_sel_0_7 & ~io_channel_status_0_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_0_8 = io_req_3_bits_vc_sel_0_8 & ~io_channel_status_0_8_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_0_9 = io_req_3_bits_vc_sel_0_9 & ~io_channel_status_0_9_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_1_0 = io_req_3_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_2_0 = io_req_3_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_3 = io_req_3_valid & (in_arb_reqs_3_0_0 | in_arb_reqs_3_0_1 | in_arb_reqs_3_0_2 | in_arb_reqs_3_0_3 | in_arb_reqs_3_0_4 | in_arb_reqs_3_0_5 | in_arb_reqs_3_0_6 | in_arb_reqs_3_0_7 | in_arb_reqs_3_0_8 | in_arb_reqs_3_0_9 | in_arb_reqs_3_1_0 | in_arb_reqs_3_2_0); // @[package.scala:81:59] wire _in_vc_sel_T_10 = in_arb_sel[0] & in_arb_reqs_0_0_0 | in_arb_sel[1] & in_arb_reqs_1_0_0 | in_arb_sel[2] & in_arb_reqs_2_0_0 | in_arb_sel[3] & in_arb_reqs_3_0_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_17 = in_arb_sel[0] & in_arb_reqs_0_0_1 | in_arb_sel[1] & in_arb_reqs_1_0_1 | in_arb_sel[2] & in_arb_reqs_2_0_1 | in_arb_sel[3] & in_arb_reqs_3_0_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_24 = in_arb_sel[0] & in_arb_reqs_0_0_2 | in_arb_sel[1] & in_arb_reqs_1_0_2 | in_arb_sel[2] & in_arb_reqs_2_0_2 | in_arb_sel[3] & in_arb_reqs_3_0_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_31 = in_arb_sel[0] & in_arb_reqs_0_0_3 | in_arb_sel[1] & in_arb_reqs_1_0_3 | in_arb_sel[2] & in_arb_reqs_2_0_3 | in_arb_sel[3] & in_arb_reqs_3_0_3; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_38 = in_arb_sel[0] & in_arb_reqs_0_0_4 | in_arb_sel[1] & in_arb_reqs_1_0_4 | in_arb_sel[2] & in_arb_reqs_2_0_4 | in_arb_sel[3] & in_arb_reqs_3_0_4; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_45 = in_arb_sel[0] & in_arb_reqs_0_0_5 | in_arb_sel[1] & in_arb_reqs_1_0_5 | in_arb_sel[2] & in_arb_reqs_2_0_5 | in_arb_sel[3] & in_arb_reqs_3_0_5; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_52 = in_arb_sel[0] & in_arb_reqs_0_0_6 | in_arb_sel[1] & in_arb_reqs_1_0_6 | in_arb_sel[2] & in_arb_reqs_2_0_6 | in_arb_sel[3] & in_arb_reqs_3_0_6; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_59 = in_arb_sel[0] & in_arb_reqs_0_0_7 | in_arb_sel[1] & in_arb_reqs_1_0_7 | in_arb_sel[2] & in_arb_reqs_2_0_7 | in_arb_sel[3] & in_arb_reqs_3_0_7; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_66 = in_arb_sel[0] & in_arb_reqs_0_0_8 | in_arb_sel[1] & in_arb_reqs_1_0_8 | in_arb_sel[2] & in_arb_reqs_2_0_8 | in_arb_sel[3] & in_arb_reqs_3_0_8; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_73 = in_arb_sel[0] & in_arb_reqs_0_0_9 | in_arb_sel[1] & in_arb_reqs_1_0_9 | in_arb_sel[2] & in_arb_reqs_2_0_9 | in_arb_sel[3] & in_arb_reqs_3_0_9; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_80 = in_arb_sel[0] & in_arb_reqs_0_1_0 | in_arb_sel[1] & in_arb_reqs_1_1_0 | in_arb_sel[2] & in_arb_reqs_2_1_0 | in_arb_sel[3] & in_arb_reqs_3_1_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_87 = in_arb_sel[0] & in_arb_reqs_0_2_0 | in_arb_sel[1] & in_arb_reqs_1_2_0 | in_arb_sel[2] & in_arb_reqs_2_2_0 | in_arb_sel[3] & in_arb_reqs_3_2_0; // @[Mux.scala:30:73, :32:36] reg [11:0] mask_1; // @[ISLIP.scala:17:25] wire [11:0] _full_T_1 = {_in_vc_sel_T_87, _in_vc_sel_T_80, _in_vc_sel_T_73, _in_vc_sel_T_66, _in_vc_sel_T_59, _in_vc_sel_T_52, _in_vc_sel_T_45, _in_vc_sel_T_38, _in_vc_sel_T_31, _in_vc_sel_T_24, _in_vc_sel_T_17, _in_vc_sel_T_10} & ~mask_1; // @[Mux.scala:30:73] wire [23:0] oh = _full_T_1[0] ? 24'h1 : _full_T_1[1] ? 24'h2 : _full_T_1[2] ? 24'h4 : _full_T_1[3] ? 24'h8 : _full_T_1[4] ? 24'h10 : _full_T_1[5] ? 24'h20 : _full_T_1[6] ? 24'h40 : _full_T_1[7] ? 24'h80 : _full_T_1[8] ? 24'h100 : _full_T_1[9] ? 24'h200 : _full_T_1[10] ? 24'h400 : _full_T_1[11] ? 24'h800 : _in_vc_sel_T_10 ? 24'h1000 : _in_vc_sel_T_17 ? 24'h2000 : _in_vc_sel_T_24 ? 24'h4000 : _in_vc_sel_T_31 ? 24'h8000 : _in_vc_sel_T_38 ? 24'h10000 : _in_vc_sel_T_45 ? 24'h20000 : _in_vc_sel_T_52 ? 24'h40000 : _in_vc_sel_T_59 ? 24'h80000 : _in_vc_sel_T_66 ? 24'h100000 : _in_vc_sel_T_73 ? 24'h200000 : _in_vc_sel_T_80 ? 24'h400000 : {_in_vc_sel_T_87, 23'h0}; // @[OneHot.scala:85:71] wire [11:0] sel = oh[11:0] | oh[23:12]; // @[Mux.scala:50:70] wire in_alloc_2_0 = _GEN & sel[11]; // @[package.scala:81:59] wire in_alloc_1_0 = _GEN & sel[10]; // @[package.scala:81:59] wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59] wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59] wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59] wire in_alloc_0_3 = _GEN & sel[3]; // @[package.scala:81:59] wire in_alloc_0_4 = _GEN & sel[4]; // @[package.scala:81:59] wire in_alloc_0_5 = _GEN & sel[5]; // @[package.scala:81:59] wire in_alloc_0_6 = _GEN & sel[6]; // @[package.scala:81:59] wire in_alloc_0_7 = _GEN & sel[7]; // @[package.scala:81:59] wire in_alloc_0_8 = _GEN & sel[8]; // @[package.scala:81:59] wire in_alloc_0_9 = _GEN & sel[9]; // @[package.scala:81:59]
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File RegField.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.regmapper import chisel3._ import chisel3.util.{DecoupledIO, ReadyValidIO} import org.json4s.JsonDSL._ import org.json4s.JsonAST.JValue import freechips.rocketchip.util.{SimpleRegIO} case class RegReadFn private(combinational: Boolean, fn: (Bool, Bool) => (Bool, Bool, UInt)) object RegReadFn { // (ivalid: Bool, oready: Bool) => (iready: Bool, ovalid: Bool, data: UInt) // iready may combinationally depend on oready // all other combinational dependencies forbidden (e.g. ovalid <= ivalid) // effects must become visible on the cycle after ovalid && oready // data is only inspected when ovalid && oready implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)) = new RegReadFn(false, x) implicit def apply(x: RegisterReadIO[UInt]): RegReadFn = RegReadFn((ivalid, oready) => { x.request.valid := ivalid x.response.ready := oready (x.request.ready, x.response.valid, x.response.bits) }) // (ready: Bool) => (valid: Bool, data: UInt) // valid must not combinationally depend on ready // effects must become visible on the cycle after valid && ready implicit def apply(x: Bool => (Bool, UInt)) = new RegReadFn(true, { case (_, oready) => val (ovalid, data) = x(oready) (true.B, ovalid, data) }) // read from a ReadyValidIO (only safe if there is a consistent source of data) implicit def apply(x: ReadyValidIO[UInt]):RegReadFn = RegReadFn(ready => { x.ready := ready; (x.valid, x.bits) }) // read from a register implicit def apply(x: UInt):RegReadFn = RegReadFn(ready => (true.B, x)) // noop implicit def apply(x: Unit):RegReadFn = RegReadFn(0.U) } case class RegWriteFn private(combinational: Boolean, fn: (Bool, Bool, UInt) => (Bool, Bool)) object RegWriteFn { // (ivalid: Bool, oready: Bool, data: UInt) => (iready: Bool, ovalid: Bool) // iready may combinationally depend on both oready and data // all other combinational dependencies forbidden (e.g. ovalid <= ivalid) // effects must become visible on the cycle after ovalid && oready // data should only be used for an effect when ivalid && iready implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)) = new RegWriteFn(false, x) implicit def apply(x: RegisterWriteIO[UInt]): RegWriteFn = RegWriteFn((ivalid, oready, data) => { x.request.valid := ivalid x.request.bits := data x.response.ready := oready (x.request.ready, x.response.valid) }) // (valid: Bool, data: UInt) => (ready: Bool) // ready may combinationally depend on data (but not valid) // effects must become visible on the cycle after valid && ready implicit def apply(x: (Bool, UInt) => Bool) = // combinational => data valid on oready new RegWriteFn(true, { case (_, oready, data) => (true.B, x(oready, data)) }) // write to a DecoupledIO (only safe if there is a consistent sink draining data) // NOTE: this is not an IrrevocableIO (even on TL2) because other fields could cause a lowered valid implicit def apply(x: DecoupledIO[UInt]): RegWriteFn = RegWriteFn((valid, data) => { x.valid := valid; x.bits := data; x.ready }) // updates a register (or adds a mux to a wire) implicit def apply(x: UInt): RegWriteFn = RegWriteFn((valid, data) => { when (valid) { x := data }; true.B }) // noop implicit def apply(x: Unit): RegWriteFn = RegWriteFn((valid, data) => { true.B }) } case class RegField(width: Int, read: RegReadFn, write: RegWriteFn, desc: Option[RegFieldDesc]) { require (width >= 0, s"RegField width must be >= 0, not $width") def pipelined = !read.combinational || !write.combinational def readOnly = this.copy(write = (), desc = this.desc.map(_.copy(access = RegFieldAccessType.R))) def toJson(byteOffset: Int, bitOffset: Int): JValue = { ( ("byteOffset" -> s"0x${byteOffset.toHexString}") ~ ("bitOffset" -> bitOffset) ~ ("bitWidth" -> width) ~ ("name" -> desc.map(_.name)) ~ ("description" -> desc.map{ d=> if (d.desc == "") None else Some(d.desc)}) ~ ("resetValue" -> desc.map{_.reset}) ~ ("group" -> desc.map{_.group}) ~ ("groupDesc" -> desc.map{_.groupDesc}) ~ ("accessType" -> desc.map {d => d.access.toString}) ~ ("writeType" -> desc.map {d => d.wrType.map(_.toString)}) ~ ("readAction" -> desc.map {d => d.rdAction.map(_.toString)}) ~ ("volatile" -> desc.map {d => if (d.volatile) Some(true) else None}) ~ ("enumerations" -> desc.map {d => Option(d.enumerations.map { case (key, (name, edesc)) => (("value" -> key) ~ ("name" -> name) ~ ("description" -> edesc)) }).filter(_.nonEmpty)}) ) } } object RegField { // Byte address => sequence of bitfields, lowest index => lowest address type Map = (Int, Seq[RegField]) def apply(n: Int) : RegField = apply(n, (), (), Some(RegFieldDesc.reserved)) def apply(n: Int, desc: RegFieldDesc) : RegField = apply(n, (), (), Some(desc)) def apply(n: Int, r: RegReadFn, w: RegWriteFn) : RegField = apply(n, r, w, None) def apply(n: Int, r: RegReadFn, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, r, w, Some(desc)) def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw, None) def apply(n: Int, rw: UInt, desc: RegFieldDesc) : RegField = apply(n, rw, rw, Some(desc)) def r(n: Int, r: RegReadFn) : RegField = apply(n, r, (), None) def r(n: Int, r: RegReadFn, desc: RegFieldDesc) : RegField = apply(n, r, (), Some(desc.copy(access = RegFieldAccessType.R))) def w(n: Int, w: RegWriteFn) : RegField = apply(n, (), w, None) def w(n: Int, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, (), w, Some(desc.copy(access = RegFieldAccessType.W))) // This RegField allows 'set' to set bits in 'reg'. // and to clear bits when the bus writes bits of value 1. // Setting takes priority over clearing. def w1ToClear(n: Int, reg: UInt, set: UInt, desc: Option[RegFieldDesc] = None): RegField = RegField(n, reg, RegWriteFn((valid, data) => { reg := (~((~reg) | Mux(valid, data, 0.U))) | set; true.B }), desc.map{_.copy(access = RegFieldAccessType.RW, wrType=Some(RegFieldWrType.ONE_TO_CLEAR), volatile = true)}) // This RegField wraps an explicit register // (e.g. Black-Boxed Register) to create a R/W register. def rwReg(n: Int, bb: SimpleRegIO, desc: Option[RegFieldDesc] = None) : RegField = RegField(n, bb.q, RegWriteFn((valid, data) => { bb.en := valid bb.d := data true.B }), desc) // Create byte-sized read-write RegFields out of a large UInt register. // It is updated when any of the (implemented) bytes are written, the non-written // bytes are just copied over from their current value. // Because the RegField are all byte-sized, this is also suitable when a register is larger // than the intended bus width of the device (atomic updates are impossible). def bytes(reg: UInt, numBytes: Int, desc: Option[RegFieldDesc]): Seq[RegField] = { require(reg.getWidth * 8 >= numBytes, "Can't break a ${reg.getWidth}-bit-wide register into only ${numBytes} bytes.") val numFullBytes = reg.getWidth/8 val numPartialBytes = if ((reg.getWidth % 8) > 0) 1 else 0 val numPadBytes = numBytes - numFullBytes - numPartialBytes val pad = reg | 0.U((8*numBytes).W) val oldBytes = VecInit.tabulate(numBytes) { i => pad(8*(i+1)-1, 8*i) } val newBytes = WireDefault(oldBytes) val valids = WireDefault(VecInit.fill(numBytes) { false.B }) when (valids.reduce(_ || _)) { reg := newBytes.asUInt } def wrFn(i: Int): RegWriteFn = RegWriteFn((valid, data) => { valids(i) := valid when (valid) {newBytes(i) := data} true.B }) val fullBytes = Seq.tabulate(numFullBytes) { i => val newDesc = desc.map {d => d.copy(name = d.name + s"_$i")} RegField(8, oldBytes(i), wrFn(i), newDesc)} val partialBytes = if (numPartialBytes > 0) { val newDesc = desc.map {d => d.copy(name = d.name + s"_$numFullBytes")} Seq(RegField(reg.getWidth % 8, oldBytes(numFullBytes), wrFn(numFullBytes), newDesc), RegField(8 - (reg.getWidth % 8))) } else Nil val padBytes = Seq.fill(numPadBytes){RegField(8)} fullBytes ++ partialBytes ++ padBytes } def bytes(reg: UInt, desc: Option[RegFieldDesc]): Seq[RegField] = { val width = reg.getWidth require (width % 8 == 0, s"RegField.bytes must be called on byte-sized reg, not ${width} bits") bytes(reg, width/8, desc) } def bytes(reg: UInt, numBytes: Int): Seq[RegField] = bytes(reg, numBytes, None) def bytes(reg: UInt): Seq[RegField] = bytes(reg, None) } trait HasRegMap { def regmap(mapping: RegField.Map*): Unit val interrupts: Vec[Bool] } // See Example.scala for an example of how to use regmap File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. */ object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct */ cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) /* Filter out any cases identical to the default */ val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2*simple.size) { /* The dense encoding case uses a Vec */ val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { /* The sparse encoding case uses switch */ val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File CLINT.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet} import freechips.rocketchip.resources.{Resource, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} import freechips.rocketchip.util.Annotated object CLINTConsts { def msipOffset(hart: Int) = hart * msipBytes def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes def timeOffset = 0xbff8 def msipBytes = 4 def timecmpBytes = 8 def size = 0x10000 def timeWidth = 64 def ipiWidth = 32 def ints = 2 } case class CLINTParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0) { def address = AddressSet(baseAddress, CLINTConsts.size-1) } case object CLINTKey extends Field[Option[CLINTParams]](None) case class CLINTAttachParams( slaveWhere: TLBusWrapperLocation = CBUS ) case object CLINTAttachKey extends Field(CLINTAttachParams()) class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule { import CLINTConsts._ // clint0 => at most 4095 devices val device = new SimpleDevice("clint", Seq("riscv,clint0")) { override val alwaysExtended = true } val node: TLRegisterNode = TLRegisterNode( address = Seq(params.address), device = device, beatBytes = beatBytes) val intnode : IntNexusNode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) lazy val module = new Impl class Impl extends LazyModuleImp(this) { Annotated.params(this, params) require (intnode.edges.in.size == 0, "CLINT only produces interrupts; it does not accept them") val io = IO(new Bundle { val rtcTick = Input(Bool()) }) val time = RegInit(0.U(timeWidth.W)) when (io.rtcTick) { time := time + 1.U } val nTiles = intnode.out.size val timecmp = Seq.fill(nTiles) { Reg(UInt(timeWidth.W)) } val ipi = Seq.fill(nTiles) { RegInit(0.U(1.W)) } val (intnode_out, _) = intnode.out.unzip intnode_out.zipWithIndex.foreach { case (int, i) => int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip } /* 0000 msip hart 0 * 0004 msip hart 1 * 4000 mtimecmp hart 0 lo * 4004 mtimecmp hart 0 hi * 4008 mtimecmp hart 1 lo * 400c mtimecmp hart 1 hi * bff8 mtime lo * bffc mtime hi */ node.regmap( 0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) => RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(ipiWidth - 1) :: Nil }), timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"), RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))}, timeOffset -> RegFieldGroup("mtime", Some("Timer Register"), RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0), volatile=true)))) ) } } /** Trait that will connect a CLINT to a subsystem */ trait CanHavePeripheryCLINT { this: BaseSubsystem => val (clintOpt, clintDomainOpt, clintTickOpt) = p(CLINTKey).map { params => val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere) val clintDomainWrapper = tlbus.generateSynchronousDomain("CLINT").suggestName("clint_domain") val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) } clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus, Some("CLINT")) := _ } } val clintTick = clintDomainWrapper { InModuleBody { val tick = IO(Input(Bool())) clint.module.io.rtcTick := tick tick }} (clint, clintDomainWrapper, clintTick) }.unzip3 }
module CLINT( // @[CLINT.scala:65:9] input clock, // @[CLINT.scala:65:9] input reset, // @[CLINT.scala:65:9] output auto_int_out_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_rtcTick // @[CLINT.scala:69:16] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [12:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_in_a_valid_0 = auto_in_a_valid; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[CLINT.scala:65:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[CLINT.scala:65:9] wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[CLINT.scala:65:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[CLINT.scala:65:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[CLINT.scala:65:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[CLINT.scala:65:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[CLINT.scala:65:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[CLINT.scala:65:9] wire io_rtcTick_0 = io_rtcTick; // @[CLINT.scala:65:9] wire [12:0] out_maskMatch = 13'h7FF; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_denied = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_corrupt = 1'h0; // @[CLINT.scala:65:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_7 = 1'h0; // @[RegField.scala:153:53] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire intnodeOut_1; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[CLINT.scala:65:9] wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[CLINT.scala:65:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[CLINT.scala:65:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[CLINT.scala:65:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[CLINT.scala:65:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[CLINT.scala:65:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[CLINT.scala:65:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_0_0; // @[CLINT.scala:65:9] wire auto_int_out_1_0; // @[CLINT.scala:65:9] wire auto_in_a_ready_0; // @[CLINT.scala:65:9] wire [2:0] auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] wire [1:0] auto_in_d_bits_size_0; // @[CLINT.scala:65:9] wire [10:0] auto_in_d_bits_source_0; // @[CLINT.scala:65:9] wire [63:0] auto_in_d_bits_data_0; // @[CLINT.scala:65:9] wire auto_in_d_valid_0; // @[CLINT.scala:65:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[CLINT.scala:65:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[CLINT.scala:65:9] wire [10:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[CLINT.scala:65:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[CLINT.scala:65:9] wire _intnodeOut_0_T; // @[CLINT.scala:82:37] assign auto_int_out_0_0 = intnodeOut_0; // @[CLINT.scala:65:9] wire _intnodeOut_1_T; // @[CLINT.scala:83:43] assign auto_int_out_1_0 = intnodeOut_1; // @[CLINT.scala:65:9] reg [63:0] time_0; // @[CLINT.scala:73:23] wire [63:0] pad_1 = time_0; // @[RegField.scala:150:19] wire [64:0] _time_T = {1'h0, time_0} + 65'h1; // @[CLINT.scala:73:23, :74:38] wire [63:0] _time_T_1 = _time_T[63:0]; // @[CLINT.scala:74:38] reg [63:0] timecmp_0; // @[CLINT.scala:77:41] wire [63:0] pad = timecmp_0; // @[RegField.scala:150:19] reg ipi_0; // @[CLINT.scala:78:41] assign _intnodeOut_0_T = ipi_0; // @[CLINT.scala:78:41, :82:37] wire _out_T_15 = ipi_0; // @[RegisterRouter.scala:87:24] assign intnodeOut_0 = _intnodeOut_0_T; // @[CLINT.scala:82:37] assign _intnodeOut_1_T = time_0 >= timecmp_0; // @[CLINT.scala:73:23, :77:41, :83:43] assign intnodeOut_1 = _intnodeOut_1_T; // @[CLINT.scala:83:43] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_123 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_16; // @[RegisterRouter.scala:87:24] wire out_f_woready_17; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] timecmp_0_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_lo = {timecmp_0_lo_hi, timecmp_0_lo_lo}; // @[RegField.scala:154:52] wire [15:0] timecmp_0_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_hi = {timecmp_0_hi_hi, timecmp_0_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _timecmp_0_T = {timecmp_0_hi, timecmp_0_lo}; // @[RegField.scala:154:52] wire [7:0] _oldBytes_T_8 = pad_1[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_0 = _oldBytes_T_8; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_9 = pad_1[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_1 = _oldBytes_T_9; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_10 = pad_1[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_2 = _oldBytes_T_10; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_11 = pad_1[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_3 = _oldBytes_T_11; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_12 = pad_1[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_4 = _oldBytes_T_12; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_13 = pad_1[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_5 = _oldBytes_T_13; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_14 = pad_1[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_6 = _oldBytes_T_14; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_15 = pad_1[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_7 = _oldBytes_T_15; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_35 = oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_1_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1_1; // @[RegField.scala:152:31] wire [7:0] newBytes_1_2; // @[RegField.scala:152:31] wire [7:0] newBytes_1_3; // @[RegField.scala:152:31] wire [7:0] newBytes_1_4; // @[RegField.scala:152:31] wire [7:0] newBytes_1_5; // @[RegField.scala:152:31] wire [7:0] newBytes_1_6; // @[RegField.scala:152:31] wire [7:0] newBytes_1_7; // @[RegField.scala:152:31] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_9; // @[RegisterRouter.scala:87:24] wire valids_1_0; // @[RegField.scala:153:29] wire valids_1_1; // @[RegField.scala:153:29] wire valids_1_2; // @[RegField.scala:153:29] wire valids_1_3; // @[RegField.scala:153:29] wire valids_1_4; // @[RegField.scala:153:29] wire valids_1_5; // @[RegField.scala:153:29] wire valids_1_6; // @[RegField.scala:153:29] wire valids_1_7; // @[RegField.scala:153:29] wire [15:0] time_lo_lo = {newBytes_1_1, newBytes_1_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_lo_hi = {newBytes_1_3, newBytes_1_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_lo = {time_lo_hi, time_lo_lo}; // @[RegField.scala:154:52] wire [15:0] time_hi_lo = {newBytes_1_5, newBytes_1_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_hi_hi = {newBytes_1_7, newBytes_1_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_hi = {time_hi_hi, time_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _time_T_2 = {time_hi, time_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [12:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = nodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[12:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [12:0] _GEN = out_front_bits_index & 13'h7FF; // @[RegisterRouter.scala:87:24] wire [12:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [12:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_T_2 = out_findex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_T_3 = out_bindex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_17; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_17; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24] wire _out_T_6 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = _out_T_15; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = _out_T_16; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_17 = out_front_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend = {1'h0, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_24 = {30'h0, out_prepend}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_25 = _out_T_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign valids_1_0 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_26 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_114 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_1_0 = out_f_woready_2 ? _out_T_26 : oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1 = _out_T_36; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign valids_1_1 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_37 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_125 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1_1 = out_f_woready_3 ? _out_T_37 : oldBytes_1_1; // @[RegisterRouter.scala:87:24] wire _out_T_42 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_44 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1 = {oldBytes_1_1, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_46 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_47 = _out_T_46; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_2 = _out_T_47; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_1_2 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_48 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_136 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_1_2 = out_f_woready_4 ? _out_T_48 : oldBytes_1_2; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_2 = {oldBytes_1_2, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_57 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_58 = _out_T_57; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_3 = _out_T_58; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_1_3 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_59 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_147 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_1_3 = out_f_woready_5 ? _out_T_59 : oldBytes_1_3; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_66 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_3 = {oldBytes_1_3, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_68 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_69 = _out_T_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_4 = _out_T_69; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_71 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_72 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_1_4 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_70 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_158 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_1_4 = out_f_woready_6 ? _out_T_70 : oldBytes_1_4; // @[RegisterRouter.scala:87:24] wire _out_T_75 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_76 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_77 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_4 = {oldBytes_1_4, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_79 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_80 = _out_T_79; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_5 = _out_T_80; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_82 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_83 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_84 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_1_5 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_81 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_169 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_1_5 = out_f_woready_7 ? _out_T_81 : oldBytes_1_5; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_88 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_5 = {oldBytes_1_5, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_90 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_91 = _out_T_90; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_6 = _out_T_91; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] assign valids_1_6 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_92 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_180 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_1_6 = out_f_woready_8 ? _out_T_92 : oldBytes_1_6; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_99 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_6 = {oldBytes_1_6, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_101 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_102 = _out_T_101; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_7 = _out_T_102; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = |_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = |_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_104 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_105 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_106 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] assign valids_1_7 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_107 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_103 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_191 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_1_7 = out_f_woready_9 ? _out_T_103 : oldBytes_1_7; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_109 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_110 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_111 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_7 = {oldBytes_1_7, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_112 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_113 = _out_T_112; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_2 = _out_T_113; // @[MuxLiteral.scala:49:48] wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_116 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_woready_10; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready_10 ? _out_T_114 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_119 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_120 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_121 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_124 = _out_T_123; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_8 = _out_T_124; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = |_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = |_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_126 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_127 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_woready_11; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_11 ? _out_T_125 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_130 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_131 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_132 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_8 = {oldBytes_1, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_134 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_135 = _out_T_134; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_9 = _out_T_135; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = |_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = |_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_137 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_138 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_woready_12; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_12 ? _out_T_136 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_141 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_9 = {oldBytes_2, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_145 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_146 = _out_T_145; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_10 = _out_T_146; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = |_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = |_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_150 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire _out_T_151 = out_f_woready_13; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_13 ? _out_T_147 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_154 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_155 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_10 = {oldBytes_3, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_156 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_157 = _out_T_156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_11 = _out_T_157; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = |_out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire out_romask_14 = |_out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_161 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_14; // @[RegisterRouter.scala:87:24] wire _out_T_162 = out_f_woready_14; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_14 ? _out_T_158 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_165 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_166 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_11 = {oldBytes_4, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_167 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_168 = _out_T_167; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_12 = _out_T_168; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_170 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_171 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_172 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire _out_T_173 = out_f_woready_15; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_15 ? _out_T_169 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_174 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_175 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_176 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_177 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_12 = {oldBytes_5, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_178 = out_prepend_12; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_179 = _out_T_178; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_13 = _out_T_179; // @[RegisterRouter.scala:87:24] wire out_rimask_16 = |_out_rimask_T_16; // @[RegisterRouter.scala:87:24] wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24] wire out_romask_16 = |_out_romask_T_16; // @[RegisterRouter.scala:87:24] wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_181 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_182 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_183 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_16; // @[RegisterRouter.scala:87:24] wire _out_T_184 = out_f_woready_16; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_16 ? _out_T_180 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_185 = ~out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_186 = ~out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_187 = ~out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_188 = ~out_womask_16; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_13 = {oldBytes_6, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_189 = out_prepend_13; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_190 = _out_T_189; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_14 = _out_T_190; // @[RegisterRouter.scala:87:24] wire out_rimask_17 = |_out_rimask_T_17; // @[RegisterRouter.scala:87:24] wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24] wire out_romask_17 = |_out_romask_T_17; // @[RegisterRouter.scala:87:24] wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_192 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_193 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_194 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_17; // @[RegisterRouter.scala:87:24] wire _out_T_195 = out_f_woready_17; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_17 ? _out_T_191 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_196 = ~out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_197 = ~out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_198 = ~out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_199 = ~out_womask_17; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_14 = {oldBytes_7, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_200 = out_prepend_14; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_201 = _out_T_200; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = _out_T_201; // @[MuxLiteral.scala:49:48] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_12, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_12, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_16 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_17 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_16 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_17 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_17 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_17 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{1'h1}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_0 = {32'h0, _out_T_25}; // @[MuxLiteral.scala:49:48] wire [3:0][63:0] _GEN_5 = {{64'h0}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[CLINT.scala:65:9] if (reset) begin // @[CLINT.scala:65:9] time_0 <= 64'h0; // @[CLINT.scala:73:23] ipi_0 <= 1'h0; // @[CLINT.scala:78:41] end else begin // @[CLINT.scala:65:9] if (valids_1_0 | valids_1_1 | valids_1_2 | valids_1_3 | valids_1_4 | valids_1_5 | valids_1_6 | valids_1_7) // @[RegField.scala:153:29, :154:27] time_0 <= _time_T_2; // @[RegField.scala:154:52] else if (io_rtcTick_0) // @[CLINT.scala:65:9] time_0 <= _time_T_1; // @[CLINT.scala:73:23, :74:38] if (out_f_woready) // @[RegisterRouter.scala:87:24] ipi_0 <= _out_T_6; // @[RegisterRouter.scala:87:24] end if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6 | valids_7) // @[RegField.scala:153:29, :154:27] timecmp_0 <= _timecmp_0_T; // @[RegField.scala:154:52] always @(posedge) TLMonitor_41 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_int_out_0 = auto_int_out_0_0; // @[CLINT.scala:65:9] assign auto_int_out_1 = auto_int_out_1_0; // @[CLINT.scala:65:9] assign auto_in_a_ready = auto_in_a_ready_0; // @[CLINT.scala:65:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[CLINT.scala:65:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_43( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [9:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [9:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_111 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_113 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_117 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_119 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_123 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_125 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_129 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_131 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_165 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_167 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_171 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_173 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_177 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_179 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_183 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_185 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_189 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_191 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_195 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_197 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_201 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_203 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_207 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_209 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_213 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_215 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_219 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_221 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_225 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_227 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_231 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_233 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_237 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_239 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_243 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_245 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_249 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_251 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_255 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_257 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_261 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_263 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_267 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_269 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_273 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_275 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_279 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_281 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_285 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_287 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_291 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_293 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [9:0] _c_first_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_first_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_first_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_first_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_set_wo_ready_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_set_wo_ready_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_opcodes_set_interm_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_opcodes_set_interm_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_sizes_set_interm_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_sizes_set_interm_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_opcodes_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_opcodes_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_sizes_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_sizes_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_probe_ack_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_probe_ack_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_probe_ack_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_probe_ack_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _same_cycle_resp_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _same_cycle_resp_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _same_cycle_resp_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _same_cycle_resp_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _same_cycle_resp_WIRE_4_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _same_cycle_resp_WIRE_5_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [8194:0] _c_opcodes_set_T_1 = 8195'h0; // @[Monitor.scala:767:54] wire [8194:0] _c_sizes_set_T_1 = 8195'h0; // @[Monitor.scala:768:52] wire [12:0] _c_opcodes_set_T = 13'h0; // @[Monitor.scala:767:79] wire [12:0] _c_sizes_set_T = 13'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [1023:0] _c_set_wo_ready_T = 1024'h1; // @[OneHot.scala:58:35] wire [1023:0] _c_set_T = 1024'h1; // @[OneHot.scala:58:35] wire [2051:0] c_opcodes_set = 2052'h0; // @[Monitor.scala:740:34] wire [2051:0] c_sizes_set = 2052'h0; // @[Monitor.scala:741:34] wire [512:0] c_set = 513'h0; // @[Monitor.scala:738:34] wire [512:0] c_set_wo_ready = 513'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [9:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_77 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_78 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_79 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_80 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_81 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_82 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_83 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_84 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_85 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_86 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_87 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_88 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_89 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_90 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_91 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_92 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_93 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_94 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_95 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_96 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_97 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_98 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_99 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_100 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_101 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_102 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_103 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_104 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_105 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_106 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_107 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_108 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_109 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_110 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_111 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_112 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_113 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_114 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_115 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_116 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_117 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_118 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_119 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_120 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_121 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_122 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_123 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_124 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_125 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_126 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_127 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_128 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_129 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_130 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_131 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_132 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_133 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_134 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_135 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_136 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_137 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_138 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_139 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_140 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_141 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_142 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_143 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_144 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_145 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_146 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_147 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_148 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_149 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_150 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_151 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_152 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_153 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_154 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_155 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_156 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_157 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_158 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_159 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_160 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_161 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_162 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_163 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_164 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_165 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_166 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_167 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_168 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_169 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_170 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_171 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_172 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_173 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_174 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_175 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_176 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_177 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_178 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_179 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_180 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_181 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_182 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_183 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_184 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_185 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_186 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_187 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_188 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_189 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_190 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_191 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_192 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_193 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_194 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_195 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_196 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_197 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_198 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_199 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_200 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_201 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_202 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_203 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_204 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_205 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_206 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_207 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_208 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_209 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_210 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_211 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_212 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_213 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_214 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_215 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_216 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_217 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_218 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_219 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_220 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_221 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_222 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_223 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_224 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_225 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_226 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_227 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_228 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_229 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_230 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_231 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_232 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_233 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_234 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_235 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_236 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_237 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_238 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_239 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_240 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_241 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_22 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_23 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_24 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_25 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_26 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_27 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_28 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_29 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_30 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_31 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_32 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_33 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_34 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_35 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_36 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_37 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_38 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_39 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_40 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_41 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_42 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_43 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 10'h1D0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [7:0] _source_ok_T_1 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_7 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_13 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_19 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_25 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_31 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_73 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_79 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 8'h70; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 8'h71; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 8'h72; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 8'h73; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 8'h7C; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 8'h7B; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_61 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_67 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_85 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_91 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_97 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_103 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_109 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_115 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_121 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_127 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'hD; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'hC; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_9 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_10 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_62 = _source_ok_T_61 == 5'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_11 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_68 = _source_ok_T_67 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_12 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_74 = _source_ok_T_73 == 8'h7A; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_13 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_80 = _source_ok_T_79 == 8'h79; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_14 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 5'h7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_15 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_16 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_16 = _source_ok_uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 5'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_17 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_17 = _source_ok_uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_18 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_18 = _source_ok_uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_110 = _source_ok_T_109 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_112 = _source_ok_T_110; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_114 = _source_ok_T_112; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_19 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_19 = _source_ok_uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_116 = _source_ok_T_115 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_118 = _source_ok_T_116; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_120 = _source_ok_T_118; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_20 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_20 = _source_ok_uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_122 = _source_ok_T_121 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_124 = _source_ok_T_122; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_126 = _source_ok_T_124; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_21 = _source_ok_T_126; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_21 = _source_ok_uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_128 = _source_ok_T_127 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_130 = _source_ok_T_128; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_132 = _source_ok_T_130; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_22 = _source_ok_T_132; // @[Parameters.scala:1138:31] wire _source_ok_T_133 = io_in_a_bits_source_0 == 10'h1E0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_23 = _source_ok_T_133; // @[Parameters.scala:1138:31] wire _source_ok_T_134 = io_in_a_bits_source_0 == 10'h1E1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_24 = _source_ok_T_134; // @[Parameters.scala:1138:31] wire _source_ok_T_135 = io_in_a_bits_source_0 == 10'h1E2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_25 = _source_ok_T_135; // @[Parameters.scala:1138:31] wire _source_ok_T_136 = io_in_a_bits_source_0 == 10'h200; // @[Monitor.scala:36:7] wire _source_ok_WIRE_26 = _source_ok_T_136; // @[Parameters.scala:1138:31] wire _source_ok_T_137 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_138 = _source_ok_T_137 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_139 = _source_ok_T_138 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_140 = _source_ok_T_139 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_141 = _source_ok_T_140 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_142 = _source_ok_T_141 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_143 = _source_ok_T_142 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_144 = _source_ok_T_143 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_145 = _source_ok_T_144 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_146 = _source_ok_T_145 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_147 = _source_ok_T_146 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_148 = _source_ok_T_147 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_149 = _source_ok_T_148 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_150 = _source_ok_T_149 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_151 = _source_ok_T_150 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_152 = _source_ok_T_151 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_153 = _source_ok_T_152 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_154 = _source_ok_T_153 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_155 = _source_ok_T_154 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_156 = _source_ok_T_155 | _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_157 = _source_ok_T_156 | _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_158 = _source_ok_T_157 | _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_159 = _source_ok_T_158 | _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_160 = _source_ok_T_159 | _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_161 = _source_ok_T_160 | _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_161 | _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_9 = _uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_14 = _uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_15 = _uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_18 = _uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_19 = _uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_20 = _uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_21 = _uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_30 = _uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_31 = _uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_32 = _uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_33 = _uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_36 = _uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_37 = _uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_38 = _uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_39 = _uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_42 = _uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_43 = _uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_50 = _uncommonBits_T_50[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_51 = _uncommonBits_T_51[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_54 = _uncommonBits_T_54[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_55 = _uncommonBits_T_55[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_60 = _uncommonBits_T_60[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_61 = _uncommonBits_T_61[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_62 = _uncommonBits_T_62[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_63 = _uncommonBits_T_63[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_69 = _uncommonBits_T_69[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_72 = _uncommonBits_T_72[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_73 = _uncommonBits_T_73[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_74 = _uncommonBits_T_74[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_75 = _uncommonBits_T_75[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_76 = _uncommonBits_T_76[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_77 = _uncommonBits_T_77[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_79 = _uncommonBits_T_79[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_80 = _uncommonBits_T_80[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_81 = _uncommonBits_T_81[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_82 = _uncommonBits_T_82[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_83 = _uncommonBits_T_83[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_84 = _uncommonBits_T_84[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_85 = _uncommonBits_T_85[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_86 = _uncommonBits_T_86[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_87 = _uncommonBits_T_87[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_89 = _uncommonBits_T_89[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_90 = _uncommonBits_T_90[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_91 = _uncommonBits_T_91[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_92 = _uncommonBits_T_92[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_93 = _uncommonBits_T_93[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_94 = _uncommonBits_T_94[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_95 = _uncommonBits_T_95[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_96 = _uncommonBits_T_96[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_97 = _uncommonBits_T_97[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_98 = _uncommonBits_T_98[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_99 = _uncommonBits_T_99[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_100 = _uncommonBits_T_100[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_101 = _uncommonBits_T_101[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_102 = _uncommonBits_T_102[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_103 = _uncommonBits_T_103[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_104 = _uncommonBits_T_104[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_105 = _uncommonBits_T_105[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_106 = _uncommonBits_T_106[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_107 = _uncommonBits_T_107[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_108 = _uncommonBits_T_108[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_109 = _uncommonBits_T_109[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_110 = _uncommonBits_T_110[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_111 = _uncommonBits_T_111[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_112 = _uncommonBits_T_112[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_113 = _uncommonBits_T_113[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_114 = _uncommonBits_T_114[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_115 = _uncommonBits_T_115[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_116 = _uncommonBits_T_116[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_117 = _uncommonBits_T_117[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_118 = _uncommonBits_T_118[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_119 = _uncommonBits_T_119[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_120 = _uncommonBits_T_120[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_121 = _uncommonBits_T_121[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_122 = _uncommonBits_T_122[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_123 = _uncommonBits_T_123[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_124 = _uncommonBits_T_124[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_125 = _uncommonBits_T_125[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_126 = _uncommonBits_T_126[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_127 = _uncommonBits_T_127[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_128 = _uncommonBits_T_128[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_129 = _uncommonBits_T_129[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_130 = _uncommonBits_T_130[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_131 = _uncommonBits_T_131[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_132 = _uncommonBits_T_132[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_133 = _uncommonBits_T_133[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_134 = _uncommonBits_T_134[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_135 = _uncommonBits_T_135[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_136 = _uncommonBits_T_136[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_137 = _uncommonBits_T_137[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_138 = _uncommonBits_T_138[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_139 = _uncommonBits_T_139[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_140 = _uncommonBits_T_140[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_141 = _uncommonBits_T_141[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_142 = _uncommonBits_T_142[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_143 = _uncommonBits_T_143[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_144 = _uncommonBits_T_144[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_145 = _uncommonBits_T_145[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_146 = _uncommonBits_T_146[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_147 = _uncommonBits_T_147[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_148 = _uncommonBits_T_148[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_149 = _uncommonBits_T_149[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_150 = _uncommonBits_T_150[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_151 = _uncommonBits_T_151[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_152 = _uncommonBits_T_152[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_153 = _uncommonBits_T_153[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_154 = _uncommonBits_T_154[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_155 = _uncommonBits_T_155[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_156 = _uncommonBits_T_156[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_157 = _uncommonBits_T_157[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_158 = _uncommonBits_T_158[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_159 = _uncommonBits_T_159[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_160 = _uncommonBits_T_160[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_161 = _uncommonBits_T_161[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_162 = _uncommonBits_T_162[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_163 = _uncommonBits_T_163[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_164 = _uncommonBits_T_164[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_165 = _uncommonBits_T_165[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_166 = _uncommonBits_T_166[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_167 = _uncommonBits_T_167[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_168 = _uncommonBits_T_168[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_169 = _uncommonBits_T_169[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_170 = _uncommonBits_T_170[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_171 = _uncommonBits_T_171[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_172 = _uncommonBits_T_172[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_173 = _uncommonBits_T_173[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_174 = _uncommonBits_T_174[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_175 = _uncommonBits_T_175[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_176 = _uncommonBits_T_176[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_177 = _uncommonBits_T_177[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_178 = _uncommonBits_T_178[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_179 = _uncommonBits_T_179[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_180 = _uncommonBits_T_180[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_181 = _uncommonBits_T_181[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_182 = _uncommonBits_T_182[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_183 = _uncommonBits_T_183[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_184 = _uncommonBits_T_184[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_185 = _uncommonBits_T_185[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_186 = _uncommonBits_T_186[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_187 = _uncommonBits_T_187[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_188 = _uncommonBits_T_188[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_189 = _uncommonBits_T_189[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_190 = _uncommonBits_T_190[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_191 = _uncommonBits_T_191[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_192 = _uncommonBits_T_192[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_193 = _uncommonBits_T_193[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_194 = _uncommonBits_T_194[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_195 = _uncommonBits_T_195[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_196 = _uncommonBits_T_196[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_197 = _uncommonBits_T_197[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_198 = _uncommonBits_T_198[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_199 = _uncommonBits_T_199[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_200 = _uncommonBits_T_200[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_201 = _uncommonBits_T_201[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_202 = _uncommonBits_T_202[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_203 = _uncommonBits_T_203[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_204 = _uncommonBits_T_204[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_205 = _uncommonBits_T_205[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_206 = _uncommonBits_T_206[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_207 = _uncommonBits_T_207[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_208 = _uncommonBits_T_208[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_209 = _uncommonBits_T_209[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_210 = _uncommonBits_T_210[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_211 = _uncommonBits_T_211[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_212 = _uncommonBits_T_212[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_213 = _uncommonBits_T_213[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_214 = _uncommonBits_T_214[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_215 = _uncommonBits_T_215[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_216 = _uncommonBits_T_216[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_217 = _uncommonBits_T_217[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_218 = _uncommonBits_T_218[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_219 = _uncommonBits_T_219[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_220 = _uncommonBits_T_220[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_221 = _uncommonBits_T_221[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_222 = _uncommonBits_T_222[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_223 = _uncommonBits_T_223[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_224 = _uncommonBits_T_224[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_225 = _uncommonBits_T_225[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_226 = _uncommonBits_T_226[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_227 = _uncommonBits_T_227[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_228 = _uncommonBits_T_228[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_229 = _uncommonBits_T_229[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_230 = _uncommonBits_T_230[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_231 = _uncommonBits_T_231[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_232 = _uncommonBits_T_232[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_233 = _uncommonBits_T_233[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_234 = _uncommonBits_T_234[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_235 = _uncommonBits_T_235[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_236 = _uncommonBits_T_236[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_237 = _uncommonBits_T_237[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_238 = _uncommonBits_T_238[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_239 = _uncommonBits_T_239[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_240 = _uncommonBits_T_240[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_241 = _uncommonBits_T_241[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_162 = io_in_d_bits_source_0 == 10'h1D0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_162; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_22 = _source_ok_uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [7:0] _source_ok_T_163 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_169 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_175 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_181 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_187 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_193 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_235 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_241 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire _source_ok_T_164 = _source_ok_T_163 == 8'h70; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_166 = _source_ok_T_164; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_168 = _source_ok_T_166; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_168; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_23 = _source_ok_uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_170 = _source_ok_T_169 == 8'h71; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_172 = _source_ok_T_170; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_174 = _source_ok_T_172; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_174; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_24 = _source_ok_uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_176 = _source_ok_T_175 == 8'h72; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_178 = _source_ok_T_176; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_180 = _source_ok_T_178; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_180; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_25 = _source_ok_uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_182 = _source_ok_T_181 == 8'h73; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_184 = _source_ok_T_182; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_186 = _source_ok_T_184; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_186; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_26 = _source_ok_uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_188 = _source_ok_T_187 == 8'h7C; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_190 = _source_ok_T_188; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_192 = _source_ok_T_190; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_192; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_27 = _source_ok_uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_194 = _source_ok_T_193 == 8'h7B; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_196 = _source_ok_T_194; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_198 = _source_ok_T_196; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_198; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_28 = _source_ok_uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_199 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_205 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_211 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_217 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_223 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_229 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_247 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_253 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_259 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_265 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_271 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_277 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_283 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_289 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire _source_ok_T_200 = _source_ok_T_199 == 5'hD; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_202 = _source_ok_T_200; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_204 = _source_ok_T_202; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_204; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_29 = _source_ok_uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_206 = _source_ok_T_205 == 5'hC; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_208 = _source_ok_T_206; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_210 = _source_ok_T_208; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_210; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_30 = _source_ok_uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_212 = _source_ok_T_211 == 5'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_214 = _source_ok_T_212; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_216 = _source_ok_T_214; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_9 = _source_ok_T_216; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_31 = _source_ok_uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_218 = _source_ok_T_217 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_220 = _source_ok_T_218; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_222 = _source_ok_T_220; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_10 = _source_ok_T_222; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_32 = _source_ok_uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_224 = _source_ok_T_223 == 5'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_226 = _source_ok_T_224; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_228 = _source_ok_T_226; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_11 = _source_ok_T_228; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_33 = _source_ok_uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_230 = _source_ok_T_229 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_232 = _source_ok_T_230; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_234 = _source_ok_T_232; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_12 = _source_ok_T_234; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_34 = _source_ok_uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_236 = _source_ok_T_235 == 8'h7A; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_238 = _source_ok_T_236; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_240 = _source_ok_T_238; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_13 = _source_ok_T_240; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_35 = _source_ok_uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_242 = _source_ok_T_241 == 8'h79; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_244 = _source_ok_T_242; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_246 = _source_ok_T_244; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_14 = _source_ok_T_246; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_36 = _source_ok_uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_248 = _source_ok_T_247 == 5'h7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_250 = _source_ok_T_248; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_252 = _source_ok_T_250; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_15 = _source_ok_T_252; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_37 = _source_ok_uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_254 = _source_ok_T_253 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_256 = _source_ok_T_254; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_258 = _source_ok_T_256; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_16 = _source_ok_T_258; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_38 = _source_ok_uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_260 = _source_ok_T_259 == 5'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_262 = _source_ok_T_260; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_264 = _source_ok_T_262; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_17 = _source_ok_T_264; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_39 = _source_ok_uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_266 = _source_ok_T_265 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_268 = _source_ok_T_266; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_270 = _source_ok_T_268; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_18 = _source_ok_T_270; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_40 = _source_ok_uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_272 = _source_ok_T_271 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_274 = _source_ok_T_272; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_276 = _source_ok_T_274; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_19 = _source_ok_T_276; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_41 = _source_ok_uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_278 = _source_ok_T_277 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_280 = _source_ok_T_278; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_282 = _source_ok_T_280; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_20 = _source_ok_T_282; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_42 = _source_ok_uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_284 = _source_ok_T_283 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_286 = _source_ok_T_284; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_288 = _source_ok_T_286; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_21 = _source_ok_T_288; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_43 = _source_ok_uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_290 = _source_ok_T_289 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_292 = _source_ok_T_290; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_294 = _source_ok_T_292; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_22 = _source_ok_T_294; // @[Parameters.scala:1138:31] wire _source_ok_T_295 = io_in_d_bits_source_0 == 10'h1E0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_23 = _source_ok_T_295; // @[Parameters.scala:1138:31] wire _source_ok_T_296 = io_in_d_bits_source_0 == 10'h1E1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_24 = _source_ok_T_296; // @[Parameters.scala:1138:31] wire _source_ok_T_297 = io_in_d_bits_source_0 == 10'h1E2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_25 = _source_ok_T_297; // @[Parameters.scala:1138:31] wire _source_ok_T_298 = io_in_d_bits_source_0 == 10'h200; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_26 = _source_ok_T_298; // @[Parameters.scala:1138:31] wire _source_ok_T_299 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_300 = _source_ok_T_299 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_301 = _source_ok_T_300 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_302 = _source_ok_T_301 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_303 = _source_ok_T_302 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_304 = _source_ok_T_303 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_305 = _source_ok_T_304 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_306 = _source_ok_T_305 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_307 = _source_ok_T_306 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_308 = _source_ok_T_307 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_309 = _source_ok_T_308 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_310 = _source_ok_T_309 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_311 = _source_ok_T_310 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_312 = _source_ok_T_311 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_313 = _source_ok_T_312 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_314 = _source_ok_T_313 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_315 = _source_ok_T_314 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_316 = _source_ok_T_315 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_317 = _source_ok_T_316 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_318 = _source_ok_T_317 | _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_319 = _source_ok_T_318 | _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_320 = _source_ok_T_319 | _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_321 = _source_ok_T_320 | _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_322 = _source_ok_T_321 | _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_323 = _source_ok_T_322 | _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_323 | _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46] wire _T_2642 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2642; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2642; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [9:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_2710 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2710; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2710; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2710; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [9:0] source_1; // @[Monitor.scala:541:22] reg [512:0] inflight; // @[Monitor.scala:614:27] reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [2051:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [512:0] a_set; // @[Monitor.scala:626:34] wire [512:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [2051:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [2051:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [12:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [12:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [12:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [12:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [12:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [12:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [12:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [12:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [12:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [2051:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [2051:0] _a_opcode_lookup_T_6 = {2048'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [2051:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[2051:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [2051:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [2051:0] _a_size_lookup_T_6 = {2048'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [2051:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[2051:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1023:0] _GEN_2 = 1024'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [1023:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [1023:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire _T_2575 = _T_2642 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2575 ? _a_set_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2575 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2575 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [12:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [12:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [12:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [8194:0] _a_opcodes_set_T_1 = {8191'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2575 ? _a_opcodes_set_T_1[2051:0] : 2052'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [8194:0] _a_sizes_set_T_1 = {8191'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2575 ? _a_sizes_set_T_1[2051:0] : 2052'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [512:0] d_clr; // @[Monitor.scala:664:34] wire [512:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [2051:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [2051:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_2621 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1023:0] _GEN_5 = 1024'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [1023:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [1023:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [1023:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [1023:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2621 & ~d_release_ack ? _d_clr_wo_ready_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire _T_2590 = _T_2710 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2590 ? _d_clr_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire [8206:0] _d_opcodes_clr_T_5 = 8207'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2590 ? _d_opcodes_clr_T_5[2051:0] : 2052'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [8206:0] _d_sizes_clr_T_5 = 8207'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2590 ? _d_sizes_clr_T_5[2051:0] : 2052'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [512:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [512:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [512:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [2051:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [2051:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [2051:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [2051:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [2051:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [2051:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [512:0] inflight_1; // @[Monitor.scala:726:35] wire [512:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [2051:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [2051:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [2051:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [2051:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [2051:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [2051:0] _c_opcode_lookup_T_6 = {2048'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [2051:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[2051:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [2051:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [2051:0] _c_size_lookup_T_6 = {2048'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [2051:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[2051:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [512:0] d_clr_1; // @[Monitor.scala:774:34] wire [512:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [2051:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [2051:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2686 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2686 & d_release_ack_1 ? _d_clr_wo_ready_T_1[512:0] : 513'h0; // @[OneHot.scala:58:35] wire _T_2668 = _T_2710 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2668 ? _d_clr_T_1[512:0] : 513'h0; // @[OneHot.scala:58:35] wire [8206:0] _d_opcodes_clr_T_11 = 8207'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2668 ? _d_opcodes_clr_T_11[2051:0] : 2052'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [8206:0] _d_sizes_clr_T_11 = 8207'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2668 ? _d_sizes_clr_T_11[2051:0] : 2052'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 10'h0; // @[Monitor.scala:36:7, :795:113] wire [512:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [512:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [2051:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [2051:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [2051:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [2051:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File lsu.scala: //****************************************************************************** // Copyright (c) 2012 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Out-of-Order Load/Store Unit //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // Load/Store Unit is made up of the Load Queue, the Store Queue (LDQ and STQ). // // Stores are sent to memory at (well, after) commit, loads are executed // optimstically ASAP. If a misspeculation was discovered, the pipeline is // cleared. Loads put to sleep are retried. If a LoadAddr and StoreAddr match, // the Load can receive its data by forwarding data out of the Store Queue. // // Currently, loads are sent to memory immediately, and in parallel do an // associative search of the STQ, on entering the LSU. If a hit on the STQ // search, the memory request is killed on the next cycle, and if the STQ entry // is valid, the store data is forwarded to the load (delayed to match the // load-use delay to delay with the write-port structural hazard). If the store // data is not present, or it's only a partial match (SB->LH), the load is put // to sleep in the LDQ. // // Memory ordering violations are detected by stores at their addr-gen time by // associatively searching the LDQ for newer loads that have been issued to // memory. // // The store queue contains both speculated and committed stores. // // Only one port to memory... loads and stores have to fight for it, West Side // Story style. // // TODO: // - Add predicting structure for ordering failures // - currently won't STD forward if DMEM is busy // - ability to turn off things if VM is disabled // - reconsider port count of the wakeup, retry stuff package boom.v3.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.Str import boom.v3.common._ import boom.v3.exu.{BrUpdateInfo, Exception, FuncUnitResp, CommitSignals, ExeUnitResp} import boom.v3.util.{BoolToChar, AgePriorityEncoder, IsKilledByBranch, GetNewBrMask, WrapInc, IsOlder, UpdateBrMask} class LSUExeIO(implicit p: Parameters) extends BoomBundle()(p) { // The "resp" of the maddrcalc is really a "req" to the LSU val req = Flipped(new ValidIO(new FuncUnitResp(xLen))) // Send load data to regfiles val iresp = new DecoupledIO(new boom.v3.exu.ExeUnitResp(xLen)) val fresp = new DecoupledIO(new boom.v3.exu.ExeUnitResp(xLen+1)) // TODO: Should this be fLen? } class BoomDCacheReq(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = UInt(coreMaxAddrBits.W) val data = Bits(coreDataBits.W) val is_hella = Bool() // Is this the hellacache req? If so this is not tracked in LDQ or STQ } class BoomDCacheResp(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val data = Bits(coreDataBits.W) val is_hella = Bool() } class LSUDMemIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { // In LSU's dmem stage, send the request val req = new DecoupledIO(Vec(memWidth, Valid(new BoomDCacheReq))) // In LSU's LCAM search stage, kill if order fail (or forwarding possible) val s1_kill = Output(Vec(memWidth, Bool())) // Get a request any cycle val resp = Flipped(Vec(memWidth, new ValidIO(new BoomDCacheResp))) // In our response stage, if we get a nack, we need to reexecute val nack = Flipped(Vec(memWidth, new ValidIO(new BoomDCacheReq))) val brupdate = Output(new BrUpdateInfo) val exception = Output(Bool()) val rob_pnr_idx = Output(UInt(robAddrSz.W)) val rob_head_idx = Output(UInt(robAddrSz.W)) val release = Flipped(new DecoupledIO(new TLBundleC(edge.bundle))) // Clears prefetching MSHRs val force_order = Output(Bool()) val ordered = Input(Bool()) val perf = Input(new Bundle { val acquire = Bool() val release = Bool() }) } class LSUCoreIO(implicit p: Parameters) extends BoomBundle()(p) { val exe = Vec(memWidth, new LSUExeIO) val dis_uops = Flipped(Vec(coreWidth, Valid(new MicroOp))) val dis_ldq_idx = Output(Vec(coreWidth, UInt(ldqAddrSz.W))) val dis_stq_idx = Output(Vec(coreWidth, UInt(stqAddrSz.W))) val ldq_full = Output(Vec(coreWidth, Bool())) val stq_full = Output(Vec(coreWidth, Bool())) val fp_stdata = Flipped(Decoupled(new ExeUnitResp(fLen))) val commit = Input(new CommitSignals) val commit_load_at_rob_head = Input(Bool()) // Stores clear busy bit when stdata is received // memWidth for int, 1 for fp (to avoid back-pressure fpstdat) val clr_bsy = Output(Vec(memWidth + 1, Valid(UInt(robAddrSz.W)))) // Speculatively safe load (barring memory ordering failure) val clr_unsafe = Output(Vec(memWidth, Valid(UInt(robAddrSz.W)))) // Tell the DCache to clear prefetches/speculating misses val fence_dmem = Input(Bool()) // Speculatively tell the IQs that we'll get load data back next cycle val spec_ld_wakeup = Output(Vec(memWidth, Valid(UInt(maxPregSz.W)))) // Tell the IQs that the load we speculated last cycle was misspeculated val ld_miss = Output(Bool()) val brupdate = Input(new BrUpdateInfo) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val exception = Input(Bool()) val fencei_rdy = Output(Bool()) val lxcpt = Output(Valid(new Exception)) val tsc_reg = Input(UInt()) val perf = Output(new Bundle { val acquire = Bool() val release = Bool() val tlbMiss = Bool() }) } class LSUIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { val ptw = new rocket.TLBPTWIO val core = new LSUCoreIO val dmem = new LSUDMemIO val hellacache = Flipped(new freechips.rocketchip.rocket.HellaCacheIO) } class LDQEntry(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = Valid(UInt(coreMaxAddrBits.W)) val addr_is_virtual = Bool() // Virtual address, we got a TLB miss val addr_is_uncacheable = Bool() // Uncacheable, wait until head of ROB to execute val executed = Bool() // load sent to memory, reset by NACKs val succeeded = Bool() val order_fail = Bool() val observed = Bool() val st_dep_mask = UInt(numStqEntries.W) // list of stores older than us val youngest_stq_idx = UInt(stqAddrSz.W) // index of the oldest store younger than us val forward_std_val = Bool() val forward_stq_idx = UInt(stqAddrSz.W) // Which store did we get the store-load forward from? val debug_wb_data = UInt(xLen.W) } class STQEntry(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = Valid(UInt(coreMaxAddrBits.W)) val addr_is_virtual = Bool() // Virtual address, we got a TLB miss val data = Valid(UInt(xLen.W)) val committed = Bool() // committed by ROB val succeeded = Bool() // D$ has ack'd this, we don't need to maintain this anymore val debug_wb_data = UInt(xLen.W) } class LSU(implicit p: Parameters, edge: TLEdgeOut) extends BoomModule()(p) with rocket.HasL1HellaCacheParameters { val io = IO(new LSUIO) io.hellacache := DontCare val ldq = Reg(Vec(numLdqEntries, Valid(new LDQEntry))) val stq = Reg(Vec(numStqEntries, Valid(new STQEntry))) val ldq_head = Reg(UInt(ldqAddrSz.W)) val ldq_tail = Reg(UInt(ldqAddrSz.W)) val stq_head = Reg(UInt(stqAddrSz.W)) // point to next store to clear from STQ (i.e., send to memory) val stq_tail = Reg(UInt(stqAddrSz.W)) val stq_commit_head = Reg(UInt(stqAddrSz.W)) // point to next store to commit val stq_execute_head = Reg(UInt(stqAddrSz.W)) // point to next store to execute // If we got a mispredict, the tail will be misaligned for 1 extra cycle assert (io.core.brupdate.b2.mispredict || stq(stq_execute_head).valid || stq_head === stq_execute_head || stq_tail === stq_execute_head, "stq_execute_head got off track.") val h_ready :: h_s1 :: h_s2 :: h_s2_nack :: h_wait :: h_replay :: h_dead :: Nil = Enum(7) // s1 : do TLB, if success and not killed, fire request go to h_s2 // store s1_data to register // if tlb miss, go to s2_nack // if don't get TLB, go to s2_nack // store tlb xcpt // s2 : If kill, go to dead // If tlb xcpt, send tlb xcpt, go to dead // s2_nack : send nack, go to dead // wait : wait for response, if nack, go to replay // replay : refire request, use already translated address // dead : wait for response, ignore it val hella_state = RegInit(h_ready) val hella_req = Reg(new rocket.HellaCacheReq) val hella_data = Reg(new rocket.HellaCacheWriteData) val hella_paddr = Reg(UInt(paddrBits.W)) val hella_xcpt = Reg(new rocket.HellaCacheExceptions) val dtlb = Module(new NBDTLB( instruction = false, lgMaxSize = log2Ceil(coreDataBytes), rocket.TLBConfig(dcacheParams.nTLBSets, dcacheParams.nTLBWays))) io.ptw <> dtlb.io.ptw io.core.perf.tlbMiss := io.ptw.req.fire io.core.perf.acquire := io.dmem.perf.acquire io.core.perf.release := io.dmem.perf.release val clear_store = WireInit(false.B) val live_store_mask = RegInit(0.U(numStqEntries.W)) var next_live_store_mask = Mux(clear_store, live_store_mask & ~(1.U << stq_head), live_store_mask) def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) //------------------------------------------------------------- //------------------------------------------------------------- // Enqueue new entries //------------------------------------------------------------- //------------------------------------------------------------- // This is a newer store than existing loads, so clear the bit in all the store dependency masks for (i <- 0 until numLdqEntries) { when (clear_store) { ldq(i).bits.st_dep_mask := ldq(i).bits.st_dep_mask & ~(1.U << stq_head) } } // Decode stage var ld_enq_idx = ldq_tail var st_enq_idx = stq_tail val stq_nonempty = (0 until numStqEntries).map{ i => stq(i).valid }.reduce(_||_) =/= 0.U var ldq_full = Bool() var stq_full = Bool() for (w <- 0 until coreWidth) { ldq_full = WrapInc(ld_enq_idx, numLdqEntries) === ldq_head io.core.ldq_full(w) := ldq_full io.core.dis_ldq_idx(w) := ld_enq_idx stq_full = WrapInc(st_enq_idx, numStqEntries) === stq_head io.core.stq_full(w) := stq_full io.core.dis_stq_idx(w) := st_enq_idx val dis_ld_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_ldq && !io.core.dis_uops(w).bits.exception val dis_st_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_stq && !io.core.dis_uops(w).bits.exception when (dis_ld_val) { ldq(ld_enq_idx).valid := true.B ldq(ld_enq_idx).bits.uop := io.core.dis_uops(w).bits ldq(ld_enq_idx).bits.youngest_stq_idx := st_enq_idx ldq(ld_enq_idx).bits.st_dep_mask := next_live_store_mask ldq(ld_enq_idx).bits.addr.valid := false.B ldq(ld_enq_idx).bits.executed := false.B ldq(ld_enq_idx).bits.succeeded := false.B ldq(ld_enq_idx).bits.order_fail := false.B ldq(ld_enq_idx).bits.observed := false.B ldq(ld_enq_idx).bits.forward_std_val := false.B assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, "[lsu] mismatch enq load tag.") assert (!ldq(ld_enq_idx).valid, "[lsu] Enqueuing uop is overwriting ldq entries") } .elsewhen (dis_st_val) { stq(st_enq_idx).valid := true.B stq(st_enq_idx).bits.uop := io.core.dis_uops(w).bits stq(st_enq_idx).bits.addr.valid := false.B stq(st_enq_idx).bits.data.valid := false.B stq(st_enq_idx).bits.committed := false.B stq(st_enq_idx).bits.succeeded := false.B assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, "[lsu] mismatch enq store tag.") assert (!stq(st_enq_idx).valid, "[lsu] Enqueuing uop is overwriting stq entries") } ld_enq_idx = Mux(dis_ld_val, WrapInc(ld_enq_idx, numLdqEntries), ld_enq_idx) next_live_store_mask = Mux(dis_st_val, next_live_store_mask | (1.U << st_enq_idx), next_live_store_mask) st_enq_idx = Mux(dis_st_val, WrapInc(st_enq_idx, numStqEntries), st_enq_idx) assert(!(dis_ld_val && dis_st_val), "A UOP is trying to go into both the LDQ and the STQ") } ldq_tail := ld_enq_idx stq_tail := st_enq_idx io.dmem.force_order := io.core.fence_dmem io.core.fencei_rdy := !stq_nonempty && io.dmem.ordered //------------------------------------------------------------- //------------------------------------------------------------- // Execute stage (access TLB, send requests to Memory) //------------------------------------------------------------- //------------------------------------------------------------- // We can only report 1 exception per cycle. // Just be sure to report the youngest one val mem_xcpt_valid = Wire(Bool()) val mem_xcpt_cause = Wire(UInt()) val mem_xcpt_uop = Wire(new MicroOp) val mem_xcpt_vaddr = Wire(UInt()) //--------------------------------------- // Can-fire logic and wakeup/retry select // // First we determine what operations are waiting to execute. // These are the "can_fire"/"will_fire" signals val will_fire_load_incoming = Wire(Vec(memWidth, Bool())) val will_fire_stad_incoming = Wire(Vec(memWidth, Bool())) val will_fire_sta_incoming = Wire(Vec(memWidth, Bool())) val will_fire_std_incoming = Wire(Vec(memWidth, Bool())) val will_fire_sfence = Wire(Vec(memWidth, Bool())) val will_fire_hella_incoming = Wire(Vec(memWidth, Bool())) val will_fire_hella_wakeup = Wire(Vec(memWidth, Bool())) val will_fire_release = Wire(Vec(memWidth, Bool())) val will_fire_load_retry = Wire(Vec(memWidth, Bool())) val will_fire_sta_retry = Wire(Vec(memWidth, Bool())) val will_fire_store_commit = Wire(Vec(memWidth, Bool())) val will_fire_load_wakeup = Wire(Vec(memWidth, Bool())) val exe_req = WireInit(VecInit(io.core.exe.map(_.req))) // Sfence goes through all pipes for (i <- 0 until memWidth) { when (io.core.exe(i).req.bits.sfence.valid) { exe_req := VecInit(Seq.fill(memWidth) { io.core.exe(i).req }) } } // ------------------------------- // Assorted signals for scheduling // Don't wakeup a load if we just sent it last cycle or two cycles ago // The block_load_mask may be wrong, but the executing_load mask must be accurate val block_load_mask = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) val p1_block_load_mask = RegNext(block_load_mask) val p2_block_load_mask = RegNext(p1_block_load_mask) // Prioritize emptying the store queue when it is almost full val stq_almost_full = RegNext(WrapInc(WrapInc(st_enq_idx, numStqEntries), numStqEntries) === stq_head || WrapInc(st_enq_idx, numStqEntries) === stq_head) // The store at the commit head needs the DCache to appear ordered // Delay firing load wakeups and retries now val store_needs_order = WireInit(false.B) val ldq_incoming_idx = widthMap(i => exe_req(i).bits.uop.ldq_idx) val ldq_incoming_e = widthMap(i => ldq(ldq_incoming_idx(i))) val stq_incoming_idx = widthMap(i => exe_req(i).bits.uop.stq_idx) val stq_incoming_e = widthMap(i => stq(stq_incoming_idx(i))) val ldq_retry_idx = RegNext(AgePriorityEncoder((0 until numLdqEntries).map(i => { val e = ldq(i).bits val block = block_load_mask(i) || p1_block_load_mask(i) e.addr.valid && e.addr_is_virtual && !block }), ldq_head)) val ldq_retry_e = ldq(ldq_retry_idx) val stq_retry_idx = RegNext(AgePriorityEncoder((0 until numStqEntries).map(i => { val e = stq(i).bits e.addr.valid && e.addr_is_virtual }), stq_commit_head)) val stq_retry_e = stq(stq_retry_idx) val stq_commit_e = stq(stq_execute_head) val ldq_wakeup_idx = RegNext(AgePriorityEncoder((0 until numLdqEntries).map(i=> { val e = ldq(i).bits val block = block_load_mask(i) || p1_block_load_mask(i) e.addr.valid && !e.executed && !e.succeeded && !e.addr_is_virtual && !block }), ldq_head)) val ldq_wakeup_e = ldq(ldq_wakeup_idx) // ----------------------- // Determine what can fire // Can we fire a incoming load val can_fire_load_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_load) // Can we fire an incoming store addrgen + store datagen val can_fire_stad_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_sta && exe_req(w).bits.uop.ctrl.is_std) // Can we fire an incoming store addrgen val can_fire_sta_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_sta && !exe_req(w).bits.uop.ctrl.is_std) // Can we fire an incoming store datagen val can_fire_std_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_std && !exe_req(w).bits.uop.ctrl.is_sta) // Can we fire an incoming sfence val can_fire_sfence = widthMap(w => exe_req(w).valid && exe_req(w).bits.sfence.valid) // Can we fire a request from dcache to release a line // This needs to go through LDQ search to mark loads as dangerous val can_fire_release = widthMap(w => (w == memWidth-1).B && io.dmem.release.valid) io.dmem.release.ready := will_fire_release.reduce(_||_) // Can we retry a load that missed in the TLB val can_fire_load_retry = widthMap(w => ( ldq_retry_e.valid && ldq_retry_e.bits.addr.valid && ldq_retry_e.bits.addr_is_virtual && !p1_block_load_mask(ldq_retry_idx) && !p2_block_load_mask(ldq_retry_idx) && RegNext(dtlb.io.miss_rdy) && !store_needs_order && (w == memWidth-1).B && // TODO: Is this best scheduling? !ldq_retry_e.bits.order_fail)) // Can we retry a store addrgen that missed in the TLB // - Weird edge case when sta_retry and std_incoming for same entry in same cycle. Delay this val can_fire_sta_retry = widthMap(w => ( stq_retry_e.valid && stq_retry_e.bits.addr.valid && stq_retry_e.bits.addr_is_virtual && (w == memWidth-1).B && RegNext(dtlb.io.miss_rdy) && !(widthMap(i => (i != w).B && can_fire_std_incoming(i) && stq_incoming_idx(i) === stq_retry_idx).reduce(_||_)) )) // Can we commit a store val can_fire_store_commit = widthMap(w => ( stq_commit_e.valid && !stq_commit_e.bits.uop.is_fence && !mem_xcpt_valid && !stq_commit_e.bits.uop.exception && (w == 0).B && (stq_commit_e.bits.committed || ( stq_commit_e.bits.uop.is_amo && stq_commit_e.bits.addr.valid && !stq_commit_e.bits.addr_is_virtual && stq_commit_e.bits.data.valid)))) // Can we wakeup a load that was nack'd val block_load_wakeup = WireInit(false.B) val can_fire_load_wakeup = widthMap(w => ( ldq_wakeup_e.valid && ldq_wakeup_e.bits.addr.valid && !ldq_wakeup_e.bits.succeeded && !ldq_wakeup_e.bits.addr_is_virtual && !ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.order_fail && !p1_block_load_mask(ldq_wakeup_idx) && !p2_block_load_mask(ldq_wakeup_idx) && !store_needs_order && !block_load_wakeup && (w == memWidth-1).B && (!ldq_wakeup_e.bits.addr_is_uncacheable || (io.core.commit_load_at_rob_head && ldq_head === ldq_wakeup_idx && ldq_wakeup_e.bits.st_dep_mask.asUInt === 0.U)))) // Can we fire an incoming hellacache request val can_fire_hella_incoming = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim ocntroller // Can we fire a hellacache request that the dcache nack'd val can_fire_hella_wakeup = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim controller //--------------------------------------------------------- // Controller logic. Arbitrate which request actually fires val exe_tlb_valid = Wire(Vec(memWidth, Bool())) for (w <- 0 until memWidth) { var tlb_avail = true.B var dc_avail = true.B var lcam_avail = true.B var rob_avail = true.B def lsu_sched(can_fire: Bool, uses_tlb:Boolean, uses_dc:Boolean, uses_lcam: Boolean, uses_rob:Boolean): Bool = { val will_fire = can_fire && !(uses_tlb.B && !tlb_avail) && !(uses_lcam.B && !lcam_avail) && !(uses_dc.B && !dc_avail) && !(uses_rob.B && !rob_avail) tlb_avail = tlb_avail && !(will_fire && uses_tlb.B) lcam_avail = lcam_avail && !(will_fire && uses_lcam.B) dc_avail = dc_avail && !(will_fire && uses_dc.B) rob_avail = rob_avail && !(will_fire && uses_rob.B) dontTouch(will_fire) // dontTouch these so we can inspect the will_fire signals will_fire } // The order of these statements is the priority // Some restrictions // - Incoming ops must get precedence, can't backpresure memaddrgen // - Incoming hellacache ops must get precedence over retrying ops (PTW must get precedence over retrying translation) // Notes on performance // - Prioritize releases, this speeds up cache line writebacks and refills // - Store commits are lowest priority, since they don't "block" younger instructions unless stq fills up will_fire_load_incoming (w) := lsu_sched(can_fire_load_incoming (w) , true , true , true , false) // TLB , DC , LCAM will_fire_stad_incoming (w) := lsu_sched(can_fire_stad_incoming (w) , true , false, true , true) // TLB , , LCAM , ROB will_fire_sta_incoming (w) := lsu_sched(can_fire_sta_incoming (w) , true , false, true , true) // TLB , , LCAM , ROB will_fire_std_incoming (w) := lsu_sched(can_fire_std_incoming (w) , false, false, false, true) // , ROB will_fire_sfence (w) := lsu_sched(can_fire_sfence (w) , true , false, false, true) // TLB , , , ROB will_fire_release (w) := lsu_sched(can_fire_release (w) , false, false, true , false) // LCAM will_fire_hella_incoming(w) := lsu_sched(can_fire_hella_incoming(w) , true , true , false, false) // TLB , DC will_fire_hella_wakeup (w) := lsu_sched(can_fire_hella_wakeup (w) , false, true , false, false) // , DC will_fire_load_retry (w) := lsu_sched(can_fire_load_retry (w) , true , true , true , false) // TLB , DC , LCAM will_fire_sta_retry (w) := lsu_sched(can_fire_sta_retry (w) , true , false, true , true) // TLB , , LCAM , ROB // TODO: This should be higher priority will_fire_load_wakeup (w) := lsu_sched(can_fire_load_wakeup (w) , false, true , true , false) // , DC , LCAM1 will_fire_store_commit (w) := lsu_sched(can_fire_store_commit (w) , false, true , false, false) // , DC assert(!(exe_req(w).valid && !(will_fire_load_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_incoming(w) || will_fire_std_incoming(w) || will_fire_sfence(w)))) when (will_fire_load_wakeup(w)) { block_load_mask(ldq_wakeup_idx) := true.B } .elsewhen (will_fire_load_incoming(w)) { block_load_mask(exe_req(w).bits.uop.ldq_idx) := true.B } .elsewhen (will_fire_load_retry(w)) { block_load_mask(ldq_retry_idx) := true.B } exe_tlb_valid(w) := !tlb_avail } assert((memWidth == 1).B || (!(will_fire_sfence.reduce(_||_) && !will_fire_sfence.reduce(_&&_)) && !will_fire_hella_incoming.reduce(_&&_) && !will_fire_hella_wakeup.reduce(_&&_) && !will_fire_load_retry.reduce(_&&_) && !will_fire_sta_retry.reduce(_&&_) && !will_fire_store_commit.reduce(_&&_) && !will_fire_load_wakeup.reduce(_&&_)), "Some operations is proceeding down multiple pipes") require(memWidth <= 2) //-------------------------------------------- // TLB Access assert(!(hella_state =/= h_ready && hella_req.cmd === rocket.M_SFENCE), "SFENCE through hella interface not supported") val exe_tlb_uop = widthMap(w => Mux(will_fire_load_incoming (w) || will_fire_stad_incoming (w) || will_fire_sta_incoming (w) || will_fire_sfence (w) , exe_req(w).bits.uop, Mux(will_fire_load_retry (w) , ldq_retry_e.bits.uop, Mux(will_fire_sta_retry (w) , stq_retry_e.bits.uop, Mux(will_fire_hella_incoming(w) , NullMicroOp, NullMicroOp))))) val exe_tlb_vaddr = widthMap(w => Mux(will_fire_load_incoming (w) || will_fire_stad_incoming (w) || will_fire_sta_incoming (w) , exe_req(w).bits.addr, Mux(will_fire_sfence (w) , exe_req(w).bits.sfence.bits.addr, Mux(will_fire_load_retry (w) , ldq_retry_e.bits.addr.bits, Mux(will_fire_sta_retry (w) , stq_retry_e.bits.addr.bits, Mux(will_fire_hella_incoming(w) , hella_req.addr, 0.U)))))) val exe_sfence = WireInit((0.U).asTypeOf(Valid(new rocket.SFenceReq))) for (w <- 0 until memWidth) { when (will_fire_sfence(w)) { exe_sfence := exe_req(w).bits.sfence } } val exe_size = widthMap(w => Mux(will_fire_load_incoming (w) || will_fire_stad_incoming (w) || will_fire_sta_incoming (w) || will_fire_sfence (w) || will_fire_load_retry (w) || will_fire_sta_retry (w) , exe_tlb_uop(w).mem_size, Mux(will_fire_hella_incoming(w) , hella_req.size, 0.U))) val exe_cmd = widthMap(w => Mux(will_fire_load_incoming (w) || will_fire_stad_incoming (w) || will_fire_sta_incoming (w) || will_fire_sfence (w) || will_fire_load_retry (w) || will_fire_sta_retry (w) , exe_tlb_uop(w).mem_cmd, Mux(will_fire_hella_incoming(w) , hella_req.cmd, 0.U))) val exe_passthr= widthMap(w => Mux(will_fire_hella_incoming(w) , hella_req.phys, false.B)) val exe_kill = widthMap(w => Mux(will_fire_hella_incoming(w) , io.hellacache.s1_kill, false.B)) for (w <- 0 until memWidth) { dtlb.io.req(w).valid := exe_tlb_valid(w) dtlb.io.req(w).bits.vaddr := exe_tlb_vaddr(w) dtlb.io.req(w).bits.size := exe_size(w) dtlb.io.req(w).bits.cmd := exe_cmd(w) dtlb.io.req(w).bits.passthrough := exe_passthr(w) dtlb.io.req(w).bits.v := io.ptw.status.v dtlb.io.req(w).bits.prv := io.ptw.status.prv } dtlb.io.kill := exe_kill.reduce(_||_) dtlb.io.sfence := exe_sfence // exceptions val ma_ld = widthMap(w => will_fire_load_incoming(w) && exe_req(w).bits.mxcpt.valid) // We get ma_ld in memaddrcalc val ma_st = widthMap(w => (will_fire_sta_incoming(w) || will_fire_stad_incoming(w)) && exe_req(w).bits.mxcpt.valid) // We get ma_ld in memaddrcalc val pf_ld = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).pf.ld && exe_tlb_uop(w).uses_ldq) val pf_st = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).pf.st && exe_tlb_uop(w).uses_stq) val ae_ld = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).ae.ld && exe_tlb_uop(w).uses_ldq) val ae_st = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).ae.st && exe_tlb_uop(w).uses_stq) // TODO check for xcpt_if and verify that never happens on non-speculative instructions. val mem_xcpt_valids = RegNext(widthMap(w => (pf_ld(w) || pf_st(w) || ae_ld(w) || ae_st(w) || ma_ld(w) || ma_st(w)) && !io.core.exception && !IsKilledByBranch(io.core.brupdate, exe_tlb_uop(w)))) val mem_xcpt_uops = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, exe_tlb_uop(w)))) val mem_xcpt_causes = RegNext(widthMap(w => Mux(ma_ld(w), rocket.Causes.misaligned_load.U, Mux(ma_st(w), rocket.Causes.misaligned_store.U, Mux(pf_ld(w), rocket.Causes.load_page_fault.U, Mux(pf_st(w), rocket.Causes.store_page_fault.U, Mux(ae_ld(w), rocket.Causes.load_access.U, rocket.Causes.store_access.U))))))) val mem_xcpt_vaddrs = RegNext(exe_tlb_vaddr) for (w <- 0 until memWidth) { assert (!(dtlb.io.req(w).valid && exe_tlb_uop(w).is_fence), "Fence is pretending to talk to the TLB") assert (!((will_fire_load_incoming(w) || will_fire_sta_incoming(w) || will_fire_stad_incoming(w)) && exe_req(w).bits.mxcpt.valid && dtlb.io.req(w).valid && !(exe_tlb_uop(w).ctrl.is_load || exe_tlb_uop(w).ctrl.is_sta)), "A uop that's not a load or store-address is throwing a memory exception.") } mem_xcpt_valid := mem_xcpt_valids.reduce(_||_) mem_xcpt_cause := mem_xcpt_causes(0) mem_xcpt_uop := mem_xcpt_uops(0) mem_xcpt_vaddr := mem_xcpt_vaddrs(0) var xcpt_found = mem_xcpt_valids(0) var oldest_xcpt_rob_idx = mem_xcpt_uops(0).rob_idx for (w <- 1 until memWidth) { val is_older = WireInit(false.B) when (mem_xcpt_valids(w) && (IsOlder(mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx, io.core.rob_head_idx) || !xcpt_found)) { is_older := true.B mem_xcpt_cause := mem_xcpt_causes(w) mem_xcpt_uop := mem_xcpt_uops(w) mem_xcpt_vaddr := mem_xcpt_vaddrs(w) } xcpt_found = xcpt_found || mem_xcpt_valids(w) oldest_xcpt_rob_idx = Mux(is_older, mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx) } val exe_tlb_miss = widthMap(w => dtlb.io.req(w).valid && (dtlb.io.resp(w).miss || !dtlb.io.req(w).ready)) val exe_tlb_paddr = widthMap(w => Cat(dtlb.io.resp(w).paddr(paddrBits-1,corePgIdxBits), exe_tlb_vaddr(w)(corePgIdxBits-1,0))) val exe_tlb_uncacheable = widthMap(w => !(dtlb.io.resp(w).cacheable)) for (w <- 0 until memWidth) { assert (exe_tlb_paddr(w) === dtlb.io.resp(w).paddr || exe_req(w).bits.sfence.valid, "[lsu] paddrs should match.") when (mem_xcpt_valids(w)) { assert(RegNext(will_fire_load_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_incoming(w) || will_fire_load_retry(w) || will_fire_sta_retry(w))) // Technically only faulting AMOs need this assert(mem_xcpt_uops(w).uses_ldq ^ mem_xcpt_uops(w).uses_stq) when (mem_xcpt_uops(w).uses_ldq) { ldq(mem_xcpt_uops(w).ldq_idx).bits.uop.exception := true.B } .otherwise { stq(mem_xcpt_uops(w).stq_idx).bits.uop.exception := true.B } } } //------------------------------ // Issue Someting to Memory // // A memory op can come from many different places // The address either was freshly translated, or we are // reading a physical address from the LDQ,STQ, or the HellaCache adapter // defaults io.dmem.brupdate := io.core.brupdate io.dmem.exception := io.core.exception io.dmem.rob_head_idx := io.core.rob_head_idx io.dmem.rob_pnr_idx := io.core.rob_pnr_idx val dmem_req = Wire(Vec(memWidth, Valid(new BoomDCacheReq))) io.dmem.req.valid := dmem_req.map(_.valid).reduce(_||_) io.dmem.req.bits := dmem_req val dmem_req_fire = widthMap(w => dmem_req(w).valid && io.dmem.req.fire) val s0_executing_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) for (w <- 0 until memWidth) { dmem_req(w).valid := false.B dmem_req(w).bits.uop := NullMicroOp dmem_req(w).bits.addr := 0.U dmem_req(w).bits.data := 0.U dmem_req(w).bits.is_hella := false.B io.dmem.s1_kill(w) := false.B when (will_fire_load_incoming(w)) { dmem_req(w).valid := !exe_tlb_miss(w) && !exe_tlb_uncacheable(w) dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.uop := exe_tlb_uop(w) s0_executing_loads(ldq_incoming_idx(w)) := dmem_req_fire(w) assert(!ldq_incoming_e(w).bits.executed) } .elsewhen (will_fire_load_retry(w)) { dmem_req(w).valid := !exe_tlb_miss(w) && !exe_tlb_uncacheable(w) dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.uop := exe_tlb_uop(w) s0_executing_loads(ldq_retry_idx) := dmem_req_fire(w) assert(!ldq_retry_e.bits.executed) } .elsewhen (will_fire_store_commit(w)) { dmem_req(w).valid := true.B dmem_req(w).bits.addr := stq_commit_e.bits.addr.bits dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( stq_commit_e.bits.uop.mem_size, 0.U, stq_commit_e.bits.data.bits, coreDataBytes)).data dmem_req(w).bits.uop := stq_commit_e.bits.uop stq_execute_head := Mux(dmem_req_fire(w), WrapInc(stq_execute_head, numStqEntries), stq_execute_head) stq(stq_execute_head).bits.succeeded := false.B } .elsewhen (will_fire_load_wakeup(w)) { dmem_req(w).valid := true.B dmem_req(w).bits.addr := ldq_wakeup_e.bits.addr.bits dmem_req(w).bits.uop := ldq_wakeup_e.bits.uop s0_executing_loads(ldq_wakeup_idx) := dmem_req_fire(w) assert(!ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.addr_is_virtual) } .elsewhen (will_fire_hella_incoming(w)) { assert(hella_state === h_s1) dmem_req(w).valid := !io.hellacache.s1_kill && (!exe_tlb_miss(w) || hella_req.phys) dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( hella_req.size, 0.U, io.hellacache.s1_data.data, coreDataBytes)).data dmem_req(w).bits.uop.mem_cmd := hella_req.cmd dmem_req(w).bits.uop.mem_size := hella_req.size dmem_req(w).bits.uop.mem_signed := hella_req.signed dmem_req(w).bits.is_hella := true.B hella_paddr := exe_tlb_paddr(w) } .elsewhen (will_fire_hella_wakeup(w)) { assert(hella_state === h_replay) dmem_req(w).valid := true.B dmem_req(w).bits.addr := hella_paddr dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( hella_req.size, 0.U, hella_data.data, coreDataBytes)).data dmem_req(w).bits.uop.mem_cmd := hella_req.cmd dmem_req(w).bits.uop.mem_size := hella_req.size dmem_req(w).bits.uop.mem_signed := hella_req.signed dmem_req(w).bits.is_hella := true.B } //------------------------------------------------------------- // Write Addr into the LAQ/SAQ when (will_fire_load_incoming(w) || will_fire_load_retry(w)) { val ldq_idx = Mux(will_fire_load_incoming(w), ldq_incoming_idx(w), ldq_retry_idx) ldq(ldq_idx).bits.addr.valid := true.B ldq(ldq_idx).bits.addr.bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w)) ldq(ldq_idx).bits.uop.pdst := exe_tlb_uop(w).pdst ldq(ldq_idx).bits.addr_is_virtual := exe_tlb_miss(w) ldq(ldq_idx).bits.addr_is_uncacheable := exe_tlb_uncacheable(w) && !exe_tlb_miss(w) assert(!(will_fire_load_incoming(w) && ldq_incoming_e(w).bits.addr.valid), "[lsu] Incoming load is overwriting a valid address") } when (will_fire_sta_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_retry(w)) { val stq_idx = Mux(will_fire_sta_incoming(w) || will_fire_stad_incoming(w), stq_incoming_idx(w), stq_retry_idx) stq(stq_idx).bits.addr.valid := !pf_st(w) // Prevent AMOs from executing! stq(stq_idx).bits.addr.bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w)) stq(stq_idx).bits.uop.pdst := exe_tlb_uop(w).pdst // Needed for AMOs stq(stq_idx).bits.addr_is_virtual := exe_tlb_miss(w) assert(!(will_fire_sta_incoming(w) && stq_incoming_e(w).bits.addr.valid), "[lsu] Incoming store is overwriting a valid address") } //------------------------------------------------------------- // Write data into the STQ if (w == 0) io.core.fp_stdata.ready := !will_fire_std_incoming(w) && !will_fire_stad_incoming(w) val fp_stdata_fire = io.core.fp_stdata.fire && (w == 0).B when (will_fire_std_incoming(w) || will_fire_stad_incoming(w) || fp_stdata_fire) { val sidx = Mux(will_fire_std_incoming(w) || will_fire_stad_incoming(w), stq_incoming_idx(w), io.core.fp_stdata.bits.uop.stq_idx) stq(sidx).bits.data.valid := true.B stq(sidx).bits.data.bits := Mux(will_fire_std_incoming(w) || will_fire_stad_incoming(w), exe_req(w).bits.data, io.core.fp_stdata.bits.data) assert(!(stq(sidx).bits.data.valid), "[lsu] Incoming store is overwriting a valid data entry") } } val will_fire_stdf_incoming = io.core.fp_stdata.fire require (xLen >= fLen) // for correct SDQ size //------------------------------------------------------------- //------------------------------------------------------------- // Cache Access Cycle (Mem) //------------------------------------------------------------- //------------------------------------------------------------- // Note the DCache may not have accepted our request val exe_req_killed = widthMap(w => IsKilledByBranch(io.core.brupdate, exe_req(w).bits.uop)) val stdf_killed = IsKilledByBranch(io.core.brupdate, io.core.fp_stdata.bits.uop) val fired_load_incoming = widthMap(w => RegNext(will_fire_load_incoming(w) && !exe_req_killed(w))) val fired_stad_incoming = widthMap(w => RegNext(will_fire_stad_incoming(w) && !exe_req_killed(w))) val fired_sta_incoming = widthMap(w => RegNext(will_fire_sta_incoming (w) && !exe_req_killed(w))) val fired_std_incoming = widthMap(w => RegNext(will_fire_std_incoming (w) && !exe_req_killed(w))) val fired_stdf_incoming = RegNext(will_fire_stdf_incoming && !stdf_killed) val fired_sfence = RegNext(will_fire_sfence) val fired_release = RegNext(will_fire_release) val fired_load_retry = widthMap(w => RegNext(will_fire_load_retry (w) && !IsKilledByBranch(io.core.brupdate, ldq_retry_e.bits.uop))) val fired_sta_retry = widthMap(w => RegNext(will_fire_sta_retry (w) && !IsKilledByBranch(io.core.brupdate, stq_retry_e.bits.uop))) val fired_store_commit = RegNext(will_fire_store_commit) val fired_load_wakeup = widthMap(w => RegNext(will_fire_load_wakeup (w) && !IsKilledByBranch(io.core.brupdate, ldq_wakeup_e.bits.uop))) val fired_hella_incoming = RegNext(will_fire_hella_incoming) val fired_hella_wakeup = RegNext(will_fire_hella_wakeup) val mem_incoming_uop = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, exe_req(w).bits.uop))) val mem_ldq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, ldq_incoming_e(w)))) val mem_stq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, stq_incoming_e(w)))) val mem_ldq_wakeup_e = RegNext(UpdateBrMask(io.core.brupdate, ldq_wakeup_e)) val mem_ldq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, ldq_retry_e)) val mem_stq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, stq_retry_e)) val mem_ldq_e = widthMap(w => Mux(fired_load_incoming(w), mem_ldq_incoming_e(w), Mux(fired_load_retry (w), mem_ldq_retry_e, Mux(fired_load_wakeup (w), mem_ldq_wakeup_e, (0.U).asTypeOf(Valid(new LDQEntry)))))) val mem_stq_e = widthMap(w => Mux(fired_stad_incoming(w) || fired_sta_incoming (w), mem_stq_incoming_e(w), Mux(fired_sta_retry (w), mem_stq_retry_e, (0.U).asTypeOf(Valid(new STQEntry))))) val mem_stdf_uop = RegNext(UpdateBrMask(io.core.brupdate, io.core.fp_stdata.bits.uop)) val mem_tlb_miss = RegNext(exe_tlb_miss) val mem_tlb_uncacheable = RegNext(exe_tlb_uncacheable) val mem_paddr = RegNext(widthMap(w => dmem_req(w).bits.addr)) // Task 1: Clr ROB busy bit val clr_bsy_valid = RegInit(widthMap(w => false.B)) val clr_bsy_rob_idx = Reg(Vec(memWidth, UInt(robAddrSz.W))) val clr_bsy_brmask = Reg(Vec(memWidth, UInt(maxBrCount.W))) for (w <- 0 until memWidth) { clr_bsy_valid (w) := false.B clr_bsy_rob_idx (w) := 0.U clr_bsy_brmask (w) := 0.U when (fired_stad_incoming(w)) { clr_bsy_valid (w) := mem_stq_incoming_e(w).valid && !mem_tlb_miss(w) && !mem_stq_incoming_e(w).bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) } .elsewhen (fired_sta_incoming(w)) { clr_bsy_valid (w) := mem_stq_incoming_e(w).valid && mem_stq_incoming_e(w).bits.data.valid && !mem_tlb_miss(w) && !mem_stq_incoming_e(w).bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) } .elsewhen (fired_std_incoming(w)) { clr_bsy_valid (w) := mem_stq_incoming_e(w).valid && mem_stq_incoming_e(w).bits.addr.valid && !mem_stq_incoming_e(w).bits.addr_is_virtual && !mem_stq_incoming_e(w).bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) } .elsewhen (fired_sfence(w)) { clr_bsy_valid (w) := (w == 0).B // SFence proceeds down all paths, only allow one to clr the rob clr_bsy_rob_idx (w) := mem_incoming_uop(w).rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_incoming_uop(w)) } .elsewhen (fired_sta_retry(w)) { clr_bsy_valid (w) := mem_stq_retry_e.valid && mem_stq_retry_e.bits.data.valid && !mem_tlb_miss(w) && !mem_stq_retry_e.bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stq_retry_e.bits.uop) clr_bsy_rob_idx (w) := mem_stq_retry_e.bits.uop.rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_retry_e.bits.uop) } io.core.clr_bsy(w).valid := clr_bsy_valid(w) && !IsKilledByBranch(io.core.brupdate, clr_bsy_brmask(w)) && !io.core.exception && !RegNext(io.core.exception) && !RegNext(RegNext(io.core.exception)) io.core.clr_bsy(w).bits := clr_bsy_rob_idx(w) } val stdf_clr_bsy_valid = RegInit(false.B) val stdf_clr_bsy_rob_idx = Reg(UInt(robAddrSz.W)) val stdf_clr_bsy_brmask = Reg(UInt(maxBrCount.W)) stdf_clr_bsy_valid := false.B stdf_clr_bsy_rob_idx := 0.U stdf_clr_bsy_brmask := 0.U when (fired_stdf_incoming) { val s_idx = mem_stdf_uop.stq_idx stdf_clr_bsy_valid := stq(s_idx).valid && stq(s_idx).bits.addr.valid && !stq(s_idx).bits.addr_is_virtual && !stq(s_idx).bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stdf_uop) stdf_clr_bsy_rob_idx := mem_stdf_uop.rob_idx stdf_clr_bsy_brmask := GetNewBrMask(io.core.brupdate, mem_stdf_uop) } io.core.clr_bsy(memWidth).valid := stdf_clr_bsy_valid && !IsKilledByBranch(io.core.brupdate, stdf_clr_bsy_brmask) && !io.core.exception && !RegNext(io.core.exception) && !RegNext(RegNext(io.core.exception)) io.core.clr_bsy(memWidth).bits := stdf_clr_bsy_rob_idx // Task 2: Do LD-LD. ST-LD searches for ordering failures // Do LD-ST search for forwarding opportunities // We have the opportunity to kill a request we sent last cycle. Use it wisely! // We translated a store last cycle val do_st_search = widthMap(w => (fired_stad_incoming(w) || fired_sta_incoming(w) || fired_sta_retry(w)) && !mem_tlb_miss(w)) // We translated a load last cycle val do_ld_search = widthMap(w => ((fired_load_incoming(w) || fired_load_retry(w)) && !mem_tlb_miss(w)) || fired_load_wakeup(w)) // We are making a local line visible to other harts val do_release_search = widthMap(w => fired_release(w)) // Store addrs don't go to memory yet, get it from the TLB response // Load wakeups don't go through TLB, get it through memory // Load incoming and load retries go through both val lcam_addr = widthMap(w => Mux(fired_stad_incoming(w) || fired_sta_incoming(w) || fired_sta_retry(w), RegNext(exe_tlb_paddr(w)), Mux(fired_release(w), RegNext(io.dmem.release.bits.address), mem_paddr(w)))) val lcam_uop = widthMap(w => Mux(do_st_search(w), mem_stq_e(w).bits.uop, Mux(do_ld_search(w), mem_ldq_e(w).bits.uop, NullMicroOp))) val lcam_mask = widthMap(w => GenByteMask(lcam_addr(w), lcam_uop(w).mem_size)) val lcam_st_dep_mask = widthMap(w => mem_ldq_e(w).bits.st_dep_mask) val lcam_is_release = widthMap(w => fired_release(w)) val lcam_ldq_idx = widthMap(w => Mux(fired_load_incoming(w), mem_incoming_uop(w).ldq_idx, Mux(fired_load_wakeup (w), RegNext(ldq_wakeup_idx), Mux(fired_load_retry (w), RegNext(ldq_retry_idx), 0.U)))) val lcam_stq_idx = widthMap(w => Mux(fired_stad_incoming(w) || fired_sta_incoming (w), mem_incoming_uop(w).stq_idx, Mux(fired_sta_retry (w), RegNext(stq_retry_idx), 0.U))) val can_forward = WireInit(widthMap(w => Mux(fired_load_incoming(w) || fired_load_retry(w), !mem_tlb_uncacheable(w), !ldq(lcam_ldq_idx(w)).bits.addr_is_uncacheable))) // Mask of stores which we conflict on address with val ldst_addr_matches = WireInit(widthMap(w => VecInit((0 until numStqEntries).map(x=>false.B)))) // Mask of stores which we can forward from val ldst_forward_matches = WireInit(widthMap(w => VecInit((0 until numStqEntries).map(x=>false.B)))) val failed_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) // Loads which we will report as failures (throws a mini-exception) val nacking_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) // Loads which are being nacked by dcache in the next stage val s1_executing_loads = RegNext(s0_executing_loads) val s1_set_execute = WireInit(s1_executing_loads) val mem_forward_valid = Wire(Vec(memWidth, Bool())) val mem_forward_ldq_idx = lcam_ldq_idx val mem_forward_ld_addr = lcam_addr val mem_forward_stq_idx = Wire(Vec(memWidth, UInt(log2Ceil(numStqEntries).W))) val wb_forward_valid = RegNext(mem_forward_valid) val wb_forward_ldq_idx = RegNext(mem_forward_ldq_idx) val wb_forward_ld_addr = RegNext(mem_forward_ld_addr) val wb_forward_stq_idx = RegNext(mem_forward_stq_idx) for (i <- 0 until numLdqEntries) { val l_valid = ldq(i).valid val l_bits = ldq(i).bits val l_addr = ldq(i).bits.addr.bits val l_mask = GenByteMask(l_addr, l_bits.uop.mem_size) val l_forwarders = widthMap(w => wb_forward_valid(w) && wb_forward_ldq_idx(w) === i.U) val l_is_forwarding = l_forwarders.reduce(_||_) val l_forward_stq_idx = Mux(l_is_forwarding, Mux1H(l_forwarders, wb_forward_stq_idx), l_bits.forward_stq_idx) val block_addr_matches = widthMap(w => lcam_addr(w) >> blockOffBits === l_addr >> blockOffBits) val dword_addr_matches = widthMap(w => block_addr_matches(w) && lcam_addr(w)(blockOffBits-1,3) === l_addr(blockOffBits-1,3)) val mask_match = widthMap(w => (l_mask & lcam_mask(w)) === l_mask) val mask_overlap = widthMap(w => (l_mask & lcam_mask(w)).orR) // Searcher is a store for (w <- 0 until memWidth) { when (do_release_search(w) && l_valid && l_bits.addr.valid && block_addr_matches(w)) { // This load has been observed, so if a younger load to the same address has not // executed yet, this load must be squashed ldq(i).bits.observed := true.B } .elsewhen (do_st_search(w) && l_valid && l_bits.addr.valid && (l_bits.executed || l_bits.succeeded || l_is_forwarding) && !l_bits.addr_is_virtual && l_bits.st_dep_mask(lcam_stq_idx(w)) && dword_addr_matches(w) && mask_overlap(w)) { val forwarded_is_older = IsOlder(l_forward_stq_idx, lcam_stq_idx(w), l_bits.youngest_stq_idx) // We are older than this load, which overlapped us. when (!l_bits.forward_std_val || // If the load wasn't forwarded, it definitely failed ((l_forward_stq_idx =/= lcam_stq_idx(w)) && forwarded_is_older)) { // If the load forwarded from us, we might be ok ldq(i).bits.order_fail := true.B failed_loads(i) := true.B } } .elsewhen (do_ld_search(w) && l_valid && l_bits.addr.valid && !l_bits.addr_is_virtual && dword_addr_matches(w) && mask_overlap(w)) { val searcher_is_older = IsOlder(lcam_ldq_idx(w), i.U, ldq_head) when (searcher_is_older) { when ((l_bits.executed || l_bits.succeeded || l_is_forwarding) && !s1_executing_loads(i) && // If the load is proceeding in parallel we don't need to kill it l_bits.observed) { // Its only a ordering failure if the cache line was observed between the younger load and us ldq(i).bits.order_fail := true.B failed_loads(i) := true.B } } .elsewhen (lcam_ldq_idx(w) =/= i.U) { // The load is older, and either it hasn't executed, it was nacked, or it is ignoring its response // we need to kill ourselves, and prevent forwarding val older_nacked = nacking_loads(i) || RegNext(nacking_loads(i)) when (!(l_bits.executed || l_bits.succeeded) || older_nacked) { s1_set_execute(lcam_ldq_idx(w)) := false.B io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w)) can_forward(w) := false.B } } } } } for (i <- 0 until numStqEntries) { val s_addr = stq(i).bits.addr.bits val s_uop = stq(i).bits.uop val dword_addr_matches = widthMap(w => ( stq(i).bits.addr.valid && !stq(i).bits.addr_is_virtual && (s_addr(corePAddrBits-1,3) === lcam_addr(w)(corePAddrBits-1,3)))) val write_mask = GenByteMask(s_addr, s_uop.mem_size) for (w <- 0 until memWidth) { when (do_ld_search(w) && stq(i).valid && lcam_st_dep_mask(w)(i)) { when (((lcam_mask(w) & write_mask) === lcam_mask(w)) && !s_uop.is_fence && !s_uop.is_amo && dword_addr_matches(w) && can_forward(w)) { ldst_addr_matches(w)(i) := true.B ldst_forward_matches(w)(i) := true.B io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w)) s1_set_execute(lcam_ldq_idx(w)) := false.B } .elsewhen (((lcam_mask(w) & write_mask) =/= 0.U) && dword_addr_matches(w)) { ldst_addr_matches(w)(i) := true.B io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w)) s1_set_execute(lcam_ldq_idx(w)) := false.B } .elsewhen (s_uop.is_fence || s_uop.is_amo) { ldst_addr_matches(w)(i) := true.B io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w)) s1_set_execute(lcam_ldq_idx(w)) := false.B } } } } // Set execute bit in LDQ for (i <- 0 until numLdqEntries) { when (s1_set_execute(i)) { ldq(i).bits.executed := true.B } } // Find the youngest store which the load is dependent on val forwarding_age_logic = Seq.fill(memWidth) { Module(new ForwardingAgeLogic(numStqEntries)) } for (w <- 0 until memWidth) { forwarding_age_logic(w).io.addr_matches := ldst_addr_matches(w).asUInt forwarding_age_logic(w).io.youngest_st_idx := lcam_uop(w).stq_idx } val forwarding_idx = widthMap(w => forwarding_age_logic(w).io.forwarding_idx) // Forward if st-ld forwarding is possible from the writemask and loadmask mem_forward_valid := widthMap(w => (ldst_forward_matches(w)(forwarding_idx(w)) && !IsKilledByBranch(io.core.brupdate, lcam_uop(w)) && !io.core.exception && !RegNext(io.core.exception))) mem_forward_stq_idx := forwarding_idx // Avoid deadlock with a 1-w LSU prioritizing load wakeups > store commits // On a 2W machine, load wakeups and store commits occupy separate pipelines, // so only add this logic for 1-w LSU if (memWidth == 1) { // Wakeups may repeatedly find a st->ld addr conflict and fail to forward, // repeated wakeups may block the store from ever committing // Disallow load wakeups 1 cycle after this happens to allow the stores to drain when (RegNext(ldst_addr_matches(0).reduce(_||_) && !mem_forward_valid(0))) { block_load_wakeup := true.B } // If stores remain blocked for 15 cycles, block load wakeups to get a store through val store_blocked_counter = Reg(UInt(4.W)) when (will_fire_store_commit(0) || !can_fire_store_commit(0)) { store_blocked_counter := 0.U } .elsewhen (can_fire_store_commit(0) && !will_fire_store_commit(0)) { store_blocked_counter := Mux(store_blocked_counter === 15.U, 15.U, store_blocked_counter + 1.U) } when (store_blocked_counter === 15.U) { block_load_wakeup := true.B } } // Task 3: Clr unsafe bit in ROB for succesful translations // Delay this a cycle to avoid going ahead of the exception broadcast // The unsafe bit is cleared on the first translation, so no need to fire for load wakeups for (w <- 0 until memWidth) { io.core.clr_unsafe(w).valid := RegNext((do_st_search(w) || do_ld_search(w)) && !fired_load_wakeup(w)) && false.B io.core.clr_unsafe(w).bits := RegNext(lcam_uop(w).rob_idx) } // detect which loads get marked as failures, but broadcast to the ROB the oldest failing load // TODO encapsulate this in an age-based priority-encoder // val l_idx = AgePriorityEncoder((Vec(Vec.tabulate(numLdqEntries)(i => failed_loads(i) && i.U >= laq_head) // ++ failed_loads)).asUInt) val temp_bits = (VecInit(VecInit.tabulate(numLdqEntries)(i => failed_loads(i) && i.U >= ldq_head) ++ failed_loads)).asUInt val l_idx = PriorityEncoder(temp_bits) // one exception port, but multiple causes! // - 1) the incoming store-address finds a faulting load (it is by definition younger) // - 2) the incoming load or store address is excepting. It must be older and thus takes precedent. val r_xcpt_valid = RegInit(false.B) val r_xcpt = Reg(new Exception) val ld_xcpt_valid = failed_loads.reduce(_|_) val ld_xcpt_uop = ldq(Mux(l_idx >= numLdqEntries.U, l_idx - numLdqEntries.U, l_idx)).bits.uop val use_mem_xcpt = (mem_xcpt_valid && IsOlder(mem_xcpt_uop.rob_idx, ld_xcpt_uop.rob_idx, io.core.rob_head_idx)) || !ld_xcpt_valid val xcpt_uop = Mux(use_mem_xcpt, mem_xcpt_uop, ld_xcpt_uop) r_xcpt_valid := (ld_xcpt_valid || mem_xcpt_valid) && !io.core.exception && !IsKilledByBranch(io.core.brupdate, xcpt_uop) r_xcpt.uop := xcpt_uop r_xcpt.uop.br_mask := GetNewBrMask(io.core.brupdate, xcpt_uop) r_xcpt.cause := Mux(use_mem_xcpt, mem_xcpt_cause, MINI_EXCEPTION_MEM_ORDERING) r_xcpt.badvaddr := mem_xcpt_vaddr // TODO is there another register we can use instead? io.core.lxcpt.valid := r_xcpt_valid && !io.core.exception && !IsKilledByBranch(io.core.brupdate, r_xcpt.uop) io.core.lxcpt.bits := r_xcpt // Task 4: Speculatively wakeup loads 1 cycle before they come back for (w <- 0 until memWidth) { io.core.spec_ld_wakeup(w).valid := enableFastLoadUse.B && fired_load_incoming(w) && !mem_incoming_uop(w).fp_val && mem_incoming_uop(w).pdst =/= 0.U io.core.spec_ld_wakeup(w).bits := mem_incoming_uop(w).pdst } //------------------------------------------------------------- //------------------------------------------------------------- // Writeback Cycle (St->Ld Forwarding Path) //------------------------------------------------------------- //------------------------------------------------------------- // Handle Memory Responses and nacks //---------------------------------- for (w <- 0 until memWidth) { io.core.exe(w).iresp.valid := false.B io.core.exe(w).iresp.bits := DontCare io.core.exe(w).fresp.valid := false.B io.core.exe(w).fresp.bits := DontCare } val dmem_resp_fired = WireInit(widthMap(w => false.B)) for (w <- 0 until memWidth) { // Handle nacks when (io.dmem.nack(w).valid) { // We have to re-execute this! when (io.dmem.nack(w).bits.is_hella) { assert(hella_state === h_wait || hella_state === h_dead) } .elsewhen (io.dmem.nack(w).bits.uop.uses_ldq) { assert(ldq(io.dmem.nack(w).bits.uop.ldq_idx).bits.executed) ldq(io.dmem.nack(w).bits.uop.ldq_idx).bits.executed := false.B nacking_loads(io.dmem.nack(w).bits.uop.ldq_idx) := true.B } .otherwise { assert(io.dmem.nack(w).bits.uop.uses_stq) when (IsOlder(io.dmem.nack(w).bits.uop.stq_idx, stq_execute_head, stq_head)) { stq_execute_head := io.dmem.nack(w).bits.uop.stq_idx } } } // Handle the response when (io.dmem.resp(w).valid) { when (io.dmem.resp(w).bits.uop.uses_ldq) { assert(!io.dmem.resp(w).bits.is_hella) val ldq_idx = io.dmem.resp(w).bits.uop.ldq_idx val send_iresp = ldq(ldq_idx).bits.uop.dst_rtype === RT_FIX val send_fresp = ldq(ldq_idx).bits.uop.dst_rtype === RT_FLT io.core.exe(w).iresp.bits.uop := ldq(ldq_idx).bits.uop io.core.exe(w).fresp.bits.uop := ldq(ldq_idx).bits.uop io.core.exe(w).iresp.valid := send_iresp io.core.exe(w).iresp.bits.data := io.dmem.resp(w).bits.data io.core.exe(w).fresp.valid := send_fresp io.core.exe(w).fresp.bits.data := io.dmem.resp(w).bits.data assert(send_iresp ^ send_fresp) dmem_resp_fired(w) := true.B ldq(ldq_idx).bits.succeeded := io.core.exe(w).iresp.valid || io.core.exe(w).fresp.valid ldq(ldq_idx).bits.debug_wb_data := io.dmem.resp(w).bits.data } .elsewhen (io.dmem.resp(w).bits.uop.uses_stq) { assert(!io.dmem.resp(w).bits.is_hella) stq(io.dmem.resp(w).bits.uop.stq_idx).bits.succeeded := true.B when (io.dmem.resp(w).bits.uop.is_amo) { dmem_resp_fired(w) := true.B io.core.exe(w).iresp.valid := true.B io.core.exe(w).iresp.bits.uop := stq(io.dmem.resp(w).bits.uop.stq_idx).bits.uop io.core.exe(w).iresp.bits.data := io.dmem.resp(w).bits.data stq(io.dmem.resp(w).bits.uop.stq_idx).bits.debug_wb_data := io.dmem.resp(w).bits.data } } } when (dmem_resp_fired(w) && wb_forward_valid(w)) { // Twiddle thumbs. Can't forward because dcache response takes precedence } .elsewhen (!dmem_resp_fired(w) && wb_forward_valid(w)) { val f_idx = wb_forward_ldq_idx(w) val forward_uop = ldq(f_idx).bits.uop val stq_e = stq(wb_forward_stq_idx(w)) val data_ready = stq_e.bits.data.valid val live = !IsKilledByBranch(io.core.brupdate, forward_uop) val storegen = new freechips.rocketchip.rocket.StoreGen( stq_e.bits.uop.mem_size, stq_e.bits.addr.bits, stq_e.bits.data.bits, coreDataBytes) val loadgen = new freechips.rocketchip.rocket.LoadGen( forward_uop.mem_size, forward_uop.mem_signed, wb_forward_ld_addr(w), storegen.data, false.B, coreDataBytes) io.core.exe(w).iresp.valid := (forward_uop.dst_rtype === RT_FIX) && data_ready && live io.core.exe(w).fresp.valid := (forward_uop.dst_rtype === RT_FLT) && data_ready && live io.core.exe(w).iresp.bits.uop := forward_uop io.core.exe(w).fresp.bits.uop := forward_uop io.core.exe(w).iresp.bits.data := loadgen.data io.core.exe(w).fresp.bits.data := loadgen.data when (data_ready && live) { ldq(f_idx).bits.succeeded := data_ready ldq(f_idx).bits.forward_std_val := true.B ldq(f_idx).bits.forward_stq_idx := wb_forward_stq_idx(w) ldq(f_idx).bits.debug_wb_data := loadgen.data } } } // Initially assume the speculative load wakeup failed io.core.ld_miss := RegNext(io.core.spec_ld_wakeup.map(_.valid).reduce(_||_)) val spec_ld_succeed = widthMap(w => !RegNext(io.core.spec_ld_wakeup(w).valid) || (io.core.exe(w).iresp.valid && io.core.exe(w).iresp.bits.uop.ldq_idx === RegNext(mem_incoming_uop(w).ldq_idx) ) ).reduce(_&&_) when (spec_ld_succeed) { io.core.ld_miss := false.B } //------------------------------------------------------------- // Kill speculated entries on branch mispredict //------------------------------------------------------------- //------------------------------------------------------------- // Kill stores val st_brkilled_mask = Wire(Vec(numStqEntries, Bool())) for (i <- 0 until numStqEntries) { st_brkilled_mask(i) := false.B when (stq(i).valid) { stq(i).bits.uop.br_mask := GetNewBrMask(io.core.brupdate, stq(i).bits.uop.br_mask) when (IsKilledByBranch(io.core.brupdate, stq(i).bits.uop)) { stq(i).valid := false.B stq(i).bits.addr.valid := false.B stq(i).bits.data.valid := false.B st_brkilled_mask(i) := true.B } } assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed), "Branch is trying to clear a committed store.") } // Kill loads for (i <- 0 until numLdqEntries) { when (ldq(i).valid) { ldq(i).bits.uop.br_mask := GetNewBrMask(io.core.brupdate, ldq(i).bits.uop.br_mask) when (IsKilledByBranch(io.core.brupdate, ldq(i).bits.uop)) { ldq(i).valid := false.B ldq(i).bits.addr.valid := false.B } } } //------------------------------------------------------------- when (io.core.brupdate.b2.mispredict && !io.core.exception) { stq_tail := io.core.brupdate.b2.uop.stq_idx ldq_tail := io.core.brupdate.b2.uop.ldq_idx } //------------------------------------------------------------- //------------------------------------------------------------- // dequeue old entries on commit //------------------------------------------------------------- //------------------------------------------------------------- var temp_stq_commit_head = stq_commit_head var temp_ldq_head = ldq_head for (w <- 0 until coreWidth) { val commit_store = io.core.commit.valids(w) && io.core.commit.uops(w).uses_stq val commit_load = io.core.commit.valids(w) && io.core.commit.uops(w).uses_ldq val idx = Mux(commit_store, temp_stq_commit_head, temp_ldq_head) when (commit_store) { stq(idx).bits.committed := true.B } .elsewhen (commit_load) { assert (ldq(idx).valid, "[lsu] trying to commit an un-allocated load entry.") assert ((ldq(idx).bits.executed || ldq(idx).bits.forward_std_val) && ldq(idx).bits.succeeded , "[lsu] trying to commit an un-executed load entry.") ldq(idx).valid := false.B ldq(idx).bits.addr.valid := false.B ldq(idx).bits.executed := false.B ldq(idx).bits.succeeded := false.B ldq(idx).bits.order_fail := false.B ldq(idx).bits.forward_std_val := false.B } if (MEMTRACE_PRINTF) { when (commit_store || commit_load) { val uop = Mux(commit_store, stq(idx).bits.uop, ldq(idx).bits.uop) val addr = Mux(commit_store, stq(idx).bits.addr.bits, ldq(idx).bits.addr.bits) val stdata = Mux(commit_store, stq(idx).bits.data.bits, 0.U) val wbdata = Mux(commit_store, stq(idx).bits.debug_wb_data, ldq(idx).bits.debug_wb_data) printf("MT %x %x %x %x %x %x %x\n", io.core.tsc_reg, uop.uopc, uop.mem_cmd, uop.mem_size, addr, stdata, wbdata) } } temp_stq_commit_head = Mux(commit_store, WrapInc(temp_stq_commit_head, numStqEntries), temp_stq_commit_head) temp_ldq_head = Mux(commit_load, WrapInc(temp_ldq_head, numLdqEntries), temp_ldq_head) } stq_commit_head := temp_stq_commit_head ldq_head := temp_ldq_head // store has been committed AND successfully sent data to memory when (stq(stq_head).valid && stq(stq_head).bits.committed) { when (stq(stq_head).bits.uop.is_fence && !io.dmem.ordered) { io.dmem.force_order := true.B store_needs_order := true.B } clear_store := Mux(stq(stq_head).bits.uop.is_fence, io.dmem.ordered, stq(stq_head).bits.succeeded) } when (clear_store) { stq(stq_head).valid := false.B stq(stq_head).bits.addr.valid := false.B stq(stq_head).bits.data.valid := false.B stq(stq_head).bits.succeeded := false.B stq(stq_head).bits.committed := false.B stq_head := WrapInc(stq_head, numStqEntries) when (stq(stq_head).bits.uop.is_fence) { stq_execute_head := WrapInc(stq_execute_head, numStqEntries) } } // ----------------------- // Hellacache interface // We need to time things like a HellaCache would io.hellacache.req.ready := false.B io.hellacache.s2_nack := false.B io.hellacache.s2_xcpt := (0.U).asTypeOf(new rocket.HellaCacheExceptions) io.hellacache.resp.valid := false.B io.hellacache.store_pending := stq.map(_.valid).reduce(_||_) when (hella_state === h_ready) { io.hellacache.req.ready := true.B when (io.hellacache.req.fire) { hella_req := io.hellacache.req.bits hella_state := h_s1 } } .elsewhen (hella_state === h_s1) { can_fire_hella_incoming(memWidth-1) := true.B hella_data := io.hellacache.s1_data hella_xcpt := dtlb.io.resp(memWidth-1) when (io.hellacache.s1_kill) { when (will_fire_hella_incoming(memWidth-1) && dmem_req_fire(memWidth-1)) { hella_state := h_dead } .otherwise { hella_state := h_ready } } .elsewhen (will_fire_hella_incoming(memWidth-1) && dmem_req_fire(memWidth-1)) { hella_state := h_s2 } .otherwise { hella_state := h_s2_nack } } .elsewhen (hella_state === h_s2_nack) { io.hellacache.s2_nack := true.B hella_state := h_ready } .elsewhen (hella_state === h_s2) { io.hellacache.s2_xcpt := hella_xcpt when (io.hellacache.s2_kill || hella_xcpt.asUInt =/= 0.U) { hella_state := h_dead } .otherwise { hella_state := h_wait } } .elsewhen (hella_state === h_wait) { for (w <- 0 until memWidth) { when (io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) { hella_state := h_ready io.hellacache.resp.valid := true.B io.hellacache.resp.bits.addr := hella_req.addr io.hellacache.resp.bits.tag := hella_req.tag io.hellacache.resp.bits.cmd := hella_req.cmd io.hellacache.resp.bits.signed := hella_req.signed io.hellacache.resp.bits.size := hella_req.size io.hellacache.resp.bits.data := io.dmem.resp(w).bits.data } .elsewhen (io.dmem.nack(w).valid && io.dmem.nack(w).bits.is_hella) { hella_state := h_replay } } } .elsewhen (hella_state === h_replay) { can_fire_hella_wakeup(memWidth-1) := true.B when (will_fire_hella_wakeup(memWidth-1) && dmem_req_fire(memWidth-1)) { hella_state := h_wait } } .elsewhen (hella_state === h_dead) { for (w <- 0 until memWidth) { when (io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) { hella_state := h_ready } } } //------------------------------------------------------------- // Exception / Reset // for the live_store_mask, need to kill stores that haven't been committed val st_exc_killed_mask = WireInit(VecInit((0 until numStqEntries).map(x=>false.B))) when (reset.asBool || io.core.exception) { ldq_head := 0.U ldq_tail := 0.U when (reset.asBool) { stq_head := 0.U stq_tail := 0.U stq_commit_head := 0.U stq_execute_head := 0.U for (i <- 0 until numStqEntries) { stq(i).valid := false.B stq(i).bits.addr.valid := false.B stq(i).bits.data.valid := false.B stq(i).bits.uop := NullMicroOp } } .otherwise // exception { stq_tail := stq_commit_head for (i <- 0 until numStqEntries) { when (!stq(i).bits.committed && !stq(i).bits.succeeded) { stq(i).valid := false.B stq(i).bits.addr.valid := false.B stq(i).bits.data.valid := false.B st_exc_killed_mask(i) := true.B } } } for (i <- 0 until numLdqEntries) { ldq(i).valid := false.B ldq(i).bits.addr.valid := false.B ldq(i).bits.executed := false.B } } //------------------------------------------------------------- // Live Store Mask // track a bit-array of stores that are alive // (could maybe be re-produced from the stq_head/stq_tail, but need to know include spec_killed entries) // TODO is this the most efficient way to compute the live store mask? live_store_mask := next_live_store_mask & ~(st_brkilled_mask.asUInt) & ~(st_exc_killed_mask.asUInt) } /** * Object to take an address and generate an 8-bit mask of which bytes within a * double-word. */ object GenByteMask { def apply(addr: UInt, size: UInt): UInt = { val mask = Wire(UInt(8.W)) mask := MuxCase(255.U(8.W), Array( (size === 0.U) -> (1.U(8.W) << addr(2,0)), (size === 1.U) -> (3.U(8.W) << (addr(2,1) << 1.U)), (size === 2.U) -> Mux(addr(2), 240.U(8.W), 15.U(8.W)), (size === 3.U) -> 255.U(8.W))) mask } } /** * ... */ class ForwardingAgeLogic(num_entries: Int)(implicit p: Parameters) extends BoomModule()(p) { val io = IO(new Bundle { val addr_matches = Input(UInt(num_entries.W)) // bit vector of addresses that match // between the load and the SAQ val youngest_st_idx = Input(UInt(stqAddrSz.W)) // needed to get "age" val forwarding_val = Output(Bool()) val forwarding_idx = Output(UInt(stqAddrSz.W)) }) // generating mask that zeroes out anything younger than tail val age_mask = Wire(Vec(num_entries, Bool())) for (i <- 0 until num_entries) { age_mask(i) := true.B when (i.U >= io.youngest_st_idx) // currently the tail points PAST last store, so use >= { age_mask(i) := false.B } } // Priority encoder with moving tail: double length val matches = Wire(UInt((2*num_entries).W)) matches := Cat(io.addr_matches & age_mask.asUInt, io.addr_matches) val found_match = Wire(Bool()) found_match := false.B io.forwarding_idx := 0.U // look for youngest, approach from the oldest side, let the last one found stick for (i <- 0 until (2*num_entries)) { when (matches(i)) { found_match := true.B io.forwarding_idx := (i % num_entries).U } } io.forwarding_val := found_match }
module ForwardingAgeLogic( // @[lsu.scala:1678:7] input clock, // @[lsu.scala:1678:7] input reset, // @[lsu.scala:1678:7] input [15:0] io_addr_matches, // @[lsu.scala:1680:15] input [3:0] io_youngest_st_idx, // @[lsu.scala:1680:15] output [3:0] io_forwarding_idx // @[lsu.scala:1680:15] ); wire [15:0] io_addr_matches_0 = io_addr_matches; // @[lsu.scala:1678:7] wire [3:0] io_youngest_st_idx_0 = io_youngest_st_idx; // @[lsu.scala:1678:7] wire age_mask_15 = 1'h0; // @[lsu.scala:1691:23] wire found_match; // @[lsu.scala:1706:26] wire io_forwarding_val; // @[lsu.scala:1678:7] wire [3:0] io_forwarding_idx_0; // @[lsu.scala:1678:7] wire age_mask_0; // @[lsu.scala:1691:23] wire age_mask_1; // @[lsu.scala:1691:23] wire age_mask_2; // @[lsu.scala:1691:23] wire age_mask_3; // @[lsu.scala:1691:23] wire age_mask_4; // @[lsu.scala:1691:23] wire age_mask_5; // @[lsu.scala:1691:23] wire age_mask_6; // @[lsu.scala:1691:23] wire age_mask_7; // @[lsu.scala:1691:23] wire age_mask_8; // @[lsu.scala:1691:23] wire age_mask_9; // @[lsu.scala:1691:23] wire age_mask_10; // @[lsu.scala:1691:23] wire age_mask_11; // @[lsu.scala:1691:23] wire age_mask_12; // @[lsu.scala:1691:23] wire age_mask_13; // @[lsu.scala:1691:23] wire age_mask_14; // @[lsu.scala:1691:23] assign age_mask_0 = |io_youngest_st_idx_0; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22] assign age_mask_1 = |(io_youngest_st_idx_0[3:1]); // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22] assign age_mask_2 = io_youngest_st_idx_0 > 4'h2; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22] assign age_mask_3 = |(io_youngest_st_idx_0[3:2]); // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22] assign age_mask_4 = io_youngest_st_idx_0 > 4'h4; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22] assign age_mask_5 = io_youngest_st_idx_0 > 4'h5; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22] assign age_mask_6 = io_youngest_st_idx_0 > 4'h6; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22] assign age_mask_7 = io_youngest_st_idx_0[3]; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22] assign age_mask_8 = io_youngest_st_idx_0 > 4'h8; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22] assign age_mask_9 = io_youngest_st_idx_0 > 4'h9; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22] assign age_mask_10 = io_youngest_st_idx_0 > 4'hA; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22] assign age_mask_11 = io_youngest_st_idx_0 > 4'hB; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22] assign age_mask_12 = io_youngest_st_idx_0 > 4'hC; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22] assign age_mask_13 = io_youngest_st_idx_0 > 4'hD; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22] assign age_mask_14 = &io_youngest_st_idx_0; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22] wire [31:0] _matches_T_2; // @[lsu.scala:1703:18] wire [31:0] matches_0; // @[lsu.scala:1702:22] wire [1:0] matches_lo_lo_lo = {age_mask_1, age_mask_0}; // @[lsu.scala:1691:23, :1703:46] wire [1:0] matches_lo_lo_hi = {age_mask_3, age_mask_2}; // @[lsu.scala:1691:23, :1703:46] wire [3:0] matches_lo_lo = {matches_lo_lo_hi, matches_lo_lo_lo}; // @[lsu.scala:1703:46] wire [1:0] matches_lo_hi_lo = {age_mask_5, age_mask_4}; // @[lsu.scala:1691:23, :1703:46] wire [1:0] matches_lo_hi_hi = {age_mask_7, age_mask_6}; // @[lsu.scala:1691:23, :1703:46] wire [3:0] matches_lo_hi = {matches_lo_hi_hi, matches_lo_hi_lo}; // @[lsu.scala:1703:46] wire [7:0] matches_lo = {matches_lo_hi, matches_lo_lo}; // @[lsu.scala:1703:46] wire [1:0] matches_hi_lo_lo = {age_mask_9, age_mask_8}; // @[lsu.scala:1691:23, :1703:46] wire [1:0] matches_hi_lo_hi = {age_mask_11, age_mask_10}; // @[lsu.scala:1691:23, :1703:46] wire [3:0] matches_hi_lo = {matches_hi_lo_hi, matches_hi_lo_lo}; // @[lsu.scala:1703:46] wire [1:0] matches_hi_hi_lo = {age_mask_13, age_mask_12}; // @[lsu.scala:1691:23, :1703:46] wire [1:0] matches_hi_hi_hi = {1'h0, age_mask_14}; // @[lsu.scala:1691:23, :1703:46] wire [3:0] matches_hi_hi = {matches_hi_hi_hi, matches_hi_hi_lo}; // @[lsu.scala:1703:46] wire [7:0] matches_hi = {matches_hi_hi, matches_hi_lo}; // @[lsu.scala:1703:46] wire [15:0] _matches_T = {matches_hi, matches_lo}; // @[lsu.scala:1703:46] wire [15:0] _matches_T_1 = io_addr_matches_0 & _matches_T; // @[lsu.scala:1678:7, :1703:{35,46}] assign _matches_T_2 = {_matches_T_1, io_addr_matches_0}; // @[lsu.scala:1678:7, :1703:{18,35}] assign matches_0 = _matches_T_2; // @[lsu.scala:1702:22, :1703:18] assign io_forwarding_val = found_match; // @[lsu.scala:1678:7, :1706:26] assign found_match = |matches_0; // @[lsu.scala:1702:22, :1706:26, :1714:7, :1715:22] assign io_forwarding_idx_0 = matches_0[31] ? 4'hF : matches_0[30] ? 4'hE : matches_0[29] ? 4'hD : matches_0[28] ? 4'hC : matches_0[27] ? 4'hB : matches_0[26] ? 4'hA : matches_0[25] ? 4'h9 : matches_0[24] ? 4'h8 : matches_0[23] ? 4'h7 : matches_0[22] ? 4'h6 : matches_0[21] ? 4'h5 : matches_0[20] ? 4'h4 : matches_0[19] ? 4'h3 : matches_0[18] ? 4'h2 : matches_0[17] ? 4'h1 : matches_0[16] ? 4'h0 : matches_0[15] ? 4'hF : matches_0[14] ? 4'hE : matches_0[13] ? 4'hD : matches_0[12] ? 4'hC : matches_0[11] ? 4'hB : matches_0[10] ? 4'hA : matches_0[9] ? 4'h9 : matches_0[8] ? 4'h8 : matches_0[7] ? 4'h7 : matches_0[6] ? 4'h6 : matches_0[5] ? 4'h5 : matches_0[4] ? 4'h4 : matches_0[3] ? 4'h3 : matches_0[2] ? 4'h2 : {3'h0, matches_0[1]}; // @[lsu.scala:1678:7, :1694:19, :1695:17, :1696:7, :1697:22, :1702:22, :1713:20, :1714:7, :1716:28] assign io_forwarding_idx = io_forwarding_idx_0; // @[lsu.scala:1678:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_56( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [6:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [1:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [1:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] b_first_counter; // @[Edges.scala:229:27] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [6:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [1:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [6:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [78:0] inflight; // @[Monitor.scala:614:27] reg [315:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [315:0] inflight_sizes; // @[Monitor.scala:618:33] reg [1:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] reg [1:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_1 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_4 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [78:0] inflight_1; // @[Monitor.scala:726:35] reg [315:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [1:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] reg [1:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [127:0] _GEN_6 = {121'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [11:0] inflight_2; // @[Monitor.scala:828:27] reg [1:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35] wire [11:0] d_set = _GEN_8 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_102( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [1:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [4:0] _GEN = 5'h3 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [4:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [1:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49] wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_0_1 = io_in_a_bits_size_0[1]; // @[Misc.scala:206:21] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_898 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_898; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_898; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [1:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_966 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_966; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN_0 = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_2 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_831 = _T_898 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_831 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_831 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_831 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _GEN_4 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [3:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_4; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_4; // @[Monitor.scala:659:79, :660:77] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_831 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_831 ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_846 = _T_966 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_942 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_942 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_924 = _T_966 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_924 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_924 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_924 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File UARTRx.scala: package sifive.blocks.devices.uart import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ /** UARTRx module recivies serial input from Rx port and transmits them to Rx fifo in parallel * * ==Datapass== * Port(Rx) -> sample -> shifter -> Rx fifo -> TL bus * * ==Structure== * - baud rate divisor counter: * generate pulse, the enable signal for sample and data shift * - sample counter: * sample happens in middle * - data counter * control signals for data shift process * - sample and data shift logic * * ==State Machine== * s_idle: detect start bit, init data_count and sample count, start pulse counter * s_data: data reciving * * @note Rx fifo transmits Rx data to TL bus */ class UARTRx(c: UARTParams) extends Module { val io = IO(new Bundle { /** enable signal from top */ val en = Input(Bool()) /** input data from rx port */ val in = Input(UInt(1.W)) /** output data to Rx fifo */ val out = Valid(UInt(c.dataBits.W)) /** divisor bits */ val div = Input(UInt(c.divisorBits.W)) /** parity enable */ val enparity = c.includeParity.option(Input(Bool())) /** parity select * * 0 -> even parity * 1 -> odd parity */ val parity = c.includeParity.option(Input(Bool())) /** parity error bit */ val errorparity = c.includeParity.option(Output(Bool())) /** databit select * * ture -> 8 * false -> 9 */ val data8or9 = (c.dataBits == 9).option(Input(Bool())) }) if (c.includeParity) io.errorparity.get := false.B val debounce = RegInit(0.U(2.W)) val debounce_max = (debounce === 3.U) val debounce_min = (debounce === 0.U) val prescaler = Reg(UInt((c.divisorBits - c.oversample + 1).W)) val start = WireDefault(false.B) /** enable signal for sampling and data shifting */ val pulse = (prescaler === 0.U) private val dataCountBits = log2Floor(c.dataBits+c.includeParity.toInt) + 1 /** init = data bits(8 or 9) + parity bit(0 or 1) + start bit(1) */ val data_count = Reg(UInt(dataCountBits.W)) val data_last = (data_count === 0.U) val parity_bit = (data_count === 1.U) && io.enparity.getOrElse(false.B) val sample_count = Reg(UInt(c.oversample.W)) val sample_mid = (sample_count === ((c.oversampleFactor - c.nSamples + 1) >> 1).U) // todo unused val sample_last = (sample_count === 0.U) /** counter for data and sample * * {{{ * | data_count | sample_count | * }}} */ val countdown = Cat(data_count, sample_count) - 1.U // Compensate for the divisor not being a multiple of the oversampling period. // Let remainder k = (io.div % c.oversampleFactor). // For the last k samples, extend the sampling delay by 1 cycle. val remainder = io.div(c.oversample-1, 0) val extend = (sample_count < remainder) // Pad head: (sample_count > ~remainder) /** prescaler reset signal * * conditions: * {{{ * start : transmisson starts * pulse : returns ture every pluse counter period * }}} */ val restore = start || pulse val prescaler_in = Mux(restore, io.div >> c.oversample, prescaler) val prescaler_next = prescaler_in - Mux(restore && extend, 0.U, 1.U) /** buffer for sample results */ val sample = Reg(UInt(c.nSamples.W)) // take the majority bit of sample buffer val voter = Majority(sample.asBools.toSet) // data buffer val shifter = Reg(UInt(c.dataBits.W)) val valid = RegInit(false.B) valid := false.B io.out.valid := valid io.out.bits := (if (c.dataBits == 8) shifter else Mux(io.data8or9.get, Cat(0.U, shifter(8,1)), shifter)) val (s_idle :: s_data :: Nil) = Enum(2) val state = RegInit(s_idle) switch (state) { is (s_idle) { // todo !(!io.in)? when (!(!io.in) && !debounce_min) { debounce := debounce - 1.U } when (!io.in) { debounce := debounce + 1.U when (debounce_max) { state := s_data start := true.B prescaler := prescaler_next // init data_count data_count := (c.dataBits+1).U + (if (c.includeParity) io.enparity.get else 0.U) - io.data8or9.getOrElse(false.B).asUInt // init sample_count = 15 sample_count := (c.oversampleFactor - 1).U } } } is (s_data) { prescaler := prescaler_next when (pulse) { // sample scan in sample := Cat(sample, io.in) data_count := countdown >> c.oversample sample_count := countdown(c.oversample-1, 0) when (sample_mid) { if (c.includeParity) { // act according to frame bit stage at its respective sampling point // check parity bit for error when (parity_bit) { io.errorparity.get := (shifter.asBools.reduce(_ ^ _) ^ voter ^ io.parity.get) } when (data_last) { state := s_idle valid := true.B } .elsewhen (!parity_bit) { // do not add parity bit to final rx data shifter := Cat(voter, shifter >> 1) } } else { when (data_last) { state := s_idle valid := true.B } .otherwise { shifter := Cat(voter, shifter >> 1) } } } } } } when (!io.en) { debounce := 0.U } } /* Copyright 2016 SiFive, Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */
module UARTRx_TestHarness_UNIQUIFIED( // @[UARTRx.scala:28:7] input clock, // @[UARTRx.scala:28:7] input reset, // @[UARTRx.scala:28:7] input io_en, // @[UARTRx.scala:29:14] input io_in, // @[UARTRx.scala:29:14] output io_out_valid, // @[UARTRx.scala:29:14] output [7:0] io_out_bits, // @[UARTRx.scala:29:14] input [15:0] io_div // @[UARTRx.scala:29:14] ); reg [1:0] debounce; // @[UARTRx.scala:59:25] reg [12:0] prescaler; // @[UARTRx.scala:63:22] reg [3:0] data_count; // @[UARTRx.scala:70:23] reg [3:0] sample_count; // @[UARTRx.scala:73:25] reg [2:0] sample; // @[UARTRx.scala:102:19] reg [7:0] shifter; // @[UARTRx.scala:106:20] reg valid; // @[UARTRx.scala:108:22] reg state; // @[UARTRx.scala:114:22] wire [7:0] _countdown_T_1 = {data_count, sample_count} - 8'h1; // @[UARTRx.scala:70:23, :73:25, :83:49] wire pulse = prescaler == 13'h0; // @[UARTRx.scala:63:22, :66:26] wire data_last = data_count == 4'h0; // @[UARTRx.scala:70:23, :71:31] wire sample_mid = sample_count == 4'h7; // @[UARTRx.scala:73:25, :74:34] wire _GEN = ~io_in & (&debounce); // @[UARTRx.scala:59:25, :60:32, :114:22, :119:15, :122:21, :124:29, :125:17] wire _GEN_0 = _GEN | state; // @[UARTRx.scala:114:22, :122:21, :124:29, :125:17] wire _GEN_1 = state & pulse; // @[UARTRx.scala:66:26, :102:19, :114:22, :116:18, :138:20, :140:16] wire _GEN_2 = state & pulse & sample_mid; // @[UARTRx.scala:66:26, :74:34, :109:9, :114:22, :116:18, :138:20, :144:27, :159:30] wire restore = ~state & ~io_in & (&debounce) | pulse; // @[UARTRx.scala:59:25, :60:32, :64:26, :66:26, :98:23, :114:22, :116:18, :119:15, :122:21, :124:29] always @(posedge clock) begin // @[UARTRx.scala:28:7] if (reset) begin // @[UARTRx.scala:28:7] debounce <= 2'h0; // @[UARTRx.scala:28:7, :59:25] valid <= 1'h0; // @[UARTRx.scala:28:7, :108:22] state <= 1'h0; // @[UARTRx.scala:28:7, :114:22] end else begin // @[UARTRx.scala:28:7] if (io_en) begin // @[UARTRx.scala:29:14] if (state) begin // @[UARTRx.scala:114:22] end else if (io_in) begin // @[UARTRx.scala:29:14] if (io_in & (|debounce)) // @[UARTRx.scala:59:25, :61:32, :119:23] debounce <= debounce - 2'h1; // @[UARTRx.scala:59:25, :120:30] end else // @[UARTRx.scala:29:14] debounce <= debounce + 2'h1; // @[UARTRx.scala:28:7, :59:25, :123:30] end else // @[UARTRx.scala:29:14] debounce <= 2'h0; // @[UARTRx.scala:28:7, :59:25] valid <= _GEN_2 & data_last; // @[UARTRx.scala:71:31, :108:22, :109:9, :116:18, :138:20, :144:27, :159:30] if (state) // @[UARTRx.scala:114:22] state <= ~(state & pulse & sample_mid & data_last) & state; // @[UARTRx.scala:66:26, :71:31, :74:34, :114:22, :116:18, :138:20, :144:27, :159:30, :160:21] else // @[UARTRx.scala:114:22] state <= _GEN_0; // @[UARTRx.scala:114:22, :122:21, :124:29, :125:17] end if (_GEN_0) // @[UARTRx.scala:114:22, :116:18, :122:21, :124:29, :125:17] prescaler <= (restore ? {1'h0, io_div[15:4]} : prescaler) - {12'h0, ~(restore & sample_count < io_div[3:0])}; // @[UARTRx.scala:28:7, :63:22, :73:25, :88:25, :89:30, :98:23, :99:{25,42}, :100:{37,42,51}] if (state) begin // @[UARTRx.scala:114:22] if (_GEN_1) begin // @[UARTRx.scala:102:19, :116:18, :138:20, :140:16] data_count <= _countdown_T_1[7:4]; // @[UARTRx.scala:70:23, :83:49, :141:33] sample_count <= _countdown_T_1[3:0]; // @[UARTRx.scala:73:25, :83:49, :142:34] end end else if (_GEN) begin // @[UARTRx.scala:114:22, :122:21, :124:29, :125:17] data_count <= 4'h9; // @[UARTRx.scala:70:23] sample_count <= 4'hF; // @[UARTRx.scala:73:25] end if (_GEN_1) // @[UARTRx.scala:102:19, :116:18, :138:20, :140:16] sample <= {sample[1:0], io_in}; // @[UARTRx.scala:102:19, :140:16] if (~state | ~_GEN_2 | data_last) begin // @[UARTRx.scala:71:31, :106:20, :109:9, :114:22, :116:18, :138:20, :144:27, :159:30] end else // @[UARTRx.scala:106:20, :116:18, :138:20, :144:27, :159:30] shifter <= {sample[0] & sample[1] | sample[0] & sample[2] | sample[1] & sample[2], shifter[7:1]}; // @[Misc.scala:167:48, :168:22] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in || corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ || !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready || !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel | count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid || full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLWidthWidget32( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [255:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [255:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [255:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [255:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [1:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [255:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [255:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [255:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] wire [255:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] cated_bits_source; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] cated_bits_address; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_2 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_3 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25] wire [255:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [31:0] cated_bits_mask; // @[WidthWidget.scala:161:25] wire [255:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [191:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[255:64]; // @[Repeater.scala:36:26] wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25] wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [19:0] _repeat_limit_T = 20'h1F << cated_bits_size; // @[package.scala:243:71] wire [4:0] _repeat_limit_T_1 = _repeat_limit_T[4:0]; // @[package.scala:243:{71,76}] wire [4:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire [1:0] repeat_limit = _repeat_limit_T_2[4:3]; // @[package.scala:243:46] reg [1:0] repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = repeat_count == 2'h0; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35] wire [2:0] _repeat_count_T = {1'h0, repeat_count} + 3'h1; // @[WidthWidget.scala:105:26, :110:24] wire [1:0] _repeat_count_T_1 = _repeat_count_T[1:0]; // @[WidthWidget.scala:110:24] wire [1:0] repeat_sel = cated_bits_address[4:3]; // @[WidthWidget.scala:116:39, :161:25] wire [1:0] repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24] wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_2 = cated_bits_data[191:128]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_2 = _repeat_anonOut_a_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_3 = cated_bits_data[255:192]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_3 = _repeat_anonOut_a_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [3:0][63:0] _GEN = {{repeat_anonOut_a_bits_data_mux_3}, {repeat_anonOut_a_bits_data_mux_2}, {repeat_anonOut_a_bits_data_mux_1}, {repeat_anonOut_a_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30] assign anonOut_a_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_2 = cated_bits_mask[23:16]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_2 = _repeat_anonOut_a_bits_mask_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_3 = cated_bits_mask[31:24]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_3 = _repeat_anonOut_a_bits_mask_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [3:0][7:0] _GEN_0 = {{repeat_anonOut_a_bits_mask_mux_3}, {repeat_anonOut_a_bits_mask_mux_2}, {repeat_anonOut_a_bits_mask_mux_1}, {repeat_anonOut_a_bits_mask_mux_0}}; // @[WidthWidget.scala:128:43, :140:53] assign anonOut_a_bits_mask = _GEN_0[repeat_index]; // @[WidthWidget.scala:126:24, :140:53] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [19:0] _limit_T = 20'h1F << anonOut_d_bits_size; // @[package.scala:243:71] wire [4:0] _limit_T_1 = _limit_T[4:0]; // @[package.scala:243:{71,76}] wire [4:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire [1:0] limit = _limit_T_2[4:3]; // @[package.scala:243:46] reg [1:0] count; // @[WidthWidget.scala:40:27] wire [1:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = count == 2'h0; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire [1:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = |_enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_3 = {count[1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = |_enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_6 = count ^ 2'h2; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_8 = |_enable_T_7; // @[WidthWidget.scala:43:{63,72}] wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_9 = ~count; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_11 = |_enable_T_10; // @[WidthWidget.scala:43:{63,72}] wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35] wire [2:0] _count_T = {1'h0, count} + 3'h1; // @[WidthWidget.scala:40:27, :50:24] wire [1:0] _count_T_1 = _count_T[1:0]; // @[WidthWidget.scala:50:24] wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_2 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_2 = enable_2 | _anonIn_d_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_3 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_3 = enable_3 | _anonIn_d_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:66:24] wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_2 = anonIn_d_bits_data_masked_enable_2 ? anonIn_d_bits_data_odata_2 : anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_3 = anonIn_d_bits_data_masked_enable_3 ? anonIn_d_bits_data_odata_3 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35] wire [127:0] anonIn_d_bits_data_lo = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [127:0] anonIn_d_bits_data_hi = {anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_hi, anonIn_d_bits_data_lo}; // @[WidthWidget.scala:73:12] assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] repeat_count <= 2'h0; // @[WidthWidget.scala:105:26] count <= 2'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] end else begin // @[WidthWidget.scala:27:9] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= repeat_last ? 2'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35] count <= last ? 2'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23] end anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] end if (_anonIn_d_bits_data_T_2) begin // @[WidthWidget.scala:69:23] anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_1 <= anonIn_d_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_2 <= anonIn_d_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88] end always @(posedge) TLMonitor_58 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleA_a32d256s2k3z4u repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonIn_a_ready), .io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_source (cated_bits_source), .io_deq_bits_address (cated_bits_address), .io_deq_bits_mask (cated_bits_mask), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_78( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_158 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_439( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_183 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_1( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [31:0] _roundMask_T_5 = 32'hFFFF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_4 = 32'hFFFF0000; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_10 = 32'hFFFF0000; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_13 = 24'hFFFF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_14 = 32'hFFFF00; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_15 = 32'hFF00FF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_20 = 32'hFF00FF00; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_23 = 28'hFF00FF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_24 = 32'hFF00FF0; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_25 = 32'hF0F0F0F; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_30 = 32'hF0F0F0F0; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_33 = 30'hF0F0F0F; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_34 = 32'h3C3C3C3C; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_35 = 32'h33333333; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_40 = 32'hCCCCCCCC; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_43 = 31'h33333333; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_44 = 32'h66666666; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_45 = 32'h55555555; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_50 = 32'hAAAAAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_56 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_55 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_61 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_64 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_65 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_66 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_71 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_74 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_75 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_76 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_81 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_84 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_85 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_86 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_91 = 16'hAAAA; // @[primitives.scala:77:20] wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire [55:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire doShiftSigDown1 = adjustedSig[55]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [11:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [11:0] _roundMask_T = io_in_sExp_0[11:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [11:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[11]; // @[primitives.scala:52:21, :58:25] wire [10:0] roundMask_lsbs = _roundMask_T_1[10:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[10]; // @[primitives.scala:58:25, :59:26] wire [9:0] roundMask_lsbs_1 = roundMask_lsbs[9:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_6 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26] wire [8:0] roundMask_lsbs_2 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26] wire [8:0] roundMask_lsbs_6 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26] wire roundMask_msb_3 = roundMask_lsbs_2[8]; // @[primitives.scala:58:25, :59:26] wire [7:0] roundMask_lsbs_3 = roundMask_lsbs_2[7:0]; // @[primitives.scala:59:26] wire roundMask_msb_4 = roundMask_lsbs_3[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_4 = roundMask_lsbs_3[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_5 = roundMask_lsbs_4[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_5 = roundMask_lsbs_4[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_5); // @[primitives.scala:59:26, :76:56] wire [50:0] _roundMask_T_2 = roundMask_shift[63:13]; // @[primitives.scala:76:56, :78:22] wire [31:0] _roundMask_T_3 = _roundMask_T_2[31:0]; // @[primitives.scala:77:20, :78:22] wire [15:0] _roundMask_T_6 = _roundMask_T_3[31:16]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_7 = {16'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_8 = _roundMask_T_3[15:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_9 = {_roundMask_T_8, 16'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_11 = _roundMask_T_9 & 32'hFFFF0000; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_16 = _roundMask_T_12[31:8]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_17 = {8'h0, _roundMask_T_16 & 24'hFF00FF}; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_18 = _roundMask_T_12[23:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_19 = {_roundMask_T_18, 8'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_21 = _roundMask_T_19 & 32'hFF00FF00; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_26 = _roundMask_T_22[31:4]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_27 = {4'h0, _roundMask_T_26 & 28'hF0F0F0F}; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_28 = _roundMask_T_22[27:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_29 = {_roundMask_T_28, 4'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_31 = _roundMask_T_29 & 32'hF0F0F0F0; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_36 = _roundMask_T_32[31:2]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_37 = {2'h0, _roundMask_T_36 & 30'h33333333}; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_38 = _roundMask_T_32[29:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_39 = {_roundMask_T_38, 2'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_41 = _roundMask_T_39 & 32'hCCCCCCCC; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_46 = _roundMask_T_42[31:1]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_47 = {1'h0, _roundMask_T_46 & 31'h55555555}; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_48 = _roundMask_T_42[30:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_49 = {_roundMask_T_48, 1'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_51 = _roundMask_T_49 & 32'hAAAAAAAA; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_52 = _roundMask_T_47 | _roundMask_T_51; // @[primitives.scala:77:20] wire [18:0] _roundMask_T_53 = _roundMask_T_2[50:32]; // @[primitives.scala:77:20, :78:22] wire [15:0] _roundMask_T_54 = _roundMask_T_53[15:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_57 = _roundMask_T_54[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_58 = {8'h0, _roundMask_T_57}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_59 = _roundMask_T_54[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_60 = {_roundMask_T_59, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_62 = _roundMask_T_60 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_63 = _roundMask_T_58 | _roundMask_T_62; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_67 = _roundMask_T_63[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_68 = {4'h0, _roundMask_T_67 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_69 = _roundMask_T_63[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_70 = {_roundMask_T_69, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_72 = _roundMask_T_70 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_73 = _roundMask_T_68 | _roundMask_T_72; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_77 = _roundMask_T_73[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_78 = {2'h0, _roundMask_T_77 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_79 = _roundMask_T_73[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_80 = {_roundMask_T_79, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_82 = _roundMask_T_80 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_83 = _roundMask_T_78 | _roundMask_T_82; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_87 = _roundMask_T_83[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_88 = {1'h0, _roundMask_T_87 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_89 = _roundMask_T_83[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_90 = {_roundMask_T_89, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_92 = _roundMask_T_90 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_93 = _roundMask_T_88 | _roundMask_T_92; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_94 = _roundMask_T_53[18:16]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_95 = _roundMask_T_94[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_96 = _roundMask_T_95[0]; // @[primitives.scala:77:20] wire _roundMask_T_97 = _roundMask_T_95[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_98 = {_roundMask_T_96, _roundMask_T_97}; // @[primitives.scala:77:20] wire _roundMask_T_99 = _roundMask_T_94[2]; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_100 = {_roundMask_T_98, _roundMask_T_99}; // @[primitives.scala:77:20] wire [18:0] _roundMask_T_101 = {_roundMask_T_93, _roundMask_T_100}; // @[primitives.scala:77:20] wire [50:0] _roundMask_T_102 = {_roundMask_T_52, _roundMask_T_101}; // @[primitives.scala:77:20] wire [50:0] _roundMask_T_103 = ~_roundMask_T_102; // @[primitives.scala:73:32, :77:20] wire [50:0] _roundMask_T_104 = roundMask_msb_5 ? 51'h0 : _roundMask_T_103; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_105 = ~_roundMask_T_104; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_106 = ~_roundMask_T_105; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_107 = roundMask_msb_4 ? 51'h0 : _roundMask_T_106; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_108 = ~_roundMask_T_107; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_109 = ~_roundMask_T_108; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_110 = roundMask_msb_3 ? 51'h0 : _roundMask_T_109; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_111 = ~_roundMask_T_110; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_112 = ~_roundMask_T_111; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_113 = roundMask_msb_2 ? 51'h0 : _roundMask_T_112; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_114 = ~_roundMask_T_113; // @[primitives.scala:73:{17,21}] wire [53:0] _roundMask_T_115 = {_roundMask_T_114, 3'h7}; // @[primitives.scala:68:58, :73:17] wire roundMask_msb_7 = roundMask_lsbs_6[8]; // @[primitives.scala:58:25, :59:26] wire [7:0] roundMask_lsbs_7 = roundMask_lsbs_6[7:0]; // @[primitives.scala:59:26] wire roundMask_msb_8 = roundMask_lsbs_7[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_8 = roundMask_lsbs_7[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_9 = roundMask_lsbs_8[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_9 = roundMask_lsbs_8[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_9); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_116 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_117 = _roundMask_T_116[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_118 = _roundMask_T_117[0]; // @[primitives.scala:77:20] wire _roundMask_T_119 = _roundMask_T_117[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_120 = {_roundMask_T_118, _roundMask_T_119}; // @[primitives.scala:77:20] wire _roundMask_T_121 = _roundMask_T_116[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_122 = {_roundMask_T_120, _roundMask_T_121}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_123 = roundMask_msb_9 ? _roundMask_T_122 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [2:0] _roundMask_T_124 = roundMask_msb_8 ? _roundMask_T_123 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [2:0] _roundMask_T_125 = roundMask_msb_7 ? _roundMask_T_124 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [2:0] _roundMask_T_126 = roundMask_msb_6 ? _roundMask_T_125 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [53:0] _roundMask_T_127 = roundMask_msb_1 ? _roundMask_T_115 : {51'h0, _roundMask_T_126}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [53:0] _roundMask_T_128 = roundMask_msb ? _roundMask_T_127 : 54'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [53:0] _roundMask_T_129 = {_roundMask_T_128[53:1], _roundMask_T_128[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [55:0] roundMask = {_roundMask_T_129, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [56:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [55:0] shiftedRoundMask = _shiftedRoundMask_T[56:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [55:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [55:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [55:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [55:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [55:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [53:0] _roundedSig_T_1 = _roundedSig_T[55:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [54:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 55'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [54:0] _roundedSig_T_6 = roundMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [54:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [54:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [54:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [55:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [55:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [53:0] _roundedSig_T_12 = _roundedSig_T_11[55:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [54:0] _roundedSig_T_14 = roundPosMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [54:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [54:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [54:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[54:53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [13:0] sRoundedExp = {io_in_sExp_0[12], io_in_sExp_0} + {{11{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [51:0] _common_fractOut_T = roundedSig[52:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [51:0] _common_fractOut_T_1 = roundedSig[51:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[13:10]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 14'sh3CE; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[54]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[12:11]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire notNaN_isSpecialInfOut = io_infiniteExc_0 | io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [11:0] _expOut_T_5 = pegMinNonzeroMagOut ? 12'hC31 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [11:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [11:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [11:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 10'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [11:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [11:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [11:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [11:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [11:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [11:0] _expOut_T_14 = pegMinNonzeroMagOut ? 12'h3CE : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [11:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [11:0] _expOut_T_16 = pegMaxFiniteMagOut ? 12'hBFF : 12'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [11:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [11:0] _expOut_T_18 = notNaN_isInfOut ? 12'hC00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [11:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [11:0] _expOut_T_20 = isNaNOut ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [11:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [51:0] _fractOut_T_2 = {isNaNOut, 51'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [51:0] _fractOut_T_4 = {52{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [51:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File HasChipyardPRCI.scala: package chipyard.clocking import chisel3._ import scala.collection.mutable.{ArrayBuffer} import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ import testchipip.boot.{TLTileResetCtrl} import testchipip.clocking.{ClockGroupFakeResetSynchronizer} case class ChipyardPRCIControlParams( slaveWhere: TLBusWrapperLocation = CBUS, baseAddress: BigInt = 0x100000, enableTileClockGating: Boolean = true, enableTileResetSetting: Boolean = true, enableResetSynchronizers: Boolean = true // this should only be disabled to work around verilator async-reset initialization problems ) { def generatePRCIXBar = enableTileClockGating || enableTileResetSetting } case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams()) trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElements => require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks") val prciParams = p(ChipyardPRCIControlKey) // Set up clock domain private val tlbus = locateTLBusWrapper(prciParams.slaveWhere) val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl") .suggestName("chipyard_prcictrl_domain") val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } } prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar := TLFIFOFixer(TLFIFOFixer.all) := TLBuffer() := _) }) // Aggregate all the clock groups into a single node val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node // The diplomatic clocks in the subsystem are routed to this allClockGroupsNode val clockNamePrefixer = ClockGroupNamePrefixer() (allClockGroupsNode :*= clockNamePrefixer :*= aggregator) // Once all the clocks are gathered in the aggregator node, several steps remain // 1. Assign frequencies to any clock groups which did not specify a frequency. // 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain) // 3. Synchronize reset to each clock group // 4. Clock gate the clock groups corresponding to Tiles (if desired). // 5. Add reset control registers to the tiles (if desired) // The final clock group here contains physically distinct clock domains, which some PRCI node in a // diplomatic IOBinder should drive val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey)) val clockGroupCombiner = ClockGroupCombiner() val resetSynchronizer = prci_ctrl_domain { if (prciParams.enableResetSynchronizers) ClockGroupResetSynchronizer() else ClockGroupFakeResetSynchronizer() } val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain { val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes)) clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get clock_gater } } val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain { val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes, tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil)) reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get reset_setter } } if (!prciParams.enableResetSynchronizers) { println(Console.RED + s""" !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! WARNING: DISABLING THE RESET SYNCHRONIZERS RESULTS IN A BROKEN DESIGN THAT WILL NOT BEHAVE PROPERLY AS ASIC OR FPGA. THESE SHOULD ONLY BE DISABLED TO WORK AROUND LIMITATIONS IN ASYNC RESET INITIALIZATION IN RTL SIMULATORS, NAMELY VERILATOR. !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! """ + Console.RESET) } // The chiptopClockGroupsNode shouuld be what ClockBinders attach to val chiptopClockGroupsNode = ClockGroupEphemeralNode() (aggregator := frequencySpecifier := clockGroupCombiner := resetSynchronizer := tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := chiptopClockGroupsNode) } File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 */ val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2*maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready || drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) || out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied || out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full || !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full || in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File ResetSynchronizer.scala: // See LICENSE for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.ResetCatchAndSync /** * Synchronizes the reset of a diplomatic clock-reset pair to its accompanying clock. */ class ResetSynchronizer(implicit p: Parameters) extends LazyModule { val node = ClockAdapterNode() lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { (node.out zip node.in).map { case ((o, _), (i, _)) => o.clock := i.clock o.reset := ResetCatchAndSync(i.clock, i.reset.asBool) } } } object ResetSynchronizer { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ResetSynchronizer()).node } /** * Instantiates a reset synchronizer on all clock-reset pairs in a clock group. */ class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule { val node = ClockGroupAdapterNode() lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { (node.out zip node.in).map { case ((oG, _), (iG, _)) => (oG.member.data zip iG.member.data).foreach { case (o, i) => o.clock := i.clock o.reset := ResetCatchAndSync(i.clock, i.reset.asBool) } } } } object ClockGroupResetSynchronizer { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupResetSynchronizer()).node } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }
module ChipyardPRCICtrlClockSinkDomain( // @[ClockDomain.scala:14:9] input auto_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_resetSynchronizer_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_resetSynchronizer_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_xbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_xbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_xbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_xbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_xbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_xbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_xbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_xbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_xbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_xbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_xbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_xbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_xbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_xbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_xbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_xbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _fragmenter_1_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34] wire _fragmenter_1_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_1_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_1_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34] wire [4:0] _fragmenter_1_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34] wire _fragmenter_1_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_1_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_1_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34] wire [1:0] _fragmenter_1_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34] wire [8:0] _fragmenter_1_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34] wire [20:0] _fragmenter_1_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34] wire [7:0] _fragmenter_1_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_1_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_1_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34] wire _fragmenter_1_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34] wire _reset_setter_auto_clock_out_member_allClocks_uncore_clock; // @[HasChipyardPRCI.scala:78:34] wire _reset_setter_auto_clock_out_member_allClocks_uncore_reset; // @[HasChipyardPRCI.scala:78:34] wire _reset_setter_auto_tl_in_a_ready; // @[HasChipyardPRCI.scala:78:34] wire _reset_setter_auto_tl_in_d_valid; // @[HasChipyardPRCI.scala:78:34] wire [2:0] _reset_setter_auto_tl_in_d_bits_opcode; // @[HasChipyardPRCI.scala:78:34] wire [1:0] _reset_setter_auto_tl_in_d_bits_size; // @[HasChipyardPRCI.scala:78:34] wire [8:0] _reset_setter_auto_tl_in_d_bits_source; // @[HasChipyardPRCI.scala:78:34] wire _fragmenter_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34] wire [4:0] _fragmenter_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_auto_anon_in_d_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34] wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34] wire [8:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34] wire [20:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34] wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34] wire _clock_gater_auto_clock_gater_in_1_a_ready; // @[HasChipyardPRCI.scala:73:33] wire _clock_gater_auto_clock_gater_in_1_d_valid; // @[HasChipyardPRCI.scala:73:33] wire [2:0] _clock_gater_auto_clock_gater_in_1_d_bits_opcode; // @[HasChipyardPRCI.scala:73:33] wire [1:0] _clock_gater_auto_clock_gater_in_1_d_bits_size; // @[HasChipyardPRCI.scala:73:33] wire [8:0] _clock_gater_auto_clock_gater_in_1_d_bits_source; // @[HasChipyardPRCI.scala:73:33] wire [63:0] _clock_gater_auto_clock_gater_in_1_d_bits_data; // @[HasChipyardPRCI.scala:73:33] wire _clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock; // @[HasChipyardPRCI.scala:73:33] wire _clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset; // @[HasChipyardPRCI.scala:73:33] wire _xbar_auto_anon_out_1_a_valid; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_1_a_bits_opcode; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_1_a_bits_param; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_1_a_bits_size; // @[Xbar.scala:346:26] wire [4:0] _xbar_auto_anon_out_1_a_bits_source; // @[Xbar.scala:346:26] wire [20:0] _xbar_auto_anon_out_1_a_bits_address; // @[Xbar.scala:346:26] wire [7:0] _xbar_auto_anon_out_1_a_bits_mask; // @[Xbar.scala:346:26] wire [63:0] _xbar_auto_anon_out_1_a_bits_data; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_1_a_bits_corrupt; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_1_d_ready; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_0_a_valid; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_0_a_bits_opcode; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_0_a_bits_param; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_0_a_bits_size; // @[Xbar.scala:346:26] wire [4:0] _xbar_auto_anon_out_0_a_bits_source; // @[Xbar.scala:346:26] wire [20:0] _xbar_auto_anon_out_0_a_bits_address; // @[Xbar.scala:346:26] wire [7:0] _xbar_auto_anon_out_0_a_bits_mask; // @[Xbar.scala:346:26] wire [63:0] _xbar_auto_anon_out_0_a_bits_data; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_0_a_bits_corrupt; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_0_d_ready; // @[Xbar.scala:346:26] wire auto_reset_setter_clock_in_member_allClocks_uncore_clock_0 = auto_reset_setter_clock_in_member_allClocks_uncore_clock; // @[ClockDomain.scala:14:9] wire auto_reset_setter_clock_in_member_allClocks_uncore_reset_0 = auto_reset_setter_clock_in_member_allClocks_uncore_reset; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_a_valid_0 = auto_xbar_anon_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_a_bits_opcode_0 = auto_xbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_a_bits_param_0 = auto_xbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_a_bits_size_0 = auto_xbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_xbar_anon_in_a_bits_source_0 = auto_xbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [20:0] auto_xbar_anon_in_a_bits_address_0 = auto_xbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_xbar_anon_in_a_bits_mask_0 = auto_xbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_xbar_anon_in_a_bits_data_0 = auto_xbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_a_bits_corrupt_0 = auto_xbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_ready_0 = auto_xbar_anon_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire [1:0] auto_xbar_anon_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_resetSynchronizer_out_member_allClocks_uncore_clock_0; // @[ClockDomain.scala:14:9] wire auto_resetSynchronizer_out_member_allClocks_uncore_reset_0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] TLXbar_prcibus_i1_o2_a21d64s5k1z3u xbar ( // @[Xbar.scala:346:26] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (auto_xbar_anon_in_a_ready_0), .auto_anon_in_a_valid (auto_xbar_anon_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_opcode (auto_xbar_anon_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_param (auto_xbar_anon_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_size (auto_xbar_anon_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_source (auto_xbar_anon_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_address (auto_xbar_anon_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_mask (auto_xbar_anon_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_data (auto_xbar_anon_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_corrupt (auto_xbar_anon_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_anon_in_d_ready (auto_xbar_anon_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_anon_in_d_valid (auto_xbar_anon_in_d_valid_0), .auto_anon_in_d_bits_opcode (auto_xbar_anon_in_d_bits_opcode_0), .auto_anon_in_d_bits_size (auto_xbar_anon_in_d_bits_size_0), .auto_anon_in_d_bits_source (auto_xbar_anon_in_d_bits_source_0), .auto_anon_in_d_bits_data (auto_xbar_anon_in_d_bits_data_0), .auto_anon_out_1_a_ready (_fragmenter_1_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34] .auto_anon_out_1_a_valid (_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_fragmenter_1_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34] .auto_anon_out_1_d_bits_opcode (_fragmenter_1_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34] .auto_anon_out_1_d_bits_size (_fragmenter_1_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34] .auto_anon_out_1_d_bits_source (_fragmenter_1_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34] .auto_anon_out_0_a_ready (_fragmenter_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34] .auto_anon_out_0_a_valid (_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_fragmenter_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_data (_fragmenter_auto_anon_in_d_bits_data) // @[Fragmenter.scala:345:34] ); // @[Xbar.scala:346:26] ClockGroupResetSynchronizer resetSynchronizer ( // @[ResetSynchronizer.scala:46:69] .auto_in_member_allClocks_uncore_clock (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock), // @[HasChipyardPRCI.scala:73:33] .auto_in_member_allClocks_uncore_reset (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset), // @[HasChipyardPRCI.scala:73:33] .auto_out_member_allClocks_uncore_clock (auto_resetSynchronizer_out_member_allClocks_uncore_clock_0), .auto_out_member_allClocks_uncore_reset (auto_resetSynchronizer_out_member_allClocks_uncore_reset_0) ); // @[ResetSynchronizer.scala:46:69] TileClockGater clock_gater ( // @[HasChipyardPRCI.scala:73:33] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_clock_gater_in_1_a_ready (_clock_gater_auto_clock_gater_in_1_a_ready), .auto_clock_gater_in_1_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_d_valid (_clock_gater_auto_clock_gater_in_1_d_valid), .auto_clock_gater_in_1_d_bits_opcode (_clock_gater_auto_clock_gater_in_1_d_bits_opcode), .auto_clock_gater_in_1_d_bits_size (_clock_gater_auto_clock_gater_in_1_d_bits_size), .auto_clock_gater_in_1_d_bits_source (_clock_gater_auto_clock_gater_in_1_d_bits_source), .auto_clock_gater_in_1_d_bits_data (_clock_gater_auto_clock_gater_in_1_d_bits_data), .auto_clock_gater_in_0_member_allClocks_uncore_clock (_reset_setter_auto_clock_out_member_allClocks_uncore_clock), // @[HasChipyardPRCI.scala:78:34] .auto_clock_gater_in_0_member_allClocks_uncore_reset (_reset_setter_auto_clock_out_member_allClocks_uncore_reset), // @[HasChipyardPRCI.scala:78:34] .auto_clock_gater_out_member_allClocks_uncore_clock (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock), .auto_clock_gater_out_member_allClocks_uncore_reset (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset) ); // @[HasChipyardPRCI.scala:73:33] TLFragmenter_TileClockGater fragmenter ( // @[Fragmenter.scala:345:34] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (_fragmenter_auto_anon_in_a_ready), .auto_anon_in_a_valid (_xbar_auto_anon_out_0_a_valid), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_opcode (_xbar_auto_anon_out_0_a_bits_opcode), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_param (_xbar_auto_anon_out_0_a_bits_param), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_size (_xbar_auto_anon_out_0_a_bits_size), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_source (_xbar_auto_anon_out_0_a_bits_source), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_address (_xbar_auto_anon_out_0_a_bits_address), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_mask (_xbar_auto_anon_out_0_a_bits_mask), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_data (_xbar_auto_anon_out_0_a_bits_data), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_corrupt (_xbar_auto_anon_out_0_a_bits_corrupt), // @[Xbar.scala:346:26] .auto_anon_in_d_ready (_xbar_auto_anon_out_0_d_ready), // @[Xbar.scala:346:26] .auto_anon_in_d_valid (_fragmenter_auto_anon_in_d_valid), .auto_anon_in_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), .auto_anon_in_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), .auto_anon_in_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), .auto_anon_in_d_bits_data (_fragmenter_auto_anon_in_d_bits_data), .auto_anon_out_a_ready (_clock_gater_auto_clock_gater_in_1_a_ready), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready), .auto_anon_out_d_valid (_clock_gater_auto_clock_gater_in_1_d_valid), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_opcode (_clock_gater_auto_clock_gater_in_1_d_bits_opcode), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_size (_clock_gater_auto_clock_gater_in_1_d_bits_size), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_source (_clock_gater_auto_clock_gater_in_1_d_bits_source), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_data (_clock_gater_auto_clock_gater_in_1_d_bits_data) // @[HasChipyardPRCI.scala:73:33] ); // @[Fragmenter.scala:345:34] TileResetSetter reset_setter ( // @[HasChipyardPRCI.scala:78:34] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_clock_in_member_allClocks_uncore_clock (auto_reset_setter_clock_in_member_allClocks_uncore_clock_0), // @[ClockDomain.scala:14:9] .auto_clock_in_member_allClocks_uncore_reset (auto_reset_setter_clock_in_member_allClocks_uncore_reset_0), // @[ClockDomain.scala:14:9] .auto_clock_out_member_allClocks_uncore_clock (_reset_setter_auto_clock_out_member_allClocks_uncore_clock), .auto_clock_out_member_allClocks_uncore_reset (_reset_setter_auto_clock_out_member_allClocks_uncore_reset), .auto_tl_in_a_ready (_reset_setter_auto_tl_in_a_ready), .auto_tl_in_a_valid (_fragmenter_1_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_opcode (_fragmenter_1_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_param (_fragmenter_1_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_size (_fragmenter_1_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_source (_fragmenter_1_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_address (_fragmenter_1_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_mask (_fragmenter_1_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_data (_fragmenter_1_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_corrupt (_fragmenter_1_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34] .auto_tl_in_d_ready (_fragmenter_1_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34] .auto_tl_in_d_valid (_reset_setter_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_reset_setter_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_reset_setter_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_reset_setter_auto_tl_in_d_bits_source) ); // @[HasChipyardPRCI.scala:78:34] TLFragmenter_TileResetSetter fragmenter_1 ( // @[Fragmenter.scala:345:34] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (_fragmenter_1_auto_anon_in_a_ready), .auto_anon_in_a_valid (_xbar_auto_anon_out_1_a_valid), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_opcode (_xbar_auto_anon_out_1_a_bits_opcode), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_param (_xbar_auto_anon_out_1_a_bits_param), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_size (_xbar_auto_anon_out_1_a_bits_size), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_source (_xbar_auto_anon_out_1_a_bits_source), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_address (_xbar_auto_anon_out_1_a_bits_address), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_mask (_xbar_auto_anon_out_1_a_bits_mask), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_data (_xbar_auto_anon_out_1_a_bits_data), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_corrupt (_xbar_auto_anon_out_1_a_bits_corrupt), // @[Xbar.scala:346:26] .auto_anon_in_d_ready (_xbar_auto_anon_out_1_d_ready), // @[Xbar.scala:346:26] .auto_anon_in_d_valid (_fragmenter_1_auto_anon_in_d_valid), .auto_anon_in_d_bits_opcode (_fragmenter_1_auto_anon_in_d_bits_opcode), .auto_anon_in_d_bits_size (_fragmenter_1_auto_anon_in_d_bits_size), .auto_anon_in_d_bits_source (_fragmenter_1_auto_anon_in_d_bits_source), .auto_anon_out_a_ready (_reset_setter_auto_tl_in_a_ready), // @[HasChipyardPRCI.scala:78:34] .auto_anon_out_a_valid (_fragmenter_1_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fragmenter_1_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fragmenter_1_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fragmenter_1_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fragmenter_1_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fragmenter_1_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fragmenter_1_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fragmenter_1_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fragmenter_1_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fragmenter_1_auto_anon_out_d_ready), .auto_anon_out_d_valid (_reset_setter_auto_tl_in_d_valid), // @[HasChipyardPRCI.scala:78:34] .auto_anon_out_d_bits_opcode (_reset_setter_auto_tl_in_d_bits_opcode), // @[HasChipyardPRCI.scala:78:34] .auto_anon_out_d_bits_size (_reset_setter_auto_tl_in_d_bits_size), // @[HasChipyardPRCI.scala:78:34] .auto_anon_out_d_bits_source (_reset_setter_auto_tl_in_d_bits_source) // @[HasChipyardPRCI.scala:78:34] ); // @[Fragmenter.scala:345:34] assign auto_resetSynchronizer_out_member_allClocks_uncore_clock = auto_resetSynchronizer_out_member_allClocks_uncore_clock_0; // @[ClockDomain.scala:14:9] assign auto_resetSynchronizer_out_member_allClocks_uncore_reset = auto_resetSynchronizer_out_member_allClocks_uncore_reset_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_a_ready = auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_valid = auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_bits_opcode = auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_bits_size = auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_bits_source = auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_bits_data = auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File IngressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class IngressUnit( ingressNodeId: Int, cParam: IngressChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean, ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits))) } val io = IO(new IngressUnitIO) val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2, flow=combineRCVA)) assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR)) route_buffer.io.enq.bits.head := io.in.bits.head route_buffer.io.enq.bits.tail := io.in.bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { route_buffer.io.enq.bits.flow := DontCare } else { route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U route_buffer.io.enq.bits.flow.egress_node := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNode.U) ) route_buffer.io.enq.bits.flow.egress_node_id := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNodeId.U) ) } route_buffer.io.enq.bits.payload := io.in.bits.payload route_buffer.io.enq.bits.virt_channel_id := DontCare io.router_req.bits.src_virt_id := 0.U io.router_req.bits.flow := route_buffer.io.enq.bits.flow val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U route_buffer.io.enq.valid := io.in.valid && ( io.router_req.ready || !io.in.bits.head || at_dest) io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest io.in.ready := route_buffer.io.enq.ready && ( io.router_req.ready || !io.in.bits.head || at_dest) route_q.io.enq.valid := io.router_req.fire route_q.io.enq.bits := io.router_resp when (io.in.fire && io.in.bits.head && at_dest) { route_q.io.enq.valid := true.B route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (egressParams(o).egressId.U === io.in.bits.egress_id) { route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B } } } assert(!(route_q.io.enq.valid && !route_q.io.enq.ready)) val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams), 1, pipe=true)) vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow io.vcalloc_req.bits.in_vc := 0.U val head = route_buffer.io.deq.bits.head val tail = route_buffer.io.deq.bits.tail vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid && (route_q.io.deq.valid || !head) && (io.vcalloc_req.ready || !head) ) io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid && head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready) route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready && (route_q.io.deq.valid || !head) && (io.vcalloc_req.ready || !head) && (vcalloc_q.io.enq.ready || !head)) route_q.io.deq.ready := (route_buffer.io.deq.fire && tail) vcalloc_q.io.enq.valid := io.vcalloc_req.fire vcalloc_q.io.enq.bits := io.vcalloc_resp assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready)) io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire val out_bundle = if (combineSAST) { Wire(Valid(new SwitchBundle(outParams, egressParams))) } else { Reg(Valid(new SwitchBundle(outParams, egressParams))) } io.out(0) := out_bundle out_bundle.valid := vcalloc_buffer.io.deq.fire out_bundle.bits.flit := vcalloc_buffer.io.deq.bits out_bundle.bits.flit.virt_channel_id := 0.U val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh, vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq) io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready // TODO: We should not generate input/ingress/output/egress units for untraversable channels if (!cParam.traversable) { io.in.ready := false.B io.router_req.valid := false.B io.router_req.bits := DontCare io.vcalloc_req.valid := false.B io.vcalloc_req.bits := DontCare io.salloc_req.foreach(_.valid := false.B) io.salloc_req.foreach(_.bits := DontCare) io.out.foreach(_.valid := false.B) io.out.foreach(_.bits := DontCare) } }
module IngressUnit_35( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [36:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [36:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [36:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'hE; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h6 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'hA : 4'h0); // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'h2; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'h2; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_193( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_349 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File regfile.scala: //****************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Register File (Abstract class and Synthesizable RegFile) //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.exu import scala.collection.mutable.ArrayBuffer import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ abstract class RegisterFile[T <: Data]( dType: T, numRegisters: Int, numReadPorts: Int, numWritePorts: Int) (implicit p: Parameters) extends BoomModule { val io = IO(new BoomBundle { val arb_read_reqs = Vec(numReadPorts, Flipped(Decoupled(UInt(log2Ceil(numRegisters).W)))) val rrd_read_resps = Vec(numReadPorts, Output(dType)) val write_ports = Vec(numWritePorts, Flipped(Valid(new Bundle { val addr = Output(UInt(maxPregSz.W)) val data = Output(dType) }))) }) // ensure there is only 1 writer per register (unless to preg0) if (numWritePorts > 1) { for (i <- 0 until (numWritePorts - 1)) { for (j <- (i + 1) until numWritePorts) { assert(!io.write_ports(i).valid || !io.write_ports(j).valid || (io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr), "[regfile] too many writers a register") } } } } class BankedRF[T <: Data]( dType: T, numBanks: Int, numLogicalReadPortsPerBank: Int, numRegisters: Int, numLogicalReadPorts: Int, numPhysicalReadPorts: Int, numWritePorts: Int, bankedWritePortArray: Seq[Option[Int]], typeStr: String )(implicit p: Parameters) extends RegisterFile(dType, numRegisters, numLogicalReadPorts, numWritePorts) { require(isPow2(numBanks)) require(numRegisters % numBanks == 0) require(bankedWritePortArray.length == numWritePorts) val numDedicatedWritePorts = bankedWritePortArray.flatten.length val writePortsPerBank = if (numDedicatedWritePorts == 0) { numWritePorts } else { numWritePorts - numDedicatedWritePorts + 1 } def bankIdx(i: UInt): UInt = i(log2Ceil(numBanks)-1,0) val rfs = (0 until numBanks) map { w => Module(new PartiallyPortedRF( dType, numRegisters / numBanks, numLogicalReadPortsPerBank, numPhysicalReadPorts, writePortsPerBank, typeStr + s" Bank ${w}" )) } if (numBanks == 1) { require(numLogicalReadPortsPerBank == numLogicalReadPorts) io <> rfs(0).io } else { val widxs = Array.fill(numBanks)(0) for (i <- 0 until numWritePorts) { if (bankedWritePortArray(i) != None) { val bank = bankedWritePortArray(i).get val widx = widxs(bank) rfs(bank).io.write_ports(widx).valid := io.write_ports(i).valid rfs(bank).io.write_ports(widx).bits.addr := io.write_ports(i).bits.addr >> log2Ceil(numBanks) rfs(bank).io.write_ports(widx).bits.data := io.write_ports(i).bits.data assert(!io.write_ports(i).valid || bankIdx(io.write_ports(i).bits.addr) === bank.U) widxs(bank) = widx + 1 } else { for (w <- 0 until numBanks) { val widx = widxs(w) rfs(w).io.write_ports(widx).valid := io.write_ports(i).valid && bankIdx(io.write_ports(i).bits.addr) === w.U rfs(w).io.write_ports(widx).bits.addr := io.write_ports(i).bits.addr >> log2Ceil(numBanks) rfs(w).io.write_ports(widx).bits.data := io.write_ports(i).bits.data widxs(w) = widx + 1 } } } require(widxs.forall(_ == writePortsPerBank), widxs.mkString(",")) if (numLogicalReadPortsPerBank == numLogicalReadPorts) { for (i <- 0 until numLogicalReadPorts) { val bidx = bankIdx(io.arb_read_reqs(i).bits) for (w <- 0 until numBanks) { rfs(w).io.arb_read_reqs(i).valid := io.arb_read_reqs(i).valid && bankIdx(io.arb_read_reqs(i).bits) === w.U rfs(w).io.arb_read_reqs(i).bits := io.arb_read_reqs(i).bits >> log2Ceil(numBanks) } val arb_data_sel = UIntToOH(bidx) val rrd_data_sel = RegNext(arb_data_sel) io.arb_read_reqs(i).ready := Mux1H(arb_data_sel, rfs.map(_.io.arb_read_reqs(i).ready)) io.rrd_read_resps(i) := Mux1H(rrd_data_sel, rfs.map(_.io.rrd_read_resps(i))) } } } override def toString: String = rfs.map(_.toString).mkString } class PartiallyPortedRF[T <: Data]( dType: T, numRegisters: Int, numLogicalReadPorts: Int, numPhysicalReadPorts: Int, numWritePorts: Int, typeStr: String )(implicit p: Parameters) extends RegisterFile(dType, numRegisters, numLogicalReadPorts, numWritePorts) { val rf = Module(new FullyPortedRF( dType = dType, numRegisters = numRegisters, numReadPorts = numPhysicalReadPorts, numWritePorts = numWritePorts, typeStr = "Partially Ported " + typeStr, )) rf.io.write_ports := io.write_ports val port_issued = Array.fill(numPhysicalReadPorts) { false.B } val port_addrs = Array.fill(numPhysicalReadPorts) { 0.U(log2Ceil(numRegisters).W) } val data_sels = Wire(Vec(numLogicalReadPorts , UInt(numPhysicalReadPorts.W))) data_sels := DontCare for (i <- 0 until numLogicalReadPorts) { var read_issued = false.B for (j <- 0 until numPhysicalReadPorts) { val issue_read = WireInit(false.B) val use_port = WireInit(false.B) when (!read_issued && !port_issued(j) && io.arb_read_reqs(i).valid) { issue_read := true.B use_port := true.B data_sels(i) := UIntToOH(j.U) } val was_port_issued_yet = port_issued(j) port_issued(j) = use_port || port_issued(j) port_addrs(j) = port_addrs(j) | Mux(was_port_issued_yet || !use_port, 0.U, io.arb_read_reqs(i).bits) read_issued = issue_read || read_issued } io.arb_read_reqs(i).ready := PopCount(io.arb_read_reqs.take(i).map(_.valid)) < numPhysicalReadPorts.U assert(!(io.arb_read_reqs(i).fire && !read_issued)) } for (j <- 0 until numPhysicalReadPorts) { rf.io.arb_read_reqs(j).valid := port_issued(j) rf.io.arb_read_reqs(j).bits := port_addrs(j) assert(rf.io.arb_read_reqs(j).ready) } val rrd_data_sels = RegNext(data_sels) for (i <- 0 until numLogicalReadPorts) { io.rrd_read_resps(i) := Mux1H(rrd_data_sels(i).asBools, rf.io.rrd_read_resps) } override def toString: String = rf.toString } class FullyPortedRF[T <: Data]( dType: T, numRegisters: Int, numReadPorts: Int, numWritePorts: Int, typeStr: String, )(implicit p: Parameters) extends RegisterFile(dType, numRegisters, numReadPorts, numWritePorts) { val rf_cost = (numReadPorts + numWritePorts) * (numReadPorts + 2*numWritePorts) override def toString: String = BoomCoreStringPrefix( "==" + typeStr + " Regfile==", "Num RF Read Ports : " + numReadPorts, "Num RF Write Ports : " + numWritePorts, "RF Cost (R+W)*(R+2W) : " + rf_cost) io.arb_read_reqs.map(p => p.ready := true.B) val regfile = Mem(numRegisters, dType) (0 until numReadPorts) map {p => io.rrd_read_resps(p) := regfile(RegNext(io.arb_read_reqs(p).bits)) } io.write_ports map { p => when (p.valid) { regfile(p.bits.addr) := p.bits.data }} }
module regfile_50x64( // @[regfile.scala:204:20] input [5:0] R0_addr, input R0_en, input R0_clk, output [63:0] R0_data, input [5:0] R1_addr, input R1_en, input R1_clk, output [63:0] R1_data, input [5:0] R2_addr, input R2_en, input R2_clk, output [63:0] R2_data, input [5:0] R3_addr, input R3_en, input R3_clk, output [63:0] R3_data, input [5:0] R4_addr, input R4_en, input R4_clk, output [63:0] R4_data, input [5:0] R5_addr, input R5_en, input R5_clk, output [63:0] R5_data, input [5:0] W0_addr, input W0_en, input W0_clk, input [63:0] W0_data, input [5:0] W1_addr, input W1_en, input W1_clk, input [63:0] W1_data, input [5:0] W2_addr, input W2_en, input W2_clk, input [63:0] W2_data, input [5:0] W3_addr, input W3_en, input W3_clk, input [63:0] W3_data, input [5:0] W4_addr, input W4_en, input W4_clk, input [63:0] W4_data ); reg [63:0] Memory[0:49]; // @[regfile.scala:204:20] always @(posedge W0_clk) begin // @[regfile.scala:204:20] if (W0_en & 1'h1) // @[regfile.scala:204:20] Memory[W0_addr] <= W0_data; // @[regfile.scala:204:20] if (W1_en & 1'h1) // @[regfile.scala:204:20] Memory[W1_addr] <= W1_data; // @[regfile.scala:204:20] if (W2_en & 1'h1) // @[regfile.scala:204:20] Memory[W2_addr] <= W2_data; // @[regfile.scala:204:20] if (W3_en & 1'h1) // @[regfile.scala:204:20] Memory[W3_addr] <= W3_data; // @[regfile.scala:204:20] if (W4_en & 1'h1) // @[regfile.scala:204:20] Memory[W4_addr] <= W4_data; // @[regfile.scala:204:20] always @(posedge) assign R0_data = R0_en ? Memory[R0_addr] : 64'bx; // @[regfile.scala:204:20] assign R1_data = R1_en ? Memory[R1_addr] : 64'bx; // @[regfile.scala:204:20] assign R2_data = R2_en ? Memory[R2_addr] : 64'bx; // @[regfile.scala:204:20] assign R3_data = R3_en ? Memory[R3_addr] : 64'bx; // @[regfile.scala:204:20] assign R4_data = R4_en ? Memory[R4_addr] : 64'bx; // @[regfile.scala:204:20] assign R5_data = R5_en ? Memory[R5_addr] : 64'bx; // @[regfile.scala:204:20] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File RVC.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class ExpandedInstruction extends Bundle { val bits = UInt(32.W) val rd = UInt(5.W) val rs1 = UInt(5.W) val rs2 = UInt(5.W) val rs3 = UInt(5.W) } class RVCDecoder(x: UInt, xLen: Int, fLen: Int, useAddiForMv: Boolean = false) { def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = { val res = Wire(new ExpandedInstruction) res.bits := bits res.rd := rd res.rs1 := rs1 res.rs2 := rs2 res.rs3 := rs3 res } def rs1p = Cat(1.U(2.W), x(9,7)) def rs2p = Cat(1.U(2.W), x(4,2)) def rs2 = x(6,2) def rd = x(11,7) def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W)) def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W)) def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W)) def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W)) def ldspImm = Cat(x(4,2), x(12), x(6,5), 0.U(3.W)) def swspImm = Cat(x(8,7), x(12,9), 0.U(2.W)) def sdspImm = Cat(x(9,7), x(12,10), 0.U(3.W)) def luiImm = Cat(Fill(15, x(12)), x(6,2), 0.U(12.W)) def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), 0.U(4.W)) def addiImm = Cat(Fill(7, x(12)), x(6,2)) def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), 0.U(1.W)) def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), 0.U(1.W)) def shamt = Cat(x(12), x(6,2)) def x0 = 0.U(5.W) def ra = 1.U(5.W) def sp = 2.U(5.W) def q0 = { def addi4spn = { val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W)) inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p) } def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p) def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p) def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) def flw = { if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) else ld } def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p) def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) def fsw = { if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) else sd } Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw) } def q1 = { def addi = inst(Cat(addiImm, rd, 0.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2p) def addiw = { val opc = Mux(rd.orR, 0x1B.U(7.W), 0x1F.U(7.W)) inst(Cat(addiImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p) } def jal = { if (xLen == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, 0x6F.U(7.W)), ra, rd, rs2p) else addiw } def li = inst(Cat(addiImm, x0, 0.U(3.W), rd, 0x13.U(7.W)), rd, x0, rs2p) def addi16sp = { val opc = Mux(addiImm.orR, 0x13.U(7.W), 0x1F.U(7.W)) inst(Cat(addi16spImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p) } def lui = { val opc = Mux(addiImm.orR, 0x37.U(7.W), 0x3F.U(7.W)) val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p) Mux(rd === x0 || rd === sp, addi16sp, me) } def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, 0x6F.U(7.W)), x0, rs1p, rs2p) def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0) def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0) def arith = { def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W)) def srai = srli | (1 << 30).U def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W)) def rtype = { val funct = Seq(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5))) val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U) val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W)) Cat(rs2p, rs1p, funct, rs1p, opc) | sub } inst(Seq(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p) } Seq(addi, jal, li, lui, arith, j, beqz, bnez) } def q2 = { val load_opc = Mux(rd.orR, 0x03.U(7.W), 0x1F.U(7.W)) def slli = inst(Cat(shamt, rd, 1.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2) def ldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, load_opc), rd, sp, rs2) def lwsp = inst(Cat(lwspImm, sp, 2.U(3.W), rd, load_opc), rd, sp, rs2) def fldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2) def flwsp = { if (xLen == 32) inst(Cat(lwspImm, sp, 2.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2) else ldsp } def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x23.U(7.W)), rd, sp, rs2) def swsp = inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x23.U(7.W)), rd, sp, rs2) def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x27.U(7.W)), rd, sp, rs2) def fswsp = { if (xLen == 32) inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x27.U(7.W)), rd, sp, rs2) else sdsp } def jalr = { val mv = { if (useAddiForMv) inst(Cat(rs2, 0.U(3.W), rd, 0x13.U(7.W)), rd, rs2, x0) else inst(Cat(rs2, x0, 0.U(3.W), rd, 0x33.U(7.W)), rd, x0, rs2) } val add = inst(Cat(rs2, rd, 0.U(3.W), rd, 0x33.U(7.W)), rd, rd, rs2) val jr = Cat(rs2, rd, 0.U(3.W), x0, 0x67.U(7.W)) val reserved = Cat(jr >> 7, 0x1F.U(7.W)) val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2) val jr_mv = Mux(rs2.orR, mv, jr_reserved) val jalr = Cat(rs2, rd, 0.U(3.W), ra, 0x67.U(7.W)) val ebreak = Cat(jr >> 7, 0x73.U(7.W)) | (1 << 20).U val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2) val jalr_add = Mux(rs2.orR, add, jalr_ebreak) Mux(x(12), jalr_add, jr_mv) } Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp) } def q3 = Seq.fill(8)(passthrough) def passthrough = inst(x) def decode = { val s = q0 ++ q1 ++ q2 ++ q3 s(Cat(x(1,0), x(15,13))) } def q0_ill = { def allz = !(x(12, 2).orR) def fld = if (fLen >= 64) false.B else true.B def flw32 = if (xLen == 64 || fLen >= 32) false.B else true.B def fsd = if (fLen >= 64) false.B else true.B def fsw32 = if (xLen == 64 || fLen >= 32) false.B else true.B Seq(allz, fld, false.B, flw32, true.B, fsd, false.B, fsw32) } def q1_ill = { def rd0 = if (xLen == 32) false.B else rd === 0.U def immz = !(x(12) | x(6, 2).orR) def arith_res = x(12, 10).andR && (if (xLen == 32) true.B else x(6) === 1.U) Seq(false.B, rd0, false.B, immz, arith_res, false.B, false.B, false.B) } def q2_ill = { def fldsp = if (fLen >= 64) false.B else true.B def rd0 = rd === 0.U def flwsp = if (xLen == 64) rd0 else if (fLen >= 32) false.B else true.B def jr_res = !(x(12 ,2).orR) def fsdsp = if (fLen >= 64) false.B else true.B def fswsp32 = if (xLen == 64) false.B else if (fLen >= 32) false.B else true.B Seq(false.B, fldsp, rd0, flwsp, jr_res, fsdsp, false.B, fswsp32) } def q3_ill = Seq.fill(8)(false.B) def ill = { val s = q0_ill ++ q1_ill ++ q2_ill ++ q3_ill s(Cat(x(1,0), x(15,13))) } } class RVCExpander(useAddiForMv: Boolean = false)(implicit val p: Parameters) extends Module with HasCoreParameters { val io = IO(new Bundle { val in = Input(UInt(32.W)) val out = Output(new ExpandedInstruction) val rvc = Output(Bool()) val ill = Output(Bool()) }) if (usingCompressed) { io.rvc := io.in(1,0) =/= 3.U val decoder = new RVCDecoder(io.in, xLen, fLen, useAddiForMv) io.out := decoder.decode io.ill := decoder.ill } else { io.rvc := false.B io.out := new RVCDecoder(io.in, xLen, fLen, useAddiForMv).passthrough io.ill := false.B // only used for RVC } }
module RVCExpander_6( // @[RVC.scala:190:7] input clock, // @[RVC.scala:190:7] input reset, // @[RVC.scala:190:7] input [31:0] io_in, // @[RVC.scala:191:14] output [31:0] io_out_bits, // @[RVC.scala:191:14] output [4:0] io_out_rd, // @[RVC.scala:191:14] output [4:0] io_out_rs1, // @[RVC.scala:191:14] output [4:0] io_out_rs2, // @[RVC.scala:191:14] output [4:0] io_out_rs3, // @[RVC.scala:191:14] output io_rvc // @[RVC.scala:191:14] ); wire [31:0] io_in_0 = io_in; // @[RVC.scala:190:7] wire [11:0] io_out_s_jr_lo = 12'h67; // @[RVC.scala:135:19] wire [4:0] io_out_s_10_rs1 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_13_rd = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_14_rs2 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_15_rd = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_15_rs2 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_mv_rs1 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_jr_reserved_rd = 5'h0; // @[RVC.scala:21:19] wire [11:0] io_out_s_jalr_lo = 12'hE7; // @[RVC.scala:139:21] wire [4:0] io_out_s_jalr_ebreak_rd = 5'h1; // @[package.scala:39:86] wire [4:0] io_out_s_0_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_17_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_18_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_19_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_21_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_22_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_23_rs1 = 5'h2; // @[package.scala:39:86] wire [31:0] io_out_s_24_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_25_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_26_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_27_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_28_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_29_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_30_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_31_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] _io_out_T_64_bits; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rd; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs1; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs2; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs3; // @[package.scala:39:76] wire _io_rvc_T_1; // @[RVC.scala:199:26] wire _io_ill_T_64; // @[package.scala:39:76] wire [31:0] io_out_bits_0; // @[RVC.scala:190:7] wire [4:0] io_out_rd_0; // @[RVC.scala:190:7] wire [4:0] io_out_rs1_0; // @[RVC.scala:190:7] wire [4:0] io_out_rs2_0; // @[RVC.scala:190:7] wire [4:0] io_out_rs3_0; // @[RVC.scala:190:7] wire io_rvc_0; // @[RVC.scala:190:7] wire io_ill; // @[RVC.scala:190:7] wire [1:0] _io_rvc_T = io_in_0[1:0]; // @[RVC.scala:190:7, :199:20] wire [1:0] _io_out_T = io_in_0[1:0]; // @[RVC.scala:154:12, :190:7, :199:20] wire [1:0] _io_ill_T = io_in_0[1:0]; // @[RVC.scala:186:12, :190:7, :199:20] assign _io_rvc_T_1 = _io_rvc_T != 2'h3; // @[RVC.scala:199:{20,26}] assign io_rvc_0 = _io_rvc_T_1; // @[RVC.scala:190:7, :199:26] wire [7:0] _io_out_s_opc_T = io_in_0[12:5]; // @[RVC.scala:53:22, :190:7] wire _io_out_s_opc_T_1 = |_io_out_s_opc_T; // @[RVC.scala:53:{22,29}] wire [6:0] io_out_s_opc = _io_out_s_opc_T_1 ? 7'h13 : 7'h1F; // @[RVC.scala:53:{20,29}] wire [3:0] _io_out_s_T = io_in_0[10:7]; // @[RVC.scala:34:26, :190:7] wire [1:0] _io_out_s_T_1 = io_in_0[12:11]; // @[RVC.scala:34:35, :190:7] wire _io_out_s_T_2 = io_in_0[5]; // @[RVC.scala:34:45, :190:7] wire _io_out_s_T_28 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_59 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_68 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_101 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_110 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_185 = io_in_0[5]; // @[RVC.scala:34:45, :42:50, :190:7] wire _io_out_s_T_3 = io_in_0[6]; // @[RVC.scala:34:51, :190:7] wire _io_out_s_T_30 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_61 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_70 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_103 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_112 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_187 = io_in_0[6]; // @[RVC.scala:34:51, :42:62, :190:7] wire _io_out_s_T_249 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_260 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_271 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_282 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_ill_s_T_9 = io_in_0[6]; // @[RVC.scala:34:51, :169:69, :190:7] wire [2:0] io_out_s_lo = {_io_out_s_T_3, 2'h0}; // @[RVC.scala:34:{24,51}] wire [5:0] io_out_s_hi_hi = {_io_out_s_T, _io_out_s_T_1}; // @[RVC.scala:34:{24,26,35}] wire [6:0] io_out_s_hi = {io_out_s_hi_hi, _io_out_s_T_2}; // @[RVC.scala:34:{24,45}] wire [9:0] _io_out_s_T_4 = {io_out_s_hi, io_out_s_lo}; // @[RVC.scala:34:24] wire [2:0] _io_out_s_T_5 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_8 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_10 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_18 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_21 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_25 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_34 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_37 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_41 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_49 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_52 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_56 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_64 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_74 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_78 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_85 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_94 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_98 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_106 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_116 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_120 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_127 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_136 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_140 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_152 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_164 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_174 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_me_T_9 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_194 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_223 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_242 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_292 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_383 = io_in_0[4:2]; // @[RVC.scala:31:29, :38:22, :190:7] wire [2:0] _io_out_s_T_401 = io_in_0[4:2]; // @[RVC.scala:31:29, :38:22, :190:7] wire [4:0] _io_out_s_T_6 = {2'h1, _io_out_s_T_5}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_1 = {_io_out_s_T_6, io_out_s_opc}; // @[RVC.scala:31:17, :53:20, :54:15] wire [14:0] io_out_s_hi_hi_1 = {_io_out_s_T_4, 5'h2}; // @[package.scala:39:86] wire [17:0] io_out_s_hi_1 = {io_out_s_hi_hi_1, 3'h0}; // @[RVC.scala:54:15] wire [29:0] _io_out_s_T_7 = {io_out_s_hi_1, io_out_s_lo_1}; // @[RVC.scala:54:15] wire [4:0] _io_out_s_T_9 = {2'h1, _io_out_s_T_8}; // @[package.scala:39:86] wire [4:0] io_out_s_0_rd = _io_out_s_T_9; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_11 = {2'h1, _io_out_s_T_10}; // @[package.scala:39:86] wire [4:0] io_out_s_0_rs2 = _io_out_s_T_11; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_12 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_27 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_43 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_58 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_80 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_100 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_122 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_142 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_154 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_166 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_176 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_me_T_11 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_196 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_244 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_294 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_334 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_372 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_382 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_391 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_400 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_409 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_mv_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_add_T_7 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_jr_reserved_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_423 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_436 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_449 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_453 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_457 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_461 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_465 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_469 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_473 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_477 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_481 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] io_out_s_0_rs3 = _io_out_s_T_12; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_0_bits; // @[RVC.scala:21:19] assign io_out_s_0_bits = {2'h0, _io_out_s_T_7}; // @[RVC.scala:21:19, :22:14, :54:15] wire [1:0] _io_out_s_T_13 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_44 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_81 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_89 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_123 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_131 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_funct_T_1 = io_in_0[6:5]; // @[RVC.scala:36:20, :102:77, :190:7] wire [1:0] _io_out_s_sub_T = io_in_0[6:5]; // @[RVC.scala:36:20, :103:24, :190:7] wire [1:0] _io_out_s_T_297 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_305 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_315 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_323 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_337 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_345 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_355 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_363 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_385 = io_in_0[6:5]; // @[RVC.scala:36:20, :38:37, :190:7] wire [1:0] _io_out_s_T_403 = io_in_0[6:5]; // @[RVC.scala:36:20, :38:37, :190:7] wire [2:0] _io_out_s_T_14 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_29 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_45 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_60 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_69 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_82 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_90 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_102 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_111 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_124 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_132 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_412 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_417 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_438 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_443 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_ill_s_T_7 = io_in_0[12:10]; // @[RVC.scala:36:28, :169:22, :190:7] wire [4:0] io_out_s_hi_2 = {_io_out_s_T_13, _io_out_s_T_14}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_15 = {io_out_s_hi_2, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_16 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_23 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_32 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_39 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_47 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_54 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_66 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_76 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_87 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_96 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_108 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_118 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_129 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_138 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_200 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_202 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_208 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_210 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_218 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_220 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_225 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_227 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_238 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_240 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_290 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_311 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_330 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_332 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_351 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_370 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_411 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_416 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_437 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_442 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [4:0] _io_out_s_T_17 = {2'h1, _io_out_s_T_16}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_19 = {2'h1, _io_out_s_T_18}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_2 = {_io_out_s_T_19, 7'h7}; // @[RVC.scala:31:17, :58:23] wire [12:0] io_out_s_hi_hi_2 = {_io_out_s_T_15, _io_out_s_T_17}; // @[RVC.scala:30:17, :36:18, :58:23] wire [15:0] io_out_s_hi_3 = {io_out_s_hi_hi_2, 3'h3}; // @[RVC.scala:58:23] wire [27:0] _io_out_s_T_20 = {io_out_s_hi_3, io_out_s_lo_2}; // @[RVC.scala:58:23] wire [4:0] _io_out_s_T_22 = {2'h1, _io_out_s_T_21}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rd = _io_out_s_T_22; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_24 = {2'h1, _io_out_s_T_23}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rs1 = _io_out_s_T_24; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_26 = {2'h1, _io_out_s_T_25}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rs2 = _io_out_s_T_26; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_1_rs3 = _io_out_s_T_27; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_1_bits; // @[RVC.scala:21:19] assign io_out_s_1_bits = {4'h0, _io_out_s_T_20}; // @[RVC.scala:21:19, :22:14, :58:23] wire [2:0] io_out_s_lo_3 = {_io_out_s_T_30, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_4 = {_io_out_s_T_28, _io_out_s_T_29}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_31 = {io_out_s_hi_4, io_out_s_lo_3}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_33 = {2'h1, _io_out_s_T_32}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_35 = {2'h1, _io_out_s_T_34}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_4 = {_io_out_s_T_35, 7'h3}; // @[RVC.scala:31:17, :57:22] wire [11:0] io_out_s_hi_hi_3 = {_io_out_s_T_31, _io_out_s_T_33}; // @[RVC.scala:30:17, :35:18, :57:22] wire [14:0] io_out_s_hi_5 = {io_out_s_hi_hi_3, 3'h2}; // @[package.scala:39:86] wire [26:0] _io_out_s_T_36 = {io_out_s_hi_5, io_out_s_lo_4}; // @[RVC.scala:57:22] wire [4:0] _io_out_s_T_38 = {2'h1, _io_out_s_T_37}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rd = _io_out_s_T_38; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_40 = {2'h1, _io_out_s_T_39}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rs1 = _io_out_s_T_40; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_42 = {2'h1, _io_out_s_T_41}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rs2 = _io_out_s_T_42; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_2_rs3 = _io_out_s_T_43; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_2_bits; // @[RVC.scala:21:19] assign io_out_s_2_bits = {5'h0, _io_out_s_T_36}; // @[RVC.scala:21:19, :22:14, :57:22] wire [4:0] io_out_s_hi_6 = {_io_out_s_T_44, _io_out_s_T_45}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_46 = {io_out_s_hi_6, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_48 = {2'h1, _io_out_s_T_47}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_50 = {2'h1, _io_out_s_T_49}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_5 = {_io_out_s_T_50, 7'h3}; // @[RVC.scala:31:17, :56:22] wire [12:0] io_out_s_hi_hi_4 = {_io_out_s_T_46, _io_out_s_T_48}; // @[RVC.scala:30:17, :36:18, :56:22] wire [15:0] io_out_s_hi_7 = {io_out_s_hi_hi_4, 3'h3}; // @[RVC.scala:56:22] wire [27:0] _io_out_s_T_51 = {io_out_s_hi_7, io_out_s_lo_5}; // @[RVC.scala:56:22] wire [4:0] _io_out_s_T_53 = {2'h1, _io_out_s_T_52}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rd = _io_out_s_T_53; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_55 = {2'h1, _io_out_s_T_54}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rs1 = _io_out_s_T_55; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_57 = {2'h1, _io_out_s_T_56}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rs2 = _io_out_s_T_57; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_3_rs3 = _io_out_s_T_58; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_3_bits; // @[RVC.scala:21:19] assign io_out_s_3_bits = {4'h0, _io_out_s_T_51}; // @[RVC.scala:21:19, :22:14, :56:22] wire [2:0] io_out_s_lo_6 = {_io_out_s_T_61, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_8 = {_io_out_s_T_59, _io_out_s_T_60}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_62 = {io_out_s_hi_8, io_out_s_lo_6}; // @[RVC.scala:35:18] wire [1:0] _io_out_s_T_63 = _io_out_s_T_62[6:5]; // @[RVC.scala:35:18, :63:32] wire [4:0] _io_out_s_T_65 = {2'h1, _io_out_s_T_64}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_67 = {2'h1, _io_out_s_T_66}; // @[package.scala:39:86] wire [2:0] io_out_s_lo_7 = {_io_out_s_T_70, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_9 = {_io_out_s_T_68, _io_out_s_T_69}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_71 = {io_out_s_hi_9, io_out_s_lo_7}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_72 = _io_out_s_T_71[4:0]; // @[RVC.scala:35:18, :63:65] wire [7:0] io_out_s_lo_hi = {3'h2, _io_out_s_T_72}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_8 = {io_out_s_lo_hi, 7'h3F}; // @[RVC.scala:63:25] wire [6:0] io_out_s_hi_hi_5 = {_io_out_s_T_63, _io_out_s_T_65}; // @[RVC.scala:31:17, :63:{25,32}] wire [11:0] io_out_s_hi_10 = {io_out_s_hi_hi_5, _io_out_s_T_67}; // @[RVC.scala:30:17, :63:25] wire [26:0] _io_out_s_T_73 = {io_out_s_hi_10, io_out_s_lo_8}; // @[RVC.scala:63:25] wire [4:0] _io_out_s_T_75 = {2'h1, _io_out_s_T_74}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rd = _io_out_s_T_75; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_77 = {2'h1, _io_out_s_T_76}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rs1 = _io_out_s_T_77; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_79 = {2'h1, _io_out_s_T_78}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rs2 = _io_out_s_T_79; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_4_rs3 = _io_out_s_T_80; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_4_bits; // @[RVC.scala:21:19] assign io_out_s_4_bits = {5'h0, _io_out_s_T_73}; // @[RVC.scala:21:19, :22:14, :63:25] wire [4:0] io_out_s_hi_11 = {_io_out_s_T_81, _io_out_s_T_82}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_83 = {io_out_s_hi_11, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_84 = _io_out_s_T_83[7:5]; // @[RVC.scala:36:18, :66:30] wire [4:0] _io_out_s_T_86 = {2'h1, _io_out_s_T_85}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_88 = {2'h1, _io_out_s_T_87}; // @[package.scala:39:86] wire [4:0] io_out_s_hi_12 = {_io_out_s_T_89, _io_out_s_T_90}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_91 = {io_out_s_hi_12, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_92 = _io_out_s_T_91[4:0]; // @[RVC.scala:36:18, :66:63] wire [7:0] io_out_s_lo_hi_1 = {3'h3, _io_out_s_T_92}; // @[RVC.scala:66:{23,63}] wire [14:0] io_out_s_lo_9 = {io_out_s_lo_hi_1, 7'h27}; // @[RVC.scala:66:23] wire [7:0] io_out_s_hi_hi_6 = {_io_out_s_T_84, _io_out_s_T_86}; // @[RVC.scala:31:17, :66:{23,30}] wire [12:0] io_out_s_hi_13 = {io_out_s_hi_hi_6, _io_out_s_T_88}; // @[RVC.scala:30:17, :66:23] wire [27:0] _io_out_s_T_93 = {io_out_s_hi_13, io_out_s_lo_9}; // @[RVC.scala:66:23] wire [4:0] _io_out_s_T_95 = {2'h1, _io_out_s_T_94}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rd = _io_out_s_T_95; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_97 = {2'h1, _io_out_s_T_96}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rs1 = _io_out_s_T_97; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_99 = {2'h1, _io_out_s_T_98}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rs2 = _io_out_s_T_99; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_5_rs3 = _io_out_s_T_100; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_5_bits; // @[RVC.scala:21:19] assign io_out_s_5_bits = {4'h0, _io_out_s_T_93}; // @[RVC.scala:21:19, :22:14, :66:23] wire [2:0] io_out_s_lo_10 = {_io_out_s_T_103, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_14 = {_io_out_s_T_101, _io_out_s_T_102}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_104 = {io_out_s_hi_14, io_out_s_lo_10}; // @[RVC.scala:35:18] wire [1:0] _io_out_s_T_105 = _io_out_s_T_104[6:5]; // @[RVC.scala:35:18, :65:29] wire [4:0] _io_out_s_T_107 = {2'h1, _io_out_s_T_106}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_109 = {2'h1, _io_out_s_T_108}; // @[package.scala:39:86] wire [2:0] io_out_s_lo_11 = {_io_out_s_T_112, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_15 = {_io_out_s_T_110, _io_out_s_T_111}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_113 = {io_out_s_hi_15, io_out_s_lo_11}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_114 = _io_out_s_T_113[4:0]; // @[RVC.scala:35:18, :65:62] wire [7:0] io_out_s_lo_hi_2 = {3'h2, _io_out_s_T_114}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_12 = {io_out_s_lo_hi_2, 7'h23}; // @[RVC.scala:65:22] wire [6:0] io_out_s_hi_hi_7 = {_io_out_s_T_105, _io_out_s_T_107}; // @[RVC.scala:31:17, :65:{22,29}] wire [11:0] io_out_s_hi_16 = {io_out_s_hi_hi_7, _io_out_s_T_109}; // @[RVC.scala:30:17, :65:22] wire [26:0] _io_out_s_T_115 = {io_out_s_hi_16, io_out_s_lo_12}; // @[RVC.scala:65:22] wire [4:0] _io_out_s_T_117 = {2'h1, _io_out_s_T_116}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rd = _io_out_s_T_117; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_119 = {2'h1, _io_out_s_T_118}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rs1 = _io_out_s_T_119; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_121 = {2'h1, _io_out_s_T_120}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rs2 = _io_out_s_T_121; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_6_rs3 = _io_out_s_T_122; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_6_bits; // @[RVC.scala:21:19] assign io_out_s_6_bits = {5'h0, _io_out_s_T_115}; // @[RVC.scala:21:19, :22:14, :65:22] wire [4:0] io_out_s_hi_17 = {_io_out_s_T_123, _io_out_s_T_124}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_125 = {io_out_s_hi_17, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_126 = _io_out_s_T_125[7:5]; // @[RVC.scala:36:18, :64:29] wire [4:0] _io_out_s_T_128 = {2'h1, _io_out_s_T_127}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_130 = {2'h1, _io_out_s_T_129}; // @[package.scala:39:86] wire [4:0] io_out_s_hi_18 = {_io_out_s_T_131, _io_out_s_T_132}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_133 = {io_out_s_hi_18, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_134 = _io_out_s_T_133[4:0]; // @[RVC.scala:36:18, :64:62] wire [7:0] io_out_s_lo_hi_3 = {3'h3, _io_out_s_T_134}; // @[RVC.scala:64:{22,62}] wire [14:0] io_out_s_lo_13 = {io_out_s_lo_hi_3, 7'h23}; // @[RVC.scala:64:22] wire [7:0] io_out_s_hi_hi_8 = {_io_out_s_T_126, _io_out_s_T_128}; // @[RVC.scala:31:17, :64:{22,29}] wire [12:0] io_out_s_hi_19 = {io_out_s_hi_hi_8, _io_out_s_T_130}; // @[RVC.scala:30:17, :64:22] wire [27:0] _io_out_s_T_135 = {io_out_s_hi_19, io_out_s_lo_13}; // @[RVC.scala:64:22] wire [4:0] _io_out_s_T_137 = {2'h1, _io_out_s_T_136}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rd = _io_out_s_T_137; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_139 = {2'h1, _io_out_s_T_138}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rs1 = _io_out_s_T_139; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_141 = {2'h1, _io_out_s_T_140}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rs2 = _io_out_s_T_141; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_7_rs3 = _io_out_s_T_142; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_7_bits; // @[RVC.scala:21:19] assign io_out_s_7_bits = {4'h0, _io_out_s_T_135}; // @[RVC.scala:21:19, :22:14, :64:22] wire _io_out_s_T_143 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_155 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_167 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_opc_T_4 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_me_T = io_in_0[12]; // @[RVC.scala:41:30, :43:30, :190:7] wire _io_out_s_opc_T_9 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_182 = io_in_0[12]; // @[RVC.scala:42:34, :43:30, :190:7] wire _io_out_s_T_197 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_205 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_214 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_funct_T = io_in_0[12]; // @[RVC.scala:43:30, :102:70, :190:7] wire _io_out_s_opc_T_14 = io_in_0[12]; // @[RVC.scala:43:30, :104:24, :190:7] wire _io_out_s_T_245 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_256 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_267 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_278 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_295 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_303 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_313 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_321 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_335 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_343 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_353 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_361 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_373 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_384 = io_in_0[12]; // @[RVC.scala:38:30, :43:30, :190:7] wire _io_out_s_T_393 = io_in_0[12]; // @[RVC.scala:37:30, :43:30, :190:7] wire _io_out_s_T_402 = io_in_0[12]; // @[RVC.scala:38:30, :43:30, :190:7] wire _io_out_s_T_410 = io_in_0[12]; // @[RVC.scala:43:30, :143:12, :190:7] wire _io_ill_s_T_3 = io_in_0[12]; // @[RVC.scala:43:30, :168:19, :190:7] wire [6:0] _io_out_s_T_144 = {7{_io_out_s_T_143}}; // @[RVC.scala:43:{25,30}] wire [4:0] _io_out_s_T_145 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_157 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_169 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_opc_T_6 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_me_T_2 = io_in_0[6:2]; // @[RVC.scala:41:38, :43:38, :190:7] wire [4:0] _io_out_s_opc_T_11 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_198 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_206 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_216 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_374 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_381 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_390 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_399 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_408 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_mv_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_mv_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_add_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_add_T_6 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_reserved_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_mv_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_add_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_415 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_422 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_428 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_435 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_441 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_448 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_ill_s_T_4 = io_in_0[6:2]; // @[RVC.scala:43:38, :168:27, :190:7] wire [11:0] _io_out_s_T_146 = {_io_out_s_T_144, _io_out_s_T_145}; // @[RVC.scala:43:{20,25,38}] wire [4:0] _io_out_s_T_147 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_148 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_150 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_151 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_opc_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_159 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_160 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_162 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_163 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_171 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_173 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_5 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_7 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_8 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_177 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_179 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_189 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_190 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_192 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_193 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_load_opc_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_376 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_377 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_379 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_380 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_387 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_389 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_396 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_398 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_405 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_407 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_mv_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_mv_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_4 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_5 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_reserved_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_reserved_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_421 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_434 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_447 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_450 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_454 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_458 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_462 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_466 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_470 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_474 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_478 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_ill_s_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_ill_s_T_11 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_ill_s_T_12 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [11:0] io_out_s_lo_14 = {_io_out_s_T_148, 7'h13}; // @[RVC.scala:33:13, :75:24] wire [16:0] io_out_s_hi_hi_9 = {_io_out_s_T_146, _io_out_s_T_147}; // @[RVC.scala:33:13, :43:20, :75:24] wire [19:0] io_out_s_hi_20 = {io_out_s_hi_hi_9, 3'h0}; // @[RVC.scala:75:24] wire [31:0] _io_out_s_T_149 = {io_out_s_hi_20, io_out_s_lo_14}; // @[RVC.scala:75:24] wire [31:0] io_out_s_8_bits = _io_out_s_T_149; // @[RVC.scala:21:19, :75:24] wire [4:0] io_out_s_8_rd = _io_out_s_T_150; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_8_rs1 = _io_out_s_T_151; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_153 = {2'h1, _io_out_s_T_152}; // @[package.scala:39:86] wire [4:0] io_out_s_8_rs2 = _io_out_s_T_153; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_8_rs3 = _io_out_s_T_154; // @[RVC.scala:20:101, :21:19] wire _io_out_s_opc_T_3 = |_io_out_s_opc_T_2; // @[RVC.scala:33:13, :77:24] wire [6:0] io_out_s_opc_1 = {4'h3, ~_io_out_s_opc_T_3, 2'h3}; // @[RVC.scala:77:{20,24}] wire [6:0] _io_out_s_T_156 = {7{_io_out_s_T_155}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_158 = {_io_out_s_T_156, _io_out_s_T_157}; // @[RVC.scala:43:{20,25,38}] wire [11:0] io_out_s_lo_15 = {_io_out_s_T_160, io_out_s_opc_1}; // @[RVC.scala:33:13, :77:20, :78:15] wire [16:0] io_out_s_hi_hi_10 = {_io_out_s_T_158, _io_out_s_T_159}; // @[RVC.scala:33:13, :43:20, :78:15] wire [19:0] io_out_s_hi_21 = {io_out_s_hi_hi_10, 3'h0}; // @[RVC.scala:78:15] wire [31:0] _io_out_s_T_161 = {io_out_s_hi_21, io_out_s_lo_15}; // @[RVC.scala:78:15] wire [31:0] io_out_s_9_bits = _io_out_s_T_161; // @[RVC.scala:21:19, :78:15] wire [4:0] io_out_s_9_rd = _io_out_s_T_162; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_9_rs1 = _io_out_s_T_163; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_165 = {2'h1, _io_out_s_T_164}; // @[package.scala:39:86] wire [4:0] io_out_s_9_rs2 = _io_out_s_T_165; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_9_rs3 = _io_out_s_T_166; // @[RVC.scala:20:101, :21:19] wire [6:0] _io_out_s_T_168 = {7{_io_out_s_T_167}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_170 = {_io_out_s_T_168, _io_out_s_T_169}; // @[RVC.scala:43:{20,25,38}] wire [11:0] io_out_s_lo_16 = {_io_out_s_T_171, 7'h13}; // @[RVC.scala:33:13, :84:22] wire [16:0] io_out_s_hi_hi_11 = {_io_out_s_T_170, 5'h0}; // @[RVC.scala:43:20, :84:22] wire [19:0] io_out_s_hi_22 = {io_out_s_hi_hi_11, 3'h0}; // @[RVC.scala:84:22] wire [31:0] _io_out_s_T_172 = {io_out_s_hi_22, io_out_s_lo_16}; // @[RVC.scala:84:22] wire [31:0] io_out_s_10_bits = _io_out_s_T_172; // @[RVC.scala:21:19, :84:22] wire [4:0] io_out_s_10_rd = _io_out_s_T_173; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_175 = {2'h1, _io_out_s_T_174}; // @[package.scala:39:86] wire [4:0] io_out_s_10_rs2 = _io_out_s_T_175; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_10_rs3 = _io_out_s_T_176; // @[RVC.scala:20:101, :21:19] wire [6:0] _io_out_s_opc_T_5 = {7{_io_out_s_opc_T_4}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_opc_T_7 = {_io_out_s_opc_T_5, _io_out_s_opc_T_6}; // @[RVC.scala:43:{20,25,38}] wire _io_out_s_opc_T_8 = |_io_out_s_opc_T_7; // @[RVC.scala:43:20, :90:29] wire [6:0] io_out_s_opc_2 = {3'h3, ~_io_out_s_opc_T_8, 3'h7}; // @[RVC.scala:90:{20,29}] wire [14:0] _io_out_s_me_T_1 = {15{_io_out_s_me_T}}; // @[RVC.scala:41:{24,30}] wire [19:0] io_out_s_me_hi = {_io_out_s_me_T_1, _io_out_s_me_T_2}; // @[RVC.scala:41:{19,24,38}] wire [31:0] _io_out_s_me_T_3 = {io_out_s_me_hi, 12'h0}; // @[RVC.scala:41:19] wire [19:0] _io_out_s_me_T_4 = _io_out_s_me_T_3[31:12]; // @[RVC.scala:41:19, :91:31] wire [24:0] io_out_s_me_hi_1 = {_io_out_s_me_T_4, _io_out_s_me_T_5}; // @[RVC.scala:33:13, :91:{24,31}] wire [31:0] _io_out_s_me_T_6 = {io_out_s_me_hi_1, io_out_s_opc_2}; // @[RVC.scala:90:20, :91:24] wire [31:0] io_out_s_me_bits = _io_out_s_me_T_6; // @[RVC.scala:21:19, :91:24] wire [4:0] io_out_s_me_rd = _io_out_s_me_T_7; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_me_rs1 = _io_out_s_me_T_8; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_me_T_10 = {2'h1, _io_out_s_me_T_9}; // @[package.scala:39:86] wire [4:0] io_out_s_me_rs2 = _io_out_s_me_T_10; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_me_rs3 = _io_out_s_me_T_11; // @[RVC.scala:20:101, :21:19] wire _io_out_s_T_178 = _io_out_s_T_177 == 5'h0; // @[RVC.scala:33:13, :92:14] wire _io_out_s_T_180 = _io_out_s_T_179 == 5'h2; // @[package.scala:39:86] wire _io_out_s_T_181 = _io_out_s_T_178 | _io_out_s_T_180; // @[RVC.scala:92:{14,21,27}] wire [6:0] _io_out_s_opc_T_10 = {7{_io_out_s_opc_T_9}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_opc_T_12 = {_io_out_s_opc_T_10, _io_out_s_opc_T_11}; // @[RVC.scala:43:{20,25,38}] wire _io_out_s_opc_T_13 = |_io_out_s_opc_T_12; // @[RVC.scala:43:20, :86:29] wire [6:0] io_out_s_opc_3 = _io_out_s_opc_T_13 ? 7'h13 : 7'h1F; // @[RVC.scala:86:{20,29}] wire [2:0] _io_out_s_T_183 = {3{_io_out_s_T_182}}; // @[RVC.scala:42:{29,34}] wire [1:0] _io_out_s_T_184 = io_in_0[4:3]; // @[RVC.scala:42:42, :190:7] wire [1:0] _io_out_s_T_300 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_308 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_318 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_326 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_340 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_348 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_358 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_366 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire _io_out_s_T_186 = io_in_0[2]; // @[RVC.scala:42:56, :190:7] wire _io_out_s_T_251 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_262 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_273 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_284 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_298 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_306 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_316 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_324 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_338 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_346 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_356 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_364 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire [1:0] io_out_s_lo_hi_4 = {_io_out_s_T_186, _io_out_s_T_187}; // @[RVC.scala:42:{24,56,62}] wire [5:0] io_out_s_lo_17 = {io_out_s_lo_hi_4, 4'h0}; // @[RVC.scala:42:24] wire [4:0] io_out_s_hi_hi_12 = {_io_out_s_T_183, _io_out_s_T_184}; // @[RVC.scala:42:{24,29,42}] wire [5:0] io_out_s_hi_23 = {io_out_s_hi_hi_12, _io_out_s_T_185}; // @[RVC.scala:42:{24,50}] wire [11:0] _io_out_s_T_188 = {io_out_s_hi_23, io_out_s_lo_17}; // @[RVC.scala:42:24] wire [11:0] io_out_s_lo_18 = {_io_out_s_T_190, io_out_s_opc_3}; // @[RVC.scala:33:13, :86:20, :87:15] wire [16:0] io_out_s_hi_hi_13 = {_io_out_s_T_188, _io_out_s_T_189}; // @[RVC.scala:33:13, :42:24, :87:15] wire [19:0] io_out_s_hi_24 = {io_out_s_hi_hi_13, 3'h0}; // @[RVC.scala:87:15] wire [31:0] _io_out_s_T_191 = {io_out_s_hi_24, io_out_s_lo_18}; // @[RVC.scala:87:15] wire [31:0] io_out_s_res_bits = _io_out_s_T_191; // @[RVC.scala:21:19, :87:15] wire [4:0] io_out_s_res_rd = _io_out_s_T_192; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_res_rs1 = _io_out_s_T_193; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_195 = {2'h1, _io_out_s_T_194}; // @[package.scala:39:86] wire [4:0] io_out_s_res_rs2 = _io_out_s_T_195; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_res_rs3 = _io_out_s_T_196; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_11_bits = _io_out_s_T_181 ? io_out_s_res_bits : io_out_s_me_bits; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rd = _io_out_s_T_181 ? io_out_s_res_rd : io_out_s_me_rd; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs1 = _io_out_s_T_181 ? io_out_s_res_rs1 : io_out_s_me_rs1; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs2 = _io_out_s_T_181 ? io_out_s_res_rs2 : io_out_s_me_rs2; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs3 = _io_out_s_T_181 ? io_out_s_res_rs3 : io_out_s_me_rs3; // @[RVC.scala:21:19, :92:{10,21}] wire [5:0] _io_out_s_T_199 = {_io_out_s_T_197, _io_out_s_T_198}; // @[RVC.scala:46:{18,20,27}] wire [4:0] _io_out_s_T_201 = {2'h1, _io_out_s_T_200}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_203 = {2'h1, _io_out_s_T_202}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_19 = {_io_out_s_T_203, 7'h13}; // @[RVC.scala:30:17, :98:21] wire [10:0] io_out_s_hi_hi_14 = {_io_out_s_T_199, _io_out_s_T_201}; // @[RVC.scala:30:17, :46:18, :98:21] wire [13:0] io_out_s_hi_25 = {io_out_s_hi_hi_14, 3'h5}; // @[RVC.scala:98:21] wire [25:0] _io_out_s_T_204 = {io_out_s_hi_25, io_out_s_lo_19}; // @[RVC.scala:98:21] wire [5:0] _io_out_s_T_207 = {_io_out_s_T_205, _io_out_s_T_206}; // @[RVC.scala:46:{18,20,27}] wire [4:0] _io_out_s_T_209 = {2'h1, _io_out_s_T_208}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_211 = {2'h1, _io_out_s_T_210}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_20 = {_io_out_s_T_211, 7'h13}; // @[RVC.scala:30:17, :98:21] wire [10:0] io_out_s_hi_hi_15 = {_io_out_s_T_207, _io_out_s_T_209}; // @[RVC.scala:30:17, :46:18, :98:21] wire [13:0] io_out_s_hi_26 = {io_out_s_hi_hi_15, 3'h5}; // @[RVC.scala:98:21] wire [25:0] _io_out_s_T_212 = {io_out_s_hi_26, io_out_s_lo_20}; // @[RVC.scala:98:21] wire [30:0] _io_out_s_T_213 = {5'h10, _io_out_s_T_212}; // @[RVC.scala:98:21, :99:23] wire [6:0] _io_out_s_T_215 = {7{_io_out_s_T_214}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_217 = {_io_out_s_T_215, _io_out_s_T_216}; // @[RVC.scala:43:{20,25,38}] wire [4:0] _io_out_s_T_219 = {2'h1, _io_out_s_T_218}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_221 = {2'h1, _io_out_s_T_220}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_21 = {_io_out_s_T_221, 7'h13}; // @[RVC.scala:30:17, :100:21] wire [16:0] io_out_s_hi_hi_16 = {_io_out_s_T_217, _io_out_s_T_219}; // @[RVC.scala:30:17, :43:20, :100:21] wire [19:0] io_out_s_hi_27 = {io_out_s_hi_hi_16, 3'h7}; // @[RVC.scala:100:21] wire [31:0] _io_out_s_T_222 = {io_out_s_hi_27, io_out_s_lo_21}; // @[RVC.scala:100:21] wire [2:0] _io_out_s_funct_T_2 = {_io_out_s_funct_T, _io_out_s_funct_T_1}; // @[RVC.scala:102:{68,70,77}] wire _io_out_s_funct_T_3 = _io_out_s_funct_T_2 == 3'h1; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_4 = {_io_out_s_funct_T_3, 2'h0}; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_5 = _io_out_s_funct_T_2 == 3'h2; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_6 = _io_out_s_funct_T_5 ? 3'h6 : _io_out_s_funct_T_4; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_7 = _io_out_s_funct_T_2 == 3'h3; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_8 = _io_out_s_funct_T_7 ? 3'h7 : _io_out_s_funct_T_6; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_9 = _io_out_s_funct_T_2 == 3'h4; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_10 = _io_out_s_funct_T_9 ? 3'h0 : _io_out_s_funct_T_8; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_11 = _io_out_s_funct_T_2 == 3'h5; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_12 = _io_out_s_funct_T_11 ? 3'h0 : _io_out_s_funct_T_10; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_13 = _io_out_s_funct_T_2 == 3'h6; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_14 = _io_out_s_funct_T_13 ? 3'h2 : _io_out_s_funct_T_12; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_15 = &_io_out_s_funct_T_2; // @[package.scala:39:86] wire [2:0] io_out_s_funct = _io_out_s_funct_T_15 ? 3'h3 : _io_out_s_funct_T_14; // @[package.scala:39:{76,86}] wire _io_out_s_sub_T_1 = _io_out_s_sub_T == 2'h0; // @[RVC.scala:103:{24,30}] wire [30:0] io_out_s_sub = {_io_out_s_sub_T_1, 30'h0}; // @[RVC.scala:103:{22,30}] wire [6:0] io_out_s_opc_4 = {3'h3, _io_out_s_opc_T_14, 3'h3}; // @[RVC.scala:104:{22,24}] wire [4:0] _io_out_s_T_224 = {2'h1, _io_out_s_T_223}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_226 = {2'h1, _io_out_s_T_225}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_228 = {2'h1, _io_out_s_T_227}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_22 = {_io_out_s_T_228, io_out_s_opc_4}; // @[RVC.scala:30:17, :104:22, :105:12] wire [9:0] io_out_s_hi_hi_17 = {_io_out_s_T_224, _io_out_s_T_226}; // @[RVC.scala:30:17, :31:17, :105:12] wire [12:0] io_out_s_hi_28 = {io_out_s_hi_hi_17, io_out_s_funct}; // @[package.scala:39:76] wire [24:0] _io_out_s_T_229 = {io_out_s_hi_28, io_out_s_lo_22}; // @[RVC.scala:105:12] wire [30:0] _io_out_s_T_230 = {6'h0, _io_out_s_T_229} | io_out_s_sub; // @[RVC.scala:103:22, :105:{12,43}] wire [1:0] _io_out_s_T_231 = io_in_0[11:10]; // @[RVC.scala:107:42, :190:7] wire [1:0] _io_out_s_T_299 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_307 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_317 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_325 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_339 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_347 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_357 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_365 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire _io_out_s_T_232 = _io_out_s_T_231 == 2'h1; // @[package.scala:39:86] wire [30:0] _io_out_s_T_233 = _io_out_s_T_232 ? _io_out_s_T_213 : {5'h0, _io_out_s_T_204}; // @[package.scala:39:{76,86}] wire _io_out_s_T_234 = _io_out_s_T_231 == 2'h2; // @[package.scala:39:86] wire [31:0] _io_out_s_T_235 = _io_out_s_T_234 ? _io_out_s_T_222 : {1'h0, _io_out_s_T_233}; // @[package.scala:39:{76,86}] wire _io_out_s_T_236 = &_io_out_s_T_231; // @[package.scala:39:86] wire [31:0] _io_out_s_T_237 = _io_out_s_T_236 ? {1'h0, _io_out_s_T_230} : _io_out_s_T_235; // @[package.scala:39:{76,86}] wire [31:0] io_out_s_12_bits = _io_out_s_T_237; // @[package.scala:39:76] wire [4:0] _io_out_s_T_239 = {2'h1, _io_out_s_T_238}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rd = _io_out_s_T_239; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_241 = {2'h1, _io_out_s_T_240}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rs1 = _io_out_s_T_241; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_243 = {2'h1, _io_out_s_T_242}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rs2 = _io_out_s_T_243; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_12_rs3 = _io_out_s_T_244; // @[RVC.scala:20:101, :21:19] wire [9:0] _io_out_s_T_246 = {10{_io_out_s_T_245}}; // @[RVC.scala:44:{22,28}] wire _io_out_s_T_247 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_258 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_269 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_280 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire [1:0] _io_out_s_T_248 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_259 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_270 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_281 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire _io_out_s_T_250 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_261 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_272 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_283 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_252 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_263 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_274 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_285 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire [2:0] _io_out_s_T_253 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_264 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_275 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_286 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [3:0] io_out_s_lo_lo = {_io_out_s_T_253, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_5 = {_io_out_s_T_251, _io_out_s_T_252}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_23 = {io_out_s_lo_hi_5, io_out_s_lo_lo}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo = {_io_out_s_T_249, _io_out_s_T_250}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi = {_io_out_s_T_246, _io_out_s_T_247}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_18 = {io_out_s_hi_hi_hi, _io_out_s_T_248}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_29 = {io_out_s_hi_hi_18, io_out_s_hi_lo}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_254 = {io_out_s_hi_29, io_out_s_lo_23}; // @[RVC.scala:44:17] wire _io_out_s_T_255 = _io_out_s_T_254[20]; // @[RVC.scala:44:17, :94:26] wire [9:0] _io_out_s_T_257 = {10{_io_out_s_T_256}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_1 = {_io_out_s_T_264, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_6 = {_io_out_s_T_262, _io_out_s_T_263}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_24 = {io_out_s_lo_hi_6, io_out_s_lo_lo_1}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_1 = {_io_out_s_T_260, _io_out_s_T_261}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_1 = {_io_out_s_T_257, _io_out_s_T_258}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_19 = {io_out_s_hi_hi_hi_1, _io_out_s_T_259}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_30 = {io_out_s_hi_hi_19, io_out_s_hi_lo_1}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_265 = {io_out_s_hi_30, io_out_s_lo_24}; // @[RVC.scala:44:17] wire [9:0] _io_out_s_T_266 = _io_out_s_T_265[10:1]; // @[RVC.scala:44:17, :94:36] wire [9:0] _io_out_s_T_268 = {10{_io_out_s_T_267}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_2 = {_io_out_s_T_275, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_7 = {_io_out_s_T_273, _io_out_s_T_274}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_25 = {io_out_s_lo_hi_7, io_out_s_lo_lo_2}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_2 = {_io_out_s_T_271, _io_out_s_T_272}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_2 = {_io_out_s_T_268, _io_out_s_T_269}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_20 = {io_out_s_hi_hi_hi_2, _io_out_s_T_270}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_31 = {io_out_s_hi_hi_20, io_out_s_hi_lo_2}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_276 = {io_out_s_hi_31, io_out_s_lo_25}; // @[RVC.scala:44:17] wire _io_out_s_T_277 = _io_out_s_T_276[11]; // @[RVC.scala:44:17, :94:48] wire [9:0] _io_out_s_T_279 = {10{_io_out_s_T_278}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_3 = {_io_out_s_T_286, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_8 = {_io_out_s_T_284, _io_out_s_T_285}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_26 = {io_out_s_lo_hi_8, io_out_s_lo_lo_3}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_3 = {_io_out_s_T_282, _io_out_s_T_283}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_3 = {_io_out_s_T_279, _io_out_s_T_280}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_21 = {io_out_s_hi_hi_hi_3, _io_out_s_T_281}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_32 = {io_out_s_hi_hi_21, io_out_s_hi_lo_3}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_287 = {io_out_s_hi_32, io_out_s_lo_26}; // @[RVC.scala:44:17] wire [7:0] _io_out_s_T_288 = _io_out_s_T_287[19:12]; // @[RVC.scala:44:17, :94:58] wire [12:0] io_out_s_lo_hi_9 = {_io_out_s_T_288, 5'h0}; // @[RVC.scala:94:{21,58}] wire [19:0] io_out_s_lo_27 = {io_out_s_lo_hi_9, 7'h6F}; // @[RVC.scala:94:21] wire [10:0] io_out_s_hi_hi_22 = {_io_out_s_T_255, _io_out_s_T_266}; // @[RVC.scala:94:{21,26,36}] wire [11:0] io_out_s_hi_33 = {io_out_s_hi_hi_22, _io_out_s_T_277}; // @[RVC.scala:94:{21,48}] wire [31:0] _io_out_s_T_289 = {io_out_s_hi_33, io_out_s_lo_27}; // @[RVC.scala:94:21] wire [31:0] io_out_s_13_bits = _io_out_s_T_289; // @[RVC.scala:21:19, :94:21] wire [4:0] _io_out_s_T_291 = {2'h1, _io_out_s_T_290}; // @[package.scala:39:86] wire [4:0] io_out_s_13_rs1 = _io_out_s_T_291; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_293 = {2'h1, _io_out_s_T_292}; // @[package.scala:39:86] wire [4:0] io_out_s_13_rs2 = _io_out_s_T_293; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_13_rs3 = _io_out_s_T_294; // @[RVC.scala:20:101, :21:19] wire [4:0] _io_out_s_T_296 = {5{_io_out_s_T_295}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_10 = {_io_out_s_T_299, _io_out_s_T_300}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_28 = {io_out_s_lo_hi_10, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_23 = {_io_out_s_T_296, _io_out_s_T_297}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_34 = {io_out_s_hi_hi_23, _io_out_s_T_298}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_301 = {io_out_s_hi_34, io_out_s_lo_28}; // @[RVC.scala:45:17] wire _io_out_s_T_302 = _io_out_s_T_301[12]; // @[RVC.scala:45:17, :95:29] wire [4:0] _io_out_s_T_304 = {5{_io_out_s_T_303}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_11 = {_io_out_s_T_307, _io_out_s_T_308}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_29 = {io_out_s_lo_hi_11, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_24 = {_io_out_s_T_304, _io_out_s_T_305}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_35 = {io_out_s_hi_hi_24, _io_out_s_T_306}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_309 = {io_out_s_hi_35, io_out_s_lo_29}; // @[RVC.scala:45:17] wire [5:0] _io_out_s_T_310 = _io_out_s_T_309[10:5]; // @[RVC.scala:45:17, :95:39] wire [4:0] _io_out_s_T_312 = {2'h1, _io_out_s_T_311}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_314 = {5{_io_out_s_T_313}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_12 = {_io_out_s_T_317, _io_out_s_T_318}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_30 = {io_out_s_lo_hi_12, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_25 = {_io_out_s_T_314, _io_out_s_T_315}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_36 = {io_out_s_hi_hi_25, _io_out_s_T_316}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_319 = {io_out_s_hi_36, io_out_s_lo_30}; // @[RVC.scala:45:17] wire [3:0] _io_out_s_T_320 = _io_out_s_T_319[4:1]; // @[RVC.scala:45:17, :95:71] wire [4:0] _io_out_s_T_322 = {5{_io_out_s_T_321}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_13 = {_io_out_s_T_325, _io_out_s_T_326}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_31 = {io_out_s_lo_hi_13, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_26 = {_io_out_s_T_322, _io_out_s_T_323}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_37 = {io_out_s_hi_hi_26, _io_out_s_T_324}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_327 = {io_out_s_hi_37, io_out_s_lo_31}; // @[RVC.scala:45:17] wire _io_out_s_T_328 = _io_out_s_T_327[11]; // @[RVC.scala:45:17, :95:82] wire [7:0] io_out_s_lo_lo_4 = {_io_out_s_T_328, 7'h63}; // @[RVC.scala:95:{24,82}] wire [6:0] io_out_s_lo_hi_14 = {3'h0, _io_out_s_T_320}; // @[RVC.scala:95:{24,71}] wire [14:0] io_out_s_lo_32 = {io_out_s_lo_hi_14, io_out_s_lo_lo_4}; // @[RVC.scala:95:24] wire [9:0] io_out_s_hi_lo_4 = {5'h0, _io_out_s_T_312}; // @[RVC.scala:30:17, :95:24] wire [6:0] io_out_s_hi_hi_27 = {_io_out_s_T_302, _io_out_s_T_310}; // @[RVC.scala:95:{24,29,39}] wire [16:0] io_out_s_hi_38 = {io_out_s_hi_hi_27, io_out_s_hi_lo_4}; // @[RVC.scala:95:24] wire [31:0] _io_out_s_T_329 = {io_out_s_hi_38, io_out_s_lo_32}; // @[RVC.scala:95:24] wire [31:0] io_out_s_14_bits = _io_out_s_T_329; // @[RVC.scala:21:19, :95:24] wire [4:0] _io_out_s_T_331 = {2'h1, _io_out_s_T_330}; // @[package.scala:39:86] wire [4:0] io_out_s_14_rd = _io_out_s_T_331; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_333 = {2'h1, _io_out_s_T_332}; // @[package.scala:39:86] wire [4:0] io_out_s_14_rs1 = _io_out_s_T_333; // @[RVC.scala:21:19, :30:17] wire [4:0] io_out_s_14_rs3 = _io_out_s_T_334; // @[RVC.scala:20:101, :21:19] wire [4:0] _io_out_s_T_336 = {5{_io_out_s_T_335}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_15 = {_io_out_s_T_339, _io_out_s_T_340}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_33 = {io_out_s_lo_hi_15, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_28 = {_io_out_s_T_336, _io_out_s_T_337}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_39 = {io_out_s_hi_hi_28, _io_out_s_T_338}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_341 = {io_out_s_hi_39, io_out_s_lo_33}; // @[RVC.scala:45:17] wire _io_out_s_T_342 = _io_out_s_T_341[12]; // @[RVC.scala:45:17, :96:29] wire [4:0] _io_out_s_T_344 = {5{_io_out_s_T_343}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_16 = {_io_out_s_T_347, _io_out_s_T_348}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_34 = {io_out_s_lo_hi_16, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_29 = {_io_out_s_T_344, _io_out_s_T_345}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_40 = {io_out_s_hi_hi_29, _io_out_s_T_346}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_349 = {io_out_s_hi_40, io_out_s_lo_34}; // @[RVC.scala:45:17] wire [5:0] _io_out_s_T_350 = _io_out_s_T_349[10:5]; // @[RVC.scala:45:17, :96:39] wire [4:0] _io_out_s_T_352 = {2'h1, _io_out_s_T_351}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_354 = {5{_io_out_s_T_353}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_17 = {_io_out_s_T_357, _io_out_s_T_358}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_35 = {io_out_s_lo_hi_17, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_30 = {_io_out_s_T_354, _io_out_s_T_355}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_41 = {io_out_s_hi_hi_30, _io_out_s_T_356}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_359 = {io_out_s_hi_41, io_out_s_lo_35}; // @[RVC.scala:45:17] wire [3:0] _io_out_s_T_360 = _io_out_s_T_359[4:1]; // @[RVC.scala:45:17, :96:71] wire [4:0] _io_out_s_T_362 = {5{_io_out_s_T_361}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_18 = {_io_out_s_T_365, _io_out_s_T_366}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_36 = {io_out_s_lo_hi_18, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_31 = {_io_out_s_T_362, _io_out_s_T_363}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_42 = {io_out_s_hi_hi_31, _io_out_s_T_364}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_367 = {io_out_s_hi_42, io_out_s_lo_36}; // @[RVC.scala:45:17] wire _io_out_s_T_368 = _io_out_s_T_367[11]; // @[RVC.scala:45:17, :96:82] wire [7:0] io_out_s_lo_lo_5 = {_io_out_s_T_368, 7'h63}; // @[RVC.scala:96:{24,82}] wire [6:0] io_out_s_lo_hi_19 = {3'h1, _io_out_s_T_360}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_37 = {io_out_s_lo_hi_19, io_out_s_lo_lo_5}; // @[RVC.scala:96:24] wire [9:0] io_out_s_hi_lo_5 = {5'h0, _io_out_s_T_352}; // @[RVC.scala:30:17, :96:24] wire [6:0] io_out_s_hi_hi_32 = {_io_out_s_T_342, _io_out_s_T_350}; // @[RVC.scala:96:{24,29,39}] wire [16:0] io_out_s_hi_43 = {io_out_s_hi_hi_32, io_out_s_hi_lo_5}; // @[RVC.scala:96:24] wire [31:0] _io_out_s_T_369 = {io_out_s_hi_43, io_out_s_lo_37}; // @[RVC.scala:96:24] wire [31:0] io_out_s_15_bits = _io_out_s_T_369; // @[RVC.scala:21:19, :96:24] wire [4:0] _io_out_s_T_371 = {2'h1, _io_out_s_T_370}; // @[package.scala:39:86] wire [4:0] io_out_s_15_rs1 = _io_out_s_T_371; // @[RVC.scala:21:19, :30:17] wire [4:0] io_out_s_15_rs3 = _io_out_s_T_372; // @[RVC.scala:20:101, :21:19] wire _io_out_s_load_opc_T_1 = |_io_out_s_load_opc_T; // @[RVC.scala:33:13, :113:27] wire [6:0] io_out_s_load_opc = _io_out_s_load_opc_T_1 ? 7'h3 : 7'h1F; // @[RVC.scala:113:{23,27}] wire [5:0] _io_out_s_T_375 = {_io_out_s_T_373, _io_out_s_T_374}; // @[RVC.scala:46:{18,20,27}] wire [11:0] io_out_s_lo_38 = {_io_out_s_T_377, 7'h13}; // @[RVC.scala:33:13, :114:24] wire [10:0] io_out_s_hi_hi_33 = {_io_out_s_T_375, _io_out_s_T_376}; // @[RVC.scala:33:13, :46:18, :114:24] wire [13:0] io_out_s_hi_44 = {io_out_s_hi_hi_33, 3'h1}; // @[package.scala:39:86] wire [25:0] _io_out_s_T_378 = {io_out_s_hi_44, io_out_s_lo_38}; // @[RVC.scala:114:24] wire [4:0] io_out_s_16_rd = _io_out_s_T_379; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_16_rs1 = _io_out_s_T_380; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_16_rs2 = _io_out_s_T_381; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_16_rs3 = _io_out_s_T_382; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_16_bits; // @[RVC.scala:21:19] assign io_out_s_16_bits = {6'h0, _io_out_s_T_378}; // @[RVC.scala:21:19, :22:14, :105:43, :114:24] wire [4:0] io_out_s_lo_39 = {_io_out_s_T_385, 3'h0}; // @[RVC.scala:38:{20,37}] wire [3:0] io_out_s_hi_45 = {_io_out_s_T_383, _io_out_s_T_384}; // @[RVC.scala:38:{20,22,30}] wire [8:0] _io_out_s_T_386 = {io_out_s_hi_45, io_out_s_lo_39}; // @[RVC.scala:38:20] wire [11:0] io_out_s_lo_40 = {_io_out_s_T_387, 7'h7}; // @[RVC.scala:33:13, :117:25] wire [13:0] io_out_s_hi_hi_34 = {_io_out_s_T_386, 5'h2}; // @[package.scala:39:86] wire [16:0] io_out_s_hi_46 = {io_out_s_hi_hi_34, 3'h3}; // @[RVC.scala:117:25] wire [28:0] _io_out_s_T_388 = {io_out_s_hi_46, io_out_s_lo_40}; // @[RVC.scala:117:25] wire [4:0] io_out_s_17_rd = _io_out_s_T_389; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_17_rs2 = _io_out_s_T_390; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_17_rs3 = _io_out_s_T_391; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_17_bits; // @[RVC.scala:21:19] assign io_out_s_17_bits = {3'h0, _io_out_s_T_388}; // @[RVC.scala:21:19, :22:14, :117:25] wire [1:0] _io_out_s_T_392 = io_in_0[3:2]; // @[RVC.scala:37:22, :190:7] wire [2:0] _io_out_s_T_394 = io_in_0[6:4]; // @[RVC.scala:37:37, :190:7] wire [4:0] io_out_s_lo_41 = {_io_out_s_T_394, 2'h0}; // @[RVC.scala:37:{20,37}] wire [2:0] io_out_s_hi_47 = {_io_out_s_T_392, _io_out_s_T_393}; // @[RVC.scala:37:{20,22,30}] wire [7:0] _io_out_s_T_395 = {io_out_s_hi_47, io_out_s_lo_41}; // @[RVC.scala:37:20] wire [11:0] io_out_s_lo_42 = {_io_out_s_T_396, io_out_s_load_opc}; // @[RVC.scala:33:13, :113:23, :116:24] wire [12:0] io_out_s_hi_hi_35 = {_io_out_s_T_395, 5'h2}; // @[package.scala:39:86] wire [15:0] io_out_s_hi_48 = {io_out_s_hi_hi_35, 3'h2}; // @[package.scala:39:86] wire [27:0] _io_out_s_T_397 = {io_out_s_hi_48, io_out_s_lo_42}; // @[RVC.scala:116:24] wire [4:0] io_out_s_18_rd = _io_out_s_T_398; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_18_rs2 = _io_out_s_T_399; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_18_rs3 = _io_out_s_T_400; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_18_bits; // @[RVC.scala:21:19] assign io_out_s_18_bits = {4'h0, _io_out_s_T_397}; // @[RVC.scala:21:19, :22:14, :116:24] wire [4:0] io_out_s_lo_43 = {_io_out_s_T_403, 3'h0}; // @[RVC.scala:38:{20,37}] wire [3:0] io_out_s_hi_49 = {_io_out_s_T_401, _io_out_s_T_402}; // @[RVC.scala:38:{20,22,30}] wire [8:0] _io_out_s_T_404 = {io_out_s_hi_49, io_out_s_lo_43}; // @[RVC.scala:38:20] wire [11:0] io_out_s_lo_44 = {_io_out_s_T_405, io_out_s_load_opc}; // @[RVC.scala:33:13, :113:23, :115:24] wire [13:0] io_out_s_hi_hi_36 = {_io_out_s_T_404, 5'h2}; // @[package.scala:39:86] wire [16:0] io_out_s_hi_50 = {io_out_s_hi_hi_36, 3'h3}; // @[RVC.scala:115:24] wire [28:0] _io_out_s_T_406 = {io_out_s_hi_50, io_out_s_lo_44}; // @[RVC.scala:115:24] wire [4:0] io_out_s_19_rd = _io_out_s_T_407; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_19_rs2 = _io_out_s_T_408; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_19_rs3 = _io_out_s_T_409; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_19_bits; // @[RVC.scala:21:19] assign io_out_s_19_bits = {3'h0, _io_out_s_T_406}; // @[RVC.scala:21:19, :22:14, :115:24] wire [11:0] io_out_s_mv_lo = {_io_out_s_mv_T_1, 7'h33}; // @[RVC.scala:33:13, :132:22] wire [9:0] io_out_s_mv_hi_hi = {_io_out_s_mv_T, 5'h0}; // @[RVC.scala:32:14, :132:22] wire [12:0] io_out_s_mv_hi = {io_out_s_mv_hi_hi, 3'h0}; // @[RVC.scala:132:22] wire [24:0] _io_out_s_mv_T_2 = {io_out_s_mv_hi, io_out_s_mv_lo}; // @[RVC.scala:132:22] wire [4:0] io_out_s_mv_rd = _io_out_s_mv_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_mv_rs2 = _io_out_s_mv_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_mv_rs3 = _io_out_s_mv_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_mv_bits; // @[RVC.scala:21:19] assign io_out_s_mv_bits = {7'h0, _io_out_s_mv_T_2}; // @[RVC.scala:21:19, :22:14, :132:22] wire [11:0] io_out_s_add_lo = {_io_out_s_add_T_2, 7'h33}; // @[RVC.scala:33:13, :134:25] wire [9:0] io_out_s_add_hi_hi = {_io_out_s_add_T, _io_out_s_add_T_1}; // @[RVC.scala:32:14, :33:13, :134:25] wire [12:0] io_out_s_add_hi = {io_out_s_add_hi_hi, 3'h0}; // @[RVC.scala:134:25] wire [24:0] _io_out_s_add_T_3 = {io_out_s_add_hi, io_out_s_add_lo}; // @[RVC.scala:134:25] wire [4:0] io_out_s_add_rd = _io_out_s_add_T_4; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_add_rs1 = _io_out_s_add_T_5; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_add_rs2 = _io_out_s_add_T_6; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_add_rs3 = _io_out_s_add_T_7; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_add_bits; // @[RVC.scala:21:19] assign io_out_s_add_bits = {7'h0, _io_out_s_add_T_3}; // @[RVC.scala:21:19, :22:14, :134:25] wire [9:0] io_out_s_jr_hi_hi = {_io_out_s_jr_T, _io_out_s_jr_T_1}; // @[RVC.scala:32:14, :33:13, :135:19] wire [12:0] io_out_s_jr_hi = {io_out_s_jr_hi_hi, 3'h0}; // @[RVC.scala:135:19] wire [24:0] io_out_s_jr = {io_out_s_jr_hi, 12'h67}; // @[RVC.scala:135:19] wire [17:0] _io_out_s_reserved_T = io_out_s_jr[24:7]; // @[RVC.scala:135:19, :136:29] wire [17:0] _io_out_s_ebreak_T = io_out_s_jr[24:7]; // @[RVC.scala:135:19, :136:29, :140:27] wire [24:0] io_out_s_reserved = {_io_out_s_reserved_T, 7'h1F}; // @[RVC.scala:136:{25,29}] wire _io_out_s_jr_reserved_T_1 = |_io_out_s_jr_reserved_T; // @[RVC.scala:33:13, :137:37] wire [24:0] _io_out_s_jr_reserved_T_2 = _io_out_s_jr_reserved_T_1 ? io_out_s_jr : io_out_s_reserved; // @[RVC.scala:135:19, :136:25, :137:{33,37}] wire [4:0] io_out_s_jr_reserved_rs1 = _io_out_s_jr_reserved_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_jr_reserved_rs2 = _io_out_s_jr_reserved_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_jr_reserved_rs3 = _io_out_s_jr_reserved_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_jr_reserved_bits; // @[RVC.scala:21:19] assign io_out_s_jr_reserved_bits = {7'h0, _io_out_s_jr_reserved_T_2}; // @[RVC.scala:21:19, :22:14, :137:33] wire _io_out_s_jr_mv_T_1 = |_io_out_s_jr_mv_T; // @[RVC.scala:32:14, :138:27] wire [31:0] io_out_s_jr_mv_bits = _io_out_s_jr_mv_T_1 ? io_out_s_mv_bits : io_out_s_jr_reserved_bits; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rd = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rd : 5'h0; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs1 = _io_out_s_jr_mv_T_1 ? 5'h0 : io_out_s_jr_reserved_rs1; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs2 = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rs2 : io_out_s_jr_reserved_rs2; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs3 = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rs3 : io_out_s_jr_reserved_rs3; // @[RVC.scala:21:19, :138:{22,27}] wire [9:0] io_out_s_jalr_hi_hi = {_io_out_s_jalr_T, _io_out_s_jalr_T_1}; // @[RVC.scala:32:14, :33:13, :139:21] wire [12:0] io_out_s_jalr_hi = {io_out_s_jalr_hi_hi, 3'h0}; // @[RVC.scala:139:21] wire [24:0] io_out_s_jalr = {io_out_s_jalr_hi, 12'hE7}; // @[RVC.scala:139:21] wire [24:0] _io_out_s_ebreak_T_1 = {_io_out_s_ebreak_T, 7'h73}; // @[RVC.scala:140:{23,27}] wire [24:0] io_out_s_ebreak = {_io_out_s_ebreak_T_1[24:21], _io_out_s_ebreak_T_1[20:0] | 21'h100000}; // @[RVC.scala:140:{23,46}] wire _io_out_s_jalr_ebreak_T_1 = |_io_out_s_jalr_ebreak_T; // @[RVC.scala:33:13, :141:37] wire [24:0] _io_out_s_jalr_ebreak_T_2 = _io_out_s_jalr_ebreak_T_1 ? io_out_s_jalr : io_out_s_ebreak; // @[RVC.scala:139:21, :140:46, :141:{33,37}] wire [4:0] io_out_s_jalr_ebreak_rs1 = _io_out_s_jalr_ebreak_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_jalr_ebreak_rs2 = _io_out_s_jalr_ebreak_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_jalr_ebreak_rs3 = _io_out_s_jalr_ebreak_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_jalr_ebreak_bits; // @[RVC.scala:21:19] assign io_out_s_jalr_ebreak_bits = {7'h0, _io_out_s_jalr_ebreak_T_2}; // @[RVC.scala:21:19, :22:14, :141:33] wire _io_out_s_jalr_add_T_1 = |_io_out_s_jalr_add_T; // @[RVC.scala:32:14, :142:30] wire [31:0] io_out_s_jalr_add_bits = _io_out_s_jalr_add_T_1 ? io_out_s_add_bits : io_out_s_jalr_ebreak_bits; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rd = _io_out_s_jalr_add_T_1 ? io_out_s_add_rd : 5'h1; // @[package.scala:39:86] wire [4:0] io_out_s_jalr_add_rs1 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs1 : io_out_s_jalr_ebreak_rs1; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rs2 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs2 : io_out_s_jalr_ebreak_rs2; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rs3 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs3 : io_out_s_jalr_ebreak_rs3; // @[RVC.scala:21:19, :142:{25,30}] wire [31:0] io_out_s_20_bits = _io_out_s_T_410 ? io_out_s_jalr_add_bits : io_out_s_jr_mv_bits; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rd = _io_out_s_T_410 ? io_out_s_jalr_add_rd : io_out_s_jr_mv_rd; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs1 = _io_out_s_T_410 ? io_out_s_jalr_add_rs1 : io_out_s_jr_mv_rs1; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs2 = _io_out_s_T_410 ? io_out_s_jalr_add_rs2 : io_out_s_jr_mv_rs2; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs3 = _io_out_s_T_410 ? io_out_s_jalr_add_rs3 : io_out_s_jr_mv_rs3; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [5:0] io_out_s_hi_51 = {_io_out_s_T_411, _io_out_s_T_412}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_413 = {io_out_s_hi_51, 3'h0}; // @[RVC.scala:40:20] wire [3:0] _io_out_s_T_414 = _io_out_s_T_413[8:5]; // @[RVC.scala:40:20, :124:34] wire [5:0] io_out_s_hi_52 = {_io_out_s_T_416, _io_out_s_T_417}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_418 = {io_out_s_hi_52, 3'h0}; // @[RVC.scala:40:20] wire [4:0] _io_out_s_T_419 = _io_out_s_T_418[4:0]; // @[RVC.scala:40:20, :124:66] wire [7:0] io_out_s_lo_hi_20 = {3'h3, _io_out_s_T_419}; // @[RVC.scala:124:{25,66}] wire [14:0] io_out_s_lo_45 = {io_out_s_lo_hi_20, 7'h27}; // @[RVC.scala:124:25] wire [8:0] io_out_s_hi_hi_37 = {_io_out_s_T_414, _io_out_s_T_415}; // @[RVC.scala:32:14, :124:{25,34}] wire [13:0] io_out_s_hi_53 = {io_out_s_hi_hi_37, 5'h2}; // @[package.scala:39:86] wire [28:0] _io_out_s_T_420 = {io_out_s_hi_53, io_out_s_lo_45}; // @[RVC.scala:124:25] wire [4:0] io_out_s_21_rd = _io_out_s_T_421; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_21_rs2 = _io_out_s_T_422; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_21_rs3 = _io_out_s_T_423; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_21_bits; // @[RVC.scala:21:19] assign io_out_s_21_bits = {3'h0, _io_out_s_T_420}; // @[RVC.scala:21:19, :22:14, :124:25] wire [1:0] _io_out_s_T_424 = io_in_0[8:7]; // @[RVC.scala:39:22, :190:7] wire [1:0] _io_out_s_T_429 = io_in_0[8:7]; // @[RVC.scala:39:22, :190:7] wire [3:0] _io_out_s_T_425 = io_in_0[12:9]; // @[RVC.scala:39:30, :190:7] wire [3:0] _io_out_s_T_430 = io_in_0[12:9]; // @[RVC.scala:39:30, :190:7] wire [5:0] io_out_s_hi_54 = {_io_out_s_T_424, _io_out_s_T_425}; // @[RVC.scala:39:{20,22,30}] wire [7:0] _io_out_s_T_426 = {io_out_s_hi_54, 2'h0}; // @[RVC.scala:39:20] wire [2:0] _io_out_s_T_427 = _io_out_s_T_426[7:5]; // @[RVC.scala:39:20, :123:33] wire [5:0] io_out_s_hi_55 = {_io_out_s_T_429, _io_out_s_T_430}; // @[RVC.scala:39:{20,22,30}] wire [7:0] _io_out_s_T_431 = {io_out_s_hi_55, 2'h0}; // @[RVC.scala:39:20] wire [4:0] _io_out_s_T_432 = _io_out_s_T_431[4:0]; // @[RVC.scala:39:20, :123:65] wire [7:0] io_out_s_lo_hi_21 = {3'h2, _io_out_s_T_432}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_46 = {io_out_s_lo_hi_21, 7'h23}; // @[RVC.scala:123:24] wire [7:0] io_out_s_hi_hi_38 = {_io_out_s_T_427, _io_out_s_T_428}; // @[RVC.scala:32:14, :123:{24,33}] wire [12:0] io_out_s_hi_56 = {io_out_s_hi_hi_38, 5'h2}; // @[package.scala:39:86] wire [27:0] _io_out_s_T_433 = {io_out_s_hi_56, io_out_s_lo_46}; // @[RVC.scala:123:24] wire [4:0] io_out_s_22_rd = _io_out_s_T_434; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_22_rs2 = _io_out_s_T_435; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_22_rs3 = _io_out_s_T_436; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_22_bits; // @[RVC.scala:21:19] assign io_out_s_22_bits = {4'h0, _io_out_s_T_433}; // @[RVC.scala:21:19, :22:14, :123:24] wire [5:0] io_out_s_hi_57 = {_io_out_s_T_437, _io_out_s_T_438}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_439 = {io_out_s_hi_57, 3'h0}; // @[RVC.scala:40:20] wire [3:0] _io_out_s_T_440 = _io_out_s_T_439[8:5]; // @[RVC.scala:40:20, :122:33] wire [5:0] io_out_s_hi_58 = {_io_out_s_T_442, _io_out_s_T_443}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_444 = {io_out_s_hi_58, 3'h0}; // @[RVC.scala:40:20] wire [4:0] _io_out_s_T_445 = _io_out_s_T_444[4:0]; // @[RVC.scala:40:20, :122:65] wire [7:0] io_out_s_lo_hi_22 = {3'h3, _io_out_s_T_445}; // @[RVC.scala:122:{24,65}] wire [14:0] io_out_s_lo_47 = {io_out_s_lo_hi_22, 7'h23}; // @[RVC.scala:122:24] wire [8:0] io_out_s_hi_hi_39 = {_io_out_s_T_440, _io_out_s_T_441}; // @[RVC.scala:32:14, :122:{24,33}] wire [13:0] io_out_s_hi_59 = {io_out_s_hi_hi_39, 5'h2}; // @[package.scala:39:86] wire [28:0] _io_out_s_T_446 = {io_out_s_hi_59, io_out_s_lo_47}; // @[RVC.scala:122:24] wire [4:0] io_out_s_23_rd = _io_out_s_T_447; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_23_rs2 = _io_out_s_T_448; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_23_rs3 = _io_out_s_T_449; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_23_bits; // @[RVC.scala:21:19] assign io_out_s_23_bits = {3'h0, _io_out_s_T_446}; // @[RVC.scala:21:19, :22:14, :122:24] wire [4:0] io_out_s_24_rd = _io_out_s_T_450; // @[RVC.scala:20:36, :21:19] wire [4:0] _io_out_s_T_451 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_455 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_459 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_463 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_467 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_471 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_475 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_479 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] io_out_s_24_rs1 = _io_out_s_T_451; // @[RVC.scala:20:57, :21:19] wire [4:0] _io_out_s_T_452 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_456 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_460 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_464 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_468 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_472 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_476 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_480 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] io_out_s_24_rs2 = _io_out_s_T_452; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_24_rs3 = _io_out_s_T_453; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_25_rd = _io_out_s_T_454; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_25_rs1 = _io_out_s_T_455; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_25_rs2 = _io_out_s_T_456; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_25_rs3 = _io_out_s_T_457; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_26_rd = _io_out_s_T_458; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_26_rs1 = _io_out_s_T_459; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_26_rs2 = _io_out_s_T_460; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_26_rs3 = _io_out_s_T_461; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_27_rd = _io_out_s_T_462; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_27_rs1 = _io_out_s_T_463; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_27_rs2 = _io_out_s_T_464; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_27_rs3 = _io_out_s_T_465; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_28_rd = _io_out_s_T_466; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_28_rs1 = _io_out_s_T_467; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_28_rs2 = _io_out_s_T_468; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_28_rs3 = _io_out_s_T_469; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_29_rd = _io_out_s_T_470; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_29_rs1 = _io_out_s_T_471; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_29_rs2 = _io_out_s_T_472; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_29_rs3 = _io_out_s_T_473; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_30_rd = _io_out_s_T_474; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_30_rs1 = _io_out_s_T_475; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_30_rs2 = _io_out_s_T_476; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_30_rs3 = _io_out_s_T_477; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_31_rd = _io_out_s_T_478; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_31_rs1 = _io_out_s_T_479; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_31_rs2 = _io_out_s_T_480; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_31_rs3 = _io_out_s_T_481; // @[RVC.scala:20:101, :21:19] wire [2:0] _io_out_T_1 = io_in_0[15:13]; // @[RVC.scala:154:20, :190:7] wire [2:0] _io_ill_T_1 = io_in_0[15:13]; // @[RVC.scala:154:20, :186:20, :190:7] wire [4:0] _io_out_T_2 = {_io_out_T, _io_out_T_1}; // @[RVC.scala:154:{10,12,20}] wire _io_out_T_3 = _io_out_T_2 == 5'h1; // @[package.scala:39:86] wire [31:0] _io_out_T_4_bits = _io_out_T_3 ? io_out_s_1_bits : io_out_s_0_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rd = _io_out_T_3 ? io_out_s_1_rd : io_out_s_0_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs1 = _io_out_T_3 ? io_out_s_1_rs1 : 5'h2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs2 = _io_out_T_3 ? io_out_s_1_rs2 : io_out_s_0_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs3 = _io_out_T_3 ? io_out_s_1_rs3 : io_out_s_0_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_5 = _io_out_T_2 == 5'h2; // @[package.scala:39:86] wire [31:0] _io_out_T_6_bits = _io_out_T_5 ? io_out_s_2_bits : _io_out_T_4_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rd = _io_out_T_5 ? io_out_s_2_rd : _io_out_T_4_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs1 = _io_out_T_5 ? io_out_s_2_rs1 : _io_out_T_4_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs2 = _io_out_T_5 ? io_out_s_2_rs2 : _io_out_T_4_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs3 = _io_out_T_5 ? io_out_s_2_rs3 : _io_out_T_4_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_7 = _io_out_T_2 == 5'h3; // @[package.scala:39:86] wire [31:0] _io_out_T_8_bits = _io_out_T_7 ? io_out_s_3_bits : _io_out_T_6_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rd = _io_out_T_7 ? io_out_s_3_rd : _io_out_T_6_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs1 = _io_out_T_7 ? io_out_s_3_rs1 : _io_out_T_6_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs2 = _io_out_T_7 ? io_out_s_3_rs2 : _io_out_T_6_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs3 = _io_out_T_7 ? io_out_s_3_rs3 : _io_out_T_6_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_9 = _io_out_T_2 == 5'h4; // @[package.scala:39:86] wire [31:0] _io_out_T_10_bits = _io_out_T_9 ? io_out_s_4_bits : _io_out_T_8_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rd = _io_out_T_9 ? io_out_s_4_rd : _io_out_T_8_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs1 = _io_out_T_9 ? io_out_s_4_rs1 : _io_out_T_8_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs2 = _io_out_T_9 ? io_out_s_4_rs2 : _io_out_T_8_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs3 = _io_out_T_9 ? io_out_s_4_rs3 : _io_out_T_8_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_11 = _io_out_T_2 == 5'h5; // @[package.scala:39:86] wire [31:0] _io_out_T_12_bits = _io_out_T_11 ? io_out_s_5_bits : _io_out_T_10_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rd = _io_out_T_11 ? io_out_s_5_rd : _io_out_T_10_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs1 = _io_out_T_11 ? io_out_s_5_rs1 : _io_out_T_10_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs2 = _io_out_T_11 ? io_out_s_5_rs2 : _io_out_T_10_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs3 = _io_out_T_11 ? io_out_s_5_rs3 : _io_out_T_10_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_13 = _io_out_T_2 == 5'h6; // @[package.scala:39:86] wire [31:0] _io_out_T_14_bits = _io_out_T_13 ? io_out_s_6_bits : _io_out_T_12_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rd = _io_out_T_13 ? io_out_s_6_rd : _io_out_T_12_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs1 = _io_out_T_13 ? io_out_s_6_rs1 : _io_out_T_12_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs2 = _io_out_T_13 ? io_out_s_6_rs2 : _io_out_T_12_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs3 = _io_out_T_13 ? io_out_s_6_rs3 : _io_out_T_12_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_15 = _io_out_T_2 == 5'h7; // @[package.scala:39:86] wire [31:0] _io_out_T_16_bits = _io_out_T_15 ? io_out_s_7_bits : _io_out_T_14_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rd = _io_out_T_15 ? io_out_s_7_rd : _io_out_T_14_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs1 = _io_out_T_15 ? io_out_s_7_rs1 : _io_out_T_14_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs2 = _io_out_T_15 ? io_out_s_7_rs2 : _io_out_T_14_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs3 = _io_out_T_15 ? io_out_s_7_rs3 : _io_out_T_14_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_17 = _io_out_T_2 == 5'h8; // @[package.scala:39:86] wire [31:0] _io_out_T_18_bits = _io_out_T_17 ? io_out_s_8_bits : _io_out_T_16_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rd = _io_out_T_17 ? io_out_s_8_rd : _io_out_T_16_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs1 = _io_out_T_17 ? io_out_s_8_rs1 : _io_out_T_16_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs2 = _io_out_T_17 ? io_out_s_8_rs2 : _io_out_T_16_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs3 = _io_out_T_17 ? io_out_s_8_rs3 : _io_out_T_16_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_19 = _io_out_T_2 == 5'h9; // @[package.scala:39:86] wire [31:0] _io_out_T_20_bits = _io_out_T_19 ? io_out_s_9_bits : _io_out_T_18_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rd = _io_out_T_19 ? io_out_s_9_rd : _io_out_T_18_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs1 = _io_out_T_19 ? io_out_s_9_rs1 : _io_out_T_18_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs2 = _io_out_T_19 ? io_out_s_9_rs2 : _io_out_T_18_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs3 = _io_out_T_19 ? io_out_s_9_rs3 : _io_out_T_18_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_21 = _io_out_T_2 == 5'hA; // @[package.scala:39:86] wire [31:0] _io_out_T_22_bits = _io_out_T_21 ? io_out_s_10_bits : _io_out_T_20_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rd = _io_out_T_21 ? io_out_s_10_rd : _io_out_T_20_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs1 = _io_out_T_21 ? 5'h0 : _io_out_T_20_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs2 = _io_out_T_21 ? io_out_s_10_rs2 : _io_out_T_20_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs3 = _io_out_T_21 ? io_out_s_10_rs3 : _io_out_T_20_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_23 = _io_out_T_2 == 5'hB; // @[package.scala:39:86] wire [31:0] _io_out_T_24_bits = _io_out_T_23 ? io_out_s_11_bits : _io_out_T_22_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rd = _io_out_T_23 ? io_out_s_11_rd : _io_out_T_22_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs1 = _io_out_T_23 ? io_out_s_11_rs1 : _io_out_T_22_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs2 = _io_out_T_23 ? io_out_s_11_rs2 : _io_out_T_22_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs3 = _io_out_T_23 ? io_out_s_11_rs3 : _io_out_T_22_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_25 = _io_out_T_2 == 5'hC; // @[package.scala:39:86] wire [31:0] _io_out_T_26_bits = _io_out_T_25 ? io_out_s_12_bits : _io_out_T_24_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rd = _io_out_T_25 ? io_out_s_12_rd : _io_out_T_24_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs1 = _io_out_T_25 ? io_out_s_12_rs1 : _io_out_T_24_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs2 = _io_out_T_25 ? io_out_s_12_rs2 : _io_out_T_24_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs3 = _io_out_T_25 ? io_out_s_12_rs3 : _io_out_T_24_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_27 = _io_out_T_2 == 5'hD; // @[package.scala:39:86] wire [31:0] _io_out_T_28_bits = _io_out_T_27 ? io_out_s_13_bits : _io_out_T_26_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rd = _io_out_T_27 ? 5'h0 : _io_out_T_26_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs1 = _io_out_T_27 ? io_out_s_13_rs1 : _io_out_T_26_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs2 = _io_out_T_27 ? io_out_s_13_rs2 : _io_out_T_26_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs3 = _io_out_T_27 ? io_out_s_13_rs3 : _io_out_T_26_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_29 = _io_out_T_2 == 5'hE; // @[package.scala:39:86] wire [31:0] _io_out_T_30_bits = _io_out_T_29 ? io_out_s_14_bits : _io_out_T_28_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rd = _io_out_T_29 ? io_out_s_14_rd : _io_out_T_28_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs1 = _io_out_T_29 ? io_out_s_14_rs1 : _io_out_T_28_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs2 = _io_out_T_29 ? 5'h0 : _io_out_T_28_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs3 = _io_out_T_29 ? io_out_s_14_rs3 : _io_out_T_28_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_31 = _io_out_T_2 == 5'hF; // @[package.scala:39:86] wire [31:0] _io_out_T_32_bits = _io_out_T_31 ? io_out_s_15_bits : _io_out_T_30_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rd = _io_out_T_31 ? 5'h0 : _io_out_T_30_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs1 = _io_out_T_31 ? io_out_s_15_rs1 : _io_out_T_30_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs2 = _io_out_T_31 ? 5'h0 : _io_out_T_30_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs3 = _io_out_T_31 ? io_out_s_15_rs3 : _io_out_T_30_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_33 = _io_out_T_2 == 5'h10; // @[package.scala:39:86] wire [31:0] _io_out_T_34_bits = _io_out_T_33 ? io_out_s_16_bits : _io_out_T_32_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rd = _io_out_T_33 ? io_out_s_16_rd : _io_out_T_32_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs1 = _io_out_T_33 ? io_out_s_16_rs1 : _io_out_T_32_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs2 = _io_out_T_33 ? io_out_s_16_rs2 : _io_out_T_32_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs3 = _io_out_T_33 ? io_out_s_16_rs3 : _io_out_T_32_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_35 = _io_out_T_2 == 5'h11; // @[package.scala:39:86] wire [31:0] _io_out_T_36_bits = _io_out_T_35 ? io_out_s_17_bits : _io_out_T_34_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rd = _io_out_T_35 ? io_out_s_17_rd : _io_out_T_34_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs1 = _io_out_T_35 ? 5'h2 : _io_out_T_34_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs2 = _io_out_T_35 ? io_out_s_17_rs2 : _io_out_T_34_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs3 = _io_out_T_35 ? io_out_s_17_rs3 : _io_out_T_34_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_37 = _io_out_T_2 == 5'h12; // @[package.scala:39:86] wire [31:0] _io_out_T_38_bits = _io_out_T_37 ? io_out_s_18_bits : _io_out_T_36_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rd = _io_out_T_37 ? io_out_s_18_rd : _io_out_T_36_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs1 = _io_out_T_37 ? 5'h2 : _io_out_T_36_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs2 = _io_out_T_37 ? io_out_s_18_rs2 : _io_out_T_36_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs3 = _io_out_T_37 ? io_out_s_18_rs3 : _io_out_T_36_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_39 = _io_out_T_2 == 5'h13; // @[package.scala:39:86] wire [31:0] _io_out_T_40_bits = _io_out_T_39 ? io_out_s_19_bits : _io_out_T_38_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rd = _io_out_T_39 ? io_out_s_19_rd : _io_out_T_38_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs1 = _io_out_T_39 ? 5'h2 : _io_out_T_38_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs2 = _io_out_T_39 ? io_out_s_19_rs2 : _io_out_T_38_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs3 = _io_out_T_39 ? io_out_s_19_rs3 : _io_out_T_38_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_41 = _io_out_T_2 == 5'h14; // @[package.scala:39:86] wire [31:0] _io_out_T_42_bits = _io_out_T_41 ? io_out_s_20_bits : _io_out_T_40_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rd = _io_out_T_41 ? io_out_s_20_rd : _io_out_T_40_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs1 = _io_out_T_41 ? io_out_s_20_rs1 : _io_out_T_40_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs2 = _io_out_T_41 ? io_out_s_20_rs2 : _io_out_T_40_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs3 = _io_out_T_41 ? io_out_s_20_rs3 : _io_out_T_40_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_43 = _io_out_T_2 == 5'h15; // @[package.scala:39:86] wire [31:0] _io_out_T_44_bits = _io_out_T_43 ? io_out_s_21_bits : _io_out_T_42_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rd = _io_out_T_43 ? io_out_s_21_rd : _io_out_T_42_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs1 = _io_out_T_43 ? 5'h2 : _io_out_T_42_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs2 = _io_out_T_43 ? io_out_s_21_rs2 : _io_out_T_42_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs3 = _io_out_T_43 ? io_out_s_21_rs3 : _io_out_T_42_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_45 = _io_out_T_2 == 5'h16; // @[package.scala:39:86] wire [31:0] _io_out_T_46_bits = _io_out_T_45 ? io_out_s_22_bits : _io_out_T_44_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rd = _io_out_T_45 ? io_out_s_22_rd : _io_out_T_44_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs1 = _io_out_T_45 ? 5'h2 : _io_out_T_44_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs2 = _io_out_T_45 ? io_out_s_22_rs2 : _io_out_T_44_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs3 = _io_out_T_45 ? io_out_s_22_rs3 : _io_out_T_44_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_47 = _io_out_T_2 == 5'h17; // @[package.scala:39:86] wire [31:0] _io_out_T_48_bits = _io_out_T_47 ? io_out_s_23_bits : _io_out_T_46_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rd = _io_out_T_47 ? io_out_s_23_rd : _io_out_T_46_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs1 = _io_out_T_47 ? 5'h2 : _io_out_T_46_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs2 = _io_out_T_47 ? io_out_s_23_rs2 : _io_out_T_46_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs3 = _io_out_T_47 ? io_out_s_23_rs3 : _io_out_T_46_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_49 = _io_out_T_2 == 5'h18; // @[package.scala:39:86] wire [31:0] _io_out_T_50_bits = _io_out_T_49 ? io_out_s_24_bits : _io_out_T_48_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rd = _io_out_T_49 ? io_out_s_24_rd : _io_out_T_48_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs1 = _io_out_T_49 ? io_out_s_24_rs1 : _io_out_T_48_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs2 = _io_out_T_49 ? io_out_s_24_rs2 : _io_out_T_48_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs3 = _io_out_T_49 ? io_out_s_24_rs3 : _io_out_T_48_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_51 = _io_out_T_2 == 5'h19; // @[package.scala:39:86] wire [31:0] _io_out_T_52_bits = _io_out_T_51 ? io_out_s_25_bits : _io_out_T_50_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rd = _io_out_T_51 ? io_out_s_25_rd : _io_out_T_50_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs1 = _io_out_T_51 ? io_out_s_25_rs1 : _io_out_T_50_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs2 = _io_out_T_51 ? io_out_s_25_rs2 : _io_out_T_50_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs3 = _io_out_T_51 ? io_out_s_25_rs3 : _io_out_T_50_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_53 = _io_out_T_2 == 5'h1A; // @[package.scala:39:86] wire [31:0] _io_out_T_54_bits = _io_out_T_53 ? io_out_s_26_bits : _io_out_T_52_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rd = _io_out_T_53 ? io_out_s_26_rd : _io_out_T_52_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs1 = _io_out_T_53 ? io_out_s_26_rs1 : _io_out_T_52_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs2 = _io_out_T_53 ? io_out_s_26_rs2 : _io_out_T_52_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs3 = _io_out_T_53 ? io_out_s_26_rs3 : _io_out_T_52_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_55 = _io_out_T_2 == 5'h1B; // @[package.scala:39:86] wire [31:0] _io_out_T_56_bits = _io_out_T_55 ? io_out_s_27_bits : _io_out_T_54_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rd = _io_out_T_55 ? io_out_s_27_rd : _io_out_T_54_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs1 = _io_out_T_55 ? io_out_s_27_rs1 : _io_out_T_54_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs2 = _io_out_T_55 ? io_out_s_27_rs2 : _io_out_T_54_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs3 = _io_out_T_55 ? io_out_s_27_rs3 : _io_out_T_54_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_57 = _io_out_T_2 == 5'h1C; // @[package.scala:39:86] wire [31:0] _io_out_T_58_bits = _io_out_T_57 ? io_out_s_28_bits : _io_out_T_56_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rd = _io_out_T_57 ? io_out_s_28_rd : _io_out_T_56_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs1 = _io_out_T_57 ? io_out_s_28_rs1 : _io_out_T_56_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs2 = _io_out_T_57 ? io_out_s_28_rs2 : _io_out_T_56_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs3 = _io_out_T_57 ? io_out_s_28_rs3 : _io_out_T_56_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_59 = _io_out_T_2 == 5'h1D; // @[package.scala:39:86] wire [31:0] _io_out_T_60_bits = _io_out_T_59 ? io_out_s_29_bits : _io_out_T_58_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rd = _io_out_T_59 ? io_out_s_29_rd : _io_out_T_58_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs1 = _io_out_T_59 ? io_out_s_29_rs1 : _io_out_T_58_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs2 = _io_out_T_59 ? io_out_s_29_rs2 : _io_out_T_58_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs3 = _io_out_T_59 ? io_out_s_29_rs3 : _io_out_T_58_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_61 = _io_out_T_2 == 5'h1E; // @[package.scala:39:86] wire [31:0] _io_out_T_62_bits = _io_out_T_61 ? io_out_s_30_bits : _io_out_T_60_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rd = _io_out_T_61 ? io_out_s_30_rd : _io_out_T_60_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs1 = _io_out_T_61 ? io_out_s_30_rs1 : _io_out_T_60_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs2 = _io_out_T_61 ? io_out_s_30_rs2 : _io_out_T_60_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs3 = _io_out_T_61 ? io_out_s_30_rs3 : _io_out_T_60_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_63 = &_io_out_T_2; // @[package.scala:39:86] assign _io_out_T_64_bits = _io_out_T_63 ? io_out_s_31_bits : _io_out_T_62_bits; // @[package.scala:39:{76,86}] assign _io_out_T_64_rd = _io_out_T_63 ? io_out_s_31_rd : _io_out_T_62_rd; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs1 = _io_out_T_63 ? io_out_s_31_rs1 : _io_out_T_62_rs1; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs2 = _io_out_T_63 ? io_out_s_31_rs2 : _io_out_T_62_rs2; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs3 = _io_out_T_63 ? io_out_s_31_rs3 : _io_out_T_62_rs3; // @[package.scala:39:{76,86}] assign io_out_bits_0 = _io_out_T_64_bits; // @[package.scala:39:76] assign io_out_rd_0 = _io_out_T_64_rd; // @[package.scala:39:76] assign io_out_rs1_0 = _io_out_T_64_rs1; // @[package.scala:39:76] assign io_out_rs2_0 = _io_out_T_64_rs2; // @[package.scala:39:76] assign io_out_rs3_0 = _io_out_T_64_rs3; // @[package.scala:39:76] wire [10:0] _io_ill_s_T = io_in_0[12:2]; // @[RVC.scala:158:19, :190:7] wire [10:0] _io_ill_s_T_13 = io_in_0[12:2]; // @[RVC.scala:158:19, :177:21, :190:7] wire _io_ill_s_T_1 = |_io_ill_s_T; // @[RVC.scala:158:{19,27}] wire io_ill_s_0 = ~_io_ill_s_T_1; // @[RVC.scala:158:{16,27}] wire io_ill_s_9 = _io_ill_s_T_2 == 5'h0; // @[RVC.scala:33:13, :167:47] wire _io_ill_s_T_5 = |_io_ill_s_T_4; // @[RVC.scala:168:{27,34}] wire _io_ill_s_T_6 = _io_ill_s_T_3 | _io_ill_s_T_5; // @[RVC.scala:168:{19,24,34}] wire io_ill_s_11 = ~_io_ill_s_T_6; // @[RVC.scala:168:{16,24}] wire _io_ill_s_T_8 = &_io_ill_s_T_7; // @[RVC.scala:169:{22,31}] wire _io_ill_s_T_10 = _io_ill_s_T_9; // @[RVC.scala:169:{69,73}] wire io_ill_s_12 = _io_ill_s_T_8 & _io_ill_s_T_10; // @[RVC.scala:169:{31,36,73}] wire io_ill_s_18 = _io_ill_s_T_11 == 5'h0; // @[RVC.scala:33:13, :175:18] wire io_ill_s_19 = _io_ill_s_T_12 == 5'h0; // @[RVC.scala:33:13, :175:18] wire _io_ill_s_T_14 = |_io_ill_s_T_13; // @[RVC.scala:177:{21,29}] wire io_ill_s_20 = ~_io_ill_s_T_14; // @[RVC.scala:177:{18,29}] wire [4:0] _io_ill_T_2 = {_io_ill_T, _io_ill_T_1}; // @[RVC.scala:186:{10,12,20}] wire _io_ill_T_3 = _io_ill_T_2 == 5'h1; // @[package.scala:39:86] wire _io_ill_T_4 = ~_io_ill_T_3 & io_ill_s_0; // @[package.scala:39:{76,86}] wire _io_ill_T_5 = _io_ill_T_2 == 5'h2; // @[package.scala:39:86] wire _io_ill_T_6 = ~_io_ill_T_5 & _io_ill_T_4; // @[package.scala:39:{76,86}] wire _io_ill_T_7 = _io_ill_T_2 == 5'h3; // @[package.scala:39:86] wire _io_ill_T_8 = ~_io_ill_T_7 & _io_ill_T_6; // @[package.scala:39:{76,86}] wire _io_ill_T_9 = _io_ill_T_2 == 5'h4; // @[package.scala:39:86] wire _io_ill_T_10 = _io_ill_T_9 | _io_ill_T_8; // @[package.scala:39:{76,86}] wire _io_ill_T_11 = _io_ill_T_2 == 5'h5; // @[package.scala:39:86] wire _io_ill_T_12 = ~_io_ill_T_11 & _io_ill_T_10; // @[package.scala:39:{76,86}] wire _io_ill_T_13 = _io_ill_T_2 == 5'h6; // @[package.scala:39:86] wire _io_ill_T_14 = ~_io_ill_T_13 & _io_ill_T_12; // @[package.scala:39:{76,86}] wire _io_ill_T_15 = _io_ill_T_2 == 5'h7; // @[package.scala:39:86] wire _io_ill_T_16 = ~_io_ill_T_15 & _io_ill_T_14; // @[package.scala:39:{76,86}] wire _io_ill_T_17 = _io_ill_T_2 == 5'h8; // @[package.scala:39:86] wire _io_ill_T_18 = ~_io_ill_T_17 & _io_ill_T_16; // @[package.scala:39:{76,86}] wire _io_ill_T_19 = _io_ill_T_2 == 5'h9; // @[package.scala:39:86] wire _io_ill_T_20 = _io_ill_T_19 ? io_ill_s_9 : _io_ill_T_18; // @[package.scala:39:{76,86}] wire _io_ill_T_21 = _io_ill_T_2 == 5'hA; // @[package.scala:39:86] wire _io_ill_T_22 = ~_io_ill_T_21 & _io_ill_T_20; // @[package.scala:39:{76,86}] wire _io_ill_T_23 = _io_ill_T_2 == 5'hB; // @[package.scala:39:86] wire _io_ill_T_24 = _io_ill_T_23 ? io_ill_s_11 : _io_ill_T_22; // @[package.scala:39:{76,86}] wire _io_ill_T_25 = _io_ill_T_2 == 5'hC; // @[package.scala:39:86] wire _io_ill_T_26 = _io_ill_T_25 ? io_ill_s_12 : _io_ill_T_24; // @[package.scala:39:{76,86}] wire _io_ill_T_27 = _io_ill_T_2 == 5'hD; // @[package.scala:39:86] wire _io_ill_T_28 = ~_io_ill_T_27 & _io_ill_T_26; // @[package.scala:39:{76,86}] wire _io_ill_T_29 = _io_ill_T_2 == 5'hE; // @[package.scala:39:86] wire _io_ill_T_30 = ~_io_ill_T_29 & _io_ill_T_28; // @[package.scala:39:{76,86}] wire _io_ill_T_31 = _io_ill_T_2 == 5'hF; // @[package.scala:39:86] wire _io_ill_T_32 = ~_io_ill_T_31 & _io_ill_T_30; // @[package.scala:39:{76,86}] wire _io_ill_T_33 = _io_ill_T_2 == 5'h10; // @[package.scala:39:86] wire _io_ill_T_34 = ~_io_ill_T_33 & _io_ill_T_32; // @[package.scala:39:{76,86}] wire _io_ill_T_35 = _io_ill_T_2 == 5'h11; // @[package.scala:39:86] wire _io_ill_T_36 = ~_io_ill_T_35 & _io_ill_T_34; // @[package.scala:39:{76,86}] wire _io_ill_T_37 = _io_ill_T_2 == 5'h12; // @[package.scala:39:86] wire _io_ill_T_38 = _io_ill_T_37 ? io_ill_s_18 : _io_ill_T_36; // @[package.scala:39:{76,86}] wire _io_ill_T_39 = _io_ill_T_2 == 5'h13; // @[package.scala:39:86] wire _io_ill_T_40 = _io_ill_T_39 ? io_ill_s_19 : _io_ill_T_38; // @[package.scala:39:{76,86}] wire _io_ill_T_41 = _io_ill_T_2 == 5'h14; // @[package.scala:39:86] wire _io_ill_T_42 = _io_ill_T_41 ? io_ill_s_20 : _io_ill_T_40; // @[package.scala:39:{76,86}] wire _io_ill_T_43 = _io_ill_T_2 == 5'h15; // @[package.scala:39:86] wire _io_ill_T_44 = ~_io_ill_T_43 & _io_ill_T_42; // @[package.scala:39:{76,86}] wire _io_ill_T_45 = _io_ill_T_2 == 5'h16; // @[package.scala:39:86] wire _io_ill_T_46 = ~_io_ill_T_45 & _io_ill_T_44; // @[package.scala:39:{76,86}] wire _io_ill_T_47 = _io_ill_T_2 == 5'h17; // @[package.scala:39:86] wire _io_ill_T_48 = ~_io_ill_T_47 & _io_ill_T_46; // @[package.scala:39:{76,86}] wire _io_ill_T_49 = _io_ill_T_2 == 5'h18; // @[package.scala:39:86] wire _io_ill_T_50 = ~_io_ill_T_49 & _io_ill_T_48; // @[package.scala:39:{76,86}] wire _io_ill_T_51 = _io_ill_T_2 == 5'h19; // @[package.scala:39:86] wire _io_ill_T_52 = ~_io_ill_T_51 & _io_ill_T_50; // @[package.scala:39:{76,86}] wire _io_ill_T_53 = _io_ill_T_2 == 5'h1A; // @[package.scala:39:86] wire _io_ill_T_54 = ~_io_ill_T_53 & _io_ill_T_52; // @[package.scala:39:{76,86}] wire _io_ill_T_55 = _io_ill_T_2 == 5'h1B; // @[package.scala:39:86] wire _io_ill_T_56 = ~_io_ill_T_55 & _io_ill_T_54; // @[package.scala:39:{76,86}] wire _io_ill_T_57 = _io_ill_T_2 == 5'h1C; // @[package.scala:39:86] wire _io_ill_T_58 = ~_io_ill_T_57 & _io_ill_T_56; // @[package.scala:39:{76,86}] wire _io_ill_T_59 = _io_ill_T_2 == 5'h1D; // @[package.scala:39:86] wire _io_ill_T_60 = ~_io_ill_T_59 & _io_ill_T_58; // @[package.scala:39:{76,86}] wire _io_ill_T_61 = _io_ill_T_2 == 5'h1E; // @[package.scala:39:86] wire _io_ill_T_62 = ~_io_ill_T_61 & _io_ill_T_60; // @[package.scala:39:{76,86}] wire _io_ill_T_63 = &_io_ill_T_2; // @[package.scala:39:86] assign _io_ill_T_64 = ~_io_ill_T_63 & _io_ill_T_62; // @[package.scala:39:{76,86}] assign io_ill = _io_ill_T_64; // @[package.scala:39:76] assign io_out_bits = io_out_bits_0; // @[RVC.scala:190:7] assign io_out_rd = io_out_rd_0; // @[RVC.scala:190:7] assign io_out_rs1 = io_out_rs1_0; // @[RVC.scala:190:7] assign io_out_rs2 = io_out_rs2_0; // @[RVC.scala:190:7] assign io_out_rs3 = io_out_rs3_0; // @[RVC.scala:190:7] assign io_rvc = io_rvc_0; // @[RVC.scala:190:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Plic.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.experimental._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet} import freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} import freechips.rocketchip.util.{Annotated, MuxT, property} import scala.math.min import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.SeqToAugmentedSeq class GatewayPLICIO extends Bundle { val valid = Output(Bool()) val ready = Input(Bool()) val complete = Input(Bool()) } class LevelGateway extends Module { val io = IO(new Bundle { val interrupt = Input(Bool()) val plic = new GatewayPLICIO }) val inFlight = RegInit(false.B) when (io.interrupt && io.plic.ready) { inFlight := true.B } when (io.plic.complete) { inFlight := false.B } io.plic.valid := io.interrupt && !inFlight } object PLICConsts { def maxDevices = 1023 def maxMaxHarts = 15872 def priorityBase = 0x0 def pendingBase = 0x1000 def enableBase = 0x2000 def hartBase = 0x200000 def claimOffset = 4 def priorityBytes = 4 def enableOffset(i: Int) = i * ((maxDevices+7)/8) def hartOffset(i: Int) = i * 0x1000 def enableBase(i: Int):Int = enableOffset(i) + enableBase def hartBase(i: Int):Int = hartOffset(i) + hartBase def size(maxHarts: Int): Int = { require(maxHarts > 0 && maxHarts <= maxMaxHarts, s"Must be: maxHarts=$maxHarts > 0 && maxHarts <= PLICConsts.maxMaxHarts=${PLICConsts.maxMaxHarts}") 1 << log2Ceil(hartBase(maxHarts)) } require(hartBase >= enableBase(maxMaxHarts)) } case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0, maxHarts: Int = PLICConsts.maxMaxHarts) { require (maxPriorities >= 0) def address = AddressSet(baseAddress, PLICConsts.size(maxHarts)-1) } case object PLICKey extends Field[Option[PLICParams]](None) case class PLICAttachParams( slaveWhere: TLBusWrapperLocation = CBUS ) case object PLICAttachKey extends Field(PLICAttachParams()) /** Platform-Level Interrupt Controller */ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // plic0 => max devices 1023 val device: SimpleDevice = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) { override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val extra = Map( "interrupt-controller" -> Nil, "riscv,ndev" -> Seq(ResourceInt(nDevices)), "riscv,max-priority" -> Seq(ResourceInt(nPriorities)), "#interrupt-cells" -> Seq(ResourceInt(1))) Description(name, mapping ++ extra) } } val node : TLRegisterNode = TLRegisterNode( address = Seq(params.address), device = device, beatBytes = beatBytes, undefZero = true, concurrency = 1) // limiting concurrency handles RAW hazards on claim registers val intnode: IntNexusNode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false, inputRequiresOutput = false) /* Negotiated sizes */ def nDevices: Int = intnode.edges.in.map(_.source.num).sum def minPriorities = min(params.maxPriorities, nDevices) def nPriorities = (1 << log2Ceil(minPriorities+1)) - 1 // round up to next 2^n-1 def nHarts = intnode.edges.out.map(_.source.num).sum // Assign all the devices unique ranges lazy val sources = intnode.edges.in.map(_.source) lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten ResourceBinding { flatSources.foreach { s => s.resources.foreach { r => // +1 because interrupt 0 is reserved (s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) } } } } lazy val module = new Impl class Impl extends LazyModuleImp(this) { Annotated.params(this, params) val (io_devices, edgesIn) = intnode.in.unzip val (io_harts, _) = intnode.out.unzip // Compact the interrupt vector the same way val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten // This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence val harts = io_harts.flatten def getNInterrupts = interrupts.size println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):") flatSources.foreach { s => // +1 because 0 is reserved, +1-1 because the range is half-open println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}") } println("") require (nDevices == interrupts.size, s"Must be: nDevices=$nDevices == interrupts.size=${interrupts.size}") require (nHarts == harts.size, s"Must be: nHarts=$nHarts == harts.size=${harts.size}") require(nDevices <= PLICConsts.maxDevices, s"Must be: nDevices=$nDevices <= PLICConsts.maxDevices=${PLICConsts.maxDevices}") require(nHarts > 0 && nHarts <= params.maxHarts, s"Must be: nHarts=$nHarts > 0 && nHarts <= PLICParams.maxHarts=${params.maxHarts}") // For now, use LevelGateways for all TL2 interrupts val gateways = interrupts.map { case i => val gateway = Module(new LevelGateway) gateway.io.interrupt := i gateway.io.plic } val prioBits = log2Ceil(nPriorities+1) val priority = if (nPriorities > 0) Reg(Vec(nDevices, UInt(prioBits.W))) else WireDefault(VecInit.fill(nDevices max 1)(1.U)) val threshold = if (nPriorities > 0) Reg(Vec(nHarts, UInt(prioBits.W))) else WireDefault(VecInit.fill(nHarts)(0.U)) val pending = RegInit(VecInit.fill(nDevices max 1){false.B}) /* Construct the enable registers, chunked into 8-bit segments to reduce verilog size */ val firstEnable = nDevices min 7 val fullEnables = (nDevices - firstEnable) / 8 val tailEnable = nDevices - firstEnable - 8*fullEnables def enableRegs = (Reg(UInt(firstEnable.W)) +: Seq.fill(fullEnables) { Reg(UInt(8.W)) }) ++ (if (tailEnable > 0) Some(Reg(UInt(tailEnable.W))) else None) val enables = Seq.fill(nHarts) { enableRegs } val enableVec = VecInit(enables.map(x => Cat(x.reverse))) val enableVec0 = VecInit(enableVec.map(x => Cat(x, 0.U(1.W)))) val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W))) val pendingUInt = Cat(pending.reverse) if(nDevices > 0) { for (hart <- 0 until nHarts) { val fanin = Module(new PLICFanIn(nDevices, prioBits)) fanin.io.prio := priority fanin.io.ip := enableVec(hart) & pendingUInt maxDevs(hart) := fanin.io.dev harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages) } } // Priority registers are 32-bit aligned so treat each as its own group. // Otherwise, the off-by-one nature of the priority registers gets confusing. require(PLICConsts.priorityBytes == 4, s"PLIC Priority register descriptions assume 32-bits per priority, not ${PLICConsts.priorityBytes}") def priorityRegDesc(i: Int) = RegFieldDesc( name = s"priority_$i", desc = s"Acting priority of interrupt source $i", group = Some(s"priority_${i}"), groupDesc = Some(s"Acting priority of interrupt source ${i}"), reset = if (nPriorities > 0) None else Some(1)) def pendingRegDesc(i: Int) = RegFieldDesc( name = s"pending_$i", desc = s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.", group = Some("pending"), groupDesc = Some("Pending Bit Array. 1 Bit for each interrupt source."), volatile = true) def enableRegDesc(i: Int, j: Int, wide: Int) = { val low = if (j == 0) 1 else j*8 val high = low + wide - 1 RegFieldDesc( name = s"enables_${j}", desc = s"Targets ${low}-${high}. Set bits to 1 if interrupt should be enabled.", group = Some(s"enables_${i}"), groupDesc = Some(s"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source.")) } def priorityRegField(x: UInt, i: Int) = if (nPriorities > 0) { RegField(prioBits, x, priorityRegDesc(i)) } else { RegField.r(prioBits, x, priorityRegDesc(i)) } val priorityRegFields = priority.zipWithIndex.map { case (p, i) => PLICConsts.priorityBase+PLICConsts.priorityBytes*(i+1) -> Seq(priorityRegField(p, i+1)) } val pendingRegFields = Seq(PLICConsts.pendingBase -> (RegField(1) +: pending.zipWithIndex.map { case (b, i) => RegField.r(1, b, pendingRegDesc(i+1))})) val enableRegFields = enables.zipWithIndex.map { case (e, i) => PLICConsts.enableBase(i) -> (RegField(1) +: e.zipWithIndex.map { case (x, j) => RegField(x.getWidth, x, enableRegDesc(i, j, x.getWidth)) }) } // When a hart reads a claim/complete register, then the // device which is currently its highest priority is no longer pending. // This code exploits the fact that, practically, only one claim/complete // register can be read at a time. We check for this because if the address map // were to change, it may no longer be true. // Note: PLIC doesn't care which hart reads the register. val claimer = Wire(Vec(nHarts, Bool())) assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot val claiming = Seq.tabulate(nHarts){i => Mux(claimer(i), maxDevs(i), 0.U)}.reduceLeft(_|_) val claimedDevs = VecInit(UIntToOH(claiming, nDevices+1).asBools) ((pending zip gateways) zip claimedDevs.tail) foreach { case ((p, g), c) => g.ready := !p when (c || g.valid) { p := !c } } // When a hart writes a claim/complete register, then // the written device (as long as it is actually enabled for that // hart) is marked complete. // This code exploits the fact that, practically, only one claim/complete register // can be written at a time. We check for this because if the address map // were to change, it may no longer be true. // Note -- PLIC doesn't care which hart writes the register. val completer = Wire(Vec(nHarts, Bool())) assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot val completerDev = Wire(UInt(log2Up(nDevices + 1).W)) val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(completerDev, nDevices+1), 0.U) (gateways zip completedDevs.asBools.tail) foreach { case (g, c) => g.complete := c } def thresholdRegDesc(i: Int) = RegFieldDesc( name = s"threshold_$i", desc = s"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.", reset = if (nPriorities > 0) None else Some(1)) def thresholdRegField(x: UInt, i: Int) = if (nPriorities > 0) { RegField(prioBits, x, thresholdRegDesc(i)) } else { RegField.r(prioBits, x, thresholdRegDesc(i)) } val hartRegFields = Seq.tabulate(nHarts) { i => PLICConsts.hartBase(i) -> Seq( thresholdRegField(threshold(i), i), RegField(32-prioBits), RegField(32, RegReadFn { valid => claimer(i) := valid (true.B, maxDevs(i)) }, RegWriteFn { (valid, data) => assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0), "completerDev should be consistent for all harts") completerDev := data.extract(log2Ceil(nDevices+1)-1, 0) completer(i) := valid && enableVec0(i)(completerDev) true.B }, Some(RegFieldDesc(s"claim_complete_$i", s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." + s"Writing the interrupt number back completes the interrupt.", reset = None, wrType = Some(RegFieldWrType.MODIFY), rdAction = Some(RegFieldRdAction.MODIFY), volatile = true)) ) ) } node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*) if (nDevices >= 2) { val claimed = claimer(0) && maxDevs(0) > 0.U val completed = completer(0) property.cover(claimed && RegEnable(claimed, false.B, claimed || completed), "TWO_CLAIMS", "two claims with no intervening complete") property.cover(completed && RegEnable(completed, false.B, claimed || completed), "TWO_COMPLETES", "two completes with no intervening claim") val ep = enables(0).asUInt & pending.asUInt val ep2 = RegNext(ep) val diff = ep & ~ep2 property.cover((diff & (diff - 1.U)) =/= 0.U, "TWO_INTS_PENDING", "two enabled interrupts became pending on same cycle") if (nPriorities > 0) ccover(maxDevs(0) > (1.U << priority(0).getWidth) && maxDevs(0) <= Cat(1.U, threshold(0)), "THRESHOLD", "interrupt pending but less than threshold") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"PLIC_$label", "Interrupts;;" + desc) } } class PLICFanIn(nDevices: Int, prioBits: Int) extends Module { val io = IO(new Bundle { val prio = Flipped(Vec(nDevices, UInt(prioBits.W))) val ip = Flipped(UInt(nDevices.W)) val dev = UInt(log2Ceil(nDevices+1).W) val max = UInt(prioBits.W) }) def findMax(x: Seq[UInt]): (UInt, UInt) = { if (x.length > 1) { val half = 1 << (log2Ceil(x.length) - 1) val left = findMax(x take half) val right = findMax(x drop half) MuxT(left._1 >= right._1, left, (right._1, half.U | right._2)) } else (x.head, 0.U) } val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) } val (maxPri, maxDev) = findMax(effectivePriority) io.max := maxPri // strips the always-constant high '1' bit io.dev := maxDev } /** Trait that will connect a PLIC to a subsystem */ trait CanHavePeripheryPLIC { this: BaseSubsystem => val (plicOpt, plicDomainOpt) = p(PLICKey).map { params => val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere) val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain") val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) } plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus, Some("PLIC")) := _ } } plicDomainWrapper { plic.intnode :=* ibus.toPLIC } (plic, plicDomainWrapper) }.unzip }
module PLICClockSinkDomain( // @[ClockDomain.scala:14:9] input auto_plic_int_in_0, // @[LazyModuleImp.scala:107:25] output auto_plic_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_plic_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_plic_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_plic_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_plic_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_plic_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_plic_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_plic_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_plic_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_plic_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_plic_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_plic_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_plic_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_plic_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_plic_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_plic_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_1_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_0_sync_0, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _plic_auto_int_out_1_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_0_0; // @[Plic.scala:367:46] wire auto_plic_int_in_0_0 = auto_plic_int_in_0; // @[ClockDomain.scala:14:9] wire auto_plic_in_a_valid_0 = auto_plic_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_plic_in_a_bits_opcode_0 = auto_plic_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_plic_in_a_bits_param_0 = auto_plic_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [1:0] auto_plic_in_a_bits_size_0 = auto_plic_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [12:0] auto_plic_in_a_bits_source_0 = auto_plic_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [27:0] auto_plic_in_a_bits_address_0 = auto_plic_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_plic_in_a_bits_mask_0 = auto_plic_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_plic_in_a_bits_data_0 = auto_plic_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_plic_in_a_bits_corrupt_0 = auto_plic_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_ready_0 = auto_plic_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire [1:0] auto_plic_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire intInClockXingOut_1_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_plic_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_plic_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_plic_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [12:0] auto_plic_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_plic_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_1_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_0_sync_0_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] wire intInClockXingIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_0_sync_0_0 = intInClockXingOut_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_1_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_1_sync_0_0 = intInClockXingOut_1_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17] TLPLIC plic ( // @[Plic.scala:367:46] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_int_in_0 (auto_plic_int_in_0_0), // @[ClockDomain.scala:14:9] .auto_int_out_1_0 (_plic_auto_int_out_1_0), .auto_int_out_0_0 (_plic_auto_int_out_0_0), .auto_in_a_ready (auto_plic_in_a_ready_0), .auto_in_a_valid (auto_plic_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_opcode (auto_plic_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_param (auto_plic_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_size (auto_plic_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_source (auto_plic_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_address (auto_plic_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_mask (auto_plic_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_data (auto_plic_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_corrupt (auto_plic_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_in_d_ready (auto_plic_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_in_d_valid (auto_plic_in_d_valid_0), .auto_in_d_bits_opcode (auto_plic_in_d_bits_opcode_0), .auto_in_d_bits_size (auto_plic_in_d_bits_size_0), .auto_in_d_bits_source (auto_plic_in_d_bits_source_0), .auto_in_d_bits_data (auto_plic_in_d_bits_data_0) ); // @[Plic.scala:367:46] IntSyncCrossingSource_n1x1_3 intsource ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_0_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_4 intsource_1 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_1_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_1_sync_0) ); // @[Crossing.scala:29:31] assign auto_plic_in_a_ready = auto_plic_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_valid = auto_plic_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_bits_opcode = auto_plic_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_bits_size = auto_plic_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_bits_source = auto_plic_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_bits_data = auto_plic_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_1_sync_0 = auto_int_in_clock_xing_out_1_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_0_sync_0 = auto_int_in_clock_xing_out_0_sync_0_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_5( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_32 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54] wire [4098:0] _c_sizes_set_T_1 = 4099'h0; // @[Monitor.scala:768:52] wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79] wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35] wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35] wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34] wire [1027:0] c_sizes_set = 1028'h0; // @[Monitor.scala:741:34] wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34] wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 9'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 9'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 9'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_28 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7] wire _source_ok_T_29 = _source_ok_T_28 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_33 = _source_ok_T_31; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_42 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_9 = _uncommonBits_T_9[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_14 = _uncommonBits_T_14[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_19 = _uncommonBits_T_19[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_24 = _uncommonBits_T_24[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_39 = _uncommonBits_T_39[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_44 = _uncommonBits_T_44[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_49 = _uncommonBits_T_49[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_54 = _uncommonBits_T_54[5:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_43 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_44 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_50 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_56 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_62 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_45 = _source_ok_T_44 == 7'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_51 = _source_ok_T_50 == 7'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_57 = _source_ok_T_56 == 7'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_63 = _source_ok_T_62 == 7'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire _source_ok_T_68 = io_in_d_bits_source_0 == 9'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire _source_ok_T_69 = io_in_d_bits_source_0 == 9'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire _source_ok_T_70 = io_in_d_bits_source_0 == 9'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[5:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_71 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7] wire _source_ok_T_72 = _source_ok_T_71 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire _source_ok_T_77 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_77; // @[Parameters.scala:1138:31] wire _source_ok_T_78 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_82 = _source_ok_T_81 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_83 = _source_ok_T_82 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_84 = _source_ok_T_83 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_85 = _source_ok_T_84 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_85 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _T_1253 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1253; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1253; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [8:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1326 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1326; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1326; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1326; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [8:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [256:0] inflight; // @[Monitor.scala:614:27] reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1027:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [256:0] a_set; // @[Monitor.scala:626:34] wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1027:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [1027:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1027:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [1027:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1027:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [511:0] _GEN_2 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [511:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1179 = _T_1253 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1179 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1179 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1179 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [11:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [11:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [11:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1179 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4098:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1179 ? _a_sizes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [256:0] d_clr; // @[Monitor.scala:664:34] wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1027:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1225 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1225 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1194 = _T_1326 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1194 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1194 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [4110:0] _d_sizes_clr_T_5 = 4111'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1194 ? _d_sizes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [256:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [1027:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1027:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1027:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1027:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [256:0] inflight_1; // @[Monitor.scala:726:35] wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1027:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1027:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1027:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1027:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [1027:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1027:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [256:0] d_clr_1; // @[Monitor.scala:774:34] wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1027:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1297 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1297 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1279 = _T_1326 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1279 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1279 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [4110:0] _d_sizes_clr_T_11 = 4111'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1279 ? _d_sizes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113] wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1027:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1027:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_149( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_265 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module RecFNToRecFN_102( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLBuffer_a32d256s8k5z3c( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [255:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [255:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [255:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [255:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [255:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [255:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [255:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [7:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [255:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [4:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [7:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [4:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [255:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_e_ready = 1'h1; // @[Nodes.scala:27:25] wire auto_out_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeIn_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_e_ready = 1'h1; // @[Nodes.scala:27:25] wire auto_in_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_out_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire [255:0] auto_in_b_bits_data = 256'h0; // @[Nodes.scala:27:25] wire [255:0] auto_out_b_bits_data = 256'h0; // @[Nodes.scala:27:25] wire [255:0] nodeIn_b_bits_data = 256'h0; // @[Nodes.scala:27:25] wire [255:0] nodeOut_b_bits_data = 256'h0; // @[Nodes.scala:27:25] wire [31:0] auto_in_b_bits_mask = 32'hFFFFFFFF; // @[Nodes.scala:27:25] wire [31:0] auto_out_b_bits_mask = 32'hFFFFFFFF; // @[Nodes.scala:27:25] wire [31:0] nodeIn_b_bits_mask = 32'hFFFFFFFF; // @[Nodes.scala:27:25] wire [31:0] nodeOut_b_bits_mask = 32'hFFFFFFFF; // @[Nodes.scala:27:25] wire [7:0] auto_in_b_bits_source = 8'h40; // @[Nodes.scala:27:25] wire [7:0] auto_out_b_bits_source = 8'h40; // @[Nodes.scala:27:25] wire [7:0] nodeIn_b_bits_source = 8'h40; // @[Nodes.scala:27:25] wire [7:0] nodeOut_b_bits_source = 8'h40; // @[Nodes.scala:27:25] wire [2:0] auto_in_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_in_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_out_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeIn_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeOut_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [255:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [255:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [255:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [255:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [255:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [7:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [4:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [255:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [4:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [7:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [255:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [255:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [255:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign nodeOut_c_valid = nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_opcode = nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_param = nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_size = nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_source = nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_address = nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_data = nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_corrupt = nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign nodeOut_e_valid = nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_e_bits_sink = nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_param = nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_address = nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_c_ready = nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_37 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a32d256s8k5z3c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a32d256s8k5z3c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_395( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_139 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_||_).init assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_||_) || winner.reduce(_||_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_*) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. */ class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /** This tests that the lowest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /** This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }
module TLXbar_sbus_i3_o2_a32d64s6k3z4c( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_2_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_2_b_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_2_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_2_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_2_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_2_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_2_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_2_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_b_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_1_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_c_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire portsEOI_filtered_2_1_ready; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_1_ready; // @[Xbar.scala:352:24] wire portsCOI_filtered_2_1_ready; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_1_ready; // @[Xbar.scala:352:24] wire [2:0] out_1_e_bits_sink; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_sink; // @[Xbar.scala:216:19] wire [3:0] out_1_d_bits_size; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [5:0] in_2_c_bits_source; // @[Xbar.scala:159:18] wire [5:0] in_2_a_bits_source; // @[Xbar.scala:159:18] wire [5:0] in_1_c_bits_source; // @[Xbar.scala:159:18] wire [5:0] in_1_a_bits_source; // @[Xbar.scala:159:18] wire [5:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_2_a_valid_0 = auto_anon_in_2_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_a_bits_opcode_0 = auto_anon_in_2_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_a_bits_param_0 = auto_anon_in_2_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_2_a_bits_size_0 = auto_anon_in_2_a_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_a_bits_source_0 = auto_anon_in_2_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_2_a_bits_address_0 = auto_anon_in_2_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_2_a_bits_mask_0 = auto_anon_in_2_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_2_a_bits_data_0 = auto_anon_in_2_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_2_a_bits_corrupt_0 = auto_anon_in_2_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_2_b_ready_0 = auto_anon_in_2_b_ready; // @[Xbar.scala:74:9] wire auto_anon_in_2_c_valid_0 = auto_anon_in_2_c_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_c_bits_opcode_0 = auto_anon_in_2_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_c_bits_param_0 = auto_anon_in_2_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_2_c_bits_size_0 = auto_anon_in_2_c_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_c_bits_source_0 = auto_anon_in_2_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_2_c_bits_address_0 = auto_anon_in_2_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_2_c_bits_data_0 = auto_anon_in_2_c_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_2_c_bits_corrupt_0 = auto_anon_in_2_c_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_2_d_ready_0 = auto_anon_in_2_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_2_e_valid_0 = auto_anon_in_2_e_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_e_bits_sink_0 = auto_anon_in_2_e_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_1_b_ready_0 = auto_anon_in_1_b_ready; // @[Xbar.scala:74:9] wire auto_anon_in_1_c_valid_0 = auto_anon_in_1_c_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_c_bits_opcode_0 = auto_anon_in_1_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_c_bits_param_0 = auto_anon_in_1_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_c_bits_size_0 = auto_anon_in_1_c_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_c_bits_source_0 = auto_anon_in_1_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_c_bits_address_0 = auto_anon_in_1_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_1_c_bits_data_0 = auto_anon_in_1_c_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_1_c_bits_corrupt_0 = auto_anon_in_1_c_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_1_e_valid_0 = auto_anon_in_1_e_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_e_bits_sink_0 = auto_anon_in_1_e_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire [4:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_b_valid_0 = auto_anon_out_1_b_valid; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_b_bits_param_0 = auto_anon_out_1_b_bits_param; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_1_b_bits_source_0 = auto_anon_out_1_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_1_b_bits_address_0 = auto_anon_out_1_b_bits_address; // @[Xbar.scala:74:9] wire auto_anon_out_1_c_ready_0 = auto_anon_out_1_c_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_0_d_bits_param_0 = auto_anon_out_0_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_sink_0 = auto_anon_out_0_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire _readys_T_13 = reset; // @[Arbiter.scala:22:12] wire _readys_T_24 = reset; // @[Arbiter.scala:22:12] wire _readys_T_34 = reset; // @[Arbiter.scala:22:12] wire _readys_T_44 = reset; // @[Arbiter.scala:22:12] wire _readys_T_54 = reset; // @[Arbiter.scala:22:12] wire _readys_T_64 = reset; // @[Arbiter.scala:22:12] wire [2:0] auto_anon_in_2_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_b_bits_size = 3'h6; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] anonIn_2_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] x1_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] in_1_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18] wire [2:0] in_2_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18] wire [2:0] out_1_b_bits_opcode = 3'h6; // @[Xbar.scala:216:19] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_1_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_2_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [3:0] auto_anon_in_2_b_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_b_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] anonIn_2_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] in_1_b_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] in_2_b_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] out_1_b_bits_size = 4'h6; // @[Xbar.scala:216:19] wire [3:0] portsBIO_filtered_1_0_bits_size = 4'h6; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_1_bits_size = 4'h6; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_2_bits_size = 4'h6; // @[Xbar.scala:352:24] wire [7:0] auto_anon_in_2_b_bits_mask = 8'hFF; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_1_b_bits_mask = 8'hFF; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_b_bits_mask = 8'hFF; // @[Xbar.scala:74:9] wire [7:0] anonIn_1_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17] wire [7:0] anonIn_2_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17] wire [7:0] x1_anonOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17] wire [7:0] in_1_b_bits_mask = 8'hFF; // @[Xbar.scala:159:18] wire [7:0] in_2_b_bits_mask = 8'hFF; // @[Xbar.scala:159:18] wire [7:0] out_1_b_bits_mask = 8'hFF; // @[Xbar.scala:216:19] wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'hFF; // @[Xbar.scala:352:24] wire [7:0] portsBIO_filtered_1_1_bits_mask = 8'hFF; // @[Xbar.scala:352:24] wire [7:0] portsBIO_filtered_1_2_bits_mask = 8'hFF; // @[Xbar.scala:352:24] wire [63:0] auto_anon_in_2_b_bits_data = 64'h0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_1_b_bits_data = 64'h0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_b_bits_data = 64'h0; // @[Xbar.scala:74:9] wire [63:0] anonIn_1_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] anonIn_2_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] x1_anonOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] in_0_b_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] in_0_c_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] in_1_b_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] in_2_b_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] out_0_b_bits_data = 64'h0; // @[Xbar.scala:216:19] wire [63:0] out_0_c_bits_data = 64'h0; // @[Xbar.scala:216:19] wire [63:0] out_1_b_bits_data = 64'h0; // @[Xbar.scala:216:19] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsBIO_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsBIO_filtered_2_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsBIO_filtered_1_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsBIO_filtered_1_2_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire auto_anon_in_2_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_1_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_2_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire x1_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_b_valid = 1'h0; // @[Xbar.scala:159:18] wire in_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_0_c_ready = 1'h0; // @[Xbar.scala:159:18] wire in_0_c_valid = 1'h0; // @[Xbar.scala:159:18] wire in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_0_e_ready = 1'h0; // @[Xbar.scala:159:18] wire in_0_e_valid = 1'h0; // @[Xbar.scala:159:18] wire in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_2_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire out_0_b_ready = 1'h0; // @[Xbar.scala:216:19] wire out_0_b_valid = 1'h0; // @[Xbar.scala:216:19] wire out_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_0_c_valid = 1'h0; // @[Xbar.scala:216:19] wire out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_0_e_valid = 1'h0; // @[Xbar.scala:216:19] wire out_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_T_6 = 1'h0; // @[Parameters.scala:54:32] wire _requestBOI_T_8 = 1'h0; // @[Parameters.scala:54:67] wire requestBOI_0_1 = 1'h0; // @[Parameters.scala:56:48] wire _requestBOI_T_11 = 1'h0; // @[Parameters.scala:54:32] wire _requestBOI_T_13 = 1'h0; // @[Parameters.scala:54:67] wire requestBOI_0_2 = 1'h0; // @[Parameters.scala:56:48] wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_T_10 = 1'h0; // @[Parameters.scala:54:10] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire beatsBO_opdata_1 = 1'h0; // @[Edges.scala:97:28] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_2_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_2_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_2_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_2_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_2_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_out_0_b_ready_T = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_3 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_4 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_WIRE = 1'h0; // @[Mux.scala:30:73] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_2_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_out_1_b_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_in_0_c_ready_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_in_0_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_in_0_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_in_0_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_in_1_c_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_2_0_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_in_2_c_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_in_0_e_ready_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_in_0_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_in_0_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_in_0_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_2 = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_in_1_e_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsEOI_filtered_2_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_2_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_4 = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_5 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_in_2_e_ready_T = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_2 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2_1 = 1'h0; // @[Arbiter.scala:88:34] wire maskedBeats_0_3 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_1_3 = 1'h0; // @[Arbiter.scala:82:69] wire initBeats_3 = 1'h0; // @[Arbiter.scala:84:44] wire _state_WIRE_3_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_3_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_4_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_4_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_5_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_5_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_6_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_6_1 = 1'h0; // @[Arbiter.scala:88:34] wire auto_anon_out_1_e_ready = 1'h1; // @[Xbar.scala:74:9] wire x1_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire in_0_b_ready = 1'h1; // @[Xbar.scala:159:18] wire out_0_c_ready = 1'h1; // @[Xbar.scala:216:19] wire out_0_e_ready = 1'h1; // @[Xbar.scala:216:19] wire out_1_e_ready = 1'h1; // @[Xbar.scala:216:19] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_14 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_19 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_24 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_2_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_29 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_2_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_14 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_17 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_19 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_22 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_24 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_14 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_17 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_19 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_22 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_24 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_0_1 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_1_1 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_11 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_13 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_14 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_2_1 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire _beatsBO_opdata_T_1 = 1'h1; // @[Edges.scala:97:37] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_4 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T_4 = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_4 = 1'h1; // @[Xbar.scala:355:54] wire [2:0] in_0_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_0_e_bits_sink = 3'h0; // @[Xbar.scala:159:18] wire [2:0] out_0_b_bits_opcode = 3'h0; // @[Xbar.scala:216:19] wire [2:0] out_0_c_bits_opcode = 3'h0; // @[Xbar.scala:216:19] wire [2:0] out_0_c_bits_param = 3'h0; // @[Xbar.scala:216:19] wire [2:0] out_0_e_bits_sink = 3'h0; // @[Xbar.scala:216:19] wire [2:0] _requestEIO_uncommonBits_T = 3'h0; // @[Parameters.scala:52:29] wire [2:0] requestEIO_uncommonBits = 3'h0; // @[Parameters.scala:52:56] wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_2_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsEOI_filtered_0_bits_sink = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsEOI_filtered_1_bits_sink = 3'h0; // @[Xbar.scala:352:24] wire [31:0] in_0_b_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] in_0_c_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] out_0_b_bits_address = 32'h0; // @[Xbar.scala:216:19] wire [31:0] out_0_c_bits_address = 32'h0; // @[Xbar.scala:216:19] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_2_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [5:0] in_0_b_bits_source = 6'h0; // @[Xbar.scala:159:18] wire [5:0] in_0_c_bits_source = 6'h0; // @[Xbar.scala:159:18] wire [5:0] out_0_b_bits_source = 6'h0; // @[Xbar.scala:216:19] wire [5:0] out_0_c_bits_source = 6'h0; // @[Xbar.scala:216:19] wire [5:0] _requestBOI_uncommonBits_T = 6'h0; // @[Parameters.scala:52:29] wire [5:0] _requestBOI_uncommonBits_T_1 = 6'h0; // @[Parameters.scala:52:29] wire [5:0] _requestBOI_uncommonBits_T_2 = 6'h0; // @[Parameters.scala:52:29] wire [5:0] _beatsBO_decode_T_4 = 6'h0; // @[package.scala:243:76] wire [5:0] portsBIO_filtered_0_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] portsBIO_filtered_1_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] portsBIO_filtered_2_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] portsCOI_filtered_0_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] portsCOI_filtered_1_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [3:0] in_0_b_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] in_0_c_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] out_0_b_bits_size = 4'h0; // @[Xbar.scala:216:19] wire [3:0] out_0_c_bits_size = 4'h0; // @[Xbar.scala:216:19] wire [3:0] _requestBOI_T_5 = 4'h0; // @[Parameters.scala:54:10] wire [3:0] _requestBOI_T_10 = 4'h0; // @[Parameters.scala:54:10] wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_2_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [7:0] in_0_b_bits_mask = 8'h0; // @[Xbar.scala:159:18] wire [7:0] out_0_b_bits_mask = 8'h0; // @[Xbar.scala:216:19] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] portsBIO_filtered_1_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] portsBIO_filtered_2_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [1:0] in_0_b_bits_param = 2'h0; // @[Xbar.scala:159:18] wire [1:0] out_0_b_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] requestBOI_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] requestBOI_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_2_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [8:0] beatsBO_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsCI_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsCI_0 = 9'h0; // @[Edges.scala:221:14] wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] beatsBO_decode_1 = 3'h7; // @[Edges.scala:220:59] wire [5:0] _beatsBO_decode_T_5 = 6'h3F; // @[package.scala:243:46] wire [20:0] _beatsBO_decode_T_3 = 21'hFC0; // @[package.scala:243:71] wire [4:0] requestBOI_uncommonBits = 5'h0; // @[Parameters.scala:52:56] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_12 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_13 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_17 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_18 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_22 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_23 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_27 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_28 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_2_a_ready; // @[MixedNode.scala:551:17] wire anonIn_2_a_valid = auto_anon_in_2_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_2_a_bits_opcode = auto_anon_in_2_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_2_a_bits_param = auto_anon_in_2_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_2_a_bits_size = auto_anon_in_2_a_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_2_a_bits_source = auto_anon_in_2_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_2_a_bits_address = auto_anon_in_2_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_2_a_bits_mask = auto_anon_in_2_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_2_a_bits_data = auto_anon_in_2_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_2_a_bits_corrupt = auto_anon_in_2_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_2_b_ready = auto_anon_in_2_b_ready_0; // @[Xbar.scala:74:9] wire anonIn_2_b_valid; // @[MixedNode.scala:551:17] wire [1:0] anonIn_2_b_bits_param; // @[MixedNode.scala:551:17] wire [1:0] anonIn_2_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] anonIn_2_b_bits_address; // @[MixedNode.scala:551:17] wire anonIn_2_c_ready; // @[MixedNode.scala:551:17] wire anonIn_2_c_valid = auto_anon_in_2_c_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_2_c_bits_opcode = auto_anon_in_2_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_2_c_bits_param = auto_anon_in_2_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_2_c_bits_size = auto_anon_in_2_c_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_2_c_bits_source = auto_anon_in_2_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_2_c_bits_address = auto_anon_in_2_c_bits_address_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_2_c_bits_data = auto_anon_in_2_c_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_2_c_bits_corrupt = auto_anon_in_2_c_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_2_d_ready = auto_anon_in_2_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_2_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_2_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_2_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_2_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] anonIn_2_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_2_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_2_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_2_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_2_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_2_e_ready; // @[MixedNode.scala:551:17] wire anonIn_2_e_valid = auto_anon_in_2_e_valid_0; // @[Xbar.scala:74:9] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire [2:0] anonIn_2_e_bits_sink = auto_anon_in_2_e_bits_sink_0; // @[Xbar.scala:74:9] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_1_b_ready = auto_anon_in_1_b_ready_0; // @[Xbar.scala:74:9] wire anonIn_1_b_valid; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_b_bits_param; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] anonIn_1_b_bits_address; // @[MixedNode.scala:551:17] wire anonIn_1_c_ready; // @[MixedNode.scala:551:17] wire anonIn_1_c_valid = auto_anon_in_1_c_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_c_bits_opcode = auto_anon_in_1_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_c_bits_param = auto_anon_in_1_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_c_bits_size = auto_anon_in_1_c_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_1_c_bits_source = auto_anon_in_1_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_c_bits_address = auto_anon_in_1_c_bits_address_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_1_c_bits_data = auto_anon_in_1_c_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_1_c_bits_corrupt = auto_anon_in_1_c_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_1_e_ready; // @[MixedNode.scala:551:17] wire anonIn_1_e_valid = auto_anon_in_1_e_valid_0; // @[Xbar.scala:74:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_e_bits_sink = auto_anon_in_1_e_bits_sink_0; // @[Xbar.scala:74:9] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_b_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_b_valid = auto_anon_out_1_b_valid_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_b_bits_param = auto_anon_out_1_b_bits_param_0; // @[Xbar.scala:74:9] wire [5:0] x1_anonOut_b_bits_source = auto_anon_out_1_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] x1_anonOut_b_bits_address = auto_anon_out_1_b_bits_address_0; // @[Xbar.scala:74:9] wire x1_anonOut_c_ready = auto_anon_out_1_c_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [5:0] x1_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire x1_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = auto_anon_out_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_a_ready_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_b_bits_param_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_2_b_bits_address_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_b_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_c_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_2_d_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_2_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_e_ready_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_b_bits_param_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_b_bits_address_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_b_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_c_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_e_ready_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_b_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_c_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_c_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_1_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_1_c_bits_address_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_c_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_c_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_c_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_e_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_e_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [28:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [4:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [4:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_1_a_bits_mask = anonIn_1_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18] wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_1_b_ready = anonIn_1_b_ready; // @[Xbar.scala:159:18] wire in_1_b_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_b_valid_0 = anonIn_1_b_valid; // @[Xbar.scala:74:9] wire [1:0] in_1_b_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_b_bits_param_0 = anonIn_1_b_bits_param; // @[Xbar.scala:74:9] wire [1:0] _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_1_b_bits_source_0 = anonIn_1_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] in_1_b_bits_address; // @[Xbar.scala:159:18] assign auto_anon_in_1_b_bits_address_0 = anonIn_1_b_bits_address; // @[Xbar.scala:74:9] wire in_1_c_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_c_ready_0 = anonIn_1_c_ready; // @[Xbar.scala:74:9] wire in_1_c_valid = anonIn_1_c_valid; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_opcode = anonIn_1_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_param = anonIn_1_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_1_c_bits_size = anonIn_1_c_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_1_c_bits_address = anonIn_1_c_bits_address; // @[Xbar.scala:159:18] wire [63:0] in_1_c_bits_data = anonIn_1_c_bits_data; // @[Xbar.scala:159:18] wire in_1_c_bits_corrupt = anonIn_1_c_bits_corrupt; // @[Xbar.scala:159:18] wire in_1_d_ready = anonIn_1_d_ready; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69] assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_1_e_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_e_ready_0 = anonIn_1_e_ready; // @[Xbar.scala:74:9] wire in_1_e_valid = anonIn_1_e_valid; // @[Xbar.scala:159:18] wire [2:0] in_1_e_bits_sink = anonIn_1_e_bits_sink; // @[Xbar.scala:159:18] wire in_2_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_2_a_ready_0 = anonIn_2_a_ready; // @[Xbar.scala:74:9] wire in_2_a_valid = anonIn_2_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_2_a_bits_opcode = anonIn_2_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_2_a_bits_param = anonIn_2_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_2_a_bits_size = anonIn_2_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_2_a_bits_address = anonIn_2_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_2_a_bits_mask = anonIn_2_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_2_a_bits_data = anonIn_2_a_bits_data; // @[Xbar.scala:159:18] wire in_2_a_bits_corrupt = anonIn_2_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_2_b_ready = anonIn_2_b_ready; // @[Xbar.scala:159:18] wire in_2_b_valid; // @[Xbar.scala:159:18] assign auto_anon_in_2_b_valid_0 = anonIn_2_b_valid; // @[Xbar.scala:74:9] wire [1:0] in_2_b_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_2_b_bits_param_0 = anonIn_2_b_bits_param; // @[Xbar.scala:74:9] wire [1:0] _anonIn_b_bits_source_T_1; // @[Xbar.scala:156:69] assign auto_anon_in_2_b_bits_source_0 = anonIn_2_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] in_2_b_bits_address; // @[Xbar.scala:159:18] assign auto_anon_in_2_b_bits_address_0 = anonIn_2_b_bits_address; // @[Xbar.scala:74:9] wire in_2_c_ready; // @[Xbar.scala:159:18] assign auto_anon_in_2_c_ready_0 = anonIn_2_c_ready; // @[Xbar.scala:74:9] wire in_2_c_valid = anonIn_2_c_valid; // @[Xbar.scala:159:18] wire [2:0] in_2_c_bits_opcode = anonIn_2_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_2_c_bits_param = anonIn_2_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_2_c_bits_size = anonIn_2_c_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_2_c_bits_address = anonIn_2_c_bits_address; // @[Xbar.scala:159:18] wire [63:0] in_2_c_bits_data = anonIn_2_c_bits_data; // @[Xbar.scala:159:18] wire in_2_c_bits_corrupt = anonIn_2_c_bits_corrupt; // @[Xbar.scala:159:18] wire in_2_d_ready = anonIn_2_d_ready; // @[Xbar.scala:159:18] wire in_2_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_valid_0 = anonIn_2_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_2_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_opcode_0 = anonIn_2_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_2_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_param_0 = anonIn_2_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_2_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_size_0 = anonIn_2_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] _anonIn_d_bits_source_T_2; // @[Xbar.scala:156:69] assign auto_anon_in_2_d_bits_source_0 = anonIn_2_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_2_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_sink_0 = anonIn_2_d_bits_sink; // @[Xbar.scala:74:9] wire in_2_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_denied_0 = anonIn_2_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_2_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_data_0 = anonIn_2_d_bits_data; // @[Xbar.scala:74:9] wire in_2_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_corrupt_0 = anonIn_2_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_2_e_ready; // @[Xbar.scala:159:18] assign auto_anon_in_2_e_ready_0 = anonIn_2_e_ready; // @[Xbar.scala:74:9] wire in_2_e_valid = anonIn_2_e_valid; // @[Xbar.scala:159:18] wire [2:0] in_2_e_bits_sink = anonIn_2_e_bits_sink; // @[Xbar.scala:159:18] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [5:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [5:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [5:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_b_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_b_ready_0 = x1_anonOut_b_ready; // @[Xbar.scala:74:9] wire out_1_b_valid = x1_anonOut_b_valid; // @[Xbar.scala:216:19] wire [1:0] out_1_b_bits_param = x1_anonOut_b_bits_param; // @[Xbar.scala:216:19] wire [5:0] out_1_b_bits_source = x1_anonOut_b_bits_source; // @[Xbar.scala:216:19] wire [31:0] out_1_b_bits_address = x1_anonOut_b_bits_address; // @[Xbar.scala:216:19] wire out_1_c_ready = x1_anonOut_c_ready; // @[Xbar.scala:216:19] wire out_1_c_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_valid_0 = x1_anonOut_c_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_c_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_opcode_0 = x1_anonOut_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_c_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_param_0 = x1_anonOut_c_bits_param; // @[Xbar.scala:74:9] assign auto_anon_out_1_c_bits_size_0 = x1_anonOut_c_bits_size; // @[Xbar.scala:74:9] wire [5:0] out_1_c_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_source_0 = x1_anonOut_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_1_c_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_address_0 = x1_anonOut_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] out_1_c_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_data_0 = x1_anonOut_c_bits_data; // @[Xbar.scala:74:9] wire out_1_c_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_corrupt_0 = x1_anonOut_c_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = x1_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [5:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [2:0] _out_1_d_bits_sink_T = x1_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_1_e_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_e_valid_0 = x1_anonOut_e_valid; // @[Xbar.scala:74:9] wire [2:0] _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] assign auto_anon_out_1_e_bits_sink_0 = x1_anonOut_e_bits_sink; // @[Xbar.scala:74:9] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [5:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire _portsAOI_in_1_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_1_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_1_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [5:0] _in_1_a_bits_source_T; // @[Xbar.scala:166:55] wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_1_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_1_0_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_1_1_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_28 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_1_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_1_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_1_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_1_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_1_ready = in_1_b_ready; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_1_valid; // @[Xbar.scala:352:24] assign anonIn_1_b_valid = in_1_b_valid; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_1_1_bits_param; // @[Xbar.scala:352:24] assign anonIn_1_b_bits_param = in_1_b_bits_param; // @[Xbar.scala:159:18] wire [5:0] portsBIO_filtered_1_1_bits_source; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_1_bits_address; // @[Xbar.scala:352:24] assign anonIn_1_b_bits_address = in_1_b_bits_address; // @[Xbar.scala:159:18] wire _portsCOI_in_1_c_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_1_c_ready = in_1_c_ready; // @[Xbar.scala:159:18] wire _portsCOI_filtered_0_valid_T_3 = in_1_c_valid; // @[Xbar.scala:159:18, :355:40] wire _portsCOI_filtered_1_valid_T_3 = in_1_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsCOI_filtered_1_0_bits_opcode = in_1_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_1_1_bits_opcode = in_1_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = in_1_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_1_1_bits_param = in_1_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [5:0] _in_1_c_bits_source_T; // @[Xbar.scala:187:55] wire [3:0] portsCOI_filtered_1_0_bits_size = in_1_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_1_1_bits_size = in_1_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsCOI_filtered_1_0_bits_source = in_1_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsCOI_filtered_1_1_bits_source = in_1_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestCIO_T_10 = in_1_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] _requestCIO_T_15 = in_1_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsCOI_filtered_1_0_bits_address = in_1_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsCOI_filtered_1_1_bits_address = in_1_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsCOI_filtered_1_0_bits_data = in_1_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsCOI_filtered_1_1_bits_data = in_1_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_1_0_bits_corrupt = in_1_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_1_1_bits_corrupt = in_1_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_1_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_1_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_1_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_1_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire [5:0] _in_1_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire _in_1_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] _in_1_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire _in_1_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire _portsEOI_in_1_e_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_1_e_ready = in_1_e_ready; // @[Xbar.scala:159:18] wire _portsEOI_filtered_1_valid_T_3 = in_1_e_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] _requestEIO_uncommonBits_T_1 = in_1_e_bits_sink; // @[Xbar.scala:159:18] wire _portsAOI_in_2_a_ready_WIRE; // @[Mux.scala:30:73] wire [2:0] portsEOI_filtered_1_0_bits_sink = in_1_e_bits_sink; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsEOI_filtered_1_1_bits_sink = in_1_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign anonIn_2_a_ready = in_2_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_2_0_bits_opcode = in_2_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_2_1_bits_opcode = in_2_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_2_0_bits_param = in_2_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_2_1_bits_param = in_2_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [5:0] _in_2_a_bits_source_T; // @[Xbar.scala:166:55] wire [3:0] portsAOI_filtered_2_0_bits_size = in_2_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_2_1_bits_size = in_2_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_2_0_bits_source = in_2_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_2_1_bits_source = in_2_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_56 = in_2_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_2_0_bits_address = in_2_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_2_1_bits_address = in_2_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_2_0_bits_mask = in_2_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_2_1_bits_mask = in_2_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_2_0_bits_data = in_2_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_2_1_bits_data = in_2_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_2_0_bits_corrupt = in_2_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_2_1_bits_corrupt = in_2_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_2_ready = in_2_b_ready; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_2_valid; // @[Xbar.scala:352:24] assign anonIn_2_b_valid = in_2_b_valid; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_1_2_bits_param; // @[Xbar.scala:352:24] assign anonIn_2_b_bits_param = in_2_b_bits_param; // @[Xbar.scala:159:18] wire [5:0] portsBIO_filtered_1_2_bits_source; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_2_bits_address; // @[Xbar.scala:352:24] assign anonIn_2_b_bits_address = in_2_b_bits_address; // @[Xbar.scala:159:18] wire _portsCOI_in_2_c_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_2_c_ready = in_2_c_ready; // @[Xbar.scala:159:18] wire _portsCOI_filtered_0_valid_T_5 = in_2_c_valid; // @[Xbar.scala:159:18, :355:40] wire _portsCOI_filtered_1_valid_T_5 = in_2_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsCOI_filtered_2_0_bits_opcode = in_2_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_2_1_bits_opcode = in_2_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_2_0_bits_param = in_2_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_2_1_bits_param = in_2_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [5:0] _in_2_c_bits_source_T; // @[Xbar.scala:187:55] wire [3:0] portsCOI_filtered_2_0_bits_size = in_2_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_2_1_bits_size = in_2_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsCOI_filtered_2_0_bits_source = in_2_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsCOI_filtered_2_1_bits_source = in_2_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestCIO_T_20 = in_2_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] _requestCIO_T_25 = in_2_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsCOI_filtered_2_0_bits_address = in_2_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsCOI_filtered_2_1_bits_address = in_2_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsCOI_filtered_2_0_bits_data = in_2_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsCOI_filtered_2_1_bits_data = in_2_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_2_0_bits_corrupt = in_2_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_2_1_bits_corrupt = in_2_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_2_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_2_d_valid = in_2_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_2_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_2_d_bits_opcode = in_2_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_2_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_2_d_bits_param = in_2_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_2_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_2_d_bits_size = in_2_d_bits_size; // @[Xbar.scala:159:18] wire [5:0] _in_2_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [2:0] _in_2_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_2_d_bits_sink = in_2_d_bits_sink; // @[Xbar.scala:159:18] wire _in_2_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_2_d_bits_denied = in_2_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] _in_2_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_2_d_bits_data = in_2_d_bits_data; // @[Xbar.scala:159:18] wire _in_2_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_2_d_bits_corrupt = in_2_d_bits_corrupt; // @[Xbar.scala:159:18] wire _portsEOI_in_2_e_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_2_e_ready = in_2_e_ready; // @[Xbar.scala:159:18] wire _portsEOI_filtered_1_valid_T_5 = in_2_e_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] _requestEIO_uncommonBits_T_2 = in_2_e_bits_sink; // @[Xbar.scala:159:18] wire [2:0] portsEOI_filtered_2_0_bits_sink = in_2_e_bits_sink; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsEOI_filtered_2_1_bits_sink = in_2_e_bits_sink; // @[Xbar.scala:159:18, :352:24] wire [5:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [5:0] in_1_b_bits_source; // @[Xbar.scala:159:18] wire [5:0] in_1_d_bits_source; // @[Xbar.scala:159:18] wire [5:0] in_2_b_bits_source; // @[Xbar.scala:159:18] wire [5:0] in_2_d_bits_source; // @[Xbar.scala:159:18] assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_d_bits_source_T = in_0_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign _in_1_a_bits_source_T = {4'h9, anonIn_1_a_bits_source}; // @[Xbar.scala:166:55] assign in_1_a_bits_source = _in_1_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign _anonIn_b_bits_source_T = in_1_b_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_1_b_bits_source = _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign _in_1_c_bits_source_T = {4'h9, anonIn_1_c_bits_source}; // @[Xbar.scala:187:55] assign in_1_c_bits_source = _in_1_c_bits_source_T; // @[Xbar.scala:159:18, :187:55] assign _anonIn_d_bits_source_T_1 = in_1_d_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_1_d_bits_source = _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69] assign _in_2_a_bits_source_T = {4'h8, anonIn_2_a_bits_source}; // @[Xbar.scala:166:55] assign in_2_a_bits_source = _in_2_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign _anonIn_b_bits_source_T_1 = in_2_b_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_2_b_bits_source = _anonIn_b_bits_source_T_1; // @[Xbar.scala:156:69] assign _in_2_c_bits_source_T = {4'h8, anonIn_2_c_bits_source}; // @[Xbar.scala:187:55] assign in_2_c_bits_source = _in_2_c_bits_source_T; // @[Xbar.scala:159:18, :187:55] assign _anonIn_d_bits_source_T_2 = in_2_d_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_2_d_bits_source = _anonIn_d_bits_source_T_2; // @[Xbar.scala:156:69] wire _out_0_a_valid_T_7; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire [5:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_2_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_2_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_2_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [5:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] _requestDOI_uncommonBits_T_1 = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] _requestDOI_uncommonBits_T_2 = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [5:0] portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [5:0] portsDIO_filtered_2_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_2_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_2_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_2_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_2_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _out_1_a_valid_T_7; // @[Arbiter.scala:96:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_1_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_1_a_bits_WIRE_param; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_1_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_WIRE_source; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_1_a_bits_WIRE_address; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_address = out_1_a_bits_address; // @[Xbar.scala:216:19] wire [7:0] _out_1_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] wire [63:0] _out_1_a_bits_WIRE_data; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] wire _out_1_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire _portsBIO_out_1_b_ready_WIRE; // @[Mux.scala:30:73] assign x1_anonOut_b_ready = out_1_b_ready; // @[Xbar.scala:216:19] wire [1:0] portsBIO_filtered_1_0_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_1_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_2_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24] wire [5:0] _requestBOI_uncommonBits_T_3 = out_1_b_bits_source; // @[Xbar.scala:216:19] wire [5:0] _requestBOI_uncommonBits_T_4 = out_1_b_bits_source; // @[Xbar.scala:216:19] wire [5:0] _requestBOI_uncommonBits_T_5 = out_1_b_bits_source; // @[Xbar.scala:216:19] wire [5:0] portsBIO_filtered_1_0_bits_source = out_1_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_1_bits_source = out_1_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_2_bits_source = out_1_b_bits_source; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsBIO_filtered_1_0_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_1_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_2_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24] wire _out_1_c_valid_T_4; // @[Arbiter.scala:96:24] assign x1_anonOut_c_valid = out_1_c_valid; // @[Xbar.scala:216:19] wire [2:0] _out_1_c_bits_WIRE_opcode; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_opcode = out_1_c_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_1_c_bits_WIRE_param; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_param = out_1_c_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_1_c_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _out_1_c_bits_WIRE_source; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_source = out_1_c_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_1_c_bits_WIRE_address; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_address = out_1_c_bits_address; // @[Xbar.scala:216:19] wire [63:0] _out_1_c_bits_WIRE_data; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_data = out_1_c_bits_data; // @[Xbar.scala:216:19] wire _out_1_c_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_corrupt = out_1_c_bits_corrupt; // @[Xbar.scala:216:19] wire _portsDIO_out_1_d_ready_WIRE; // @[Mux.scala:30:73] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_1_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_2_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_1_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_2_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_1_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_2_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [5:0] _requestDOI_uncommonBits_T_3 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] _requestDOI_uncommonBits_T_4 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] _requestDOI_uncommonBits_T_5 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [5:0] portsDIO_filtered_1_1_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [5:0] portsDIO_filtered_1_2_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_0_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_1_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_2_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_1_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_2_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_1_1_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_1_2_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_1_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_2_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _out_1_e_valid_T_4; // @[Arbiter.scala:96:24] assign x1_anonOut_e_valid = out_1_e_valid; // @[Xbar.scala:216:19] wire _beatsLeft_T_12 = out_1_e_valid; // @[Decoupled.scala:51:35] wire [2:0] _out_1_e_bits_WIRE_sink; // @[Mux.scala:30:73] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign _anonOut_e_bits_sink_T = out_1_e_bits_sink; // @[Xbar.scala:156:69, :216:19] wire [3:0] out_1_a_bits_size; // @[Xbar.scala:216:19] wire [3:0] out_1_c_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address[28:0]; // @[Xbar.scala:216:19, :222:41] assign out_0_d_bits_sink = {2'h0, _out_0_d_bits_sink_T}; // @[Xbar.scala:216:19, :251:{28,53}] assign x1_anonOut_a_bits_size = out_1_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41] assign x1_anonOut_c_bits_size = out_1_c_bits_size[2:0]; // @[Xbar.scala:216:19, :241:41] assign out_1_d_bits_size = {1'h0, x1_anonOut_d_bits_size}; // @[Xbar.scala:216:19, :250:29] assign out_1_d_bits_sink = _out_1_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign x1_anonOut_e_bits_sink = _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_2 = _requestAIO_T_1 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_5 = {in_0_a_bits_address[31:17], in_0_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_7 = _requestAIO_T_6 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_10 = {in_0_a_bits_address[31:28], in_0_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_11 = {1'h0, _requestAIO_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_12 = _requestAIO_T_11 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_13 = _requestAIO_T_12; // @[Parameters.scala:137:46] wire _requestAIO_T_14 = _requestAIO_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_15 = _requestAIO_T_4 | _requestAIO_T_9; // @[Xbar.scala:291:92] wire _requestAIO_T_16 = _requestAIO_T_15 | _requestAIO_T_14; // @[Xbar.scala:291:92] wire requestAIO_0_0 = _requestAIO_T_16; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_17 = {in_0_a_bits_address[31:28], in_0_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_18 = {1'h0, _requestAIO_T_17}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_19 = _requestAIO_T_18 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_20 = _requestAIO_T_19; // @[Parameters.scala:137:46] wire _requestAIO_T_21 = _requestAIO_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_22 = in_0_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_23 = {1'h0, _requestAIO_T_22}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_24 = _requestAIO_T_23 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_25 = _requestAIO_T_24; // @[Parameters.scala:137:46] wire _requestAIO_T_26 = _requestAIO_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_27 = _requestAIO_T_21 | _requestAIO_T_26; // @[Xbar.scala:291:92] wire requestAIO_0_1 = _requestAIO_T_27; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_29 = {1'h0, _requestAIO_T_28}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_30 = _requestAIO_T_29 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_31 = _requestAIO_T_30; // @[Parameters.scala:137:46] wire _requestAIO_T_32 = _requestAIO_T_31 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_33 = {in_1_a_bits_address[31:17], in_1_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_34 = {1'h0, _requestAIO_T_33}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_35 = _requestAIO_T_34 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_36 = _requestAIO_T_35; // @[Parameters.scala:137:46] wire _requestAIO_T_37 = _requestAIO_T_36 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_38 = {in_1_a_bits_address[31:28], in_1_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_39 = {1'h0, _requestAIO_T_38}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_40 = _requestAIO_T_39 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_41 = _requestAIO_T_40; // @[Parameters.scala:137:46] wire _requestAIO_T_42 = _requestAIO_T_41 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_43 = _requestAIO_T_32 | _requestAIO_T_37; // @[Xbar.scala:291:92] wire _requestAIO_T_44 = _requestAIO_T_43 | _requestAIO_T_42; // @[Xbar.scala:291:92] wire requestAIO_1_0 = _requestAIO_T_44; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T_2 = requestAIO_1_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_45 = {in_1_a_bits_address[31:28], in_1_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_46 = {1'h0, _requestAIO_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_47 = _requestAIO_T_46 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_48 = _requestAIO_T_47; // @[Parameters.scala:137:46] wire _requestAIO_T_49 = _requestAIO_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_50 = in_1_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_51 = {1'h0, _requestAIO_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_52 = _requestAIO_T_51 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_53 = _requestAIO_T_52; // @[Parameters.scala:137:46] wire _requestAIO_T_54 = _requestAIO_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_55 = _requestAIO_T_49 | _requestAIO_T_54; // @[Xbar.scala:291:92] wire requestAIO_1_1 = _requestAIO_T_55; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T_2 = requestAIO_1_1; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_57 = {1'h0, _requestAIO_T_56}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_58 = _requestAIO_T_57 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_59 = _requestAIO_T_58; // @[Parameters.scala:137:46] wire _requestAIO_T_60 = _requestAIO_T_59 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_61 = {in_2_a_bits_address[31:17], in_2_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_62 = {1'h0, _requestAIO_T_61}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_63 = _requestAIO_T_62 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_64 = _requestAIO_T_63; // @[Parameters.scala:137:46] wire _requestAIO_T_65 = _requestAIO_T_64 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_66 = {in_2_a_bits_address[31:28], in_2_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_67 = {1'h0, _requestAIO_T_66}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_68 = _requestAIO_T_67 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_69 = _requestAIO_T_68; // @[Parameters.scala:137:46] wire _requestAIO_T_70 = _requestAIO_T_69 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_71 = _requestAIO_T_60 | _requestAIO_T_65; // @[Xbar.scala:291:92] wire _requestAIO_T_72 = _requestAIO_T_71 | _requestAIO_T_70; // @[Xbar.scala:291:92] wire requestAIO_2_0 = _requestAIO_T_72; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T_4 = requestAIO_2_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_73 = {in_2_a_bits_address[31:28], in_2_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_74 = {1'h0, _requestAIO_T_73}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_75 = _requestAIO_T_74 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_76 = _requestAIO_T_75; // @[Parameters.scala:137:46] wire _requestAIO_T_77 = _requestAIO_T_76 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_78 = in_2_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_79 = {1'h0, _requestAIO_T_78}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_80 = _requestAIO_T_79 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_81 = _requestAIO_T_80; // @[Parameters.scala:137:46] wire _requestAIO_T_82 = _requestAIO_T_81 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_83 = _requestAIO_T_77 | _requestAIO_T_82; // @[Xbar.scala:291:92] wire requestAIO_2_1 = _requestAIO_T_83; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T_4 = requestAIO_2_1; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestCIO_T_11 = {1'h0, _requestCIO_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_16 = {1'h0, _requestCIO_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_21 = {1'h0, _requestCIO_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_26 = {1'h0, _requestCIO_T_25}; // @[Parameters.scala:137:{31,41}] wire [4:0] requestBOI_uncommonBits_3 = _requestBOI_uncommonBits_T_3[4:0]; // @[Parameters.scala:52:{29,56}] wire _requestBOI_T_15 = out_1_b_bits_source[5]; // @[Xbar.scala:216:19] wire _requestBOI_T_16 = ~_requestBOI_T_15; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_18 = _requestBOI_T_16; // @[Parameters.scala:54:{32,67}] wire requestBOI_1_0 = _requestBOI_T_18; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_0_valid_T_2 = requestBOI_1_0; // @[Xbar.scala:355:54] wire [1:0] requestBOI_uncommonBits_4 = _requestBOI_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _requestBOI_T_20 = out_1_b_bits_source[5:2]; // @[Xbar.scala:216:19] wire [3:0] _requestBOI_T_25 = out_1_b_bits_source[5:2]; // @[Xbar.scala:216:19] wire _requestBOI_T_21 = _requestBOI_T_20 == 4'h9; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_23 = _requestBOI_T_21; // @[Parameters.scala:54:{32,67}] wire requestBOI_1_1 = _requestBOI_T_23; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_1_valid_T_2 = requestBOI_1_1; // @[Xbar.scala:355:54] wire [1:0] requestBOI_uncommonBits_5 = _requestBOI_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _requestBOI_T_26 = _requestBOI_T_25 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_28 = _requestBOI_T_26; // @[Parameters.scala:54:{32,67}] wire requestBOI_1_2 = _requestBOI_T_28; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_2_valid_T_2 = requestBOI_1_2; // @[Xbar.scala:355:54] wire [4:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[4:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T = out_0_d_bits_source[5]; // @[Xbar.scala:216:19] wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire [1:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _requestDOI_T_5 = out_0_d_bits_source[5:2]; // @[Xbar.scala:216:19] wire [3:0] _requestDOI_T_10 = out_0_d_bits_source[5:2]; // @[Xbar.scala:216:19] wire _requestDOI_T_6 = _requestDOI_T_5 == 4'h9; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_8 = _requestDOI_T_6; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_1 = _requestDOI_T_8; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire [1:0] requestDOI_uncommonBits_2 = _requestDOI_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T_11 = _requestDOI_T_10 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_13 = _requestDOI_T_11; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_2 = _requestDOI_T_13; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_2_valid_T = requestDOI_0_2; // @[Xbar.scala:355:54] wire [4:0] requestDOI_uncommonBits_3 = _requestDOI_uncommonBits_T_3[4:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T_15 = out_1_d_bits_source[5]; // @[Xbar.scala:216:19] wire _requestDOI_T_16 = ~_requestDOI_T_15; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_18 = _requestDOI_T_16; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_0 = _requestDOI_T_18; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T_2 = requestDOI_1_0; // @[Xbar.scala:355:54] wire [1:0] requestDOI_uncommonBits_4 = _requestDOI_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _requestDOI_T_20 = out_1_d_bits_source[5:2]; // @[Xbar.scala:216:19] wire [3:0] _requestDOI_T_25 = out_1_d_bits_source[5:2]; // @[Xbar.scala:216:19] wire _requestDOI_T_21 = _requestDOI_T_20 == 4'h9; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_23 = _requestDOI_T_21; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_1 = _requestDOI_T_23; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_1_valid_T_2 = requestDOI_1_1; // @[Xbar.scala:355:54] wire [1:0] requestDOI_uncommonBits_5 = _requestDOI_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T_26 = _requestDOI_T_25 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_28 = _requestDOI_T_26; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_2 = _requestDOI_T_28; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_2_valid_T_2 = requestDOI_1_2; // @[Xbar.scala:355:54] wire [2:0] requestEIO_uncommonBits_1 = _requestEIO_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [2:0] requestEIO_uncommonBits_2 = _requestEIO_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsAI_decode_T_6 = 27'hFFF << in_2_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_7 = _beatsAI_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_8 = ~_beatsAI_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] beatsAI_decode_2 = _beatsAI_decode_T_8[11:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T_2 = in_2_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata_2 = ~_beatsAI_opdata_T_2; // @[Edges.scala:92:{28,37}] wire [8:0] beatsAI_2 = beatsAI_opdata_2 ? beatsAI_decode_2 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF << in_1_c_bits_size; // @[package.scala:243:71] wire [11:0] _beatsCI_decode_T_4 = _beatsCI_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsCI_decode_T_5 = ~_beatsCI_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] beatsCI_decode_1 = _beatsCI_decode_T_5[11:3]; // @[package.scala:243:46] wire beatsCI_opdata_1 = in_1_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [8:0] beatsCI_1 = beatsCI_opdata_1 ? beatsCI_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] _beatsCI_decode_T_6 = 27'hFFF << in_2_c_bits_size; // @[package.scala:243:71] wire [11:0] _beatsCI_decode_T_7 = _beatsCI_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsCI_decode_T_8 = ~_beatsCI_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] beatsCI_decode_2 = _beatsCI_decode_T_8[11:3]; // @[package.scala:243:46] wire beatsCI_opdata_2 = in_2_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [8:0] beatsCI_2 = beatsCI_opdata_2 ? beatsCI_decode_2 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [20:0] _beatsDO_decode_T_3 = 21'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_1_ready_T; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T | _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_1; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_3; // @[Xbar.scala:355:40] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_3 = in_1_a_valid & _portsAOI_filtered_0_valid_T_2; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_3 = in_1_a_valid & _portsAOI_filtered_1_valid_T_2; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_1_valid = _portsAOI_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_1_a_ready_T = requestAIO_1_0 & portsAOI_filtered_1_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_1_a_ready_T_1 = requestAIO_1_1 & portsAOI_filtered_1_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_1_a_ready_T_2 = _portsAOI_in_1_a_ready_T | _portsAOI_in_1_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_1_a_ready_WIRE = _portsAOI_in_1_a_ready_T_2; // @[Mux.scala:30:73] assign in_1_a_ready = _portsAOI_in_1_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_2; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_5; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_2; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_5; // @[Xbar.scala:355:40] wire portsAOI_filtered_2_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_2_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_2_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_2_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_5 = in_2_a_valid & _portsAOI_filtered_0_valid_T_4; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_2_0_valid = _portsAOI_filtered_0_valid_T_5; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_5 = in_2_a_valid & _portsAOI_filtered_1_valid_T_4; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_2_1_valid = _portsAOI_filtered_1_valid_T_5; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_2_a_ready_T = requestAIO_2_0 & portsAOI_filtered_2_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_2_a_ready_T_1 = requestAIO_2_1 & portsAOI_filtered_2_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_2_a_ready_T_2 = _portsAOI_in_2_a_ready_T | _portsAOI_in_2_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_2_a_ready_WIRE = _portsAOI_in_2_a_ready_T_2; // @[Mux.scala:30:73] assign in_2_a_ready = _portsAOI_in_2_a_ready_WIRE; // @[Mux.scala:30:73] wire _portsBIO_filtered_0_valid_T_3; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T_3; // @[Xbar.scala:355:40] assign in_1_b_valid = portsBIO_filtered_1_1_valid; // @[Xbar.scala:159:18, :352:24] assign in_1_b_bits_param = portsBIO_filtered_1_1_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_1_b_bits_source = portsBIO_filtered_1_1_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_1_b_bits_address = portsBIO_filtered_1_1_bits_address; // @[Xbar.scala:159:18, :352:24] wire _portsBIO_filtered_2_valid_T_3; // @[Xbar.scala:355:40] assign in_2_b_valid = portsBIO_filtered_1_2_valid; // @[Xbar.scala:159:18, :352:24] assign in_2_b_bits_param = portsBIO_filtered_1_2_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_2_b_bits_source = portsBIO_filtered_1_2_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_2_b_bits_address = portsBIO_filtered_1_2_bits_address; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_0_valid; // @[Xbar.scala:352:24] assign _portsBIO_filtered_0_valid_T_3 = out_1_b_valid & _portsBIO_filtered_0_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_0_valid = _portsBIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsBIO_filtered_1_valid_T_3 = out_1_b_valid & _portsBIO_filtered_1_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_1_valid = _portsBIO_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsBIO_filtered_2_valid_T_3 = out_1_b_valid & _portsBIO_filtered_2_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_2_valid = _portsBIO_filtered_2_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsBIO_out_1_b_ready_T_1 = requestBOI_1_1 & portsBIO_filtered_1_1_ready; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_3 = _portsBIO_out_1_b_ready_T_1; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_2 = requestBOI_1_2 & portsBIO_filtered_1_2_ready; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_4 = _portsBIO_out_1_b_ready_T_3 | _portsBIO_out_1_b_ready_T_2; // @[Mux.scala:30:73] assign _portsBIO_out_1_b_ready_WIRE = _portsBIO_out_1_b_ready_T_4; // @[Mux.scala:30:73] assign out_1_b_ready = _portsBIO_out_1_b_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_3; // @[Arbiter.scala:94:31] wire _portsCOI_in_1_c_ready_T_1 = portsCOI_filtered_1_1_ready; // @[Mux.scala:30:73] wire portsCOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_1_valid; // @[Xbar.scala:352:24] assign portsCOI_filtered_1_0_valid = _portsCOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign portsCOI_filtered_1_1_valid = _portsCOI_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsCOI_in_1_c_ready_T_2 = _portsCOI_in_1_c_ready_T_1; // @[Mux.scala:30:73] assign _portsCOI_in_1_c_ready_WIRE = _portsCOI_in_1_c_ready_T_2; // @[Mux.scala:30:73] assign in_1_c_ready = _portsCOI_in_1_c_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_4; // @[Arbiter.scala:94:31] wire _portsCOI_in_2_c_ready_T_1 = portsCOI_filtered_2_1_ready; // @[Mux.scala:30:73] wire portsCOI_filtered_2_0_valid; // @[Xbar.scala:352:24] wire portsCOI_filtered_2_1_valid; // @[Xbar.scala:352:24] assign portsCOI_filtered_2_0_valid = _portsCOI_filtered_0_valid_T_5; // @[Xbar.scala:352:24, :355:40] assign portsCOI_filtered_2_1_valid = _portsCOI_filtered_1_valid_T_5; // @[Xbar.scala:352:24, :355:40] wire _portsCOI_in_2_c_ready_T_2 = _portsCOI_in_2_c_ready_T_1; // @[Mux.scala:30:73] assign _portsCOI_in_2_c_ready_WIRE = _portsCOI_in_2_c_ready_T_2; // @[Mux.scala:30:73] assign in_2_c_ready = _portsCOI_in_2_c_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_3; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_7; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_2_ready_T; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_2_valid_T_1; // @[Xbar.scala:355:40] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_2_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_2_valid; // @[Xbar.scala:352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_2_valid_T_1 = out_0_d_valid & _portsDIO_filtered_2_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_2_valid = _portsDIO_filtered_2_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = requestDOI_0_2 & portsDIO_filtered_2_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_3 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_4 = _portsDIO_out_0_d_ready_T_3 | _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_4; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_4; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_8; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_1_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_2_ready_T_1; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_2_valid_T_3; // @[Xbar.scala:355:40] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_1_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_2_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_2_valid; // @[Xbar.scala:352:24] assign _portsDIO_filtered_0_valid_T_3 = out_1_d_valid & _portsDIO_filtered_0_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_3 = out_1_d_valid & _portsDIO_filtered_1_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_1_valid = _portsDIO_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_2_valid_T_3 = out_1_d_valid & _portsDIO_filtered_2_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_2_valid = _portsDIO_filtered_2_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_1_d_ready_T = requestDOI_1_0 & portsDIO_filtered_1_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_1 = requestDOI_1_1 & portsDIO_filtered_1_1_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_2 = requestDOI_1_2 & portsDIO_filtered_1_2_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_3 = _portsDIO_out_1_d_ready_T | _portsDIO_out_1_d_ready_T_1; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_4 = _portsDIO_out_1_d_ready_T_3 | _portsDIO_out_1_d_ready_T_2; // @[Mux.scala:30:73] assign _portsDIO_out_1_d_ready_WIRE = _portsDIO_out_1_d_ready_T_4; // @[Mux.scala:30:73] assign out_1_d_ready = _portsDIO_out_1_d_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_5; // @[Arbiter.scala:94:31] wire _portsEOI_in_1_e_ready_T_1 = portsEOI_filtered_1_1_ready; // @[Mux.scala:30:73] wire portsEOI_filtered_1_1_valid; // @[Xbar.scala:352:24] assign portsEOI_filtered_1_1_valid = _portsEOI_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsEOI_in_1_e_ready_T_2 = _portsEOI_in_1_e_ready_T_1; // @[Mux.scala:30:73] assign _portsEOI_in_1_e_ready_WIRE = _portsEOI_in_1_e_ready_T_2; // @[Mux.scala:30:73] assign in_1_e_ready = _portsEOI_in_1_e_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_6; // @[Arbiter.scala:94:31] wire _portsEOI_in_2_e_ready_T_1 = portsEOI_filtered_2_1_ready; // @[Mux.scala:30:73] wire portsEOI_filtered_2_1_valid; // @[Xbar.scala:352:24] assign portsEOI_filtered_2_1_valid = _portsEOI_filtered_1_valid_T_5; // @[Xbar.scala:352:24, :355:40] wire _portsEOI_in_2_e_ready_T_2 = _portsEOI_in_2_e_ready_T_1; // @[Mux.scala:30:73] assign _portsEOI_in_2_e_ready_WIRE = _portsEOI_in_2_e_ready_T_2; // @[Mux.scala:30:73] assign in_2_e_ready = _portsEOI_in_2_e_ready_WIRE; // @[Mux.scala:30:73] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] readys_hi = {portsAOI_filtered_2_0_valid, portsAOI_filtered_1_0_valid}; // @[Xbar.scala:352:24] wire [2:0] _readys_T = {readys_hi, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [2:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [2:0] readys_mask; // @[Arbiter.scala:23:23] wire [2:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [2:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [5:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [4:0] _readys_unready_T = readys_filter[5:1]; // @[package.scala:262:48] wire [5:0] _readys_unready_T_1 = {readys_filter[5], readys_filter[4:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1[5:2]; // @[package.scala:262:{43,48}] wire [5:0] _readys_unready_T_3 = {_readys_unready_T_1[5:4], _readys_unready_T_1[3:0] | _readys_unready_T_2}; // @[package.scala:262:{43,48}] wire [5:0] _readys_unready_T_4 = _readys_unready_T_3; // @[package.scala:262:43, :263:17] wire [4:0] _readys_unready_T_5 = _readys_unready_T_4[5:1]; // @[package.scala:263:17] wire [5:0] _readys_unready_T_6 = {readys_mask, 3'h0}; // @[Arbiter.scala:23:23, :25:66] wire [5:0] readys_unready = {1'h0, _readys_unready_T_5} | _readys_unready_T_6; // @[Arbiter.scala:25:{52,58,66}] wire [2:0] _readys_readys_T = readys_unready[5:3]; // @[Arbiter.scala:25:58, :26:29] wire [2:0] _readys_readys_T_1 = readys_unready[2:0]; // @[Arbiter.scala:25:58, :26:48] wire [2:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [2:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [2:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [2:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [3:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [2:0] _readys_mask_T_2 = _readys_mask_T_1[2:0]; // @[package.scala:253:{48,53}] wire [2:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [4:0] _readys_mask_T_4 = {_readys_mask_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [2:0] _readys_mask_T_5 = _readys_mask_T_4[2:0]; // @[package.scala:253:{48,53}] wire [2:0] _readys_mask_T_6 = _readys_mask_T_3 | _readys_mask_T_5; // @[package.scala:253:{43,53}] wire [2:0] _readys_mask_T_7 = _readys_mask_T_6; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _readys_T_10 = _readys_T_7[2]; // @[Arbiter.scala:30:11, :68:76] wire readys_2 = _readys_T_10; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire _winner_T_2 = readys_2 & portsAOI_filtered_2_0_valid; // @[Xbar.scala:352:24] wire winner_2 = _winner_T_2; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2 = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_2 | winner_2; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire [8:0] maskedBeats_0 = winner_0 ? beatsAI_0 : 9'h0; // @[Edges.scala:221:14] wire [8:0] maskedBeats_1 = winner_1 ? beatsAI_1 : 9'h0; // @[Edges.scala:221:14] wire [8:0] maskedBeats_2 = winner_2 ? beatsAI_2 : 9'h0; // @[Edges.scala:221:14] wire [8:0] _initBeats_T = maskedBeats_0 | maskedBeats_1; // @[Arbiter.scala:82:69, :84:44] wire [8:0] initBeats = _initBeats_T | maskedBeats_2; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T = out_0_a_ready & out_0_a_valid; // @[Decoupled.scala:51:35] wire [9:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {9'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_2 = _beatsLeft_T_1[8:0]; // @[Arbiter.scala:85:52] wire [8:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_0; // @[Arbiter.scala:88:26] reg state_1; // @[Arbiter.scala:88:26] reg state_2; // @[Arbiter.scala:88:26] wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_2 = idle ? winner_2 : state_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_2 = idle ? readys_2 : state_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_0_ready_T = out_0_a_ready & allowed_0; // @[Xbar.scala:216:19] assign portsAOI_filtered_0_ready = _filtered_0_ready_T; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_1 = out_0_a_ready & allowed_1; // @[Xbar.scala:216:19] assign portsAOI_filtered_1_0_ready = _filtered_0_ready_T_1; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_2 = out_0_a_ready & allowed_2; // @[Xbar.scala:216:19] assign portsAOI_filtered_2_0_ready = _filtered_0_ready_T_2; // @[Xbar.scala:352:24] wire _out_0_a_valid_T_1 = _out_0_a_valid_T | portsAOI_filtered_2_0_valid; // @[Xbar.scala:352:24] wire _out_0_a_valid_T_2 = state_0 & portsAOI_filtered_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_3 = state_1 & portsAOI_filtered_1_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_4 = state_2 & portsAOI_filtered_2_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_5 = _out_0_a_valid_T_2 | _out_0_a_valid_T_3; // @[Mux.scala:30:73] wire _out_0_a_valid_T_6 = _out_0_a_valid_T_5 | _out_0_a_valid_T_4; // @[Mux.scala:30:73] wire _out_0_a_valid_WIRE = _out_0_a_valid_T_6; // @[Mux.scala:30:73] assign _out_0_a_valid_T_7 = idle ? _out_0_a_valid_T_1 : _out_0_a_valid_WIRE; // @[Mux.scala:30:73] assign out_0_a_valid = _out_0_a_valid_T_7; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_10; // @[Mux.scala:30:73] assign out_0_a_bits_opcode = _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_WIRE_9; // @[Mux.scala:30:73] assign out_0_a_bits_param = _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_WIRE_8; // @[Mux.scala:30:73] assign out_0_a_bits_size = _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _out_0_a_bits_WIRE_7; // @[Mux.scala:30:73] assign out_0_a_bits_source = _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_WIRE_6; // @[Mux.scala:30:73] assign out_0_a_bits_address = _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [7:0] _out_0_a_bits_WIRE_3; // @[Mux.scala:30:73] assign out_0_a_bits_mask = _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] wire [63:0] _out_0_a_bits_WIRE_2; // @[Mux.scala:30:73] assign out_0_a_bits_data = _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] wire _out_0_a_bits_WIRE_1; // @[Mux.scala:30:73] assign out_0_a_bits_corrupt = _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T = muxState_0 & portsAOI_filtered_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_1 = muxState_1 & portsAOI_filtered_1_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_2 = muxState_2 & portsAOI_filtered_2_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_3 = _out_0_a_bits_T | _out_0_a_bits_T_1; // @[Mux.scala:30:73] wire _out_0_a_bits_T_4 = _out_0_a_bits_T_3 | _out_0_a_bits_T_2; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_1 = _out_0_a_bits_T_4; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_corrupt = _out_0_a_bits_WIRE_1; // @[Mux.scala:30:73] wire [63:0] _out_0_a_bits_T_5 = muxState_0 ? portsAOI_filtered_0_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_0_a_bits_T_6 = muxState_1 ? portsAOI_filtered_1_0_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_0_a_bits_T_7 = muxState_2 ? portsAOI_filtered_2_0_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_0_a_bits_T_8 = _out_0_a_bits_T_5 | _out_0_a_bits_T_6; // @[Mux.scala:30:73] wire [63:0] _out_0_a_bits_T_9 = _out_0_a_bits_T_8 | _out_0_a_bits_T_7; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_2 = _out_0_a_bits_T_9; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_data = _out_0_a_bits_WIRE_2; // @[Mux.scala:30:73] wire [7:0] _out_0_a_bits_T_10 = muxState_0 ? portsAOI_filtered_0_bits_mask : 8'h0; // @[Mux.scala:30:73] wire [7:0] _out_0_a_bits_T_11 = muxState_1 ? portsAOI_filtered_1_0_bits_mask : 8'h0; // @[Mux.scala:30:73] wire [7:0] _out_0_a_bits_T_12 = muxState_2 ? portsAOI_filtered_2_0_bits_mask : 8'h0; // @[Mux.scala:30:73] wire [7:0] _out_0_a_bits_T_13 = _out_0_a_bits_T_10 | _out_0_a_bits_T_11; // @[Mux.scala:30:73] wire [7:0] _out_0_a_bits_T_14 = _out_0_a_bits_T_13 | _out_0_a_bits_T_12; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_3 = _out_0_a_bits_T_14; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_mask = _out_0_a_bits_WIRE_3; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_15 = muxState_0 ? portsAOI_filtered_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_16 = muxState_1 ? portsAOI_filtered_1_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_17 = muxState_2 ? portsAOI_filtered_2_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_18 = _out_0_a_bits_T_15 | _out_0_a_bits_T_16; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_19 = _out_0_a_bits_T_18 | _out_0_a_bits_T_17; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_6 = _out_0_a_bits_T_19; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_address = _out_0_a_bits_WIRE_6; // @[Mux.scala:30:73] wire [5:0] _out_0_a_bits_T_20 = muxState_0 ? portsAOI_filtered_0_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _out_0_a_bits_T_21 = muxState_1 ? portsAOI_filtered_1_0_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _out_0_a_bits_T_22 = muxState_2 ? portsAOI_filtered_2_0_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _out_0_a_bits_T_23 = _out_0_a_bits_T_20 | _out_0_a_bits_T_21; // @[Mux.scala:30:73] wire [5:0] _out_0_a_bits_T_24 = _out_0_a_bits_T_23 | _out_0_a_bits_T_22; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_7 = _out_0_a_bits_T_24; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_source = _out_0_a_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_25 = muxState_0 ? portsAOI_filtered_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_26 = muxState_1 ? portsAOI_filtered_1_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_27 = muxState_2 ? portsAOI_filtered_2_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_28 = _out_0_a_bits_T_25 | _out_0_a_bits_T_26; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_29 = _out_0_a_bits_T_28 | _out_0_a_bits_T_27; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_8 = _out_0_a_bits_T_29; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_size = _out_0_a_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_30 = muxState_0 ? portsAOI_filtered_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_31 = muxState_1 ? portsAOI_filtered_1_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_32 = muxState_2 ? portsAOI_filtered_2_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_33 = _out_0_a_bits_T_30 | _out_0_a_bits_T_31; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_34 = _out_0_a_bits_T_33 | _out_0_a_bits_T_32; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_9 = _out_0_a_bits_T_34; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_param = _out_0_a_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_35 = muxState_0 ? portsAOI_filtered_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_36 = muxState_1 ? portsAOI_filtered_1_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_37 = muxState_2 ? portsAOI_filtered_2_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_38 = _out_0_a_bits_T_35 | _out_0_a_bits_T_36; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_39 = _out_0_a_bits_T_38 | _out_0_a_bits_T_37; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_10 = _out_0_a_bits_T_39; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_opcode = _out_0_a_bits_WIRE_10; // @[Mux.scala:30:73] reg [8:0] beatsLeft_1; // @[Arbiter.scala:60:30] wire idle_1 = beatsLeft_1 == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_1 = idle_1 & out_1_a_ready; // @[Xbar.scala:216:19] wire [1:0] readys_hi_1 = {portsAOI_filtered_2_1_valid, portsAOI_filtered_1_1_valid}; // @[Xbar.scala:352:24] wire [2:0] _readys_T_11 = {readys_hi_1, portsAOI_filtered_1_valid}; // @[Xbar.scala:352:24] wire [2:0] readys_valid_1 = _readys_T_11; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_12 = readys_valid_1 == _readys_T_11; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_14 = ~_readys_T_13; // @[Arbiter.scala:22:12] wire _readys_T_15 = ~_readys_T_12; // @[Arbiter.scala:22:{12,19}] reg [2:0] readys_mask_1; // @[Arbiter.scala:23:23] wire [2:0] _readys_filter_T_2 = ~readys_mask_1; // @[Arbiter.scala:23:23, :24:30] wire [2:0] _readys_filter_T_3 = readys_valid_1 & _readys_filter_T_2; // @[Arbiter.scala:21:23, :24:{28,30}] wire [5:0] readys_filter_1 = {_readys_filter_T_3, readys_valid_1}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [4:0] _readys_unready_T_7 = readys_filter_1[5:1]; // @[package.scala:262:48] wire [5:0] _readys_unready_T_8 = {readys_filter_1[5], readys_filter_1[4:0] | _readys_unready_T_7}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_9 = _readys_unready_T_8[5:2]; // @[package.scala:262:{43,48}] wire [5:0] _readys_unready_T_10 = {_readys_unready_T_8[5:4], _readys_unready_T_8[3:0] | _readys_unready_T_9}; // @[package.scala:262:{43,48}] wire [5:0] _readys_unready_T_11 = _readys_unready_T_10; // @[package.scala:262:43, :263:17] wire [4:0] _readys_unready_T_12 = _readys_unready_T_11[5:1]; // @[package.scala:263:17] wire [5:0] _readys_unready_T_13 = {readys_mask_1, 3'h0}; // @[Arbiter.scala:23:23, :25:66] wire [5:0] readys_unready_1 = {1'h0, _readys_unready_T_12} | _readys_unready_T_13; // @[Arbiter.scala:25:{52,58,66}] wire [2:0] _readys_readys_T_3 = readys_unready_1[5:3]; // @[Arbiter.scala:25:58, :26:29] wire [2:0] _readys_readys_T_4 = readys_unready_1[2:0]; // @[Arbiter.scala:25:58, :26:48] wire [2:0] _readys_readys_T_5 = _readys_readys_T_3 & _readys_readys_T_4; // @[Arbiter.scala:26:{29,39,48}] wire [2:0] readys_readys_1 = ~_readys_readys_T_5; // @[Arbiter.scala:26:{18,39}] wire [2:0] _readys_T_18 = readys_readys_1; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_16 = |readys_valid_1; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_17 = latch_1 & _readys_T_16; // @[Arbiter.scala:27:{18,27}, :62:24] wire [2:0] _readys_mask_T_8 = readys_readys_1 & readys_valid_1; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [3:0] _readys_mask_T_9 = {_readys_mask_T_8, 1'h0}; // @[package.scala:253:48] wire [2:0] _readys_mask_T_10 = _readys_mask_T_9[2:0]; // @[package.scala:253:{48,53}] wire [2:0] _readys_mask_T_11 = _readys_mask_T_8 | _readys_mask_T_10; // @[package.scala:253:{43,53}] wire [4:0] _readys_mask_T_12 = {_readys_mask_T_11, 2'h0}; // @[package.scala:253:{43,48}] wire [2:0] _readys_mask_T_13 = _readys_mask_T_12[2:0]; // @[package.scala:253:{48,53}] wire [2:0] _readys_mask_T_14 = _readys_mask_T_11 | _readys_mask_T_13; // @[package.scala:253:{43,53}] wire [2:0] _readys_mask_T_15 = _readys_mask_T_14; // @[package.scala:253:43, :254:17] wire _readys_T_19 = _readys_T_18[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_0 = _readys_T_19; // @[Arbiter.scala:68:{27,76}] wire _readys_T_20 = _readys_T_18[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_1 = _readys_T_20; // @[Arbiter.scala:68:{27,76}] wire _readys_T_21 = _readys_T_18[2]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_2 = _readys_T_21; // @[Arbiter.scala:68:{27,76}] wire _winner_T_3 = readys_1_0 & portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] wire winner_1_0 = _winner_T_3; // @[Arbiter.scala:71:{27,69}] wire _winner_T_4 = readys_1_1 & portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24] wire winner_1_1 = _winner_T_4; // @[Arbiter.scala:71:{27,69}] wire _winner_T_5 = readys_1_2 & portsAOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire winner_1_2 = _winner_T_5; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_1 = winner_1_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2_1 = prefixOR_1_1 | winner_1_1; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_1 = prefixOR_2_1 | winner_1_2; // @[Arbiter.scala:71:27, :76:48] wire _out_1_a_valid_T = portsAOI_filtered_1_valid | portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24] wire [8:0] maskedBeats_0_1 = winner_1_0 ? beatsAI_0 : 9'h0; // @[Edges.scala:221:14] wire [8:0] maskedBeats_1_1 = winner_1_1 ? beatsAI_1 : 9'h0; // @[Edges.scala:221:14] wire [8:0] maskedBeats_2_1 = winner_1_2 ? beatsAI_2 : 9'h0; // @[Edges.scala:221:14] wire [8:0] _initBeats_T_1 = maskedBeats_0_1 | maskedBeats_1_1; // @[Arbiter.scala:82:69, :84:44] wire [8:0] initBeats_1 = _initBeats_T_1 | maskedBeats_2_1; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_4 = out_1_a_ready & out_1_a_valid; // @[Decoupled.scala:51:35] wire [9:0] _beatsLeft_T_5 = {1'h0, beatsLeft_1} - {9'h0, _beatsLeft_T_4}; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_6 = _beatsLeft_T_5[8:0]; // @[Arbiter.scala:85:52] wire [8:0] _beatsLeft_T_7 = latch_1 ? initBeats_1 : _beatsLeft_T_6; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_1_0; // @[Arbiter.scala:88:26] reg state_1_1; // @[Arbiter.scala:88:26] reg state_1_2; // @[Arbiter.scala:88:26] wire muxState_1_0 = idle_1 ? winner_1_0 : state_1_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1_1 = idle_1 ? winner_1_1 : state_1_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1_2 = idle_1 ? winner_1_2 : state_1_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_1_0 = idle_1 ? readys_1_0 : state_1_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1_1 = idle_1 ? readys_1_1 : state_1_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1_2 = idle_1 ? readys_1_2 : state_1_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_1_ready_T = out_1_a_ready & allowed_1_0; // @[Xbar.scala:216:19] assign portsAOI_filtered_1_ready = _filtered_1_ready_T; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_1 = out_1_a_ready & allowed_1_1; // @[Xbar.scala:216:19] assign portsAOI_filtered_1_1_ready = _filtered_1_ready_T_1; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_2 = out_1_a_ready & allowed_1_2; // @[Xbar.scala:216:19] assign portsAOI_filtered_2_1_ready = _filtered_1_ready_T_2; // @[Xbar.scala:352:24] wire _out_1_a_valid_T_1 = _out_1_a_valid_T | portsAOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire _out_1_a_valid_T_2 = state_1_0 & portsAOI_filtered_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_3 = state_1_1 & portsAOI_filtered_1_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_4 = state_1_2 & portsAOI_filtered_2_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_5 = _out_1_a_valid_T_2 | _out_1_a_valid_T_3; // @[Mux.scala:30:73] wire _out_1_a_valid_T_6 = _out_1_a_valid_T_5 | _out_1_a_valid_T_4; // @[Mux.scala:30:73] wire _out_1_a_valid_WIRE = _out_1_a_valid_T_6; // @[Mux.scala:30:73] assign _out_1_a_valid_T_7 = idle_1 ? _out_1_a_valid_T_1 : _out_1_a_valid_WIRE; // @[Mux.scala:30:73] assign out_1_a_valid = _out_1_a_valid_T_7; // @[Xbar.scala:216:19] wire [2:0] _out_1_a_bits_WIRE_10; // @[Mux.scala:30:73] assign out_1_a_bits_opcode = _out_1_a_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_WIRE_9; // @[Mux.scala:30:73] assign out_1_a_bits_param = _out_1_a_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_WIRE_8; // @[Mux.scala:30:73] assign out_1_a_bits_size = _out_1_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_WIRE_7; // @[Mux.scala:30:73] assign out_1_a_bits_source = _out_1_a_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_WIRE_6; // @[Mux.scala:30:73] assign out_1_a_bits_address = _out_1_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [7:0] _out_1_a_bits_WIRE_3; // @[Mux.scala:30:73] assign out_1_a_bits_mask = _out_1_a_bits_WIRE_mask; // @[Mux.scala:30:73] wire [63:0] _out_1_a_bits_WIRE_2; // @[Mux.scala:30:73] assign out_1_a_bits_data = _out_1_a_bits_WIRE_data; // @[Mux.scala:30:73] wire _out_1_a_bits_WIRE_1; // @[Mux.scala:30:73] assign out_1_a_bits_corrupt = _out_1_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T = muxState_1_0 & portsAOI_filtered_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_1 = muxState_1_1 & portsAOI_filtered_1_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_2 = muxState_1_2 & portsAOI_filtered_2_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_3 = _out_1_a_bits_T | _out_1_a_bits_T_1; // @[Mux.scala:30:73] wire _out_1_a_bits_T_4 = _out_1_a_bits_T_3 | _out_1_a_bits_T_2; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_1 = _out_1_a_bits_T_4; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_corrupt = _out_1_a_bits_WIRE_1; // @[Mux.scala:30:73] wire [63:0] _out_1_a_bits_T_5 = muxState_1_0 ? portsAOI_filtered_1_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_1_a_bits_T_6 = muxState_1_1 ? portsAOI_filtered_1_1_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_1_a_bits_T_7 = muxState_1_2 ? portsAOI_filtered_2_1_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_1_a_bits_T_8 = _out_1_a_bits_T_5 | _out_1_a_bits_T_6; // @[Mux.scala:30:73] wire [63:0] _out_1_a_bits_T_9 = _out_1_a_bits_T_8 | _out_1_a_bits_T_7; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_2 = _out_1_a_bits_T_9; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_data = _out_1_a_bits_WIRE_2; // @[Mux.scala:30:73] wire [7:0] _out_1_a_bits_T_10 = muxState_1_0 ? portsAOI_filtered_1_bits_mask : 8'h0; // @[Mux.scala:30:73] wire [7:0] _out_1_a_bits_T_11 = muxState_1_1 ? portsAOI_filtered_1_1_bits_mask : 8'h0; // @[Mux.scala:30:73] wire [7:0] _out_1_a_bits_T_12 = muxState_1_2 ? portsAOI_filtered_2_1_bits_mask : 8'h0; // @[Mux.scala:30:73] wire [7:0] _out_1_a_bits_T_13 = _out_1_a_bits_T_10 | _out_1_a_bits_T_11; // @[Mux.scala:30:73] wire [7:0] _out_1_a_bits_T_14 = _out_1_a_bits_T_13 | _out_1_a_bits_T_12; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_3 = _out_1_a_bits_T_14; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_mask = _out_1_a_bits_WIRE_3; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_15 = muxState_1_0 ? portsAOI_filtered_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_16 = muxState_1_1 ? portsAOI_filtered_1_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_17 = muxState_1_2 ? portsAOI_filtered_2_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_18 = _out_1_a_bits_T_15 | _out_1_a_bits_T_16; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_19 = _out_1_a_bits_T_18 | _out_1_a_bits_T_17; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_6 = _out_1_a_bits_T_19; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_address = _out_1_a_bits_WIRE_6; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_T_20 = muxState_1_0 ? portsAOI_filtered_1_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_T_21 = muxState_1_1 ? portsAOI_filtered_1_1_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_T_22 = muxState_1_2 ? portsAOI_filtered_2_1_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_T_23 = _out_1_a_bits_T_20 | _out_1_a_bits_T_21; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_T_24 = _out_1_a_bits_T_23 | _out_1_a_bits_T_22; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_7 = _out_1_a_bits_T_24; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_source = _out_1_a_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_25 = muxState_1_0 ? portsAOI_filtered_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_26 = muxState_1_1 ? portsAOI_filtered_1_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_27 = muxState_1_2 ? portsAOI_filtered_2_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_28 = _out_1_a_bits_T_25 | _out_1_a_bits_T_26; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_29 = _out_1_a_bits_T_28 | _out_1_a_bits_T_27; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_8 = _out_1_a_bits_T_29; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_size = _out_1_a_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_30 = muxState_1_0 ? portsAOI_filtered_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_31 = muxState_1_1 ? portsAOI_filtered_1_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_32 = muxState_1_2 ? portsAOI_filtered_2_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_33 = _out_1_a_bits_T_30 | _out_1_a_bits_T_31; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_34 = _out_1_a_bits_T_33 | _out_1_a_bits_T_32; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_9 = _out_1_a_bits_T_34; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_param = _out_1_a_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_35 = muxState_1_0 ? portsAOI_filtered_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_36 = muxState_1_1 ? portsAOI_filtered_1_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_37 = muxState_1_2 ? portsAOI_filtered_2_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_38 = _out_1_a_bits_T_35 | _out_1_a_bits_T_36; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_39 = _out_1_a_bits_T_38 | _out_1_a_bits_T_37; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_10 = _out_1_a_bits_T_39; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_opcode = _out_1_a_bits_WIRE_10; // @[Mux.scala:30:73] reg [8:0] beatsLeft_2; // @[Arbiter.scala:60:30] wire idle_2 = beatsLeft_2 == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_2 = idle_2 & out_1_c_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T_22 = {portsCOI_filtered_2_1_valid, portsCOI_filtered_1_1_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_2 = _readys_T_22; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_23 = readys_valid_2 == _readys_T_22; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_25 = ~_readys_T_24; // @[Arbiter.scala:22:12] wire _readys_T_26 = ~_readys_T_23; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_2; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_4 = ~readys_mask_2; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_5 = readys_valid_2 & _readys_filter_T_4; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_2 = {_readys_filter_T_5, readys_valid_2}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_14 = readys_filter_2[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_15 = {readys_filter_2[3], readys_filter_2[2:0] | _readys_unready_T_14}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_16 = _readys_unready_T_15; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_17 = _readys_unready_T_16[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_18 = {readys_mask_2, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_2 = {1'h0, _readys_unready_T_17} | _readys_unready_T_18; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_6 = readys_unready_2[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_7 = readys_unready_2[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_8 = _readys_readys_T_6 & _readys_readys_T_7; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_2 = ~_readys_readys_T_8; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_29 = readys_readys_2; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_27 = |readys_valid_2; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_28 = latch_2 & _readys_T_27; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_16 = readys_readys_2 & readys_valid_2; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_17 = {_readys_mask_T_16, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_18 = _readys_mask_T_17[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_19 = _readys_mask_T_16 | _readys_mask_T_18; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_20 = _readys_mask_T_19; // @[package.scala:253:43, :254:17] wire _readys_T_30 = _readys_T_29[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_2_0 = _readys_T_30; // @[Arbiter.scala:68:{27,76}] wire _readys_T_31 = _readys_T_29[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_2_1 = _readys_T_31; // @[Arbiter.scala:68:{27,76}] wire _winner_T_6 = readys_2_0 & portsCOI_filtered_1_1_valid; // @[Xbar.scala:352:24] wire winner_2_0 = _winner_T_6; // @[Arbiter.scala:71:{27,69}] wire _winner_T_7 = readys_2_1 & portsCOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire winner_2_1 = _winner_T_7; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_2 = winner_2_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_2 = prefixOR_1_2 | winner_2_1; // @[Arbiter.scala:71:27, :76:48] wire _out_1_c_valid_T = portsCOI_filtered_1_1_valid | portsCOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire [8:0] maskedBeats_0_2 = winner_2_0 ? beatsCI_1 : 9'h0; // @[Edges.scala:221:14] wire [8:0] maskedBeats_1_2 = winner_2_1 ? beatsCI_2 : 9'h0; // @[Edges.scala:221:14] wire [8:0] initBeats_2 = maskedBeats_0_2 | maskedBeats_1_2; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_8 = out_1_c_ready & out_1_c_valid; // @[Decoupled.scala:51:35] wire [9:0] _beatsLeft_T_9 = {1'h0, beatsLeft_2} - {9'h0, _beatsLeft_T_8}; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_10 = _beatsLeft_T_9[8:0]; // @[Arbiter.scala:85:52] wire [8:0] _beatsLeft_T_11 = latch_2 ? initBeats_2 : _beatsLeft_T_10; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_2_0; // @[Arbiter.scala:88:26] reg state_2_1; // @[Arbiter.scala:88:26] wire muxState_2_0 = idle_2 ? winner_2_0 : state_2_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_2_1 = idle_2 ? winner_2_1 : state_2_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_2_0 = idle_2 ? readys_2_0 : state_2_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_2_1 = idle_2 ? readys_2_1 : state_2_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_1_ready_T_3 = out_1_c_ready & allowed_2_0; // @[Xbar.scala:216:19] assign portsCOI_filtered_1_1_ready = _filtered_1_ready_T_3; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_4 = out_1_c_ready & allowed_2_1; // @[Xbar.scala:216:19] assign portsCOI_filtered_2_1_ready = _filtered_1_ready_T_4; // @[Xbar.scala:352:24] wire _out_1_c_valid_T_1 = state_2_0 & portsCOI_filtered_1_1_valid; // @[Mux.scala:30:73] wire _out_1_c_valid_T_2 = state_2_1 & portsCOI_filtered_2_1_valid; // @[Mux.scala:30:73] wire _out_1_c_valid_T_3 = _out_1_c_valid_T_1 | _out_1_c_valid_T_2; // @[Mux.scala:30:73] wire _out_1_c_valid_WIRE = _out_1_c_valid_T_3; // @[Mux.scala:30:73] assign _out_1_c_valid_T_4 = idle_2 ? _out_1_c_valid_T : _out_1_c_valid_WIRE; // @[Mux.scala:30:73] assign out_1_c_valid = _out_1_c_valid_T_4; // @[Xbar.scala:216:19] wire [2:0] _out_1_c_bits_WIRE_9; // @[Mux.scala:30:73] assign out_1_c_bits_opcode = _out_1_c_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_WIRE_8; // @[Mux.scala:30:73] assign out_1_c_bits_param = _out_1_c_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_WIRE_7; // @[Mux.scala:30:73] assign out_1_c_bits_size = _out_1_c_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _out_1_c_bits_WIRE_6; // @[Mux.scala:30:73] assign out_1_c_bits_source = _out_1_c_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_WIRE_5; // @[Mux.scala:30:73] assign out_1_c_bits_address = _out_1_c_bits_WIRE_address; // @[Mux.scala:30:73] wire [63:0] _out_1_c_bits_WIRE_2; // @[Mux.scala:30:73] assign out_1_c_bits_data = _out_1_c_bits_WIRE_data; // @[Mux.scala:30:73] wire _out_1_c_bits_WIRE_1; // @[Mux.scala:30:73] assign out_1_c_bits_corrupt = _out_1_c_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _out_1_c_bits_T = muxState_2_0 & portsCOI_filtered_1_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_c_bits_T_1 = muxState_2_1 & portsCOI_filtered_2_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_c_bits_T_2 = _out_1_c_bits_T | _out_1_c_bits_T_1; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_1 = _out_1_c_bits_T_2; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_corrupt = _out_1_c_bits_WIRE_1; // @[Mux.scala:30:73] wire [63:0] _out_1_c_bits_T_3 = muxState_2_0 ? portsCOI_filtered_1_1_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_1_c_bits_T_4 = muxState_2_1 ? portsCOI_filtered_2_1_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _out_1_c_bits_T_5 = _out_1_c_bits_T_3 | _out_1_c_bits_T_4; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_2 = _out_1_c_bits_T_5; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_data = _out_1_c_bits_WIRE_2; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_6 = muxState_2_0 ? portsCOI_filtered_1_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_7 = muxState_2_1 ? portsCOI_filtered_2_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_8 = _out_1_c_bits_T_6 | _out_1_c_bits_T_7; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_5 = _out_1_c_bits_T_8; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_address = _out_1_c_bits_WIRE_5; // @[Mux.scala:30:73] wire [5:0] _out_1_c_bits_T_9 = muxState_2_0 ? portsCOI_filtered_1_1_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _out_1_c_bits_T_10 = muxState_2_1 ? portsCOI_filtered_2_1_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _out_1_c_bits_T_11 = _out_1_c_bits_T_9 | _out_1_c_bits_T_10; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_6 = _out_1_c_bits_T_11; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_source = _out_1_c_bits_WIRE_6; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_12 = muxState_2_0 ? portsCOI_filtered_1_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_13 = muxState_2_1 ? portsCOI_filtered_2_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_14 = _out_1_c_bits_T_12 | _out_1_c_bits_T_13; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_7 = _out_1_c_bits_T_14; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_size = _out_1_c_bits_WIRE_7; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_15 = muxState_2_0 ? portsCOI_filtered_1_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_16 = muxState_2_1 ? portsCOI_filtered_2_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_17 = _out_1_c_bits_T_15 | _out_1_c_bits_T_16; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_8 = _out_1_c_bits_T_17; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_param = _out_1_c_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_18 = muxState_2_0 ? portsCOI_filtered_1_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_19 = muxState_2_1 ? portsCOI_filtered_2_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_20 = _out_1_c_bits_T_18 | _out_1_c_bits_T_19; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_9 = _out_1_c_bits_T_20; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_opcode = _out_1_c_bits_WIRE_9; // @[Mux.scala:30:73] reg beatsLeft_3; // @[Arbiter.scala:60:30] wire idle_3 = ~beatsLeft_3; // @[Arbiter.scala:60:30, :61:28] wire latch_3 = idle_3; // @[Arbiter.scala:61:28, :62:24] wire [1:0] _readys_T_32 = {portsEOI_filtered_2_1_valid, portsEOI_filtered_1_1_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_3 = _readys_T_32; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_33 = readys_valid_3 == _readys_T_32; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_35 = ~_readys_T_34; // @[Arbiter.scala:22:12] wire _readys_T_36 = ~_readys_T_33; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_3; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_6 = ~readys_mask_3; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_7 = readys_valid_3 & _readys_filter_T_6; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_3 = {_readys_filter_T_7, readys_valid_3}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_19 = readys_filter_3[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_20 = {readys_filter_3[3], readys_filter_3[2:0] | _readys_unready_T_19}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_21 = _readys_unready_T_20; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_22 = _readys_unready_T_21[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_23 = {readys_mask_3, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_3 = {1'h0, _readys_unready_T_22} | _readys_unready_T_23; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_9 = readys_unready_3[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_10 = readys_unready_3[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_11 = _readys_readys_T_9 & _readys_readys_T_10; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_3 = ~_readys_readys_T_11; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_39 = readys_readys_3; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_37 = |readys_valid_3; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_38 = latch_3 & _readys_T_37; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_21 = readys_readys_3 & readys_valid_3; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_22 = {_readys_mask_T_21, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_23 = _readys_mask_T_22[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_24 = _readys_mask_T_21 | _readys_mask_T_23; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_25 = _readys_mask_T_24; // @[package.scala:253:43, :254:17] wire _readys_T_40 = _readys_T_39[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_3_0 = _readys_T_40; // @[Arbiter.scala:68:{27,76}] wire _readys_T_41 = _readys_T_39[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_3_1 = _readys_T_41; // @[Arbiter.scala:68:{27,76}] wire _winner_T_8 = readys_3_0 & portsEOI_filtered_1_1_valid; // @[Xbar.scala:352:24] wire winner_3_0 = _winner_T_8; // @[Arbiter.scala:71:{27,69}] wire _winner_T_9 = readys_3_1 & portsEOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire winner_3_1 = _winner_T_9; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_3 = winner_3_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_3 = prefixOR_1_3 | winner_3_1; // @[Arbiter.scala:71:27, :76:48] wire _out_1_e_valid_T = portsEOI_filtered_1_1_valid | portsEOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire [1:0] _beatsLeft_T_13 = {1'h0, beatsLeft_3} - {1'h0, _beatsLeft_T_12}; // @[Decoupled.scala:51:35] wire _beatsLeft_T_14 = _beatsLeft_T_13[0]; // @[Arbiter.scala:85:52] wire _beatsLeft_T_15 = ~latch_3 & _beatsLeft_T_14; // @[Arbiter.scala:62:24, :85:{23,52}] reg state_3_0; // @[Arbiter.scala:88:26] reg state_3_1; // @[Arbiter.scala:88:26] wire muxState_3_0 = idle_3 ? winner_3_0 : state_3_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_3_1 = idle_3 ? winner_3_1 : state_3_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_3_0 = idle_3 ? readys_3_0 : state_3_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_3_1 = idle_3 ? readys_3_1 : state_3_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_1_ready_T_5 = allowed_3_0; // @[Arbiter.scala:92:24, :94:31] assign _filtered_1_ready_T_6 = allowed_3_1; // @[Arbiter.scala:92:24, :94:31] assign portsEOI_filtered_1_1_ready = _filtered_1_ready_T_5; // @[Xbar.scala:352:24] assign portsEOI_filtered_2_1_ready = _filtered_1_ready_T_6; // @[Xbar.scala:352:24] wire _out_1_e_valid_T_1 = state_3_0 & portsEOI_filtered_1_1_valid; // @[Mux.scala:30:73] wire _out_1_e_valid_T_2 = state_3_1 & portsEOI_filtered_2_1_valid; // @[Mux.scala:30:73] wire _out_1_e_valid_T_3 = _out_1_e_valid_T_1 | _out_1_e_valid_T_2; // @[Mux.scala:30:73] wire _out_1_e_valid_WIRE = _out_1_e_valid_T_3; // @[Mux.scala:30:73] assign _out_1_e_valid_T_4 = idle_3 ? _out_1_e_valid_T : _out_1_e_valid_WIRE; // @[Mux.scala:30:73] assign out_1_e_valid = _out_1_e_valid_T_4; // @[Xbar.scala:216:19] wire [2:0] _out_1_e_bits_WIRE_1; // @[Mux.scala:30:73] assign out_1_e_bits_sink = _out_1_e_bits_WIRE_sink; // @[Mux.scala:30:73] wire [2:0] _out_1_e_bits_T = muxState_3_0 ? portsEOI_filtered_1_1_bits_sink : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_e_bits_T_1 = muxState_3_1 ? portsEOI_filtered_2_1_bits_sink : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_e_bits_T_2 = _out_1_e_bits_T | _out_1_e_bits_T_1; // @[Mux.scala:30:73] assign _out_1_e_bits_WIRE_1 = _out_1_e_bits_T_2; // @[Mux.scala:30:73] assign _out_1_e_bits_WIRE_sink = _out_1_e_bits_WIRE_1; // @[Mux.scala:30:73] reg [8:0] beatsLeft_4; // @[Arbiter.scala:60:30] wire idle_4 = beatsLeft_4 == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_4 = idle_4 & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_42 = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_4 = _readys_T_42; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_43 = readys_valid_4 == _readys_T_42; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_45 = ~_readys_T_44; // @[Arbiter.scala:22:12] wire _readys_T_46 = ~_readys_T_43; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_4; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_8 = ~readys_mask_4; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_9 = readys_valid_4 & _readys_filter_T_8; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_4 = {_readys_filter_T_9, readys_valid_4}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_24 = readys_filter_4[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_25 = {readys_filter_4[3], readys_filter_4[2:0] | _readys_unready_T_24}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_26 = _readys_unready_T_25; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_27 = _readys_unready_T_26[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_28 = {readys_mask_4, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_4 = {1'h0, _readys_unready_T_27} | _readys_unready_T_28; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_12 = readys_unready_4[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_13 = readys_unready_4[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_14 = _readys_readys_T_12 & _readys_readys_T_13; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_4 = ~_readys_readys_T_14; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_49 = readys_readys_4; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_47 = |readys_valid_4; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_48 = latch_4 & _readys_T_47; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_26 = readys_readys_4 & readys_valid_4; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_27 = {_readys_mask_T_26, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_28 = _readys_mask_T_27[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_29 = _readys_mask_T_26 | _readys_mask_T_28; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_30 = _readys_mask_T_29; // @[package.scala:253:43, :254:17] wire _readys_T_50 = _readys_T_49[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_4_0 = _readys_T_50; // @[Arbiter.scala:68:{27,76}] wire _readys_T_51 = _readys_T_49[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_4_1 = _readys_T_51; // @[Arbiter.scala:68:{27,76}] wire _winner_T_10 = readys_4_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_4_0 = _winner_T_10; // @[Arbiter.scala:71:{27,69}] wire _winner_T_11 = readys_4_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_4_1 = _winner_T_11; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_4 = winner_4_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_4 = prefixOR_1_4 | winner_4_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire [8:0] maskedBeats_0_4 = winner_4_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14] wire [2:0] maskedBeats_1_4 = winner_4_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14] wire [8:0] initBeats_4 = {maskedBeats_0_4[8:3], maskedBeats_0_4[2:0] | maskedBeats_1_4}; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_16 = in_0_d_ready & in_0_d_valid; // @[Decoupled.scala:51:35] wire [9:0] _beatsLeft_T_17 = {1'h0, beatsLeft_4} - {9'h0, _beatsLeft_T_16}; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_18 = _beatsLeft_T_17[8:0]; // @[Arbiter.scala:85:52] wire [8:0] _beatsLeft_T_19 = latch_4 ? initBeats_4 : _beatsLeft_T_18; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_4_0; // @[Arbiter.scala:88:26] reg state_4_1; // @[Arbiter.scala:88:26] wire muxState_4_0 = idle_4 ? winner_4_0 : state_4_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_4_1 = idle_4 ? winner_4_1 : state_4_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_4_0 = idle_4 ? readys_4_0 : state_4_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_4_1 = idle_4 ? readys_4_1 : state_4_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_0_ready_T_3 = in_0_d_ready & allowed_4_0; // @[Xbar.scala:159:18] assign portsDIO_filtered_0_ready = _filtered_0_ready_T_3; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_4 = in_0_d_ready & allowed_4_1; // @[Xbar.scala:159:18] assign portsDIO_filtered_1_0_ready = _filtered_0_ready_T_4; // @[Xbar.scala:352:24] wire _in_0_d_valid_T_1 = state_4_0 & portsDIO_filtered_0_valid; // @[Mux.scala:30:73] wire _in_0_d_valid_T_2 = state_4_1 & portsDIO_filtered_1_0_valid; // @[Mux.scala:30:73] wire _in_0_d_valid_T_3 = _in_0_d_valid_T_1 | _in_0_d_valid_T_2; // @[Mux.scala:30:73] wire _in_0_d_valid_WIRE = _in_0_d_valid_T_3; // @[Mux.scala:30:73] assign _in_0_d_valid_T_4 = idle_4 ? _in_0_d_valid_T : _in_0_d_valid_WIRE; // @[Mux.scala:30:73] assign in_0_d_valid = _in_0_d_valid_T_4; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_10; // @[Mux.scala:30:73] assign in_0_d_bits_opcode = _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_WIRE_9; // @[Mux.scala:30:73] assign in_0_d_bits_param = _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_WIRE_8; // @[Mux.scala:30:73] assign in_0_d_bits_size = _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _in_0_d_bits_WIRE_7; // @[Mux.scala:30:73] assign in_0_d_bits_source = _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_WIRE_6; // @[Mux.scala:30:73] assign in_0_d_bits_sink = _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_5; // @[Mux.scala:30:73] assign in_0_d_bits_denied = _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] wire [63:0] _in_0_d_bits_WIRE_2; // @[Mux.scala:30:73] assign in_0_d_bits_data = _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_1; // @[Mux.scala:30:73] assign in_0_d_bits_corrupt = _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _in_0_d_bits_T = muxState_4_0 & portsDIO_filtered_0_bits_corrupt; // @[Mux.scala:30:73] wire _in_0_d_bits_T_1 = muxState_4_1 & portsDIO_filtered_1_0_bits_corrupt; // @[Mux.scala:30:73] wire _in_0_d_bits_T_2 = _in_0_d_bits_T | _in_0_d_bits_T_1; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_1 = _in_0_d_bits_T_2; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_corrupt = _in_0_d_bits_WIRE_1; // @[Mux.scala:30:73] wire [63:0] _in_0_d_bits_T_3 = muxState_4_0 ? portsDIO_filtered_0_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _in_0_d_bits_T_4 = muxState_4_1 ? portsDIO_filtered_1_0_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _in_0_d_bits_T_5 = _in_0_d_bits_T_3 | _in_0_d_bits_T_4; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_2 = _in_0_d_bits_T_5; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_data = _in_0_d_bits_WIRE_2; // @[Mux.scala:30:73] wire _in_0_d_bits_T_6 = muxState_4_0 & portsDIO_filtered_0_bits_denied; // @[Mux.scala:30:73] wire _in_0_d_bits_T_7 = muxState_4_1 & portsDIO_filtered_1_0_bits_denied; // @[Mux.scala:30:73] wire _in_0_d_bits_T_8 = _in_0_d_bits_T_6 | _in_0_d_bits_T_7; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_5 = _in_0_d_bits_T_8; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_denied = _in_0_d_bits_WIRE_5; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_9 = muxState_4_0 ? portsDIO_filtered_0_bits_sink : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_10 = muxState_4_1 ? portsDIO_filtered_1_0_bits_sink : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_11 = _in_0_d_bits_T_9 | _in_0_d_bits_T_10; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_6 = _in_0_d_bits_T_11; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_sink = _in_0_d_bits_WIRE_6; // @[Mux.scala:30:73] wire [5:0] _in_0_d_bits_T_12 = muxState_4_0 ? portsDIO_filtered_0_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _in_0_d_bits_T_13 = muxState_4_1 ? portsDIO_filtered_1_0_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _in_0_d_bits_T_14 = _in_0_d_bits_T_12 | _in_0_d_bits_T_13; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_7 = _in_0_d_bits_T_14; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_source = _in_0_d_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_15 = muxState_4_0 ? portsDIO_filtered_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_16 = muxState_4_1 ? portsDIO_filtered_1_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_17 = _in_0_d_bits_T_15 | _in_0_d_bits_T_16; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_8 = _in_0_d_bits_T_17; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_size = _in_0_d_bits_WIRE_8; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_18 = muxState_4_0 ? portsDIO_filtered_0_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_19 = muxState_4_1 ? portsDIO_filtered_1_0_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_20 = _in_0_d_bits_T_18 | _in_0_d_bits_T_19; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_9 = _in_0_d_bits_T_20; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_param = _in_0_d_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_21 = muxState_4_0 ? portsDIO_filtered_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_22 = muxState_4_1 ? portsDIO_filtered_1_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_23 = _in_0_d_bits_T_21 | _in_0_d_bits_T_22; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_10 = _in_0_d_bits_T_23; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_opcode = _in_0_d_bits_WIRE_10; // @[Mux.scala:30:73] reg [8:0] beatsLeft_5; // @[Arbiter.scala:60:30] wire idle_5 = beatsLeft_5 == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_5 = idle_5 & in_1_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_52 = {portsDIO_filtered_1_1_valid, portsDIO_filtered_1_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_5 = _readys_T_52; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_53 = readys_valid_5 == _readys_T_52; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_55 = ~_readys_T_54; // @[Arbiter.scala:22:12] wire _readys_T_56 = ~_readys_T_53; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_5; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_10 = ~readys_mask_5; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_11 = readys_valid_5 & _readys_filter_T_10; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_5 = {_readys_filter_T_11, readys_valid_5}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_29 = readys_filter_5[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_30 = {readys_filter_5[3], readys_filter_5[2:0] | _readys_unready_T_29}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_31 = _readys_unready_T_30; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_32 = _readys_unready_T_31[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_33 = {readys_mask_5, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_5 = {1'h0, _readys_unready_T_32} | _readys_unready_T_33; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_15 = readys_unready_5[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_16 = readys_unready_5[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_17 = _readys_readys_T_15 & _readys_readys_T_16; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_5 = ~_readys_readys_T_17; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_59 = readys_readys_5; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_57 = |readys_valid_5; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_58 = latch_5 & _readys_T_57; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_31 = readys_readys_5 & readys_valid_5; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_32 = {_readys_mask_T_31, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_33 = _readys_mask_T_32[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_34 = _readys_mask_T_31 | _readys_mask_T_33; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_35 = _readys_mask_T_34; // @[package.scala:253:43, :254:17] wire _readys_T_60 = _readys_T_59[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_5_0 = _readys_T_60; // @[Arbiter.scala:68:{27,76}] wire _readys_T_61 = _readys_T_59[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_5_1 = _readys_T_61; // @[Arbiter.scala:68:{27,76}] wire _winner_T_12 = readys_5_0 & portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] wire winner_5_0 = _winner_T_12; // @[Arbiter.scala:71:{27,69}] wire _winner_T_13 = readys_5_1 & portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24] wire winner_5_1 = _winner_T_13; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_5 = winner_5_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_5 = prefixOR_1_5 | winner_5_1; // @[Arbiter.scala:71:27, :76:48] wire _in_1_d_valid_T = portsDIO_filtered_1_valid | portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24] wire [8:0] maskedBeats_0_5 = winner_5_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14] wire [2:0] maskedBeats_1_5 = winner_5_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14] wire [8:0] initBeats_5 = {maskedBeats_0_5[8:3], maskedBeats_0_5[2:0] | maskedBeats_1_5}; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_20 = in_1_d_ready & in_1_d_valid; // @[Decoupled.scala:51:35] wire [9:0] _beatsLeft_T_21 = {1'h0, beatsLeft_5} - {9'h0, _beatsLeft_T_20}; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_22 = _beatsLeft_T_21[8:0]; // @[Arbiter.scala:85:52] wire [8:0] _beatsLeft_T_23 = latch_5 ? initBeats_5 : _beatsLeft_T_22; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_5_0; // @[Arbiter.scala:88:26] reg state_5_1; // @[Arbiter.scala:88:26] wire muxState_5_0 = idle_5 ? winner_5_0 : state_5_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_5_1 = idle_5 ? winner_5_1 : state_5_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_5_0 = idle_5 ? readys_5_0 : state_5_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_5_1 = idle_5 ? readys_5_1 : state_5_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_1_ready_T_7 = in_1_d_ready & allowed_5_0; // @[Xbar.scala:159:18] assign portsDIO_filtered_1_ready = _filtered_1_ready_T_7; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_8 = in_1_d_ready & allowed_5_1; // @[Xbar.scala:159:18] assign portsDIO_filtered_1_1_ready = _filtered_1_ready_T_8; // @[Xbar.scala:352:24] wire _in_1_d_valid_T_1 = state_5_0 & portsDIO_filtered_1_valid; // @[Mux.scala:30:73] wire _in_1_d_valid_T_2 = state_5_1 & portsDIO_filtered_1_1_valid; // @[Mux.scala:30:73] wire _in_1_d_valid_T_3 = _in_1_d_valid_T_1 | _in_1_d_valid_T_2; // @[Mux.scala:30:73] wire _in_1_d_valid_WIRE = _in_1_d_valid_T_3; // @[Mux.scala:30:73] assign _in_1_d_valid_T_4 = idle_5 ? _in_1_d_valid_T : _in_1_d_valid_WIRE; // @[Mux.scala:30:73] assign in_1_d_valid = _in_1_d_valid_T_4; // @[Xbar.scala:159:18] wire [2:0] _in_1_d_bits_WIRE_10; // @[Mux.scala:30:73] assign in_1_d_bits_opcode = _in_1_d_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [1:0] _in_1_d_bits_WIRE_9; // @[Mux.scala:30:73] assign in_1_d_bits_param = _in_1_d_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_WIRE_8; // @[Mux.scala:30:73] assign in_1_d_bits_size = _in_1_d_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _in_1_d_bits_WIRE_7; // @[Mux.scala:30:73] assign in_1_d_bits_source = _in_1_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_WIRE_6; // @[Mux.scala:30:73] assign in_1_d_bits_sink = _in_1_d_bits_WIRE_sink; // @[Mux.scala:30:73] wire _in_1_d_bits_WIRE_5; // @[Mux.scala:30:73] assign in_1_d_bits_denied = _in_1_d_bits_WIRE_denied; // @[Mux.scala:30:73] wire [63:0] _in_1_d_bits_WIRE_2; // @[Mux.scala:30:73] assign in_1_d_bits_data = _in_1_d_bits_WIRE_data; // @[Mux.scala:30:73] wire _in_1_d_bits_WIRE_1; // @[Mux.scala:30:73] assign in_1_d_bits_corrupt = _in_1_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _in_1_d_bits_T = muxState_5_0 & portsDIO_filtered_1_bits_corrupt; // @[Mux.scala:30:73] wire _in_1_d_bits_T_1 = muxState_5_1 & portsDIO_filtered_1_1_bits_corrupt; // @[Mux.scala:30:73] wire _in_1_d_bits_T_2 = _in_1_d_bits_T | _in_1_d_bits_T_1; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_1 = _in_1_d_bits_T_2; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_corrupt = _in_1_d_bits_WIRE_1; // @[Mux.scala:30:73] wire [63:0] _in_1_d_bits_T_3 = muxState_5_0 ? portsDIO_filtered_1_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _in_1_d_bits_T_4 = muxState_5_1 ? portsDIO_filtered_1_1_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _in_1_d_bits_T_5 = _in_1_d_bits_T_3 | _in_1_d_bits_T_4; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_2 = _in_1_d_bits_T_5; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_data = _in_1_d_bits_WIRE_2; // @[Mux.scala:30:73] wire _in_1_d_bits_T_6 = muxState_5_0 & portsDIO_filtered_1_bits_denied; // @[Mux.scala:30:73] wire _in_1_d_bits_T_7 = muxState_5_1 & portsDIO_filtered_1_1_bits_denied; // @[Mux.scala:30:73] wire _in_1_d_bits_T_8 = _in_1_d_bits_T_6 | _in_1_d_bits_T_7; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_5 = _in_1_d_bits_T_8; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_denied = _in_1_d_bits_WIRE_5; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_T_9 = muxState_5_0 ? portsDIO_filtered_1_bits_sink : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_T_10 = muxState_5_1 ? portsDIO_filtered_1_1_bits_sink : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_T_11 = _in_1_d_bits_T_9 | _in_1_d_bits_T_10; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_6 = _in_1_d_bits_T_11; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_sink = _in_1_d_bits_WIRE_6; // @[Mux.scala:30:73] wire [5:0] _in_1_d_bits_T_12 = muxState_5_0 ? portsDIO_filtered_1_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _in_1_d_bits_T_13 = muxState_5_1 ? portsDIO_filtered_1_1_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _in_1_d_bits_T_14 = _in_1_d_bits_T_12 | _in_1_d_bits_T_13; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_7 = _in_1_d_bits_T_14; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_source = _in_1_d_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_T_15 = muxState_5_0 ? portsDIO_filtered_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_T_16 = muxState_5_1 ? portsDIO_filtered_1_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_T_17 = _in_1_d_bits_T_15 | _in_1_d_bits_T_16; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_8 = _in_1_d_bits_T_17; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_size = _in_1_d_bits_WIRE_8; // @[Mux.scala:30:73] wire [1:0] _in_1_d_bits_T_18 = muxState_5_0 ? portsDIO_filtered_1_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_1_d_bits_T_19 = muxState_5_1 ? portsDIO_filtered_1_1_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_1_d_bits_T_20 = _in_1_d_bits_T_18 | _in_1_d_bits_T_19; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_9 = _in_1_d_bits_T_20; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_param = _in_1_d_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_T_21 = muxState_5_0 ? portsDIO_filtered_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_T_22 = muxState_5_1 ? portsDIO_filtered_1_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_T_23 = _in_1_d_bits_T_21 | _in_1_d_bits_T_22; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_10 = _in_1_d_bits_T_23; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_opcode = _in_1_d_bits_WIRE_10; // @[Mux.scala:30:73] reg [8:0] beatsLeft_6; // @[Arbiter.scala:60:30] wire idle_6 = beatsLeft_6 == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_6 = idle_6 & in_2_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_62 = {portsDIO_filtered_1_2_valid, portsDIO_filtered_2_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_6 = _readys_T_62; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_63 = readys_valid_6 == _readys_T_62; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_65 = ~_readys_T_64; // @[Arbiter.scala:22:12] wire _readys_T_66 = ~_readys_T_63; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_6; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_12 = ~readys_mask_6; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_13 = readys_valid_6 & _readys_filter_T_12; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_6 = {_readys_filter_T_13, readys_valid_6}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_34 = readys_filter_6[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_35 = {readys_filter_6[3], readys_filter_6[2:0] | _readys_unready_T_34}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_36 = _readys_unready_T_35; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_37 = _readys_unready_T_36[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_38 = {readys_mask_6, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_6 = {1'h0, _readys_unready_T_37} | _readys_unready_T_38; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_18 = readys_unready_6[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_19 = readys_unready_6[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_20 = _readys_readys_T_18 & _readys_readys_T_19; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_6 = ~_readys_readys_T_20; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_69 = readys_readys_6; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_67 = |readys_valid_6; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_68 = latch_6 & _readys_T_67; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_36 = readys_readys_6 & readys_valid_6; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_37 = {_readys_mask_T_36, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_38 = _readys_mask_T_37[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_39 = _readys_mask_T_36 | _readys_mask_T_38; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_40 = _readys_mask_T_39; // @[package.scala:253:43, :254:17] wire _readys_T_70 = _readys_T_69[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_6_0 = _readys_T_70; // @[Arbiter.scala:68:{27,76}] wire _readys_T_71 = _readys_T_69[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_6_1 = _readys_T_71; // @[Arbiter.scala:68:{27,76}] wire _winner_T_14 = readys_6_0 & portsDIO_filtered_2_valid; // @[Xbar.scala:352:24] wire winner_6_0 = _winner_T_14; // @[Arbiter.scala:71:{27,69}] wire _winner_T_15 = readys_6_1 & portsDIO_filtered_1_2_valid; // @[Xbar.scala:352:24] wire winner_6_1 = _winner_T_15; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_6 = winner_6_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_6 = prefixOR_1_6 | winner_6_1; // @[Arbiter.scala:71:27, :76:48] wire _in_2_d_valid_T = portsDIO_filtered_2_valid | portsDIO_filtered_1_2_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_PTE_5( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [9:0] io_x_reserved_for_future, // @[package.scala:268:18] input [43:0] io_x_ppn, // @[package.scala:268:18] input [1:0] io_x_reserved_for_software, // @[package.scala:268:18] input io_x_d, // @[package.scala:268:18] input io_x_a, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_x, // @[package.scala:268:18] input io_x_w, // @[package.scala:268:18] input io_x_r, // @[package.scala:268:18] input io_x_v, // @[package.scala:268:18] output [9:0] io_y_reserved_for_future, // @[package.scala:268:18] output [43:0] io_y_ppn, // @[package.scala:268:18] output [1:0] io_y_reserved_for_software, // @[package.scala:268:18] output io_y_d, // @[package.scala:268:18] output io_y_a, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_x, // @[package.scala:268:18] output io_y_w, // @[package.scala:268:18] output io_y_r, // @[package.scala:268:18] output io_y_v // @[package.scala:268:18] ); wire [9:0] io_x_reserved_for_future_0 = io_x_reserved_for_future; // @[package.scala:267:30] wire [43:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire [1:0] io_x_reserved_for_software_0 = io_x_reserved_for_software; // @[package.scala:267:30] wire io_x_d_0 = io_x_d; // @[package.scala:267:30] wire io_x_a_0 = io_x_a; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_x_0 = io_x_x; // @[package.scala:267:30] wire io_x_w_0 = io_x_w; // @[package.scala:267:30] wire io_x_r_0 = io_x_r; // @[package.scala:267:30] wire io_x_v_0 = io_x_v; // @[package.scala:267:30] wire [9:0] io_y_reserved_for_future_0 = io_x_reserved_for_future_0; // @[package.scala:267:30] wire [43:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire [1:0] io_y_reserved_for_software_0 = io_x_reserved_for_software_0; // @[package.scala:267:30] wire io_y_d_0 = io_x_d_0; // @[package.scala:267:30] wire io_y_a_0 = io_x_a_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_x_0 = io_x_x_0; // @[package.scala:267:30] wire io_y_w_0 = io_x_w_0; // @[package.scala:267:30] wire io_y_r_0 = io_x_r_0; // @[package.scala:267:30] wire io_y_v_0 = io_x_v_0; // @[package.scala:267:30] assign io_y_reserved_for_future = io_y_reserved_for_future_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_reserved_for_software = io_y_reserved_for_software_0; // @[package.scala:267:30] assign io_y_d = io_y_d_0; // @[package.scala:267:30] assign io_y_a = io_y_a_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_x = io_y_x_0; // @[package.scala:267:30] assign io_y_w = io_y_w_0; // @[package.scala:267:30] assign io_y_r = io_y_r_0; // @[package.scala:267:30] assign io_y_v = io_y_v_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first | last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first | last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB || !io.status.bits.blockB) assert (!io.status.bits.nestC || !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe || !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid || io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid || io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty || request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) | Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid || meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U || !(request.opcode === PutFullData || request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r || p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c || m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read || clean release can lead to this state eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_D, true) // MMIO write || dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done | probe_bit probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst || last_probe w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst || last_probe w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U) w_pprobeack := w_pprobeack || set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U || io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f || p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read || clean release can lead to this state bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_D, true) // MMIO write || dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid || (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT || new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") }
module MSHR( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [6:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [6:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [6:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire [2:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _req_clientBit_T = request_source[6:3]; // @[Parameters.scala:54:10] wire _req_clientBit_T_1 = _req_clientBit_T == 4'h8; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_4 = req_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire req_clientBit = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:56:48] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:56:48] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:56:48] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:56:48] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire [2:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _probe_bit_T = io_sinkc_bits_source_0[6:3]; // @[Parameters.scala:54:10] wire _probe_bit_T_1 = _probe_bit_T == 4'h8; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_4 = probe_bit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire probe_bit = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:56:48] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:56:48] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [6:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire [2:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _new_clientBit_T = new_request_source[6:3]; // @[Parameters.scala:54:10] wire _new_clientBit_T_1 = _new_clientBit_T == 4'h8; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_4 = new_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire new_clientBit = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:56:48] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_142( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_152 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_377( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_121 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }
module AsyncResetRegVec_w1_i0_44( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_65( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54] wire [4098:0] _c_sizes_set_T_1 = 4099'h0; // @[Monitor.scala:768:52] wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79] wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35] wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35] wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34] wire [1027:0] c_sizes_set = 1028'h0; // @[Monitor.scala:741:34] wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34] wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 9'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 9'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 9'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_22 = _uncommonBits_T_22[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_23 = _uncommonBits_T_23[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_34 = _uncommonBits_T_34[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_35 = _uncommonBits_T_35[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_46 = _uncommonBits_T_46[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_47 = _uncommonBits_T_47[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_51 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_57 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_63 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_69 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 7'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 7'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 7'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 7'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 9'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 9'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 9'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1266 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1266; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1266; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [8:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1334 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1334; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1334; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1334; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [8:0] source_1; // @[Monitor.scala:541:22] reg [256:0] inflight; // @[Monitor.scala:614:27] reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1027:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [256:0] a_set; // @[Monitor.scala:626:34] wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1027:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [1027:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1027:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [1027:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1027:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [511:0] _GEN_2 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [511:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1199 = _T_1266 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1199 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1199 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1199 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [11:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [11:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [11:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1199 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4098:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1199 ? _a_sizes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [256:0] d_clr; // @[Monitor.scala:664:34] wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1027:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1245 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1245 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1214 = _T_1334 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1214 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1214 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [4110:0] _d_sizes_clr_T_5 = 4111'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1214 ? _d_sizes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [256:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [1027:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1027:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1027:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1027:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [256:0] inflight_1; // @[Monitor.scala:726:35] wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1027:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1027:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1027:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1027:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [1027:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1027:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [256:0] d_clr_1; // @[Monitor.scala:774:34] wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1027:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1310 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1310 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35] wire _T_1292 = _T_1334 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1292 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1292 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [4110:0] _d_sizes_clr_T_11 = 4111'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1292 ? _d_sizes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113] wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1027:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1027:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_86( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_97 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_494( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_238 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w4_d3_i0_57( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_497 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_498 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_499 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_500 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_401( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_145 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }
module cc_banks_7_0( // @[DescribedSRAM.scala:17:26] input [14:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [63:0] RW0_wdata, output [63:0] RW0_rdata ); cc_banks_0_ext cc_banks_0_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_74( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_118 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module TLBuffer_a14d64s7k1z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [13:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [6:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_27 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a14d64s7k1z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a14d64s7k1z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_294( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_38 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid || io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }
module PriorityQueueStage_203( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body || !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body || !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLAToNoC_11( // @[TilelinkAdapters.scala:112:7] input clock, // @[TilelinkAdapters.scala:112:7] input reset, // @[TilelinkAdapters.scala:112:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [7:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [72:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [5:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire [8:0] _GEN; // @[TilelinkAdapters.scala:119:{45,69}] wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [7:0] _q_io_deq_bits_mask; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3]); // @[package.scala:243:{46,71,76}] reg [8:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire _io_flit_bits_tail_T = _GEN == 9'h0; // @[TilelinkAdapters.scala:119:{45,69}] wire q_io_deq_ready = io_flit_ready & (is_body | _io_flit_bits_tail_T); // @[TilelinkAdapters.scala:39:24, :41:{35,47}, :119:{45,69}] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 9'h1 | tail_beats1 == 9'h0) & (is_body | _io_flit_bits_tail_T); // @[Edges.scala:221:14, :229:27, :232:{25,33,43}] wire [21:0] _GEN_0 = _q_io_deq_bits_address[27:6] ^ 22'h200001; // @[Parameters.scala:137:31] wire [25:0] _io_flit_bits_egress_id_requestOH_T_35 = _q_io_deq_bits_address[31:6] ^ 26'h2000001; // @[Parameters.scala:137:31] wire [21:0] _GEN_1 = _q_io_deq_bits_address[27:6] ^ 22'h200002; // @[Parameters.scala:137:31] wire [25:0] _io_flit_bits_egress_id_requestOH_T_47 = _q_io_deq_bits_address[31:6] ^ 26'h2000002; // @[Parameters.scala:137:31] wire [21:0] _GEN_2 = _q_io_deq_bits_address[27:6] ^ 22'h200003; // @[Parameters.scala:137:31] wire [25:0] _io_flit_bits_egress_id_requestOH_T_59 = _q_io_deq_bits_address[31:6] ^ 26'h2000003; // @[Parameters.scala:137:31] assign _GEN = {~(_q_io_deq_bits_opcode[2]), ~_q_io_deq_bits_mask}; // @[Edges.scala:92:{28,37}] wire _GEN_3 = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:112:7] if (reset) begin // @[TilelinkAdapters.scala:112:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :112:7] end else begin // @[TilelinkAdapters.scala:112:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3])) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN_3 & io_flit_bits_tail_0) & (_GEN_3 & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_39( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_47 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }
module array_4_0_0( // @[DescribedSRAM.scala:17:26] input [8:0] R0_addr, input R0_en, input R0_clk, output [63:0] R0_data, input [8:0] W0_addr, input W0_en, input W0_clk, input [63:0] W0_data ); array_0_0_0_ext array_0_0_0_ext ( // @[DescribedSRAM.scala:17:26] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File issue-unit-age-ordered.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Logic //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.exu import chisel3._ import chisel3.util.{log2Ceil, PopCount} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import FUConstants._ import boom.v3.common._ /** * Specific type of issue unit * * @param params issue queue params * @param numWakeupPorts number of wakeup ports for the issue queue */ class IssueUnitCollapsing( params: IssueParams, numWakeupPorts: Int) (implicit p: Parameters) extends IssueUnit(params.numEntries, params.issueWidth, numWakeupPorts, params.iqType, params.dispatchWidth) { //------------------------------------------------------------- // Figure out how much to shift entries by val maxShift = dispatchWidth val vacants = issue_slots.map(s => !(s.valid)) ++ io.dis_uops.map(_.valid).map(!_.asBool) val shamts_oh = Array.fill(numIssueSlots+dispatchWidth) {Wire(UInt(width=maxShift.W))} // track how many to shift up this entry by by counting previous vacant spots def SaturatingCounterOH(count_oh:UInt, inc: Bool, max: Int): UInt = { val next = Wire(UInt(width=max.W)) next := count_oh when (count_oh === 0.U && inc) { next := 1.U } .elsewhen (!count_oh(max-1) && inc) { next := (count_oh << 1.U) } next } shamts_oh(0) := 0.U for (i <- 1 until numIssueSlots + dispatchWidth) { shamts_oh(i) := SaturatingCounterOH(shamts_oh(i-1), vacants(i-1), maxShift) } //------------------------------------------------------------- // which entries' uops will still be next cycle? (not being issued and vacated) val will_be_valid = (0 until numIssueSlots).map(i => issue_slots(i).will_be_valid) ++ (0 until dispatchWidth).map(i => io.dis_uops(i).valid && !dis_uops(i).exception && !dis_uops(i).is_fence && !dis_uops(i).is_fencei) val uops = issue_slots.map(s=>s.out_uop) ++ dis_uops.map(s=>s) for (i <- 0 until numIssueSlots) { issue_slots(i).in_uop.valid := false.B issue_slots(i).in_uop.bits := uops(i+1) for (j <- 1 to maxShift by 1) { when (shamts_oh(i+j) === (1 << (j-1)).U) { issue_slots(i).in_uop.valid := will_be_valid(i+j) issue_slots(i).in_uop.bits := uops(i+j) } } issue_slots(i).clear := shamts_oh(i) =/= 0.U } //------------------------------------------------------------- // Dispatch/Entry Logic // did we find a spot to slide the new dispatched uops into? val will_be_available = (0 until numIssueSlots).map(i => (!issue_slots(i).will_be_valid || issue_slots(i).clear) && !(issue_slots(i).in_uop.valid)) val num_available = PopCount(will_be_available) for (w <- 0 until dispatchWidth) { io.dis_uops(w).ready := RegNext(num_available > w.U) } //------------------------------------------------------------- // Issue Select Logic // set default for (w <- 0 until issueWidth) { io.iss_valids(w) := false.B io.iss_uops(w) := NullMicroOp // unsure if this is overkill io.iss_uops(w).prs1 := 0.U io.iss_uops(w).prs2 := 0.U io.iss_uops(w).prs3 := 0.U io.iss_uops(w).lrs1_rtype := RT_X io.iss_uops(w).lrs2_rtype := RT_X } val requests = issue_slots.map(s => s.request) val port_issued = Array.fill(issueWidth){Bool()} for (w <- 0 until issueWidth) { port_issued(w) = false.B } for (i <- 0 until numIssueSlots) { issue_slots(i).grant := false.B var uop_issued = false.B for (w <- 0 until issueWidth) { val can_allocate = (issue_slots(i).uop.fu_code & io.fu_types(w)) =/= 0.U when (requests(i) && !uop_issued && can_allocate && !port_issued(w)) { issue_slots(i).grant := true.B io.iss_valids(w) := true.B io.iss_uops(w) := issue_slots(i).uop } val was_port_issued_yet = port_issued(w) port_issued(w) = (requests(i) && !uop_issued && can_allocate) | port_issued(w) uop_issued = (requests(i) && can_allocate && !was_port_issued_yet) | uop_issued } } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-unit.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Logic //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.{Str} import boom.v3.common._ import boom.v3.exu.FUConstants._ import boom.v3.util.{BoolToChar} /** * Class used for configurations * * @param issueWidth amount of things that can be issued * @param numEntries size of issue queue * @param iqType type of issue queue */ case class IssueParams( dispatchWidth: Int = 1, issueWidth: Int = 1, numEntries: Int = 8, iqType: BigInt ) /** * Constants for knowing about the status of a MicroOp */ trait IssueUnitConstants { // invalid : slot holds no valid uop. // s_valid_1: slot holds a valid uop. // s_valid_2: slot holds a store-like uop that may be broken into two micro-ops. val s_invalid :: s_valid_1 :: s_valid_2 :: Nil = Enum(3) } /** * What physical register is broadcasting its wakeup? * Is the physical register poisoned (aka, was it woken up by a speculative issue)? * * @param pregSz size of physical destination register */ class IqWakeup(val pregSz: Int) extends Bundle { val pdst = UInt(width=pregSz.W) val poisoned = Bool() } /** * IO bundle to interact with the issue unit * * @param issueWidth amount of operations that can be issued at once * @param numWakeupPorts number of wakeup ports for issue unit */ class IssueUnitIO( val issueWidth: Int, val numWakeupPorts: Int, val dispatchWidth: Int) (implicit p: Parameters) extends BoomBundle { val dis_uops = Vec(dispatchWidth, Flipped(Decoupled(new MicroOp))) val iss_valids = Output(Vec(issueWidth, Bool())) val iss_uops = Output(Vec(issueWidth, new MicroOp())) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) // tell the issue unit what each execution pipeline has in terms of functional units val fu_types = Input(Vec(issueWidth, Bits(width=FUC_SZ.W))) val brupdate = Input(new BrUpdateInfo()) val flush_pipeline = Input(Bool()) val ld_miss = Input(Bool()) val event_empty = Output(Bool()) // used by HPM events; is the issue unit empty? val tsc_reg = Input(UInt(width=xLen.W)) } /** * Abstract top level issue unit * * @param numIssueSlots depth of issue queue * @param issueWidth amoutn of operations that can be issued at once * @param numWakeupPorts number of wakeup ports for issue unit * @param iqType type of issue queue (mem, int, fp) */ abstract class IssueUnit( val numIssueSlots: Int, val issueWidth: Int, val numWakeupPorts: Int, val iqType: BigInt, val dispatchWidth: Int) (implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueUnitIO(issueWidth, numWakeupPorts, dispatchWidth)) //------------------------------------------------------------- // Set up the dispatch uops // special case "storing" 2 uops within one issue slot. val dis_uops = Array.fill(dispatchWidth) {Wire(new MicroOp())} for (w <- 0 until dispatchWidth) { dis_uops(w) := io.dis_uops(w).bits dis_uops(w).iw_p1_poisoned := false.B dis_uops(w).iw_p2_poisoned := false.B dis_uops(w).iw_state := s_valid_1 if (iqType == IQT_MEM.litValue || iqType == IQT_INT.litValue) { // For StoreAddrGen for Int, or AMOAddrGen, we go to addr gen state when ((io.dis_uops(w).bits.uopc === uopSTA && io.dis_uops(w).bits.lrs2_rtype === RT_FIX) || io.dis_uops(w).bits.uopc === uopAMO_AG) { dis_uops(w).iw_state := s_valid_2 // For store addr gen for FP, rs2 is the FP register, and we don't wait for that here } .elsewhen (io.dis_uops(w).bits.uopc === uopSTA && io.dis_uops(w).bits.lrs2_rtype =/= RT_FIX) { dis_uops(w).lrs2_rtype := RT_X dis_uops(w).prs2_busy := false.B } dis_uops(w).prs3_busy := false.B } else if (iqType == IQT_FP.litValue) { // FP "StoreAddrGen" is really storeDataGen, and rs1 is the integer address register when (io.dis_uops(w).bits.uopc === uopSTA) { dis_uops(w).lrs1_rtype := RT_X dis_uops(w).prs1_busy := false.B } } if (iqType != IQT_INT.litValue) { assert(!(io.dis_uops(w).bits.ppred_busy && io.dis_uops(w).valid)) dis_uops(w).ppred_busy := false.B } } //------------------------------------------------------------- // Issue Table val slots = for (i <- 0 until numIssueSlots) yield { val slot = Module(new IssueSlot(numWakeupPorts)); slot } val issue_slots = VecInit(slots.map(_.io)) for (i <- 0 until numIssueSlots) { issue_slots(i).wakeup_ports := io.wakeup_ports issue_slots(i).pred_wakeup_port := io.pred_wakeup_port issue_slots(i).spec_ld_wakeup := io.spec_ld_wakeup issue_slots(i).ldspec_miss := io.ld_miss issue_slots(i).brupdate := io.brupdate issue_slots(i).kill := io.flush_pipeline } io.event_empty := !(issue_slots.map(s => s.valid).reduce(_|_)) val count = PopCount(slots.map(_.io.valid)) dontTouch(count) //------------------------------------------------------------- assert (PopCount(issue_slots.map(s => s.grant)) <= issueWidth.U, "[issue] window giving out too many grants.") //------------------------------------------------------------- def getType: String = if (iqType == IQT_INT.litValue) "int" else if (iqType == IQT_MEM.litValue) "mem" else if (iqType == IQT_FP.litValue) " fp" else "unknown" }
module IssueUnitCollapsing_5( // @[issue-unit-age-ordered.scala:29:7] input clock, // @[issue-unit-age-ordered.scala:29:7] input reset, // @[issue-unit-age-ordered.scala:29:7] output io_dis_uops_0_ready, // @[issue-unit.scala:112:14] input io_dis_uops_0_valid, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_0_bits_uopc, // @[issue-unit.scala:112:14] input [31:0] io_dis_uops_0_bits_inst, // @[issue-unit.scala:112:14] input [31:0] io_dis_uops_0_bits_debug_inst, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_rvc, // @[issue-unit.scala:112:14] input [39:0] io_dis_uops_0_bits_debug_pc, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_iq_type, // @[issue-unit.scala:112:14] input [9:0] io_dis_uops_0_bits_fu_code, // @[issue-unit.scala:112:14] input [3:0] io_dis_uops_0_bits_ctrl_br_type, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_ctrl_op1_sel, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_ctrl_op2_sel, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_ctrl_imm_sel, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_0_bits_ctrl_op_fcn, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ctrl_fcn_dw, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_ctrl_csr_cmd, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ctrl_is_load, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ctrl_is_sta, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ctrl_is_std, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_iw_state, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_iw_p1_poisoned, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_iw_p2_poisoned, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_br, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_jalr, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_jal, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_sfb, // @[issue-unit.scala:112:14] input [7:0] io_dis_uops_0_bits_br_mask, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_br_tag, // @[issue-unit.scala:112:14] input [3:0] io_dis_uops_0_bits_ftq_idx, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_edge_inst, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_pc_lob, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_taken, // @[issue-unit.scala:112:14] input [19:0] io_dis_uops_0_bits_imm_packed, // @[issue-unit.scala:112:14] input [11:0] io_dis_uops_0_bits_csr_addr, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_0_bits_rob_idx, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_ldq_idx, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_stq_idx, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_rxq_idx, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_pdst, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_prs1, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_prs2, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_prs3, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_prs1_busy, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_prs2_busy, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_prs3_busy, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_stale_pdst, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_exception, // @[issue-unit.scala:112:14] input [63:0] io_dis_uops_0_bits_exc_cause, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_bypassable, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_0_bits_mem_cmd, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_mem_size, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_mem_signed, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_fence, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_fencei, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_amo, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_uses_ldq, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_uses_stq, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_unique, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_flush_on_commit, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_ldst, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_lrs1, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_lrs2, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_lrs3, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ldst_val, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_dst_rtype, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_frs3_en, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_fp_val, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_fp_single, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_bp_debug_if, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_debug_fsrc, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_debug_tsrc, // @[issue-unit.scala:112:14] output io_iss_valids_0, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_0_uopc, // @[issue-unit.scala:112:14] output [31:0] io_iss_uops_0_inst, // @[issue-unit.scala:112:14] output [31:0] io_iss_uops_0_debug_inst, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_rvc, // @[issue-unit.scala:112:14] output [39:0] io_iss_uops_0_debug_pc, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_iq_type, // @[issue-unit.scala:112:14] output [9:0] io_iss_uops_0_fu_code, // @[issue-unit.scala:112:14] output [3:0] io_iss_uops_0_ctrl_br_type, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_ctrl_op1_sel, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_ctrl_op2_sel, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_ctrl_imm_sel, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_0_ctrl_op_fcn, // @[issue-unit.scala:112:14] output io_iss_uops_0_ctrl_fcn_dw, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_ctrl_csr_cmd, // @[issue-unit.scala:112:14] output io_iss_uops_0_ctrl_is_load, // @[issue-unit.scala:112:14] output io_iss_uops_0_ctrl_is_sta, // @[issue-unit.scala:112:14] output io_iss_uops_0_ctrl_is_std, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_iw_state, // @[issue-unit.scala:112:14] output io_iss_uops_0_iw_p1_poisoned, // @[issue-unit.scala:112:14] output io_iss_uops_0_iw_p2_poisoned, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_br, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_jalr, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_jal, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_sfb, // @[issue-unit.scala:112:14] output [7:0] io_iss_uops_0_br_mask, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_br_tag, // @[issue-unit.scala:112:14] output [3:0] io_iss_uops_0_ftq_idx, // @[issue-unit.scala:112:14] output io_iss_uops_0_edge_inst, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_pc_lob, // @[issue-unit.scala:112:14] output io_iss_uops_0_taken, // @[issue-unit.scala:112:14] output [19:0] io_iss_uops_0_imm_packed, // @[issue-unit.scala:112:14] output [11:0] io_iss_uops_0_csr_addr, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_0_rob_idx, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_ldq_idx, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_stq_idx, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_rxq_idx, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_pdst, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_prs1, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_prs2, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_prs3, // @[issue-unit.scala:112:14] output [3:0] io_iss_uops_0_ppred, // @[issue-unit.scala:112:14] output io_iss_uops_0_prs1_busy, // @[issue-unit.scala:112:14] output io_iss_uops_0_prs2_busy, // @[issue-unit.scala:112:14] output io_iss_uops_0_prs3_busy, // @[issue-unit.scala:112:14] output io_iss_uops_0_ppred_busy, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_stale_pdst, // @[issue-unit.scala:112:14] output io_iss_uops_0_exception, // @[issue-unit.scala:112:14] output [63:0] io_iss_uops_0_exc_cause, // @[issue-unit.scala:112:14] output io_iss_uops_0_bypassable, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_0_mem_cmd, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_mem_size, // @[issue-unit.scala:112:14] output io_iss_uops_0_mem_signed, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_fence, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_fencei, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_amo, // @[issue-unit.scala:112:14] output io_iss_uops_0_uses_ldq, // @[issue-unit.scala:112:14] output io_iss_uops_0_uses_stq, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_sys_pc2epc, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_unique, // @[issue-unit.scala:112:14] output io_iss_uops_0_flush_on_commit, // @[issue-unit.scala:112:14] output io_iss_uops_0_ldst_is_rs1, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_ldst, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_lrs1, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_lrs2, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_lrs3, // @[issue-unit.scala:112:14] output io_iss_uops_0_ldst_val, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_dst_rtype, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_lrs1_rtype, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_lrs2_rtype, // @[issue-unit.scala:112:14] output io_iss_uops_0_frs3_en, // @[issue-unit.scala:112:14] output io_iss_uops_0_fp_val, // @[issue-unit.scala:112:14] output io_iss_uops_0_fp_single, // @[issue-unit.scala:112:14] output io_iss_uops_0_xcpt_pf_if, // @[issue-unit.scala:112:14] output io_iss_uops_0_xcpt_ae_if, // @[issue-unit.scala:112:14] output io_iss_uops_0_xcpt_ma_if, // @[issue-unit.scala:112:14] output io_iss_uops_0_bp_debug_if, // @[issue-unit.scala:112:14] output io_iss_uops_0_bp_xcpt_if, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_debug_fsrc, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_debug_tsrc, // @[issue-unit.scala:112:14] input io_wakeup_ports_0_valid, // @[issue-unit.scala:112:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-unit.scala:112:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-unit.scala:112:14] input io_wakeup_ports_1_valid, // @[issue-unit.scala:112:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-unit.scala:112:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-unit.scala:112:14] input io_wakeup_ports_2_valid, // @[issue-unit.scala:112:14] input [5:0] io_wakeup_ports_2_bits_pdst, // @[issue-unit.scala:112:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-unit.scala:112:14] input io_spec_ld_wakeup_0_valid, // @[issue-unit.scala:112:14] input [5:0] io_spec_ld_wakeup_0_bits, // @[issue-unit.scala:112:14] input [9:0] io_fu_types_0, // @[issue-unit.scala:112:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-unit.scala:112:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-unit.scala:112:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-unit.scala:112:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-unit.scala:112:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_rvc, // @[issue-unit.scala:112:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-unit.scala:112:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-unit.scala:112:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-unit.scala:112:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_br, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_jalr, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_jal, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_sfb, // @[issue-unit.scala:112:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-unit.scala:112:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_edge_inst, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_taken, // @[issue-unit.scala:112:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-unit.scala:112:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-unit.scala:112:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-unit.scala:112:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_exception, // @[issue-unit.scala:112:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_bypassable, // @[issue-unit.scala:112:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_mem_signed, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_fence, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_fencei, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_amo, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_uses_stq, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_unique, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ldst_val, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_frs3_en, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_fp_val, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_fp_single, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-unit.scala:112:14] input io_brupdate_b2_valid, // @[issue-unit.scala:112:14] input io_brupdate_b2_mispredict, // @[issue-unit.scala:112:14] input io_brupdate_b2_taken, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-unit.scala:112:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-unit.scala:112:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-unit.scala:112:14] input io_flush_pipeline, // @[issue-unit.scala:112:14] input io_ld_miss, // @[issue-unit.scala:112:14] input [63:0] io_tsc_reg // @[issue-unit.scala:112:14] ); wire _slots_7_io_valid; // @[issue-unit.scala:153:73] wire _slots_6_io_valid; // @[issue-unit.scala:153:73] wire _slots_5_io_valid; // @[issue-unit.scala:153:73] wire _slots_4_io_valid; // @[issue-unit.scala:153:73] wire _slots_3_io_valid; // @[issue-unit.scala:153:73] wire _slots_2_io_valid; // @[issue-unit.scala:153:73] wire _slots_1_io_valid; // @[issue-unit.scala:153:73] wire _slots_0_io_valid; // @[issue-unit.scala:153:73] wire io_dis_uops_0_valid_0 = io_dis_uops_0_valid; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_0_bits_uopc_0 = io_dis_uops_0_bits_uopc; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_dis_uops_0_bits_inst_0 = io_dis_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_dis_uops_0_bits_debug_inst_0 = io_dis_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_rvc_0 = io_dis_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:29:7] wire [39:0] io_dis_uops_0_bits_debug_pc_0 = io_dis_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_iq_type_0 = io_dis_uops_0_bits_iq_type; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_dis_uops_0_bits_fu_code_0 = io_dis_uops_0_bits_fu_code; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_dis_uops_0_bits_ctrl_br_type_0 = io_dis_uops_0_bits_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_ctrl_op1_sel_0 = io_dis_uops_0_bits_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_ctrl_op2_sel_0 = io_dis_uops_0_bits_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_ctrl_imm_sel_0 = io_dis_uops_0_bits_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_0_bits_ctrl_op_fcn_0 = io_dis_uops_0_bits_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ctrl_fcn_dw_0 = io_dis_uops_0_bits_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_ctrl_csr_cmd_0 = io_dis_uops_0_bits_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ctrl_is_load_0 = io_dis_uops_0_bits_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ctrl_is_sta_0 = io_dis_uops_0_bits_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ctrl_is_std_0 = io_dis_uops_0_bits_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_iw_state_0 = io_dis_uops_0_bits_iw_state; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_iw_p1_poisoned_0 = io_dis_uops_0_bits_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_iw_p2_poisoned_0 = io_dis_uops_0_bits_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_br_0 = io_dis_uops_0_bits_is_br; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_jalr_0 = io_dis_uops_0_bits_is_jalr; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_jal_0 = io_dis_uops_0_bits_is_jal; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_sfb_0 = io_dis_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:29:7] wire [7:0] io_dis_uops_0_bits_br_mask_0 = io_dis_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_br_tag_0 = io_dis_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_dis_uops_0_bits_ftq_idx_0 = io_dis_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_edge_inst_0 = io_dis_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_pc_lob_0 = io_dis_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_taken_0 = io_dis_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:29:7] wire [19:0] io_dis_uops_0_bits_imm_packed_0 = io_dis_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:29:7] wire [11:0] io_dis_uops_0_bits_csr_addr_0 = io_dis_uops_0_bits_csr_addr; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_0_bits_rob_idx_0 = io_dis_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_ldq_idx_0 = io_dis_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_stq_idx_0 = io_dis_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_rxq_idx_0 = io_dis_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_pdst_0 = io_dis_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_prs1_0 = io_dis_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_prs2_0 = io_dis_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_prs3_0 = io_dis_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_prs1_busy_0 = io_dis_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_prs2_busy_0 = io_dis_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_prs3_busy_0 = io_dis_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_stale_pdst_0 = io_dis_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_exception_0 = io_dis_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:29:7] wire [63:0] io_dis_uops_0_bits_exc_cause_0 = io_dis_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_bypassable_0 = io_dis_uops_0_bits_bypassable; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_0_bits_mem_cmd_0 = io_dis_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_mem_size_0 = io_dis_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_mem_signed_0 = io_dis_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_fence_0 = io_dis_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_fencei_0 = io_dis_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_amo_0 = io_dis_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_uses_ldq_0 = io_dis_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_uses_stq_0 = io_dis_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_sys_pc2epc_0 = io_dis_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_unique_0 = io_dis_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_flush_on_commit_0 = io_dis_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ldst_is_rs1_0 = io_dis_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_ldst_0 = io_dis_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_lrs1_0 = io_dis_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_lrs2_0 = io_dis_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_lrs3_0 = io_dis_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ldst_val_0 = io_dis_uops_0_bits_ldst_val; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_dst_rtype_0 = io_dis_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_lrs1_rtype_0 = io_dis_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_lrs2_rtype_0 = io_dis_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_frs3_en_0 = io_dis_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_fp_val_0 = io_dis_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_fp_single_0 = io_dis_uops_0_bits_fp_single; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_xcpt_pf_if_0 = io_dis_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_xcpt_ae_if_0 = io_dis_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_xcpt_ma_if_0 = io_dis_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_bp_debug_if_0 = io_dis_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_bp_xcpt_if_0 = io_dis_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_debug_fsrc_0 = io_dis_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_debug_tsrc_0 = io_dis_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_fu_types_0_0 = io_fu_types_0; // @[issue-unit-age-ordered.scala:29:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-unit-age-ordered.scala:29:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-unit-age-ordered.scala:29:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-unit-age-ordered.scala:29:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-unit-age-ordered.scala:29:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-unit-age-ordered.scala:29:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-unit-age-ordered.scala:29:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-unit-age-ordered.scala:29:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-unit-age-ordered.scala:29:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-unit-age-ordered.scala:29:7] wire io_flush_pipeline_0 = io_flush_pipeline; // @[issue-unit-age-ordered.scala:29:7] wire io_ld_miss_0 = io_ld_miss; // @[issue-unit-age-ordered.scala:29:7] wire [63:0] io_tsc_reg_0 = io_tsc_reg; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:29:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:29:7] wire issue_slots_0_clear = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_0_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_1_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_2_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_3_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_4_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_5_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_6_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_prs3_busy = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ppred_busy = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_prs3_busy = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ppred_busy = 1'h0; // @[issue-unit.scala:154:28] wire _issue_slots_0_clear_T = 1'h0; // @[issue-unit-age-ordered.scala:76:49] wire io_iss_uops_0_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_br = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_taken = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_exception = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_0_cs_is_load = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_0_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_0_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [3:0] io_dis_uops_0_bits_ppred = 4'h0; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] issue_slots_0_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_in_uop_bits_ppred = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_in_uop_bits_ppred = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_out_uop_ppred = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_uop_ppred = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] io_iss_uops_0_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] io_iss_uops_0_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] io_iss_uops_0_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] io_iss_uops_0_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [2:0] io_iss_uops_0_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] io_iss_uops_0_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] io_iss_uops_0_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] io_iss_uops_0_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_0_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_0_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_0_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] _next_T = 2'h0; // @[issue-unit-age-ordered.scala:48:26] wire [1:0] io_iss_uops_0_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] io_iss_uops_0_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] io_iss_uops_0_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] io_iss_uops_0_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] io_iss_uops_0_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] io_iss_uops_0_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] io_iss_uops_0_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] io_iss_uops_0_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] io_iss_uops_0_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] io_iss_uops_0_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_0_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] issue_slots_7_in_uop_bits_uopc = io_dis_uops_0_bits_uopc_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_in_uop_bits_inst = io_dis_uops_0_bits_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_in_uop_bits_debug_inst = io_dis_uops_0_bits_debug_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_rvc = io_dis_uops_0_bits_is_rvc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_7_in_uop_bits_debug_pc = io_dis_uops_0_bits_debug_pc_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_iq_type = io_dis_uops_0_bits_iq_type_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_7_in_uop_bits_fu_code = io_dis_uops_0_bits_fu_code_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_in_uop_bits_ctrl_br_type = io_dis_uops_0_bits_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_ctrl_op1_sel = io_dis_uops_0_bits_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_ctrl_op2_sel = io_dis_uops_0_bits_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_ctrl_imm_sel = io_dis_uops_0_bits_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_in_uop_bits_ctrl_op_fcn = io_dis_uops_0_bits_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ctrl_fcn_dw = io_dis_uops_0_bits_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_ctrl_csr_cmd = io_dis_uops_0_bits_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ctrl_is_load = io_dis_uops_0_bits_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ctrl_is_sta = io_dis_uops_0_bits_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ctrl_is_std = io_dis_uops_0_bits_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_br = io_dis_uops_0_bits_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_jalr = io_dis_uops_0_bits_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_jal = io_dis_uops_0_bits_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_sfb = io_dis_uops_0_bits_is_sfb_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_7_in_uop_bits_br_mask = io_dis_uops_0_bits_br_mask_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_br_tag = io_dis_uops_0_bits_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_in_uop_bits_ftq_idx = io_dis_uops_0_bits_ftq_idx_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_edge_inst = io_dis_uops_0_bits_edge_inst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_pc_lob = io_dis_uops_0_bits_pc_lob_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_taken = io_dis_uops_0_bits_taken_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_7_in_uop_bits_imm_packed = io_dis_uops_0_bits_imm_packed_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_7_in_uop_bits_csr_addr = io_dis_uops_0_bits_csr_addr_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_in_uop_bits_rob_idx = io_dis_uops_0_bits_rob_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_ldq_idx = io_dis_uops_0_bits_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_stq_idx = io_dis_uops_0_bits_stq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_rxq_idx = io_dis_uops_0_bits_rxq_idx_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_pdst = io_dis_uops_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_prs1 = io_dis_uops_0_bits_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_prs2 = io_dis_uops_0_bits_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_prs3 = io_dis_uops_0_bits_prs3_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_prs1_busy = io_dis_uops_0_bits_prs1_busy_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_stale_pdst = io_dis_uops_0_bits_stale_pdst_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_exception = io_dis_uops_0_bits_exception_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_7_in_uop_bits_exc_cause = io_dis_uops_0_bits_exc_cause_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_bypassable = io_dis_uops_0_bits_bypassable_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_in_uop_bits_mem_cmd = io_dis_uops_0_bits_mem_cmd_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_mem_size = io_dis_uops_0_bits_mem_size_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_mem_signed = io_dis_uops_0_bits_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_fence = io_dis_uops_0_bits_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_fencei = io_dis_uops_0_bits_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_amo = io_dis_uops_0_bits_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_uses_ldq = io_dis_uops_0_bits_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_uses_stq = io_dis_uops_0_bits_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_sys_pc2epc = io_dis_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_unique = io_dis_uops_0_bits_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_flush_on_commit = io_dis_uops_0_bits_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ldst_is_rs1 = io_dis_uops_0_bits_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_ldst = io_dis_uops_0_bits_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_lrs1 = io_dis_uops_0_bits_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_lrs2 = io_dis_uops_0_bits_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_lrs3 = io_dis_uops_0_bits_lrs3_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ldst_val = io_dis_uops_0_bits_ldst_val_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_dst_rtype = io_dis_uops_0_bits_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_lrs1_rtype = io_dis_uops_0_bits_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_frs3_en = io_dis_uops_0_bits_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_fp_val = io_dis_uops_0_bits_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_fp_single = io_dis_uops_0_bits_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_xcpt_pf_if = io_dis_uops_0_bits_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_xcpt_ae_if = io_dis_uops_0_bits_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_xcpt_ma_if = io_dis_uops_0_bits_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_bp_debug_if = io_dis_uops_0_bits_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_bp_xcpt_if = io_dis_uops_0_bits_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_debug_fsrc = io_dis_uops_0_bits_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_debug_tsrc = io_dis_uops_0_bits_debug_tsrc_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_0_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_0_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_1_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_2_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_3_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_4_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_5_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_6_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_7_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_0_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_1_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_2_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_3_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_4_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_5_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_6_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_7_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_0_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_1_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_2_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_3_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_4_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_5_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_6_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_7_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_0_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_1_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_2_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_3_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_4_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_5_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_6_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_7_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_0_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_1_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_2_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_3_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_4_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_5_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_6_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_7_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_0_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_1_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_2_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_3_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_4_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_5_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_6_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_7_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_0_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_1_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_2_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_3_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_4_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_5_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_6_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_7_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_0_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_1_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_2_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_3_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_4_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_5_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_6_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_7_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_0_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_1_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_2_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_3_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_4_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_5_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_6_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_7_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_0_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_1_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_2_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_3_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_4_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_5_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_6_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_7_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire issue_slots_0_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_1_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_2_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_3_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_4_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_5_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_6_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_7_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_0_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_1_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_2_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_3_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_4_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_5_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_6_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_7_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire _io_event_empty_T_7; // @[issue-unit.scala:165:21] wire io_dis_uops_0_ready_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_valids_0_0; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_iss_uops_0_ctrl_br_type_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_ctrl_op1_sel_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_ctrl_op2_sel_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_ctrl_imm_sel_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_0_ctrl_op_fcn_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ctrl_fcn_dw_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_ctrl_csr_cmd_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ctrl_is_load_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ctrl_is_sta_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ctrl_is_std_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_0_uopc_0; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_iss_uops_0_inst_0; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_iss_uops_0_debug_inst_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_rvc_0; // @[issue-unit-age-ordered.scala:29:7] wire [39:0] io_iss_uops_0_debug_pc_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_iq_type_0; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_iss_uops_0_fu_code_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_iw_state_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_iw_p1_poisoned_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_iw_p2_poisoned_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_br_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_jalr_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_jal_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_sfb_0; // @[issue-unit-age-ordered.scala:29:7] wire [7:0] io_iss_uops_0_br_mask_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_br_tag_0; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_iss_uops_0_ftq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_edge_inst_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_pc_lob_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_taken_0; // @[issue-unit-age-ordered.scala:29:7] wire [19:0] io_iss_uops_0_imm_packed_0; // @[issue-unit-age-ordered.scala:29:7] wire [11:0] io_iss_uops_0_csr_addr_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_0_rob_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_ldq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_stq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_rxq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_pdst_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_prs1_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_prs2_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_prs3_0; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_iss_uops_0_ppred_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_prs1_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_prs2_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_prs3_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ppred_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_stale_pdst_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_exception_0; // @[issue-unit-age-ordered.scala:29:7] wire [63:0] io_iss_uops_0_exc_cause_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_bypassable_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_0_mem_cmd_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_mem_size_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_mem_signed_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_fence_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_fencei_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_amo_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_uses_ldq_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_uses_stq_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_unique_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_flush_on_commit_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_ldst_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_lrs1_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_lrs2_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_lrs3_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ldst_val_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_dst_rtype_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_frs3_en_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_fp_val_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_fp_single_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_bp_debug_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_debug_fsrc_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_debug_tsrc_0; // @[issue-unit-age-ordered.scala:29:7] wire io_event_empty; // @[issue-unit-age-ordered.scala:29:7] wire _T_5 = io_dis_uops_0_bits_uopc_0 == 7'h2; // @[issue-unit.scala:127:39] wire _T_4 = _T_5 & io_dis_uops_0_bits_lrs2_rtype_0 == 2'h0 | io_dis_uops_0_bits_uopc_0 == 7'h43; // @[issue-unit.scala:127:{39,50,84,96}, :128:39] wire [1:0] issue_slots_7_in_uop_bits_iw_state = _T_4 ? 2'h2 : 2'h1; // @[issue-unit.scala:123:26, :127:96, :128:54, :129:30, :154:28] wire _GEN = _T_4 | ~(_T_5 & (|io_dis_uops_0_bits_lrs2_rtype_0)); // @[issue-unit.scala:120:17, :127:{39,96}, :128:54, :131:{56,90,102}] wire [1:0] issue_slots_7_in_uop_bits_lrs2_rtype = _GEN ? io_dis_uops_0_bits_lrs2_rtype_0 : 2'h2; // @[issue-unit.scala:120:17, :128:54, :131:102, :154:28] wire issue_slots_7_in_uop_bits_prs2_busy = _GEN & io_dis_uops_0_bits_prs2_busy_0; // @[issue-unit.scala:120:17, :128:54, :131:102, :154:28] wire [6:0] issue_slots_1_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_1_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_1_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_1_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_1_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_1_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_1_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire [6:0] issue_slots_2_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_2_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_2_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_2_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_2_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_2_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_2_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_in_uop_bits_uopc = issue_slots_1_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_in_uop_bits_inst = issue_slots_1_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_in_uop_bits_debug_inst = issue_slots_1_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_rvc = issue_slots_1_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_0_in_uop_bits_debug_pc = issue_slots_1_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_iq_type = issue_slots_1_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_0_in_uop_bits_fu_code = issue_slots_1_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_in_uop_bits_ctrl_br_type = issue_slots_1_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_ctrl_op1_sel = issue_slots_1_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_ctrl_op2_sel = issue_slots_1_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_ctrl_imm_sel = issue_slots_1_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_in_uop_bits_ctrl_op_fcn = issue_slots_1_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ctrl_fcn_dw = issue_slots_1_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_ctrl_csr_cmd = issue_slots_1_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ctrl_is_load = issue_slots_1_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ctrl_is_sta = issue_slots_1_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ctrl_is_std = issue_slots_1_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_iw_state = issue_slots_1_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_iw_p1_poisoned = issue_slots_1_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_iw_p2_poisoned = issue_slots_1_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_br = issue_slots_1_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_jalr = issue_slots_1_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_jal = issue_slots_1_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_sfb = issue_slots_1_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_0_in_uop_bits_br_mask = issue_slots_1_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_br_tag = issue_slots_1_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_in_uop_bits_ftq_idx = issue_slots_1_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_edge_inst = issue_slots_1_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_pc_lob = issue_slots_1_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_taken = issue_slots_1_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_0_in_uop_bits_imm_packed = issue_slots_1_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_0_in_uop_bits_csr_addr = issue_slots_1_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_in_uop_bits_rob_idx = issue_slots_1_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_ldq_idx = issue_slots_1_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_stq_idx = issue_slots_1_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_rxq_idx = issue_slots_1_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_pdst = issue_slots_1_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_prs1 = issue_slots_1_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_prs2 = issue_slots_1_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_prs3 = issue_slots_1_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_in_uop_bits_ppred = issue_slots_1_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_prs1_busy = issue_slots_1_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_prs2_busy = issue_slots_1_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_prs3_busy = issue_slots_1_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ppred_busy = issue_slots_1_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_stale_pdst = issue_slots_1_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_exception = issue_slots_1_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_0_in_uop_bits_exc_cause = issue_slots_1_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_bypassable = issue_slots_1_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_in_uop_bits_mem_cmd = issue_slots_1_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_mem_size = issue_slots_1_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_mem_signed = issue_slots_1_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_fence = issue_slots_1_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_fencei = issue_slots_1_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_amo = issue_slots_1_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_uses_ldq = issue_slots_1_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_uses_stq = issue_slots_1_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_sys_pc2epc = issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_unique = issue_slots_1_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_flush_on_commit = issue_slots_1_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ldst_is_rs1 = issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_ldst = issue_slots_1_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_lrs1 = issue_slots_1_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_lrs2 = issue_slots_1_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_lrs3 = issue_slots_1_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ldst_val = issue_slots_1_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_dst_rtype = issue_slots_1_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_lrs1_rtype = issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_lrs2_rtype = issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_frs3_en = issue_slots_1_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_fp_val = issue_slots_1_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_fp_single = issue_slots_1_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_xcpt_pf_if = issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_xcpt_ae_if = issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_xcpt_ma_if = issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_bp_debug_if = issue_slots_1_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_bp_xcpt_if = issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_debug_fsrc = issue_slots_1_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_debug_tsrc = issue_slots_1_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire [6:0] issue_slots_3_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_3_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_3_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_3_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_3_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_3_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_3_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_in_uop_bits_uopc = issue_slots_2_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_in_uop_bits_inst = issue_slots_2_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_in_uop_bits_debug_inst = issue_slots_2_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_rvc = issue_slots_2_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_1_in_uop_bits_debug_pc = issue_slots_2_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_iq_type = issue_slots_2_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_1_in_uop_bits_fu_code = issue_slots_2_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_in_uop_bits_ctrl_br_type = issue_slots_2_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_ctrl_op1_sel = issue_slots_2_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_ctrl_op2_sel = issue_slots_2_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_ctrl_imm_sel = issue_slots_2_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_in_uop_bits_ctrl_op_fcn = issue_slots_2_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ctrl_fcn_dw = issue_slots_2_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_ctrl_csr_cmd = issue_slots_2_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ctrl_is_load = issue_slots_2_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ctrl_is_sta = issue_slots_2_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ctrl_is_std = issue_slots_2_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_iw_state = issue_slots_2_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_iw_p1_poisoned = issue_slots_2_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_iw_p2_poisoned = issue_slots_2_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_br = issue_slots_2_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_jalr = issue_slots_2_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_jal = issue_slots_2_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_sfb = issue_slots_2_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_1_in_uop_bits_br_mask = issue_slots_2_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_br_tag = issue_slots_2_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_in_uop_bits_ftq_idx = issue_slots_2_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_edge_inst = issue_slots_2_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_pc_lob = issue_slots_2_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_taken = issue_slots_2_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_1_in_uop_bits_imm_packed = issue_slots_2_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_1_in_uop_bits_csr_addr = issue_slots_2_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_in_uop_bits_rob_idx = issue_slots_2_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_ldq_idx = issue_slots_2_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_stq_idx = issue_slots_2_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_rxq_idx = issue_slots_2_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_pdst = issue_slots_2_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_prs1 = issue_slots_2_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_prs2 = issue_slots_2_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_prs3 = issue_slots_2_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_in_uop_bits_ppred = issue_slots_2_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_prs1_busy = issue_slots_2_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_prs2_busy = issue_slots_2_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_prs3_busy = issue_slots_2_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ppred_busy = issue_slots_2_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_stale_pdst = issue_slots_2_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_exception = issue_slots_2_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_1_in_uop_bits_exc_cause = issue_slots_2_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_bypassable = issue_slots_2_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_in_uop_bits_mem_cmd = issue_slots_2_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_mem_size = issue_slots_2_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_mem_signed = issue_slots_2_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_fence = issue_slots_2_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_fencei = issue_slots_2_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_amo = issue_slots_2_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_uses_ldq = issue_slots_2_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_uses_stq = issue_slots_2_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_sys_pc2epc = issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_unique = issue_slots_2_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_flush_on_commit = issue_slots_2_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ldst_is_rs1 = issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_ldst = issue_slots_2_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_lrs1 = issue_slots_2_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_lrs2 = issue_slots_2_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_lrs3 = issue_slots_2_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ldst_val = issue_slots_2_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_dst_rtype = issue_slots_2_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_lrs1_rtype = issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_lrs2_rtype = issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_frs3_en = issue_slots_2_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_fp_val = issue_slots_2_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_fp_single = issue_slots_2_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_xcpt_pf_if = issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_xcpt_ae_if = issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_xcpt_ma_if = issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_bp_debug_if = issue_slots_2_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_bp_xcpt_if = issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_debug_fsrc = issue_slots_2_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_debug_tsrc = issue_slots_2_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire [6:0] issue_slots_4_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_4_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_4_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_4_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_4_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_4_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_4_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_in_uop_bits_uopc = issue_slots_3_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_in_uop_bits_inst = issue_slots_3_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_in_uop_bits_debug_inst = issue_slots_3_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_rvc = issue_slots_3_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_2_in_uop_bits_debug_pc = issue_slots_3_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_iq_type = issue_slots_3_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_2_in_uop_bits_fu_code = issue_slots_3_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_in_uop_bits_ctrl_br_type = issue_slots_3_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_ctrl_op1_sel = issue_slots_3_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_ctrl_op2_sel = issue_slots_3_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_ctrl_imm_sel = issue_slots_3_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_in_uop_bits_ctrl_op_fcn = issue_slots_3_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ctrl_fcn_dw = issue_slots_3_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_ctrl_csr_cmd = issue_slots_3_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ctrl_is_load = issue_slots_3_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ctrl_is_sta = issue_slots_3_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ctrl_is_std = issue_slots_3_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_iw_state = issue_slots_3_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_iw_p1_poisoned = issue_slots_3_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_iw_p2_poisoned = issue_slots_3_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_br = issue_slots_3_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_jalr = issue_slots_3_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_jal = issue_slots_3_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_sfb = issue_slots_3_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_2_in_uop_bits_br_mask = issue_slots_3_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_br_tag = issue_slots_3_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_in_uop_bits_ftq_idx = issue_slots_3_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_edge_inst = issue_slots_3_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_pc_lob = issue_slots_3_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_taken = issue_slots_3_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_2_in_uop_bits_imm_packed = issue_slots_3_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_2_in_uop_bits_csr_addr = issue_slots_3_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_in_uop_bits_rob_idx = issue_slots_3_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_ldq_idx = issue_slots_3_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_stq_idx = issue_slots_3_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_rxq_idx = issue_slots_3_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_pdst = issue_slots_3_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_prs1 = issue_slots_3_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_prs2 = issue_slots_3_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_prs3 = issue_slots_3_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_in_uop_bits_ppred = issue_slots_3_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_prs1_busy = issue_slots_3_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_prs2_busy = issue_slots_3_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_prs3_busy = issue_slots_3_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ppred_busy = issue_slots_3_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_stale_pdst = issue_slots_3_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_exception = issue_slots_3_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_2_in_uop_bits_exc_cause = issue_slots_3_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_bypassable = issue_slots_3_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_in_uop_bits_mem_cmd = issue_slots_3_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_mem_size = issue_slots_3_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_mem_signed = issue_slots_3_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_fence = issue_slots_3_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_fencei = issue_slots_3_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_amo = issue_slots_3_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_uses_ldq = issue_slots_3_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_uses_stq = issue_slots_3_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_sys_pc2epc = issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_unique = issue_slots_3_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_flush_on_commit = issue_slots_3_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ldst_is_rs1 = issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_ldst = issue_slots_3_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_lrs1 = issue_slots_3_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_lrs2 = issue_slots_3_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_lrs3 = issue_slots_3_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ldst_val = issue_slots_3_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_dst_rtype = issue_slots_3_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_lrs1_rtype = issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_lrs2_rtype = issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_frs3_en = issue_slots_3_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_fp_val = issue_slots_3_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_fp_single = issue_slots_3_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_xcpt_pf_if = issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_xcpt_ae_if = issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_xcpt_ma_if = issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_bp_debug_if = issue_slots_3_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_bp_xcpt_if = issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_debug_fsrc = issue_slots_3_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_debug_tsrc = issue_slots_3_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire [6:0] issue_slots_5_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_5_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_5_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_5_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_5_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_5_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_5_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_in_uop_bits_uopc = issue_slots_4_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_in_uop_bits_inst = issue_slots_4_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_in_uop_bits_debug_inst = issue_slots_4_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_rvc = issue_slots_4_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_3_in_uop_bits_debug_pc = issue_slots_4_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_iq_type = issue_slots_4_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_3_in_uop_bits_fu_code = issue_slots_4_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_in_uop_bits_ctrl_br_type = issue_slots_4_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_ctrl_op1_sel = issue_slots_4_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_ctrl_op2_sel = issue_slots_4_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_ctrl_imm_sel = issue_slots_4_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_in_uop_bits_ctrl_op_fcn = issue_slots_4_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ctrl_fcn_dw = issue_slots_4_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_ctrl_csr_cmd = issue_slots_4_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ctrl_is_load = issue_slots_4_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ctrl_is_sta = issue_slots_4_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ctrl_is_std = issue_slots_4_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_iw_state = issue_slots_4_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_iw_p1_poisoned = issue_slots_4_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_iw_p2_poisoned = issue_slots_4_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_br = issue_slots_4_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_jalr = issue_slots_4_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_jal = issue_slots_4_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_sfb = issue_slots_4_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_3_in_uop_bits_br_mask = issue_slots_4_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_br_tag = issue_slots_4_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_in_uop_bits_ftq_idx = issue_slots_4_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_edge_inst = issue_slots_4_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_pc_lob = issue_slots_4_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_taken = issue_slots_4_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_3_in_uop_bits_imm_packed = issue_slots_4_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_3_in_uop_bits_csr_addr = issue_slots_4_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_in_uop_bits_rob_idx = issue_slots_4_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_ldq_idx = issue_slots_4_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_stq_idx = issue_slots_4_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_rxq_idx = issue_slots_4_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_pdst = issue_slots_4_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_prs1 = issue_slots_4_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_prs2 = issue_slots_4_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_prs3 = issue_slots_4_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_in_uop_bits_ppred = issue_slots_4_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_prs1_busy = issue_slots_4_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_prs2_busy = issue_slots_4_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_prs3_busy = issue_slots_4_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ppred_busy = issue_slots_4_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_stale_pdst = issue_slots_4_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_exception = issue_slots_4_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_3_in_uop_bits_exc_cause = issue_slots_4_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_bypassable = issue_slots_4_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_in_uop_bits_mem_cmd = issue_slots_4_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_mem_size = issue_slots_4_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_mem_signed = issue_slots_4_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_fence = issue_slots_4_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_fencei = issue_slots_4_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_amo = issue_slots_4_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_uses_ldq = issue_slots_4_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_uses_stq = issue_slots_4_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_sys_pc2epc = issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_unique = issue_slots_4_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_flush_on_commit = issue_slots_4_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ldst_is_rs1 = issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_ldst = issue_slots_4_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_lrs1 = issue_slots_4_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_lrs2 = issue_slots_4_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_lrs3 = issue_slots_4_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ldst_val = issue_slots_4_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_dst_rtype = issue_slots_4_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_lrs1_rtype = issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_lrs2_rtype = issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_frs3_en = issue_slots_4_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_fp_val = issue_slots_4_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_fp_single = issue_slots_4_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_xcpt_pf_if = issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_xcpt_ae_if = issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_xcpt_ma_if = issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_bp_debug_if = issue_slots_4_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_bp_xcpt_if = issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_debug_fsrc = issue_slots_4_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_debug_tsrc = issue_slots_4_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire [6:0] issue_slots_6_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_6_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_6_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_6_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_6_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_6_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_6_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_in_uop_bits_uopc = issue_slots_5_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_in_uop_bits_inst = issue_slots_5_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_in_uop_bits_debug_inst = issue_slots_5_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_rvc = issue_slots_5_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_4_in_uop_bits_debug_pc = issue_slots_5_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_iq_type = issue_slots_5_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_4_in_uop_bits_fu_code = issue_slots_5_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_in_uop_bits_ctrl_br_type = issue_slots_5_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_ctrl_op1_sel = issue_slots_5_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_ctrl_op2_sel = issue_slots_5_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_ctrl_imm_sel = issue_slots_5_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_in_uop_bits_ctrl_op_fcn = issue_slots_5_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ctrl_fcn_dw = issue_slots_5_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_ctrl_csr_cmd = issue_slots_5_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ctrl_is_load = issue_slots_5_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ctrl_is_sta = issue_slots_5_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ctrl_is_std = issue_slots_5_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_iw_state = issue_slots_5_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_iw_p1_poisoned = issue_slots_5_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_iw_p2_poisoned = issue_slots_5_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_br = issue_slots_5_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_jalr = issue_slots_5_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_jal = issue_slots_5_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_sfb = issue_slots_5_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_4_in_uop_bits_br_mask = issue_slots_5_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_br_tag = issue_slots_5_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_in_uop_bits_ftq_idx = issue_slots_5_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_edge_inst = issue_slots_5_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_pc_lob = issue_slots_5_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_taken = issue_slots_5_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_4_in_uop_bits_imm_packed = issue_slots_5_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_4_in_uop_bits_csr_addr = issue_slots_5_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_in_uop_bits_rob_idx = issue_slots_5_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_ldq_idx = issue_slots_5_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_stq_idx = issue_slots_5_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_rxq_idx = issue_slots_5_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_pdst = issue_slots_5_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_prs1 = issue_slots_5_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_prs2 = issue_slots_5_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_prs3 = issue_slots_5_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_in_uop_bits_ppred = issue_slots_5_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_prs1_busy = issue_slots_5_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_prs2_busy = issue_slots_5_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_prs3_busy = issue_slots_5_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ppred_busy = issue_slots_5_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_stale_pdst = issue_slots_5_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_exception = issue_slots_5_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_4_in_uop_bits_exc_cause = issue_slots_5_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_bypassable = issue_slots_5_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_in_uop_bits_mem_cmd = issue_slots_5_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_mem_size = issue_slots_5_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_mem_signed = issue_slots_5_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_fence = issue_slots_5_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_fencei = issue_slots_5_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_amo = issue_slots_5_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_uses_ldq = issue_slots_5_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_uses_stq = issue_slots_5_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_sys_pc2epc = issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_unique = issue_slots_5_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_flush_on_commit = issue_slots_5_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ldst_is_rs1 = issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_ldst = issue_slots_5_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_lrs1 = issue_slots_5_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_lrs2 = issue_slots_5_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_lrs3 = issue_slots_5_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ldst_val = issue_slots_5_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_dst_rtype = issue_slots_5_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_lrs1_rtype = issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_lrs2_rtype = issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_frs3_en = issue_slots_5_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_fp_val = issue_slots_5_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_fp_single = issue_slots_5_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_xcpt_pf_if = issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_xcpt_ae_if = issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_xcpt_ma_if = issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_bp_debug_if = issue_slots_5_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_bp_xcpt_if = issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_debug_fsrc = issue_slots_5_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_debug_tsrc = issue_slots_5_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire [6:0] issue_slots_7_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_7_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_7_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_7_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_7_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_7_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_prs3; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_7_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_in_uop_bits_uopc = issue_slots_6_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_in_uop_bits_inst = issue_slots_6_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_in_uop_bits_debug_inst = issue_slots_6_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_rvc = issue_slots_6_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_5_in_uop_bits_debug_pc = issue_slots_6_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_iq_type = issue_slots_6_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_5_in_uop_bits_fu_code = issue_slots_6_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_in_uop_bits_ctrl_br_type = issue_slots_6_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_ctrl_op1_sel = issue_slots_6_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_ctrl_op2_sel = issue_slots_6_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_ctrl_imm_sel = issue_slots_6_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_in_uop_bits_ctrl_op_fcn = issue_slots_6_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ctrl_fcn_dw = issue_slots_6_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_ctrl_csr_cmd = issue_slots_6_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ctrl_is_load = issue_slots_6_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ctrl_is_sta = issue_slots_6_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ctrl_is_std = issue_slots_6_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_iw_state = issue_slots_6_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_iw_p1_poisoned = issue_slots_6_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_iw_p2_poisoned = issue_slots_6_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_br = issue_slots_6_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_jalr = issue_slots_6_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_jal = issue_slots_6_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_sfb = issue_slots_6_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_5_in_uop_bits_br_mask = issue_slots_6_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_br_tag = issue_slots_6_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_in_uop_bits_ftq_idx = issue_slots_6_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_edge_inst = issue_slots_6_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_pc_lob = issue_slots_6_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_taken = issue_slots_6_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_5_in_uop_bits_imm_packed = issue_slots_6_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_5_in_uop_bits_csr_addr = issue_slots_6_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_in_uop_bits_rob_idx = issue_slots_6_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_ldq_idx = issue_slots_6_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_stq_idx = issue_slots_6_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_rxq_idx = issue_slots_6_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_pdst = issue_slots_6_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_prs1 = issue_slots_6_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_prs2 = issue_slots_6_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_prs3 = issue_slots_6_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_in_uop_bits_ppred = issue_slots_6_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_prs1_busy = issue_slots_6_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_prs2_busy = issue_slots_6_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_prs3_busy = issue_slots_6_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ppred_busy = issue_slots_6_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_stale_pdst = issue_slots_6_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_exception = issue_slots_6_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_5_in_uop_bits_exc_cause = issue_slots_6_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_bypassable = issue_slots_6_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_in_uop_bits_mem_cmd = issue_slots_6_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_mem_size = issue_slots_6_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_mem_signed = issue_slots_6_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_fence = issue_slots_6_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_fencei = issue_slots_6_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_amo = issue_slots_6_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_uses_ldq = issue_slots_6_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_uses_stq = issue_slots_6_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_sys_pc2epc = issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_unique = issue_slots_6_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_flush_on_commit = issue_slots_6_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ldst_is_rs1 = issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_ldst = issue_slots_6_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_lrs1 = issue_slots_6_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_lrs2 = issue_slots_6_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_lrs3 = issue_slots_6_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ldst_val = issue_slots_6_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_dst_rtype = issue_slots_6_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_lrs1_rtype = issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_lrs2_rtype = issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_frs3_en = issue_slots_6_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_fp_val = issue_slots_6_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_fp_single = issue_slots_6_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_xcpt_pf_if = issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_xcpt_ae_if = issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_xcpt_ma_if = issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_bp_debug_if = issue_slots_6_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_bp_xcpt_if = issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_debug_fsrc = issue_slots_6_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_debug_tsrc = issue_slots_6_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire [6:0] issue_slots_6_in_uop_bits_uopc = issue_slots_7_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_in_uop_bits_inst = issue_slots_7_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_in_uop_bits_debug_inst = issue_slots_7_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_rvc = issue_slots_7_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_6_in_uop_bits_debug_pc = issue_slots_7_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_iq_type = issue_slots_7_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_6_in_uop_bits_fu_code = issue_slots_7_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_in_uop_bits_ctrl_br_type = issue_slots_7_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_ctrl_op1_sel = issue_slots_7_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_ctrl_op2_sel = issue_slots_7_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_ctrl_imm_sel = issue_slots_7_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_in_uop_bits_ctrl_op_fcn = issue_slots_7_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ctrl_fcn_dw = issue_slots_7_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_ctrl_csr_cmd = issue_slots_7_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ctrl_is_load = issue_slots_7_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ctrl_is_sta = issue_slots_7_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ctrl_is_std = issue_slots_7_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_iw_state = issue_slots_7_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_iw_p1_poisoned = issue_slots_7_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_iw_p2_poisoned = issue_slots_7_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_br = issue_slots_7_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_jalr = issue_slots_7_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_jal = issue_slots_7_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_sfb = issue_slots_7_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_6_in_uop_bits_br_mask = issue_slots_7_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_br_tag = issue_slots_7_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_in_uop_bits_ftq_idx = issue_slots_7_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_edge_inst = issue_slots_7_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_pc_lob = issue_slots_7_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_taken = issue_slots_7_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_6_in_uop_bits_imm_packed = issue_slots_7_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_6_in_uop_bits_csr_addr = issue_slots_7_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_in_uop_bits_rob_idx = issue_slots_7_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_ldq_idx = issue_slots_7_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_stq_idx = issue_slots_7_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_rxq_idx = issue_slots_7_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_pdst = issue_slots_7_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_prs1 = issue_slots_7_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_prs2 = issue_slots_7_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_prs3 = issue_slots_7_out_uop_prs3; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_prs1_busy = issue_slots_7_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_prs2_busy = issue_slots_7_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_prs3_busy = issue_slots_7_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ppred_busy = issue_slots_7_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_stale_pdst = issue_slots_7_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_exception = issue_slots_7_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_6_in_uop_bits_exc_cause = issue_slots_7_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_bypassable = issue_slots_7_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_in_uop_bits_mem_cmd = issue_slots_7_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_mem_size = issue_slots_7_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_mem_signed = issue_slots_7_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_fence = issue_slots_7_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_fencei = issue_slots_7_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_amo = issue_slots_7_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_uses_ldq = issue_slots_7_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_uses_stq = issue_slots_7_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_sys_pc2epc = issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_unique = issue_slots_7_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_flush_on_commit = issue_slots_7_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ldst_is_rs1 = issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_ldst = issue_slots_7_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_lrs1 = issue_slots_7_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_lrs2 = issue_slots_7_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_lrs3 = issue_slots_7_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ldst_val = issue_slots_7_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_dst_rtype = issue_slots_7_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_lrs1_rtype = issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_lrs2_rtype = issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_frs3_en = issue_slots_7_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_fp_val = issue_slots_7_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_fp_single = issue_slots_7_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_xcpt_pf_if = issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_xcpt_ae_if = issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_xcpt_ma_if = issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_bp_debug_if = issue_slots_7_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_bp_xcpt_if = issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_debug_fsrc = issue_slots_7_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_debug_tsrc = issue_slots_7_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_0_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_0_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_0_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_0_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_0_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_0_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_0_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_0_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_0_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_0_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_0_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_0_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_0_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_0_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_0_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_0_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_0_valid; // @[issue-unit.scala:154:28] wire issue_slots_0_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_0_request; // @[issue-unit.scala:154:28] wire issue_slots_0_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_0_grant; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_1_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_1_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_1_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_1_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_1_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_1_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_1_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_1_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_1_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_1_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_1_valid; // @[issue-unit.scala:154:28] wire issue_slots_1_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_1_request; // @[issue-unit.scala:154:28] wire issue_slots_1_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_1_grant; // @[issue-unit.scala:154:28] wire issue_slots_1_clear; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_2_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_2_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_2_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_2_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_2_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_2_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_2_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_2_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_2_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_2_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_2_valid; // @[issue-unit.scala:154:28] wire issue_slots_2_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_2_request; // @[issue-unit.scala:154:28] wire issue_slots_2_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_2_grant; // @[issue-unit.scala:154:28] wire issue_slots_2_clear; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_3_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_3_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_3_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_3_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_3_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_3_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_3_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_3_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_3_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_3_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_3_valid; // @[issue-unit.scala:154:28] wire issue_slots_3_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_3_request; // @[issue-unit.scala:154:28] wire issue_slots_3_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_3_grant; // @[issue-unit.scala:154:28] wire issue_slots_3_clear; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_4_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_4_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_4_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_4_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_4_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_4_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_4_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_4_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_4_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_4_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_4_valid; // @[issue-unit.scala:154:28] wire issue_slots_4_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_4_request; // @[issue-unit.scala:154:28] wire issue_slots_4_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_4_grant; // @[issue-unit.scala:154:28] wire issue_slots_4_clear; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_5_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_5_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_5_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_5_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_5_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_5_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_5_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_5_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_5_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_5_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_5_valid; // @[issue-unit.scala:154:28] wire issue_slots_5_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_5_request; // @[issue-unit.scala:154:28] wire issue_slots_5_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_5_grant; // @[issue-unit.scala:154:28] wire issue_slots_5_clear; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_6_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_6_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_6_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_6_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_6_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_6_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_6_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_6_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_6_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_6_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_6_valid; // @[issue-unit.scala:154:28] wire issue_slots_6_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_6_request; // @[issue-unit.scala:154:28] wire issue_slots_6_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_6_grant; // @[issue-unit.scala:154:28] wire issue_slots_6_clear; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_7_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_7_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_7_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_7_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_7_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_prs3; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_prs2_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_7_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_7_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_7_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_7_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_7_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_7_valid; // @[issue-unit.scala:154:28] wire issue_slots_7_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_7_request; // @[issue-unit.scala:154:28] wire issue_slots_7_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_7_grant; // @[issue-unit.scala:154:28] wire issue_slots_7_clear; // @[issue-unit.scala:154:28] wire _io_event_empty_T = issue_slots_0_valid | issue_slots_1_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_1 = _io_event_empty_T | issue_slots_2_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_2 = _io_event_empty_T_1 | issue_slots_3_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_3 = _io_event_empty_T_2 | issue_slots_4_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_4 = _io_event_empty_T_3 | issue_slots_5_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_5 = _io_event_empty_T_4 | issue_slots_6_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_6 = _io_event_empty_T_5 | issue_slots_7_valid; // @[issue-unit.scala:154:28, :165:61] assign _io_event_empty_T_7 = ~_io_event_empty_T_6; // @[issue-unit.scala:165:{21,61}] assign io_event_empty = _io_event_empty_T_7; // @[issue-unit.scala:165:21] wire [1:0] _count_T = {1'h0, _slots_0_io_valid} + {1'h0, _slots_1_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_1 = _count_T; // @[issue-unit.scala:167:23] wire [1:0] _count_T_2 = {1'h0, _slots_2_io_valid} + {1'h0, _slots_3_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_3 = _count_T_2; // @[issue-unit.scala:167:23] wire [2:0] _count_T_4 = {1'h0, _count_T_1} + {1'h0, _count_T_3}; // @[issue-unit.scala:167:23] wire [2:0] _count_T_5 = _count_T_4; // @[issue-unit.scala:167:23] wire [1:0] _count_T_6 = {1'h0, _slots_4_io_valid} + {1'h0, _slots_5_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_7 = _count_T_6; // @[issue-unit.scala:167:23] wire [1:0] _count_T_8 = {1'h0, _slots_6_io_valid} + {1'h0, _slots_7_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_9 = _count_T_8; // @[issue-unit.scala:167:23] wire [2:0] _count_T_10 = {1'h0, _count_T_7} + {1'h0, _count_T_9}; // @[issue-unit.scala:167:23] wire [2:0] _count_T_11 = _count_T_10; // @[issue-unit.scala:167:23] wire [3:0] _count_T_12 = {1'h0, _count_T_5} + {1'h0, _count_T_11}; // @[issue-unit.scala:167:23] wire [3:0] count = _count_T_12; // @[issue-unit.scala:167:23]
Generate the Verilog code corresponding to the following Chisel files. File SinkD.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ class SinkDResponse(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val last = Bool() val opcode = UInt(3.W) val param = UInt(3.W) val source = UInt(params.outer.bundle.sourceBits.W) val sink = UInt(params.outer.bundle.sinkBits.W) val denied = Bool() } class SinkD(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val resp = Valid(new SinkDResponse(params)) // Grant or ReleaseAck val d = Flipped(Decoupled(new TLBundleD(params.outer.bundle))) // Lookup the set+way from MSHRs val source = UInt(params.outer.bundle.sourceBits.W) val way = Flipped(UInt(params.wayBits.W)) val set = Flipped(UInt(params.setBits.W)) // Banked Store port val bs_adr = Decoupled(new BankedStoreOuterAddress(params)) val bs_dat = new BankedStoreOuterPoison(params) // WaR hazard val grant_req = new SourceDHazard(params) val grant_safe = Flipped(Bool()) }) // No restrictions on buffer val d = params.micro.outerBuf.d(io.d) val (first, last, _, beat) = params.outer.count(d) val hasData = params.outer.hasData(d.bits) io.source := Mux(d.valid, d.bits.source, RegEnable(d.bits.source, d.valid)) io.grant_req.way := io.way io.grant_req.set := io.set // Also send Grant(NoData) to BS to ensure correct data ordering io.resp.valid := (first || last) && d.fire d.ready := io.bs_adr.ready && (!first || io.grant_safe) io.bs_adr.valid := !first || (d.valid && io.grant_safe) params.ccover(d.valid && first && !io.grant_safe, "SINKD_HAZARD", "Prevented Grant data hazard with backpressure") params.ccover(io.bs_adr.valid && !io.bs_adr.ready, "SINKD_SRAM_STALL", "Data SRAM busy") io.resp.bits.last := last io.resp.bits.opcode := d.bits.opcode io.resp.bits.param := d.bits.param io.resp.bits.source := d.bits.source io.resp.bits.sink := d.bits.sink io.resp.bits.denied := d.bits.denied io.bs_adr.bits.noop := !d.valid || !hasData io.bs_adr.bits.way := io.way io.bs_adr.bits.set := io.set io.bs_adr.bits.beat := Mux(d.valid, beat, RegEnable(beat + io.bs_adr.ready.asUInt, d.valid)) io.bs_adr.bits.mask := ~0.U(params.outerMaskBits.W) io.bs_dat.data := d.bits.data assert (!(d.valid && d.bits.corrupt && !d.bits.denied), "Data poisoning unsupported") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module SinkD( // @[SinkD.scala:34:7] input clock, // @[SinkD.scala:34:7] input reset, // @[SinkD.scala:34:7] output io_resp_valid, // @[SinkD.scala:36:14] output io_resp_bits_last, // @[SinkD.scala:36:14] output [2:0] io_resp_bits_opcode, // @[SinkD.scala:36:14] output [2:0] io_resp_bits_param, // @[SinkD.scala:36:14] output [3:0] io_resp_bits_source, // @[SinkD.scala:36:14] output [2:0] io_resp_bits_sink, // @[SinkD.scala:36:14] output io_resp_bits_denied, // @[SinkD.scala:36:14] output io_d_ready, // @[SinkD.scala:36:14] input io_d_valid, // @[SinkD.scala:36:14] input [2:0] io_d_bits_opcode, // @[SinkD.scala:36:14] input [1:0] io_d_bits_param, // @[SinkD.scala:36:14] input [2:0] io_d_bits_size, // @[SinkD.scala:36:14] input [3:0] io_d_bits_source, // @[SinkD.scala:36:14] input [2:0] io_d_bits_sink, // @[SinkD.scala:36:14] input io_d_bits_denied, // @[SinkD.scala:36:14] input [63:0] io_d_bits_data, // @[SinkD.scala:36:14] input io_d_bits_corrupt, // @[SinkD.scala:36:14] output [3:0] io_source, // @[SinkD.scala:36:14] input [2:0] io_way, // @[SinkD.scala:36:14] input [9:0] io_set, // @[SinkD.scala:36:14] input io_bs_adr_ready, // @[SinkD.scala:36:14] output io_bs_adr_valid, // @[SinkD.scala:36:14] output io_bs_adr_bits_noop, // @[SinkD.scala:36:14] output [2:0] io_bs_adr_bits_way, // @[SinkD.scala:36:14] output [9:0] io_bs_adr_bits_set, // @[SinkD.scala:36:14] output [2:0] io_bs_adr_bits_beat, // @[SinkD.scala:36:14] output [63:0] io_bs_dat_data, // @[SinkD.scala:36:14] output [9:0] io_grant_req_set, // @[SinkD.scala:36:14] output [2:0] io_grant_req_way, // @[SinkD.scala:36:14] input io_grant_safe // @[SinkD.scala:36:14] ); wire d_q_io_deq_ready; // @[SinkD.scala:63:30] wire _d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [3:0] _d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _io_resp_valid_T_1 = d_q_io_deq_ready & _d_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21] wire [12:0] _r_beats1_decode_T = 13'h3F << _d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [2:0] r_beats1 = _d_q_io_deq_bits_opcode[0] ? ~(_r_beats1_decode_T[5:3]) : 3'h0; // @[Decoupled.scala:362:21] reg [2:0] r_counter; // @[Edges.scala:229:27] wire [2:0] _r_counter1_T = r_counter - 3'h1; // @[Edges.scala:229:27, :230:28] wire last = r_counter == 3'h1 | r_beats1 == 3'h0; // @[Edges.scala:221:14, :229:27, :232:{25,33,43}] wire [2:0] beat = r_beats1 & ~_r_counter1_T; // @[Edges.scala:221:14, :230:28, :234:{25,27}] reg [3:0] io_source_r; // @[SinkD.scala:57:53] assign d_q_io_deq_ready = io_bs_adr_ready & ((|r_counter) | io_grant_safe); // @[Edges.scala:229:27, :231:25] reg [2:0] io_bs_adr_bits_beat_r; // @[SinkD.scala:78:54]
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module RecFNToRecFN_229( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_20( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34] wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34] wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_7 = _source_ok_T_6 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_13 = _source_ok_T_12 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_19 = &_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_25 = _source_ok_T_24 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_25 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_27 = _source_ok_T_26 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_0 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_33 = _source_ok_T_32 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = _source_ok_T_38 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_45 = &_source_ok_T_44; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_51 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _T_1602 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1602; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1602; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1675; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1675; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1675; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [15:0] inflight; // @[Monitor.scala:614:27] reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [127:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] a_set; // @[Monitor.scala:626:34] wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [127:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1528 = _T_1602 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1528 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1528 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1528 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1528 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1528 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [15:0] d_clr; // @[Monitor.scala:664:34] wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1574 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1574 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1543 = _T_1675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1543 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1543 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1543 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [15:0] inflight_1; // @[Monitor.scala:726:35] wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [15:0] d_clr_1; // @[Monitor.scala:774:34] wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1646 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1646 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35] wire _T_1628 = _T_1675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1628 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1628 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1628 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid || io.clear || io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 || rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_||_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_||_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_||_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready || agen_ready || dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }
module IssueSlot_89( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_37( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_732; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_732; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_805; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_805; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_805; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_658 = _T_732 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_658 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_704 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_673 = _T_805 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_673 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_776 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_758 = _T_805 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_758 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid || io.clear || io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 || rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_||_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_||_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_||_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready || agen_ready || dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }
module IssueSlot_49( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [1:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7] wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_14( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_a_bits_mask = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sizeOH = 1'h1; // @[Misc.scala:202:81] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] c_first_beats1_decode = 12'h0; // @[Edges.scala:220:59] wire [11:0] c_first_beats1 = 12'h0; // @[Edges.scala:221:14] wire [11:0] _c_first_count_T = 12'h0; // @[Edges.scala:234:27] wire [11:0] c_first_count = 12'h0; // @[Edges.scala:234:25] wire [11:0] _c_first_counter_T = 12'h0; // @[Edges.scala:236:21] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] c_first_counter1 = 12'hFFF; // @[Edges.scala:230:28] wire [12:0] _c_first_counter1_T = 13'h1FFF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [7:0] _c_set_wo_ready_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [11:0] a_first_beats1_decode = _a_first_beats1_decode_T_2; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [11:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 12'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [11:0] a_first_counter; // @[Edges.scala:229:27] wire [12:0] _a_first_counter1_T = {1'h0, a_first_counter} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] a_first_counter1 = _a_first_counter1_T[11:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 12'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 12'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [11:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [11:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [11:0] d_first_beats1_decode = _d_first_beats1_decode_T_2; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [11:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [11:0] d_first_counter; // @[Edges.scala:229:27] wire [12:0] _d_first_counter1_T = {1'h0, d_first_counter} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] d_first_counter1 = _d_first_counter1_T[11:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 12'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 12'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [11:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [11:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [11:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [11:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 12'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [11:0] a_first_counter_1; // @[Edges.scala:229:27] wire [12:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] a_first_counter1_1 = _a_first_counter1_T_1[11:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 12'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 12'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [11:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [11:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [11:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5; // @[package.scala:243:46] wire [11:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [11:0] d_first_counter_1; // @[Edges.scala:229:27] wire [12:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] d_first_counter1_1 = _d_first_counter1_T_1[11:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 12'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 12'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [11:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [11:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1194 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [11:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8; // @[package.scala:243:46] wire [11:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [11:0] d_first_counter_2; // @[Edges.scala:229:27] wire [12:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] d_first_counter1_2 = _d_first_counter1_T_2[11:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 12'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 12'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 12'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [11:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [11:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. */ object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct */ cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) /* Filter out any cases identical to the default */ val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2*simple.size) { /* The dense encoding case uses a Vec */ val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { /* The sparse encoding case uses switch */ val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Control.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ class InclusiveCacheControl(outer: InclusiveCache, control: InclusiveCacheControlParameters)(implicit p: Parameters) extends LazyModule()(p) { val ctrlnode = TLRegisterNode( address = Seq(AddressSet(control.address, InclusiveCacheParameters.L2ControlSize-1)), device = outer.device, concurrency = 1, // Only one flush at a time (else need to track who answers) beatBytes = control.beatBytes) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val flush_match = Input(Bool()) val flush_req = Decoupled(UInt(64.W)) val flush_resp = Input(Bool()) }) // Flush directive val flushInValid = RegInit(false.B) val flushInAddress = Reg(UInt(64.W)) val flushOutValid = RegInit(false.B) val flushOutReady = WireInit(init = false.B) when (flushOutReady) { flushOutValid := false.B } when (io.flush_resp) { flushOutValid := true.B } when (io.flush_req.ready) { flushInValid := false.B } io.flush_req.valid := flushInValid io.flush_req.bits := flushInAddress when (!io.flush_match && flushInValid) { flushInValid := false.B flushOutValid := true.B } val flush32 = RegField.w(32, RegWriteFn((ivalid, oready, data) => { when (oready) { flushOutReady := true.B } when (ivalid) { flushInValid := true.B } when (ivalid && !flushInValid) { flushInAddress := data << 4 } (!flushInValid, flushOutValid) }), RegFieldDesc("Flush32", "Flush the physical address equal to the 32-bit written data << 4 from the cache")) val flush64 = RegField.w(64, RegWriteFn((ivalid, oready, data) => { when (oready) { flushOutReady := true.B } when (ivalid) { flushInValid := true.B } when (ivalid && !flushInValid) { flushInAddress := data } (!flushInValid, flushOutValid) }), RegFieldDesc("Flush64", "Flush the phsyical address equal to the 64-bit written data from the cache")) // Information about the cache configuration val banksR = RegField.r(8, outer.node.edges.in.size.U, RegFieldDesc("Banks", "Number of banks in the cache", reset=Some(outer.node.edges.in.size))) val waysR = RegField.r(8, outer.cache.ways.U, RegFieldDesc("Ways", "Number of ways per bank", reset=Some(outer.cache.ways))) val lgSetsR = RegField.r(8, log2Ceil(outer.cache.sets).U, RegFieldDesc("lgSets", "Base-2 logarithm of the sets per bank", reset=Some(log2Ceil(outer.cache.sets)))) val lgBlockBytesR = RegField.r(8, log2Ceil(outer.cache.blockBytes).U, RegFieldDesc("lgBlockBytes", "Base-2 logarithm of the bytes per cache block", reset=Some(log2Ceil(outer.cache.blockBytes)))) val regmap = ctrlnode.regmap( 0x000 -> RegFieldGroup("Config", Some("Information about the Cache Configuration"), Seq(banksR, waysR, lgSetsR, lgBlockBytesR)), 0x200 -> (if (control.beatBytes >= 8) Seq(flush64) else Nil), 0x240 -> Seq(flush32) ) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module InclusiveCacheControl( // @[Control.scala:38:9] input clock, // @[Control.scala:38:9] input reset, // @[Control.scala:38:9] output auto_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_flush_match, // @[Control.scala:39:16] input io_flush_req_ready, // @[Control.scala:39:16] output io_flush_req_valid, // @[Control.scala:39:16] output [63:0] io_flush_req_bits, // @[Control.scala:39:16] input io_flush_resp // @[Control.scala:39:16] ); wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire auto_ctrl_in_a_valid_0 = auto_ctrl_in_a_valid; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_a_bits_opcode_0 = auto_ctrl_in_a_bits_opcode; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_a_bits_param_0 = auto_ctrl_in_a_bits_param; // @[Control.scala:38:9] wire [1:0] auto_ctrl_in_a_bits_size_0 = auto_ctrl_in_a_bits_size; // @[Control.scala:38:9] wire [10:0] auto_ctrl_in_a_bits_source_0 = auto_ctrl_in_a_bits_source; // @[Control.scala:38:9] wire [25:0] auto_ctrl_in_a_bits_address_0 = auto_ctrl_in_a_bits_address; // @[Control.scala:38:9] wire [7:0] auto_ctrl_in_a_bits_mask_0 = auto_ctrl_in_a_bits_mask; // @[Control.scala:38:9] wire [63:0] auto_ctrl_in_a_bits_data_0 = auto_ctrl_in_a_bits_data; // @[Control.scala:38:9] wire auto_ctrl_in_a_bits_corrupt_0 = auto_ctrl_in_a_bits_corrupt; // @[Control.scala:38:9] wire auto_ctrl_in_d_ready_0 = auto_ctrl_in_d_ready; // @[Control.scala:38:9] wire io_flush_match_0 = io_flush_match; // @[Control.scala:38:9] wire io_flush_req_ready_0 = io_flush_req_ready; // @[Control.scala:38:9] wire io_flush_resp_0 = io_flush_resp; // @[Control.scala:38:9] wire [3:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h60B1008}; wire [8:0] out_maskMatch = 9'h1B7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_13 = 8'h8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_14 = 8'h8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = 8'h8; // @[RegisterRouter.scala:87:24] wire [12:0] out_prepend = 13'h1008; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_22 = 16'h1008; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_23 = 16'h1008; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = 16'h1008; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_1 = 20'hB1008; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_31 = 24'hB1008; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_32 = 24'hB1008; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = 24'hB1008; // @[RegisterRouter.scala:87:24] wire [26:0] out_prepend_2 = 27'h60B1008; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_40 = 32'h60B1008; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_41 = 32'h60B1008; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_66 = 32'h0; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_67 = 32'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = 64'h60B1008; // @[MuxLiteral.scala:49:48] wire [2:0] ctrlnodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_T_53 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_54 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_2 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] ctrlnodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_ctrl_in_d_bits_sink = 1'h0; // @[Control.scala:38:9] wire auto_ctrl_in_d_bits_denied = 1'h0; // @[Control.scala:38:9] wire auto_ctrl_in_d_bits_corrupt = 1'h0; // @[Control.scala:38:9] wire ctrlnodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire ctrlnodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire ctrlnodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire ctrlnodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_ctrl_in_d_bits_param = 2'h0; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] ctrlnodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_a_ready; // @[MixedNode.scala:551:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire ctrlnodeIn_a_valid = auto_ctrl_in_a_valid_0; // @[Control.scala:38:9] wire [2:0] ctrlnodeIn_a_bits_opcode = auto_ctrl_in_a_bits_opcode_0; // @[Control.scala:38:9] wire [2:0] ctrlnodeIn_a_bits_param = auto_ctrl_in_a_bits_param_0; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_a_bits_size = auto_ctrl_in_a_bits_size_0; // @[Control.scala:38:9] wire [10:0] ctrlnodeIn_a_bits_source = auto_ctrl_in_a_bits_source_0; // @[Control.scala:38:9] wire [25:0] ctrlnodeIn_a_bits_address = auto_ctrl_in_a_bits_address_0; // @[Control.scala:38:9] wire [7:0] ctrlnodeIn_a_bits_mask = auto_ctrl_in_a_bits_mask_0; // @[Control.scala:38:9] wire [63:0] ctrlnodeIn_a_bits_data = auto_ctrl_in_a_bits_data_0; // @[Control.scala:38:9] wire ctrlnodeIn_a_bits_corrupt = auto_ctrl_in_a_bits_corrupt_0; // @[Control.scala:38:9] wire ctrlnodeIn_d_ready = auto_ctrl_in_d_ready_0; // @[Control.scala:38:9] wire ctrlnodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] ctrlnodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] ctrlnodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] ctrlnodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] ctrlnodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_ctrl_in_a_ready_0; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9] wire [1:0] auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9] wire [10:0] auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9] wire [63:0] auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9] wire auto_ctrl_in_d_valid_0; // @[Control.scala:38:9] wire io_flush_req_valid_0; // @[Control.scala:38:9] wire [63:0] io_flush_req_bits_0; // @[Control.scala:38:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_ctrl_in_a_ready_0 = ctrlnodeIn_a_ready; // @[Control.scala:38:9] wire in_valid = ctrlnodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = ctrlnodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = ctrlnodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = ctrlnodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = ctrlnodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = ctrlnodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_valid_0 = ctrlnodeIn_d_valid; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_opcode_0 = ctrlnodeIn_d_bits_opcode; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_size_0 = ctrlnodeIn_d_bits_size; // @[Control.scala:38:9] wire [10:0] ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_source_0 = ctrlnodeIn_d_bits_source; // @[Control.scala:38:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_bits_data_0 = ctrlnodeIn_d_bits_data; // @[Control.scala:38:9] reg flushInValid; // @[Control.scala:45:33] assign io_flush_req_valid_0 = flushInValid; // @[Control.scala:38:9, :45:33] reg [63:0] flushInAddress; // @[Control.scala:46:29] assign io_flush_req_bits_0 = flushInAddress; // @[Control.scala:38:9, :46:29] reg flushOutValid; // @[Control.scala:47:33] wire flushOutReady; // @[Control.scala:48:34] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = ctrlnodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = ctrlnodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _ctrlnodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign ctrlnodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_front_valid_T; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_42 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = _out_back_front_q_io_deq_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_rimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_wimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_romask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_womask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6 = _out_back_front_q_io_deq_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_T_9 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_16 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_17 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_15 = _out_back_front_q_io_deq_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_25 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_26 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_24 = _out_back_front_q_io_deq_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire _out_T_27 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_34 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_35 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_33 = _out_back_front_q_io_deq_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire _out_T_36 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_37 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~flushInValid; // @[Control.scala:45:33, :71:23] wire _out_T_44 = out_f_wivalid_4 & _out_T_43; // @[RegisterRouter.scala:87:24] wire out_f_wiready = ~flushInValid; // @[Control.scala:45:33, :71:23, :72:8] wire _out_T_45 = out_f_wivalid_4 & out_f_wiready; // @[RegisterRouter.scala:87:24] wire _out_T_46 = flushOutValid & out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_wiready | _out_T_48; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = _out_T_49; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = flushOutValid | _out_T_51; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = _out_T_52; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_55 = out_front_bits_data[31:0]; // @[RegisterRouter.scala:87:24] assign flushOutReady = out_f_woready_5 | out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~flushInValid; // @[Control.scala:45:33, :64:23, :71:23] wire _out_T_57 = out_f_wivalid_5 & _out_T_56; // @[RegisterRouter.scala:87:24] wire [35:0] _out_flushInAddress_T = {_out_T_55, 4'h0}; // @[RegisterRouter.scala:87:24] wire out_f_wiready_1 = ~flushInValid; // @[Control.scala:45:33, :65:8, :71:23] wire _out_T_58 = out_f_wivalid_5 & out_f_wiready_1; // @[RegisterRouter.scala:87:24] wire _out_T_59 = flushOutValid & out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wiready_1 | _out_T_61; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = _out_T_62; // @[RegisterRouter.scala:87:24] wire _out_T_63 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = flushOutValid | _out_T_64; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = _out_T_65; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_6, _out_iindex_T_3}; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = _out_back_front_q_io_deq_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = _out_back_front_q_io_deq_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = _out_back_front_q_io_deq_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = _out_back_front_q_io_deq_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = _out_back_front_q_io_deq_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = _out_back_front_q_io_deq_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = _out_back_front_q_io_deq_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = _out_back_front_q_io_deq_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = _out_back_front_q_io_deq_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_6, _out_oindex_T_3}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7 = _out_rifireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8 = _out_wifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire out_wifireMux_all = _out_wifireMux_T_12 & _out_T_49; // @[ReduceOthers.scala:47:21] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = out_wifireMux_out_2 | _out_wifireMux_T_13; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_2 = _out_wifireMux_T_14; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wifireMux_all_1 = _out_wifireMux_T_16 & _out_T_62; // @[ReduceOthers.scala:47:21] wire _out_wifireMux_T_17 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = out_wifireMux_out_3 | _out_wifireMux_T_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_3 = _out_wifireMux_T_18; // @[MuxLiteral.scala:49:48] wire [3:0] _GEN_3 = {{_out_wifireMux_WIRE_3}, {_out_wifireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}] wire out_wifireMux = _GEN_3[out_iindex]; // @[MuxLiteral.scala:49:10] wire _GEN_4 = _out_back_front_q_io_deq_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7 = _out_rofireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~_out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8 = _out_wofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all = _out_wofireMux_T_12 & _out_T_52; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = out_wofireMux_out_2 | _out_wofireMux_T_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_2 = _out_wofireMux_T_14; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all_1 = _out_wofireMux_T_16 & _out_T_65; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_17 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = out_wofireMux_out_3 | _out_wofireMux_T_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_3 = _out_wofireMux_T_18; // @[MuxLiteral.scala:49:48] wire [3:0] _GEN_5 = {{_out_wofireMux_WIRE_3}, {_out_wofireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}] wire out_wofireMux = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] wire out_iready = out_front_bits_read | out_wifireMux; // @[MuxLiteral.scala:49:10] wire out_oready = _out_back_front_q_io_deq_bits_read | out_wofireMux; // @[MuxLiteral.scala:49:10] assign _out_in_ready_T = out_front_ready & out_iready; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign _out_front_valid_T = in_valid & out_iready; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] wire _out_front_q_io_deq_ready_T = out_ready & out_oready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = _out_back_front_q_io_deq_valid & out_oready; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_6 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {1'h1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_6[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_T_3 = _GEN[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_size = ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign ctrlnodeIn_d_bits_source = ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign ctrlnodeIn_d_bits_opcode = {2'h0, _ctrlnodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] wire _T_1 = ~io_flush_match_0 & flushInValid; // @[Control.scala:38:9, :45:33, :56:{11,27}] always @(posedge clock) begin // @[Control.scala:38:9] if (reset) begin // @[Control.scala:38:9] flushInValid <= 1'h0; // @[Control.scala:45:33] flushOutValid <= 1'h0; // @[Control.scala:47:33] end else begin // @[Control.scala:38:9] flushInValid <= out_f_wivalid_5 | out_f_wivalid_4 | ~(_T_1 | io_flush_req_ready_0) & flushInValid; // @[RegisterRouter.scala:87:24] flushOutValid <= _T_1 | io_flush_resp_0 | ~flushOutReady & flushOutValid; // @[Control.scala:38:9, :47:33, :48:34, :50:{26,42}, :51:{26,42}, :56:{27,44}, :58:21] end if (_out_T_57) // @[Control.scala:64:20] flushInAddress <= {28'h0, _out_flushInAddress_T}; // @[Control.scala:46:29, :64:{55,63}] else if (_out_T_44) // @[Control.scala:71:20] flushInAddress <= _out_T_42; // @[RegisterRouter.scala:87:24] always @(posedge) TLMonitor_49 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (ctrlnodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (ctrlnodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (ctrlnodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (ctrlnodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (ctrlnodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (ctrlnodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (ctrlnodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (ctrlnodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (ctrlnodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (ctrlnodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (ctrlnodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (ctrlnodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (ctrlnodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (ctrlnodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (ctrlnodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (ctrlnodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_RegMapperInput_i9_m8 out_back_front_q ( // @[RegisterRouter.scala:87:24] .clock (clock), .reset (reset), .io_enq_ready (out_front_ready), .io_enq_valid (out_front_valid), // @[RegisterRouter.scala:87:24] .io_enq_bits_read (out_front_bits_read), // @[RegisterRouter.scala:87:24] .io_enq_bits_index (out_front_bits_index), // @[RegisterRouter.scala:87:24] .io_enq_bits_data (out_front_bits_data), // @[RegisterRouter.scala:87:24] .io_enq_bits_mask (out_front_bits_mask), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_source (out_front_bits_extra_tlrr_extra_source), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_size (out_front_bits_extra_tlrr_extra_size), // @[RegisterRouter.scala:87:24] .io_deq_ready (_out_front_q_io_deq_ready_T), // @[RegisterRouter.scala:87:24] .io_deq_valid (_out_back_front_q_io_deq_valid), .io_deq_bits_read (_out_back_front_q_io_deq_bits_read), .io_deq_bits_index (_out_back_front_q_io_deq_bits_index), .io_deq_bits_data (_out_back_front_q_io_deq_bits_data), .io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask), .io_deq_bits_extra_tlrr_extra_source (out_bits_extra_tlrr_extra_source), .io_deq_bits_extra_tlrr_extra_size (out_bits_extra_tlrr_extra_size) ); // @[RegisterRouter.scala:87:24] assign out_bits_read = _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_a_ready = auto_ctrl_in_a_ready_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_valid = auto_ctrl_in_d_valid_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_opcode = auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_size = auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_source = auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_data = auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9] assign io_flush_req_valid = io_flush_req_valid_0; // @[Control.scala:38:9] assign io_flush_req_bits = io_flush_req_bits_0; // @[Control.scala:38:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File OutputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class OutputCreditAlloc extends Bundle { val alloc = Bool() val tail = Bool() } class OutputChannelStatus(implicit val p: Parameters) extends Bundle with HasNoCParams { val occupied = Bool() def available = !occupied val flow = new FlowRoutingBundle } class OutputChannelAlloc(implicit val p: Parameters) extends Bundle with HasNoCParams { val alloc = Bool() val flow = new FlowRoutingBundle } class AbstractOutputUnitIO( val inParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val cParam: BaseChannelParams )(implicit val p: Parameters) extends Bundle with HasRouterInputParams { val nodeId = cParam.srcId val nVirtualChannels = cParam.nVirtualChannels val in = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val credit_available = Output(Vec(nVirtualChannels, Bool())) val channel_status = Output(Vec(nVirtualChannels, new OutputChannelStatus)) val allocs = Input(Vec(nVirtualChannels, new OutputChannelAlloc)) val credit_alloc = Input(Vec(nVirtualChannels, new OutputCreditAlloc)) } abstract class AbstractOutputUnit( val inParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val cParam: BaseChannelParams )(implicit val p: Parameters) extends Module with HasRouterInputParams with HasNoCParams { val nodeId = cParam.srcId def io: AbstractOutputUnitIO } class OutputUnit(inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: ChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class OutputUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = new Channel(cParam.asInstanceOf[ChannelParams]) } val io = IO(new OutputUnitIO) class OutputState(val bufferSize: Int) extends Bundle { val occupied = Bool() val c = UInt(log2Up(1+bufferSize).W) val flow = new FlowRoutingBundle } val states = Reg(MixedVec(cParam.virtualChannelParams.map { u => new OutputState(u.bufferSize) })) (states zip io.channel_status).map { case (s,a) => a.occupied := s.occupied a.flow := s.flow } io.out.flit := io.in states.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) { when (io.out.vc_free(i)) { assert(s.occupied) s.occupied := false.B } } } (states zip io.allocs).zipWithIndex.map { case ((s,a),i) => if (cParam.virtualChannelParams(i).traversable) { when (a.alloc) { s.occupied := true.B s.flow := a.flow } } } (io.credit_available zip states).zipWithIndex.map { case ((c,s),i) => c := s.c =/= 0.U //|| (io.out.credit_return.valid && io.out.credit_return.bits === i.U) } states.zipWithIndex.map { case (s,i) => val free = io.out.credit_return(i) val alloc = io.credit_alloc(i).alloc if (cParam.virtualChannelParams(i).traversable) { s.c := s.c +& free - alloc } } when (reset.asBool) { states.foreach(_.occupied := false.B) states.foreach(s => s.c := s.bufferSize.U) } }
module OutputUnit_20( // @[OutputUnit.scala:52:7] input clock, // @[OutputUnit.scala:52:7] input reset, // @[OutputUnit.scala:52:7] input io_in_0_valid, // @[OutputUnit.scala:58:14] input io_in_0_bits_head, // @[OutputUnit.scala:58:14] input io_in_0_bits_tail, // @[OutputUnit.scala:58:14] input [36:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14] input io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] input io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] input io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] output io_credit_available_0, // @[OutputUnit.scala:58:14] output io_credit_available_1, // @[OutputUnit.scala:58:14] output io_channel_status_0_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_1_occupied, // @[OutputUnit.scala:58:14] input io_allocs_0_alloc, // @[OutputUnit.scala:58:14] input io_allocs_1_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_0_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_1_alloc, // @[OutputUnit.scala:58:14] output io_out_flit_0_valid, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14] output [36:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] input [3:0] io_out_credit_return, // @[OutputUnit.scala:58:14] input [3:0] io_out_vc_free // @[OutputUnit.scala:58:14] ); reg states_1_occupied; // @[OutputUnit.scala:66:19] reg states_1_c; // @[OutputUnit.scala:66:19] reg states_0_occupied; // @[OutputUnit.scala:66:19] reg states_0_c; // @[OutputUnit.scala:66:19]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_69( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File EgressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = Decoupled(new EgressFlit(cParam.payloadBits)) } val io = IO(new EgressUnitIO) val channel_empty = RegInit(true.B) val flow = Reg(new FlowRoutingBundle) val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true)) q.io.enq.valid := io.in(0).valid q.io.enq.bits.head := io.in(0).bits.head q.io.enq.bits.tail := io.in(0).bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { q.io.enq.bits.ingress_id := 0.U(1.W) } else { q.io.enq.bits.ingress_id := Mux1H( flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node && f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)), flows.map(f => f.ingressId.U(ingressIdBits.W)) ) } q.io.enq.bits.payload := io.in(0).bits.payload io.out <> q.io.deq assert(!(q.io.enq.valid && !q.io.enq.ready)) io.credit_available(0) := q.io.count === 0.U io.channel_status(0).occupied := !channel_empty io.channel_status(0).flow := flow when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) { channel_empty := true.B if (coupleSAVA) io.channel_status(0).occupied := false.B } when (io.allocs(0).alloc) { channel_empty := false.B flow := io.allocs(0).flow } }
module EgressUnit_47( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [5:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 3'h4; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in || corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ || !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready || !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel | count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid || full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLWidthWidget1( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [63:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [7:0] _anonOut_a_bits_mask_T_5 = 8'hFF; // @[WidthWidget.scala:85:119] wire auto_anon_in_a_bits_mask = 1'h1; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_mask = 1'h1; // @[MixedNode.scala:551:17] wire anonOut_a_bits_mask_odata_0 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_1 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_2 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_3 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_4 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_5 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_6 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_7 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_mdata_7 = 1'h1; // @[WidthWidget.scala:68:88] wire _repeat_sel_sel_bypass_T = 1'h1; // @[WidthWidget.scala:200:53] wire [2:0] auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] anonOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire cated_bits_source = 1'h0; // @[WidthWidget.scala:161:25] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [7:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] wire _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire repeat_sel_sel_bypass = anonIn_a_valid; // @[WidthWidget.scala:200:33] assign anonOut_a_bits_opcode = anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_size = anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_address = anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] anonOut_a_bits_data_odata_0 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_1 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_2 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_3 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_4 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_5 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_6 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_7 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire cated_ready = anonIn_d_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_sink; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] wire cated_bits_denied; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_a_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [3:0] _anonOut_a_bits_mask_sizeOH_T = anonOut_a_bits_size; // @[Misc.scala:202:34] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] wire _hasData_opdata_T = anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire hasData = ~_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [17:0] _limit_T = 18'h7 << anonIn_a_bits_size; // @[package.scala:243:71] wire [2:0] _limit_T_1 = _limit_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire [2:0] limit = _limit_T_2; // @[package.scala:243:46] reg [2:0] count; // @[WidthWidget.scala:40:27] wire [2:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = count == 3'h0; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire [2:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = |_enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_3 = {count[2:1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = |_enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_6 = {count[2], count[1:0] ^ 2'h2}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_8 = |_enable_T_7; // @[WidthWidget.scala:43:{63,72}] wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_9 = {count[2], ~(count[1:0])}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_11 = |_enable_T_10; // @[WidthWidget.scala:43:{63,72}] wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_12 = count ^ 3'h4; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_13 = _enable_T_12 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_14 = |_enable_T_13; // @[WidthWidget.scala:43:{63,72}] wire enable_4 = ~_enable_T_14; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_15 = count ^ 3'h5; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_16 = _enable_T_15 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_17 = |_enable_T_16; // @[WidthWidget.scala:43:{63,72}] wire enable_5 = ~_enable_T_17; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_18 = count ^ 3'h6; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_19 = _enable_T_18 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_20 = |_enable_T_19; // @[WidthWidget.scala:43:{63,72}] wire enable_6 = ~_enable_T_20; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_21 = ~count; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_22 = _enable_T_21 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_23 = |_enable_T_22; // @[WidthWidget.scala:43:{63,72}] wire enable_7 = ~_enable_T_23; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonOut_a_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _T = anonIn_a_ready & anonIn_a_valid; // @[Decoupled.scala:51:35] wire _anonOut_a_bits_data_T; // @[Decoupled.scala:51:35] assign _anonOut_a_bits_data_T = _T; // @[Decoupled.scala:51:35] wire _anonOut_a_bits_mask_T_1; // @[Decoupled.scala:51:35] assign _anonOut_a_bits_mask_T_1 = _T; // @[Decoupled.scala:51:35] wire _repeat_sel_sel_T; // @[Decoupled.scala:51:35] assign _repeat_sel_sel_T = _T; // @[Decoupled.scala:51:35] wire [3:0] _count_T = {1'h0, count} + 4'h1; // @[WidthWidget.scala:40:27, :50:24] wire [2:0] _count_T_1 = _count_T[2:0]; // @[WidthWidget.scala:50:24] wire _anonIn_a_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonIn_a_ready_T_1 = anonOut_a_ready | _anonIn_a_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonIn_a_ready = _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonOut_a_valid_T = anonIn_a_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonOut_a_valid = _anonOut_a_valid_T; // @[WidthWidget.scala:77:29] reg anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonOut_a_bits_data_masked_enable_T = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_0 = enable_0 | _anonOut_a_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_1 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_1 = enable_1 | _anonOut_a_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_2 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_2 = enable_2 | _anonOut_a_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_3 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_3 = enable_3 | _anonOut_a_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_4 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_4 = enable_4 | _anonOut_a_bits_data_masked_enable_T_4; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_5 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_5 = enable_5 | _anonOut_a_bits_data_masked_enable_T_5; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_6 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_6 = enable_6 | _anonOut_a_bits_data_masked_enable_T_6; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_7 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_7 = enable_7 | _anonOut_a_bits_data_masked_enable_T_7; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [7:0] anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_1; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_2; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_3; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_4; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_5; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_6; // @[WidthWidget.scala:66:24] wire [7:0] anonOut_a_bits_data_mdata_0 = anonOut_a_bits_data_masked_enable_0 ? anonOut_a_bits_data_odata_0 : anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_1 = anonOut_a_bits_data_masked_enable_1 ? anonOut_a_bits_data_odata_1 : anonOut_a_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_2 = anonOut_a_bits_data_masked_enable_2 ? anonOut_a_bits_data_odata_2 : anonOut_a_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_3 = anonOut_a_bits_data_masked_enable_3 ? anonOut_a_bits_data_odata_3 : anonOut_a_bits_data_rdata_3; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_4 = anonOut_a_bits_data_masked_enable_4 ? anonOut_a_bits_data_odata_4 : anonOut_a_bits_data_rdata_4; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_5 = anonOut_a_bits_data_masked_enable_5 ? anonOut_a_bits_data_odata_5 : anonOut_a_bits_data_rdata_5; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_6 = anonOut_a_bits_data_masked_enable_6 ? anonOut_a_bits_data_odata_6 : anonOut_a_bits_data_rdata_6; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_7 = anonOut_a_bits_data_masked_enable_7 ? anonOut_a_bits_data_odata_7 : anonIn_a_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonOut_a_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonOut_a_bits_data_T_2 = _anonOut_a_bits_data_T & _anonOut_a_bits_data_T_1; // @[Decoupled.scala:51:35] wire [15:0] anonOut_a_bits_data_lo_lo = {anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [15:0] anonOut_a_bits_data_lo_hi = {anonOut_a_bits_data_mdata_3, anonOut_a_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] wire [31:0] anonOut_a_bits_data_lo = {anonOut_a_bits_data_lo_hi, anonOut_a_bits_data_lo_lo}; // @[WidthWidget.scala:73:12] wire [15:0] anonOut_a_bits_data_hi_lo = {anonOut_a_bits_data_mdata_5, anonOut_a_bits_data_mdata_4}; // @[WidthWidget.scala:68:88, :73:12] wire [15:0] anonOut_a_bits_data_hi_hi = {anonOut_a_bits_data_mdata_7, anonOut_a_bits_data_mdata_6}; // @[WidthWidget.scala:68:88, :73:12] wire [31:0] anonOut_a_bits_data_hi = {anonOut_a_bits_data_hi_hi, anonOut_a_bits_data_hi_lo}; // @[WidthWidget.scala:73:12] assign _anonOut_a_bits_data_T_3 = {anonOut_a_bits_data_hi, anonOut_a_bits_data_lo}; // @[WidthWidget.scala:73:12] assign anonOut_a_bits_data = _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12] wire [1:0] anonOut_a_bits_mask_sizeOH_shiftAmount = _anonOut_a_bits_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _anonOut_a_bits_mask_sizeOH_T_1 = 4'h1 << anonOut_a_bits_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _anonOut_a_bits_mask_sizeOH_T_2 = _anonOut_a_bits_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] anonOut_a_bits_mask_sizeOH = {_anonOut_a_bits_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire anonOut_a_bits_mask_sub_sub_sub_0_1 = anonOut_a_bits_size > 4'h2; // @[Misc.scala:206:21] wire anonOut_a_bits_mask_sub_sub_size = anonOut_a_bits_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_sub_sub_bit = anonOut_a_bits_address[2]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_sub_sub_1_2 = anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire anonOut_a_bits_mask_sub_sub_nbit = ~anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_sub_sub_0_2 = anonOut_a_bits_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_sub_acc_T = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_sub_0_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _anonOut_a_bits_mask_sub_sub_acc_T_1 = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_sub_1_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire anonOut_a_bits_mask_sub_size = anonOut_a_bits_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_sub_bit = anonOut_a_bits_address[1]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_sub_nbit = ~anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_sub_0_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_acc_T = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_0_1 = anonOut_a_bits_mask_sub_sub_0_1 | _anonOut_a_bits_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_1_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_1 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_1_1 = anonOut_a_bits_mask_sub_sub_0_1 | _anonOut_a_bits_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_2_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_2 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_2_1 = anonOut_a_bits_mask_sub_sub_1_1 | _anonOut_a_bits_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_3_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_3 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_3_1 = anonOut_a_bits_mask_sub_sub_1_1 | _anonOut_a_bits_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_size = anonOut_a_bits_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_bit = anonOut_a_bits_address[0]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_nbit = ~anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_eq = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc = anonOut_a_bits_mask_sub_0_1 | _anonOut_a_bits_mask_acc_T; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_1 = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_1 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_1 = anonOut_a_bits_mask_sub_0_1 | _anonOut_a_bits_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_2 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_2 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_2 = anonOut_a_bits_mask_sub_1_1 | _anonOut_a_bits_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_3 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_3 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_3 = anonOut_a_bits_mask_sub_1_1 | _anonOut_a_bits_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_4 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_4 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_4 = anonOut_a_bits_mask_sub_2_1 | _anonOut_a_bits_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_5 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_5 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_5 = anonOut_a_bits_mask_sub_2_1 | _anonOut_a_bits_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_6 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_6 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_6 = anonOut_a_bits_mask_sub_3_1 | _anonOut_a_bits_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_7 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_7 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_7 = anonOut_a_bits_mask_sub_3_1 | _anonOut_a_bits_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] anonOut_a_bits_mask_lo_lo = {anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] anonOut_a_bits_mask_lo_hi = {anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] anonOut_a_bits_mask_lo = {anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] anonOut_a_bits_mask_hi_lo = {anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] anonOut_a_bits_mask_hi_hi = {anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] anonOut_a_bits_mask_hi = {anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] _anonOut_a_bits_mask_T = {anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo}; // @[Misc.scala:222:10] reg anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonOut_a_bits_mask_masked_enable_T = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_0 = enable_0 | _anonOut_a_bits_mask_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_1 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_1 = enable_1 | _anonOut_a_bits_mask_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_2 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_2 = enable_2 | _anonOut_a_bits_mask_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_3 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_3 = enable_3 | _anonOut_a_bits_mask_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_4 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_4 = enable_4 | _anonOut_a_bits_mask_masked_enable_T_4; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_5 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_5 = enable_5 | _anonOut_a_bits_mask_masked_enable_T_5; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_6 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_6 = enable_6 | _anonOut_a_bits_mask_masked_enable_T_6; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_7 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_7 = enable_7 | _anonOut_a_bits_mask_masked_enable_T_7; // @[WidthWidget.scala:43:47, :63:{42,45}] reg anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_1; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_2; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_3; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_4; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_5; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_6; // @[WidthWidget.scala:66:24] wire anonOut_a_bits_mask_mdata_0 = anonOut_a_bits_mask_masked_enable_0 | anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_1 = anonOut_a_bits_mask_masked_enable_1 | anonOut_a_bits_mask_rdata_1; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_2 = anonOut_a_bits_mask_masked_enable_2 | anonOut_a_bits_mask_rdata_2; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_3 = anonOut_a_bits_mask_masked_enable_3 | anonOut_a_bits_mask_rdata_3; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_4 = anonOut_a_bits_mask_masked_enable_4 | anonOut_a_bits_mask_rdata_4; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_5 = anonOut_a_bits_mask_masked_enable_5 | anonOut_a_bits_mask_rdata_5; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_6 = anonOut_a_bits_mask_masked_enable_6 | anonOut_a_bits_mask_rdata_6; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire _anonOut_a_bits_mask_T_2 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonOut_a_bits_mask_T_3 = _anonOut_a_bits_mask_T_1 & _anonOut_a_bits_mask_T_2; // @[Decoupled.scala:51:35] wire [1:0] anonOut_a_bits_mask_lo_lo_1 = {anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [1:0] anonOut_a_bits_mask_lo_hi_1 = {anonOut_a_bits_mask_mdata_3, anonOut_a_bits_mask_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] wire [3:0] anonOut_a_bits_mask_lo_1 = {anonOut_a_bits_mask_lo_hi_1, anonOut_a_bits_mask_lo_lo_1}; // @[WidthWidget.scala:73:12] wire [1:0] anonOut_a_bits_mask_hi_lo_1 = {anonOut_a_bits_mask_mdata_5, anonOut_a_bits_mask_mdata_4}; // @[WidthWidget.scala:68:88, :73:12] wire [1:0] anonOut_a_bits_mask_hi_hi_1 = {1'h1, anonOut_a_bits_mask_mdata_6}; // @[WidthWidget.scala:68:88, :73:12] wire [3:0] anonOut_a_bits_mask_hi_1 = {anonOut_a_bits_mask_hi_hi_1, anonOut_a_bits_mask_hi_lo_1}; // @[WidthWidget.scala:73:12] wire [7:0] _anonOut_a_bits_mask_T_4 = {anonOut_a_bits_mask_hi_1, anonOut_a_bits_mask_lo_1}; // @[WidthWidget.scala:73:12] wire [7:0] _anonOut_a_bits_mask_T_6 = hasData ? _anonOut_a_bits_mask_T_4 : 8'hFF; // @[WidthWidget.scala:73:12, :85:93] assign _anonOut_a_bits_mask_T_7 = _anonOut_a_bits_mask_T & _anonOut_a_bits_mask_T_6; // @[Misc.scala:222:10] assign anonOut_a_bits_mask = _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonIn_d_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_sink = cated_bits_sink; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_denied = cated_bits_denied; // @[WidthWidget.scala:161:25] wire [63:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonIn_d_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [63:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [55:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[63:8]; // @[Repeater.scala:36:26] wire [7:0] _cated_bits_data_T_1 = anonOut_d_bits_data[7:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire repeat_hasData = cated_bits_opcode[0]; // @[WidthWidget.scala:161:25] wire [17:0] _repeat_limit_T = 18'h7 << cated_bits_size; // @[package.scala:243:71] wire [2:0] _repeat_limit_T_1 = _repeat_limit_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire [2:0] repeat_limit = _repeat_limit_T_2; // @[package.scala:243:46] reg [2:0] repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = repeat_count == 3'h0; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonIn_d_ready & anonIn_d_valid; // @[Decoupled.scala:51:35] wire [3:0] _repeat_count_T = {1'h0, repeat_count} + 4'h1; // @[WidthWidget.scala:105:26, :110:24] wire [2:0] _repeat_count_T_1 = _repeat_count_T[2:0]; // @[WidthWidget.scala:110:24] reg [2:0] repeat_sel_sel_sources_0; // @[WidthWidget.scala:187:27] wire [2:0] repeat_sel_sel_a_sel = anonIn_a_bits_address[2:0]; // @[WidthWidget.scala:188:38] reg [2:0] repeat_sel_hold_r; // @[WidthWidget.scala:121:47] wire [2:0] repeat_sel_hold = repeat_first ? repeat_sel_sel_sources_0 : repeat_sel_hold_r; // @[WidthWidget.scala:106:25, :121:{25,47}, :187:27] wire [2:0] _repeat_sel_T = ~repeat_limit; // @[WidthWidget.scala:103:47, :122:18] wire [2:0] repeat_sel = repeat_sel_hold & _repeat_sel_T; // @[WidthWidget.scala:121:25, :122:{16,18}] wire [2:0] repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :122:16, :126:24] wire [7:0] _repeat_anonIn_d_bits_data_mux_T = cated_bits_data[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_0 = _repeat_anonIn_d_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_1 = cated_bits_data[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_1 = _repeat_anonIn_d_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_2 = cated_bits_data[23:16]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_2 = _repeat_anonIn_d_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_3 = cated_bits_data[31:24]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_3 = _repeat_anonIn_d_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_4 = cated_bits_data[39:32]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_4 = _repeat_anonIn_d_bits_data_mux_T_4; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_5 = cated_bits_data[47:40]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_5 = _repeat_anonIn_d_bits_data_mux_T_5; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_6 = cated_bits_data[55:48]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_6 = _repeat_anonIn_d_bits_data_mux_T_6; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_7 = cated_bits_data[63:56]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_7 = _repeat_anonIn_d_bits_data_mux_T_7; // @[WidthWidget.scala:128:{43,55}] wire [7:0][7:0] _GEN = {{repeat_anonIn_d_bits_data_mux_7}, {repeat_anonIn_d_bits_data_mux_6}, {repeat_anonIn_d_bits_data_mux_5}, {repeat_anonIn_d_bits_data_mux_4}, {repeat_anonIn_d_bits_data_mux_3}, {repeat_anonIn_d_bits_data_mux_2}, {repeat_anonIn_d_bits_data_mux_1}, {repeat_anonIn_d_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30] assign anonIn_d_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] count <= 3'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonOut_a_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] anonOut_a_bits_mask_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] repeat_count <= 3'h0; // @[WidthWidget.scala:105:26] end else begin // @[WidthWidget.scala:27:9] if (_T) begin // @[Decoupled.scala:51:35] count <= last ? 3'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23] end anonOut_a_bits_data_rdata_written_once <= _anonOut_a_bits_data_T_2 | anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] anonOut_a_bits_mask_rdata_written_once <= _anonOut_a_bits_mask_T_3 | anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= repeat_last ? 3'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] end if (_anonOut_a_bits_data_T_2) begin // @[WidthWidget.scala:69:23] anonOut_a_bits_data_rdata_0 <= anonOut_a_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_1 <= anonOut_a_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_2 <= anonOut_a_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_3 <= anonOut_a_bits_data_mdata_3; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_4 <= anonOut_a_bits_data_mdata_4; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_5 <= anonOut_a_bits_data_mdata_5; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_6 <= anonOut_a_bits_data_mdata_6; // @[WidthWidget.scala:66:24, :68:88] end if (_anonOut_a_bits_mask_T_3) begin // @[WidthWidget.scala:69:23] anonOut_a_bits_mask_rdata_0 <= anonOut_a_bits_mask_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_1 <= anonOut_a_bits_mask_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_2 <= anonOut_a_bits_mask_mdata_2; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_3 <= anonOut_a_bits_mask_mdata_3; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_4 <= anonOut_a_bits_mask_mdata_4; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_5 <= anonOut_a_bits_mask_mdata_5; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_6 <= anonOut_a_bits_mask_mdata_6; // @[WidthWidget.scala:66:24, :68:88] end if (_repeat_sel_sel_T) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_0 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (repeat_first) // @[WidthWidget.scala:106:25] repeat_sel_hold_r <= repeat_sel_sel_sources_0; // @[WidthWidget.scala:121:47, :187:27] always @(posedge) TLMonitor_17 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleD_a32d64s1k4z4u repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonOut_d_ready), .io_enq_valid (anonOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (anonOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (anonOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (anonOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_sink (anonOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (anonOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (anonOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (anonOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_sink (cated_bits_sink), .io_deq_bits_denied (cated_bits_denied), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File Util.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants object CompressAccelLogger { def logInfo(format: String, args: Bits*)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_*)) } def logCritical(format: String, args: Bits*)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U if (p(CompressAccelPrintfEnable)) { printf(midas.targetutils.SynthesizePrintf("cy: %d, ", loginfo_cycles)) printf(midas.targetutils.SynthesizePrintf(format, args:_*)) } else { printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_*)) } } def logWaveStyle(format: String, args: Bits*)(implicit p: Parameters) { } } object CompressAccelParams { } File MemLoader.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants class MemLoader(memLoaderQueDepth: Int = 16*4)(implicit p: Parameters) extends Module with MemoryOpConstants { val io = IO(new Bundle { val l2helperUser = new L2MemHelperBundle val src_info = Flipped(Decoupled(new StreamInfo)) val consumer = new MemLoaderConsumerBundle }) val buf_info_queue = Module(new Queue(new BufInfoBundle, 16)) val load_info_queue = Module(new Queue(new LoadInfoBundle, 256)) val base_addr_bytes = io.src_info.bits.ip val base_len = io.src_info.bits.isize val base_addr_start_index = io.src_info.bits.ip & 0x1F.U val aligned_loadlen = base_len + base_addr_start_index val base_addr_end_index = (base_len + base_addr_start_index) & 0x1F.U val base_addr_end_index_inclusive = (base_len + base_addr_start_index - 1.U) & 0x1F.U val extra_word = ((aligned_loadlen & 0x1F.U) =/= 0.U).asUInt val base_addr_bytes_aligned = (base_addr_bytes >> 5.U) << 5.U val words_to_load = (aligned_loadlen >> 5.U) + extra_word val words_to_load_minus_one = words_to_load - 1.U val print_not_done = RegInit(true.B) when (io.src_info.valid && print_not_done) { CompressAccelLogger.logInfo("base_addr_bytes: %x\n", base_addr_bytes) CompressAccelLogger.logInfo("base_len: %x\n", base_len) CompressAccelLogger.logInfo("base_addr_start_index: %x\n", base_addr_start_index) CompressAccelLogger.logInfo("aligned_loadlen: %x\n", aligned_loadlen) CompressAccelLogger.logInfo("base_addr_end_index: %x\n", base_addr_end_index) CompressAccelLogger.logInfo("base_addr_end_index_inclusive: %x\n", base_addr_end_index_inclusive) CompressAccelLogger.logInfo("extra_word: %x\n", extra_word) CompressAccelLogger.logInfo("base_addr_bytes_aligned: %x\n", base_addr_bytes_aligned) CompressAccelLogger.logInfo("words_to_load: %x\n", words_to_load) CompressAccelLogger.logInfo("words_to_load_minus_one: %x\n", words_to_load_minus_one) when (io.src_info.ready) { print_not_done := true.B } .otherwise { print_not_done := false.B } } val request_fire = DecoupledHelper( io.l2helperUser.req.ready, io.src_info.valid, buf_info_queue.io.enq.ready, load_info_queue.io.enq.ready ) io.l2helperUser.req.bits.cmd := M_XRD io.l2helperUser.req.bits.size := log2Ceil(32).U io.l2helperUser.req.bits.data := 0.U val addrinc = RegInit(0.U(64.W)) load_info_queue.io.enq.bits.start_byte := Mux(addrinc === 0.U, base_addr_start_index, 0.U) load_info_queue.io.enq.bits.end_byte := Mux(addrinc === words_to_load_minus_one, base_addr_end_index_inclusive, 31.U) when (request_fire.fire && (addrinc === words_to_load_minus_one)) { addrinc := 0.U } .elsewhen (request_fire.fire) { addrinc := addrinc + 1.U } when (io.src_info.fire) { CompressAccelLogger.logInfo("COMPLETED INPUT LOAD FOR DECOMPRESSION\n") } io.src_info.ready := request_fire.fire(io.src_info.valid, addrinc === words_to_load_minus_one) buf_info_queue.io.enq.valid := request_fire.fire(buf_info_queue.io.enq.ready, addrinc === 0.U) load_info_queue.io.enq.valid := request_fire.fire(load_info_queue.io.enq.ready) buf_info_queue.io.enq.bits.len_bytes := base_len io.l2helperUser.req.bits.addr := (base_addr_bytes_aligned) + (addrinc << 5) io.l2helperUser.req.valid := request_fire.fire(io.l2helperUser.req.ready) val NUM_QUEUES = 32 val QUEUE_DEPTHS = memLoaderQueDepth val write_start_index = RegInit(0.U(log2Up(NUM_QUEUES+1).W)) val mem_resp_queues = Seq.fill(NUM_QUEUES)(Module(new Queue(UInt(8.W), QUEUE_DEPTHS)).io) val align_shamt = (load_info_queue.io.deq.bits.start_byte << 3) val memresp_bits_shifted = io.l2helperUser.resp.bits.data >> align_shamt for ( queueno <- 0 until NUM_QUEUES ) { mem_resp_queues(queueno).enq.bits := 0.U } for ( queueno <- 0 until NUM_QUEUES ) { val idx = (write_start_index +& queueno.U) % NUM_QUEUES.U for (j <- 0 until NUM_QUEUES) { when (j.U === idx) { mem_resp_queues(j).enq.bits := memresp_bits_shifted >> (queueno * 8) } } } val len_to_write = (load_info_queue.io.deq.bits.end_byte - load_info_queue.io.deq.bits.start_byte) +& 1.U val wrap_len_index_wide = write_start_index +& len_to_write val wrap_len_index_end = wrap_len_index_wide % NUM_QUEUES.U val wrapped = wrap_len_index_wide >= NUM_QUEUES.U when (load_info_queue.io.deq.valid) { CompressAccelLogger.logInfo("memloader start %x, end %x\n", load_info_queue.io.deq.bits.start_byte, load_info_queue.io.deq.bits.end_byte) } val resp_fire_noqueues = DecoupledHelper( io.l2helperUser.resp.valid, load_info_queue.io.deq.valid ) val all_queues_ready = mem_resp_queues.map(_.enq.ready).reduce(_ && _) load_info_queue.io.deq.ready := resp_fire_noqueues.fire(load_info_queue.io.deq.valid, all_queues_ready) io.l2helperUser.resp.ready := resp_fire_noqueues.fire(io.l2helperUser.resp.valid, all_queues_ready) val resp_fire_allqueues = resp_fire_noqueues.fire && all_queues_ready when (resp_fire_allqueues) { write_start_index := wrap_len_index_end } for ( queueno <- 0 until NUM_QUEUES ) { val use_this_queue = Mux(wrapped, (queueno.U >= write_start_index) || (queueno.U < wrap_len_index_end), (queueno.U >= write_start_index) && (queueno.U < wrap_len_index_end) ) mem_resp_queues(queueno).enq.valid := resp_fire_noqueues.fire && use_this_queue && all_queues_ready } for ( queueno <- 0 until NUM_QUEUES ) { when (mem_resp_queues(queueno).deq.valid) { CompressAccelLogger.logInfo("queueind %d, val %x\n", queueno.U, mem_resp_queues(queueno).deq.bits) } } val read_start_index = RegInit(0.U(log2Up(NUM_QUEUES+1).W)) val len_already_consumed = RegInit(0.U(64.W)) val remapVecData = Wire(Vec(NUM_QUEUES, UInt(8.W))) val remapVecValids = Wire(Vec(NUM_QUEUES, Bool())) val remapVecReadys = Wire(Vec(NUM_QUEUES, Bool())) for (queueno <- 0 until NUM_QUEUES) { remapVecData(queueno) := 0.U remapVecValids(queueno) := false.B mem_resp_queues(queueno).deq.ready := false.B } for (queueno <- 0 until NUM_QUEUES) { val remapindex = (queueno.U +& read_start_index) % NUM_QUEUES.U for (j <- 0 until NUM_QUEUES) { when (j.U === remapindex) { remapVecData(queueno) := mem_resp_queues(j).deq.bits remapVecValids(queueno) := mem_resp_queues(j).deq.valid mem_resp_queues(j).deq.ready := remapVecReadys(queueno) } } } io.consumer.output_data := Cat(remapVecData.reverse) val buf_last = (len_already_consumed + io.consumer.user_consumed_bytes) === buf_info_queue.io.deq.bits.len_bytes val count_valids = remapVecValids.map(_.asUInt).reduce(_ +& _) val unconsumed_bytes_so_far = buf_info_queue.io.deq.bits.len_bytes - len_already_consumed val enough_data = Mux(unconsumed_bytes_so_far >= NUM_QUEUES.U, count_valids === NUM_QUEUES.U, count_valids >= unconsumed_bytes_so_far) io.consumer.available_output_bytes := Mux(unconsumed_bytes_so_far >= NUM_QUEUES.U, NUM_QUEUES.U, unconsumed_bytes_so_far) io.consumer.output_last_chunk := (unconsumed_bytes_so_far <= NUM_QUEUES.U) val read_fire = DecoupledHelper( io.consumer.output_ready, buf_info_queue.io.deq.valid, enough_data ) when (read_fire.fire) { CompressAccelLogger.logInfo("MEMLOADER READ: bytesread %d\n", io.consumer.user_consumed_bytes) } io.consumer.output_valid := read_fire.fire(io.consumer.output_ready) for (queueno <- 0 until NUM_QUEUES) { remapVecReadys(queueno) := (queueno.U < io.consumer.user_consumed_bytes) && read_fire.fire } when (read_fire.fire) { read_start_index := (read_start_index +& io.consumer.user_consumed_bytes) % NUM_QUEUES.U } buf_info_queue.io.deq.ready := read_fire.fire(buf_info_queue.io.deq.valid) && buf_last when (read_fire.fire) { when (buf_last) { len_already_consumed := 0.U } .otherwise { len_already_consumed := len_already_consumed + io.consumer.user_consumed_bytes } } }
module MemLoader_3( // @[MemLoader.scala:15:7] input clock, // @[MemLoader.scala:15:7] input reset, // @[MemLoader.scala:15:7] input io_l2helperUser_req_ready, // @[MemLoader.scala:18:14] output io_l2helperUser_req_valid, // @[MemLoader.scala:18:14] output [70:0] io_l2helperUser_req_bits_addr, // @[MemLoader.scala:18:14] output io_l2helperUser_resp_ready, // @[MemLoader.scala:18:14] input io_l2helperUser_resp_valid, // @[MemLoader.scala:18:14] input [255:0] io_l2helperUser_resp_bits_data, // @[MemLoader.scala:18:14] input io_l2helperUser_no_memops_inflight, // @[MemLoader.scala:18:14] output io_src_info_ready, // @[MemLoader.scala:18:14] input io_src_info_valid, // @[MemLoader.scala:18:14] input [63:0] io_src_info_bits_ip, // @[MemLoader.scala:18:14] input [63:0] io_src_info_bits_isize, // @[MemLoader.scala:18:14] output [5:0] io_consumer_available_output_bytes, // @[MemLoader.scala:18:14] output io_consumer_output_valid, // @[MemLoader.scala:18:14] input io_consumer_output_ready, // @[MemLoader.scala:18:14] output [255:0] io_consumer_output_data, // @[MemLoader.scala:18:14] output io_consumer_output_last_chunk // @[MemLoader.scala:18:14] ); wire _Queue64_UInt8_31_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_31_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_31_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_30_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_30_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_30_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_29_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_29_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_29_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_28_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_28_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_28_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_27_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_27_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_27_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_26_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_26_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_26_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_25_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_25_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_25_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_24_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_24_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_24_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_23_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_23_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_23_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_22_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_22_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_22_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_21_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_21_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_21_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_20_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_20_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_20_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_19_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_19_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_19_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_18_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_18_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_18_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_17_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_17_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_17_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_16_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_16_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_16_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_15_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_15_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_15_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_14_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_14_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_14_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_13_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_13_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_13_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_12_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_12_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_12_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_11_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_11_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_11_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_10_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_10_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_10_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_9_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_9_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_9_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_8_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_8_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_8_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_7_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_7_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_7_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_6_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_6_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_6_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_5_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_5_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_5_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_4_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_4_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_4_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_3_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_3_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_3_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_2_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_2_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_2_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_1_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_1_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_1_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_io_deq_bits; // @[MemLoader.scala:106:52] wire _load_info_queue_io_enq_ready; // @[MemLoader.scala:28:31] wire _load_info_queue_io_deq_valid; // @[MemLoader.scala:28:31] wire [4:0] _load_info_queue_io_deq_bits_start_byte; // @[MemLoader.scala:28:31] wire [4:0] _load_info_queue_io_deq_bits_end_byte; // @[MemLoader.scala:28:31] wire _buf_info_queue_io_enq_ready; // @[MemLoader.scala:26:30] wire _buf_info_queue_io_deq_valid; // @[MemLoader.scala:26:30] wire [63:0] _buf_info_queue_io_deq_bits_len_bytes; // @[MemLoader.scala:26:30] wire io_l2helperUser_req_ready_0 = io_l2helperUser_req_ready; // @[MemLoader.scala:15:7] wire io_l2helperUser_resp_valid_0 = io_l2helperUser_resp_valid; // @[MemLoader.scala:15:7] wire [255:0] io_l2helperUser_resp_bits_data_0 = io_l2helperUser_resp_bits_data; // @[MemLoader.scala:15:7] wire io_l2helperUser_no_memops_inflight_0 = io_l2helperUser_no_memops_inflight; // @[MemLoader.scala:15:7] wire io_src_info_valid_0 = io_src_info_valid; // @[MemLoader.scala:15:7] wire [63:0] io_src_info_bits_ip_0 = io_src_info_bits_ip; // @[MemLoader.scala:15:7] wire [63:0] io_src_info_bits_isize_0 = io_src_info_bits_isize; // @[MemLoader.scala:15:7] wire io_consumer_output_ready_0 = io_consumer_output_ready; // @[MemLoader.scala:15:7] wire [2:0] io_l2helperUser_req_bits_size = 3'h5; // @[MemLoader.scala:15:7] wire [255:0] io_l2helperUser_req_bits_data = 256'h0; // @[MemLoader.scala:15:7] wire io_l2helperUser_req_bits_cmd = 1'h0; // @[MemLoader.scala:15:7] wire remapVecReadys_12 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_13 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_14 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_15 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_16 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_17 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_18 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_19 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_20 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_21 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_22 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_23 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_24 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_25 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_26 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_27 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_28 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_29 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_30 = 1'h0; // @[MemLoader.scala:168:28] wire remapVecReadys_31 = 1'h0; // @[MemLoader.scala:168:28] wire _remapVecReadys_12_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_12_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_13_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_13_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_14_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_14_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_15_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_15_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_16_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_16_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_17_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_17_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_18_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_18_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_19_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_19_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_20_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_20_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_21_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_21_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_22_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_22_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_23_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_23_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_24_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_24_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_25_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_25_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_26_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_26_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_27_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_27_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_28_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_28_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_29_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_29_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_30_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_30_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire _remapVecReadys_31_T = 1'h0; // @[MemLoader.scala:217:43] wire _remapVecReadys_31_T_3 = 1'h0; // @[MemLoader.scala:217:78] wire [5:0] io_consumer_user_consumed_bytes = 6'hC; // @[MemLoader.scala:15:7] wire _remapVecReadys_0_T = 1'h1; // @[MemLoader.scala:217:43] wire _remapVecReadys_1_T = 1'h1; // @[MemLoader.scala:217:43] wire _remapVecReadys_2_T = 1'h1; // @[MemLoader.scala:217:43] wire _remapVecReadys_3_T = 1'h1; // @[MemLoader.scala:217:43] wire _remapVecReadys_4_T = 1'h1; // @[MemLoader.scala:217:43] wire _remapVecReadys_5_T = 1'h1; // @[MemLoader.scala:217:43] wire _remapVecReadys_6_T = 1'h1; // @[MemLoader.scala:217:43] wire _remapVecReadys_7_T = 1'h1; // @[MemLoader.scala:217:43] wire _remapVecReadys_8_T = 1'h1; // @[MemLoader.scala:217:43] wire _remapVecReadys_9_T = 1'h1; // @[MemLoader.scala:217:43] wire _remapVecReadys_10_T = 1'h1; // @[MemLoader.scala:217:43] wire _remapVecReadys_11_T = 1'h1; // @[MemLoader.scala:217:43] wire _io_l2helperUser_req_valid_T_1; // @[Misc.scala:26:53] wire [70:0] _io_l2helperUser_req_bits_addr_T_2; // @[MemLoader.scala:100:62] wire _io_l2helperUser_resp_ready_T; // @[Misc.scala:26:53] wire _io_src_info_ready_T_3; // @[Misc.scala:26:53] wire _io_consumer_output_valid_T; // @[Misc.scala:26:53] wire [255:0] _io_consumer_output_data_T; // @[MemLoader.scala:186:33] wire _io_consumer_output_last_chunk_T; // @[MemLoader.scala:201:61] wire [70:0] io_l2helperUser_req_bits_addr_0; // @[MemLoader.scala:15:7] wire io_l2helperUser_req_valid_0; // @[MemLoader.scala:15:7] wire io_l2helperUser_resp_ready_0; // @[MemLoader.scala:15:7] wire io_src_info_ready_0; // @[MemLoader.scala:15:7] wire [5:0] io_consumer_available_output_bytes_0; // @[MemLoader.scala:15:7] wire io_consumer_output_valid_0; // @[MemLoader.scala:15:7] wire [255:0] io_consumer_output_data_0; // @[MemLoader.scala:15:7] wire io_consumer_output_last_chunk_0; // @[MemLoader.scala:15:7] wire [63:0] base_addr_start_index = {59'h0, io_src_info_bits_ip_0[4:0]}; // @[MemLoader.scala:15:7, :32:51] wire [64:0] _GEN = {1'h0, io_src_info_bits_isize_0} + {1'h0, base_addr_start_index}; // @[MemLoader.scala:15:7, :32:51, :33:35] wire [64:0] _aligned_loadlen_T; // @[MemLoader.scala:33:35] assign _aligned_loadlen_T = _GEN; // @[MemLoader.scala:33:35] wire [64:0] _base_addr_end_index_T; // @[MemLoader.scala:34:39] assign _base_addr_end_index_T = _GEN; // @[MemLoader.scala:33:35, :34:39] wire [64:0] _base_addr_end_index_inclusive_T; // @[MemLoader.scala:35:49] assign _base_addr_end_index_inclusive_T = _GEN; // @[MemLoader.scala:33:35, :35:49] wire [63:0] aligned_loadlen = _aligned_loadlen_T[63:0]; // @[MemLoader.scala:33:35] wire [63:0] _base_addr_end_index_T_1 = _base_addr_end_index_T[63:0]; // @[MemLoader.scala:34:39] wire [63:0] base_addr_end_index = {59'h0, _base_addr_end_index_T_1[4:0]}; // @[MemLoader.scala:34:{39,64}] wire [63:0] _base_addr_end_index_inclusive_T_1 = _base_addr_end_index_inclusive_T[63:0]; // @[MemLoader.scala:35:49] wire [64:0] _base_addr_end_index_inclusive_T_2 = {1'h0, _base_addr_end_index_inclusive_T_1} - 65'h1; // @[MemLoader.scala:35:{49,73}] wire [63:0] _base_addr_end_index_inclusive_T_3 = _base_addr_end_index_inclusive_T_2[63:0]; // @[MemLoader.scala:35:73] wire [63:0] base_addr_end_index_inclusive = {59'h0, _base_addr_end_index_inclusive_T_3[4:0]}; // @[MemLoader.scala:35:{73,80}] wire [63:0] _extra_word_T = {59'h0, aligned_loadlen[4:0]}; // @[MemLoader.scala:33:35, :36:38] wire extra_word = |_extra_word_T; // @[MemLoader.scala:36:{38,48}] wire [63:0] _base_addr_bytes_aligned_T = {5'h0, io_src_info_bits_ip_0[63:5]}; // @[MemLoader.scala:15:7, :38:50] wire [70:0] base_addr_bytes_aligned = {2'h0, _base_addr_bytes_aligned_T, 5'h0}; // @[MemLoader.scala:38:{50,58}] wire [63:0] _words_to_load_T = {5'h0, aligned_loadlen[63:5]}; // @[MemLoader.scala:33:35, :39:40] wire [64:0] _words_to_load_T_1 = {1'h0, _words_to_load_T} + {64'h0, extra_word}; // @[MemLoader.scala:36:48, :39:{40,48}] wire [63:0] words_to_load = _words_to_load_T_1[63:0]; // @[MemLoader.scala:39:48] wire [64:0] _words_to_load_minus_one_T = {1'h0, words_to_load} - 65'h1; // @[MemLoader.scala:39:48, :40:47] wire [63:0] words_to_load_minus_one = _words_to_load_minus_one_T[63:0]; // @[MemLoader.scala:40:47] reg print_not_done; // @[MemLoader.scala:43:31] wire _T = io_src_info_valid_0 & print_not_done; // @[MemLoader.scala:15:7, :43:31, :45:27] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] addrinc; // @[MemLoader.scala:74:24] wire _GEN_0 = addrinc == 64'h0; // @[MemLoader.scala:74:24, :76:57] wire _load_info_queue_io_enq_bits_start_byte_T; // @[MemLoader.scala:76:57] assign _load_info_queue_io_enq_bits_start_byte_T = _GEN_0; // @[MemLoader.scala:76:57] wire _buf_info_queue_io_enq_valid_T; // @[MemLoader.scala:95:53] assign _buf_info_queue_io_enq_valid_T = _GEN_0; // @[MemLoader.scala:76:57, :95:53] wire [63:0] _load_info_queue_io_enq_bits_start_byte_T_1 = _load_info_queue_io_enq_bits_start_byte_T ? base_addr_start_index : 64'h0; // @[MemLoader.scala:32:51, :76:{48,57}] wire _T_44 = addrinc == words_to_load_minus_one; // @[MemLoader.scala:40:47, :74:24, :77:55] wire _load_info_queue_io_enq_bits_end_byte_T; // @[MemLoader.scala:77:55] assign _load_info_queue_io_enq_bits_end_byte_T = _T_44; // @[MemLoader.scala:77:55] wire _io_src_info_ready_T; // @[MemLoader.scala:92:53] assign _io_src_info_ready_T = _T_44; // @[MemLoader.scala:77:55, :92:53] wire [63:0] _load_info_queue_io_enq_bits_end_byte_T_1 = _load_info_queue_io_enq_bits_end_byte_T ? base_addr_end_index_inclusive : 64'h1F; // @[MemLoader.scala:35:80, :77:{46,55}] wire _T_46 = io_l2helperUser_req_ready_0 & io_src_info_valid_0; // @[Misc.scala:29:18] wire _buf_info_queue_io_enq_valid_T_1; // @[Misc.scala:26:53] assign _buf_info_queue_io_enq_valid_T_1 = _T_46; // @[Misc.scala:26:53, :29:18] wire _load_info_queue_io_enq_valid_T; // @[Misc.scala:26:53] assign _load_info_queue_io_enq_valid_T = _T_46; // @[Misc.scala:26:53, :29:18] wire [64:0] _addrinc_T = {1'h0, addrinc} + 65'h1; // @[MemLoader.scala:74:24, :83:24] wire [63:0] _addrinc_T_1 = _addrinc_T[63:0]; // @[MemLoader.scala:83:24] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] wire _io_src_info_ready_T_1 = io_l2helperUser_req_ready_0 & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53] wire _io_src_info_ready_T_2 = _io_src_info_ready_T_1 & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53] assign _io_src_info_ready_T_3 = _io_src_info_ready_T_2 & _io_src_info_ready_T; // @[Misc.scala:26:53] assign io_src_info_ready_0 = _io_src_info_ready_T_3; // @[Misc.scala:26:53] wire _buf_info_queue_io_enq_valid_T_2 = _buf_info_queue_io_enq_valid_T_1 & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53] wire _buf_info_queue_io_enq_valid_T_3 = _buf_info_queue_io_enq_valid_T_2 & _buf_info_queue_io_enq_valid_T; // @[Misc.scala:26:53] wire _load_info_queue_io_enq_valid_T_1 = _load_info_queue_io_enq_valid_T & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53] wire [68:0] _io_l2helperUser_req_bits_addr_T = {addrinc, 5'h0}; // @[MemLoader.scala:74:24, :100:73] wire [71:0] _io_l2helperUser_req_bits_addr_T_1 = {1'h0, base_addr_bytes_aligned} + {3'h0, _io_l2helperUser_req_bits_addr_T}; // @[MemLoader.scala:38:58, :100:{62,73}] assign _io_l2helperUser_req_bits_addr_T_2 = _io_l2helperUser_req_bits_addr_T_1[70:0]; // @[MemLoader.scala:100:62] assign io_l2helperUser_req_bits_addr_0 = _io_l2helperUser_req_bits_addr_T_2; // @[MemLoader.scala:15:7, :100:62] wire _io_l2helperUser_req_valid_T = io_src_info_valid_0 & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53] assign _io_l2helperUser_req_valid_T_1 = _io_l2helperUser_req_valid_T & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53] assign io_l2helperUser_req_valid_0 = _io_l2helperUser_req_valid_T_1; // @[Misc.scala:26:53] reg [5:0] write_start_index; // @[MemLoader.scala:105:34] wire [7:0] align_shamt = {_load_info_queue_io_deq_bits_start_byte, 3'h0}; // @[MemLoader.scala:28:31, :108:61] wire [255:0] memresp_bits_shifted = io_l2helperUser_resp_bits_data_0 >> align_shamt; // @[MemLoader.scala:15:7, :108:61, :109:61] wire [6:0] _idx_T = {1'h0, write_start_index}; // @[MemLoader.scala:105:34, :116:34] wire [6:0] _GEN_1 = _idx_T % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx = _GEN_1[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_1 = _idx_T + 7'h1; // @[MemLoader.scala:116:34] wire [6:0] _GEN_2 = _idx_T_1 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_1 = _GEN_2[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_2 = _idx_T + 7'h2; // @[MemLoader.scala:116:34] wire [6:0] _GEN_3 = _idx_T_2 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_2 = _GEN_3[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_3 = _idx_T + 7'h3; // @[MemLoader.scala:116:34] wire [6:0] _GEN_4 = _idx_T_3 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_3 = _GEN_4[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_4 = _idx_T + 7'h4; // @[MemLoader.scala:116:34] wire [6:0] _GEN_5 = _idx_T_4 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_4 = _GEN_5[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_5 = _idx_T + 7'h5; // @[MemLoader.scala:116:34] wire [6:0] _GEN_6 = _idx_T_5 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_5 = _GEN_6[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_6 = _idx_T + 7'h6; // @[MemLoader.scala:116:34] wire [6:0] _GEN_7 = _idx_T_6 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_6 = _GEN_7[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_7 = _idx_T + 7'h7; // @[MemLoader.scala:116:34] wire [6:0] _GEN_8 = _idx_T_7 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_7 = _GEN_8[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_8 = _idx_T + 7'h8; // @[MemLoader.scala:116:34] wire [6:0] _GEN_9 = _idx_T_8 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_8 = _GEN_9[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_9 = _idx_T + 7'h9; // @[MemLoader.scala:116:34] wire [6:0] _GEN_10 = _idx_T_9 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_9 = _GEN_10[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_10 = _idx_T + 7'hA; // @[MemLoader.scala:116:34] wire [6:0] _GEN_11 = _idx_T_10 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_10 = _GEN_11[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_11 = _idx_T + 7'hB; // @[MemLoader.scala:116:34] wire [6:0] _GEN_12 = _idx_T_11 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_11 = _GEN_12[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_12 = _idx_T + 7'hC; // @[MemLoader.scala:116:34] wire [6:0] _GEN_13 = _idx_T_12 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_12 = _GEN_13[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_13 = _idx_T + 7'hD; // @[MemLoader.scala:116:34] wire [6:0] _GEN_14 = _idx_T_13 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_13 = _GEN_14[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_14 = _idx_T + 7'hE; // @[MemLoader.scala:116:34] wire [6:0] _GEN_15 = _idx_T_14 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_14 = _GEN_15[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_15 = _idx_T + 7'hF; // @[MemLoader.scala:116:34] wire [6:0] _GEN_16 = _idx_T_15 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_15 = _GEN_16[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_16 = _idx_T + 7'h10; // @[MemLoader.scala:116:34] wire [6:0] _GEN_17 = _idx_T_16 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_16 = _GEN_17[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_17 = _idx_T + 7'h11; // @[MemLoader.scala:116:34] wire [6:0] _GEN_18 = _idx_T_17 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_17 = _GEN_18[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_18 = _idx_T + 7'h12; // @[MemLoader.scala:116:34] wire [6:0] _GEN_19 = _idx_T_18 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_18 = _GEN_19[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_19 = _idx_T + 7'h13; // @[MemLoader.scala:116:34] wire [6:0] _GEN_20 = _idx_T_19 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_19 = _GEN_20[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_20 = _idx_T + 7'h14; // @[MemLoader.scala:116:34] wire [6:0] _GEN_21 = _idx_T_20 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_20 = _GEN_21[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_21 = _idx_T + 7'h15; // @[MemLoader.scala:116:34] wire [6:0] _GEN_22 = _idx_T_21 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_21 = _GEN_22[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_22 = _idx_T + 7'h16; // @[MemLoader.scala:116:34] wire [6:0] _GEN_23 = _idx_T_22 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_22 = _GEN_23[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_23 = _idx_T + 7'h17; // @[MemLoader.scala:116:34] wire [6:0] _GEN_24 = _idx_T_23 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_23 = _GEN_24[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_24 = _idx_T + 7'h18; // @[MemLoader.scala:116:34] wire [6:0] _GEN_25 = _idx_T_24 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_24 = _GEN_25[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_25 = _idx_T + 7'h19; // @[MemLoader.scala:116:34] wire [6:0] _GEN_26 = _idx_T_25 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_25 = _GEN_26[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_26 = _idx_T + 7'h1A; // @[MemLoader.scala:116:34] wire [6:0] _GEN_27 = _idx_T_26 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_26 = _GEN_27[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_27 = _idx_T + 7'h1B; // @[MemLoader.scala:116:34] wire [6:0] _GEN_28 = _idx_T_27 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_27 = _GEN_28[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_28 = _idx_T + 7'h1C; // @[MemLoader.scala:116:34] wire [6:0] _GEN_29 = _idx_T_28 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_28 = _GEN_29[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_29 = _idx_T + 7'h1D; // @[MemLoader.scala:116:34] wire [6:0] _GEN_30 = _idx_T_29 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_29 = _GEN_30[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_30 = _idx_T + 7'h1E; // @[MemLoader.scala:116:34] wire [6:0] _GEN_31 = _idx_T_30 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_30 = _GEN_31[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_31 = _idx_T + 7'h1F; // @[MemLoader.scala:116:34] wire [6:0] _GEN_32 = _idx_T_31 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_31 = _GEN_32[5:0]; // @[MemLoader.scala:116:48] wire [5:0] _len_to_write_T = {1'h0, _load_info_queue_io_deq_bits_end_byte} - {1'h0, _load_info_queue_io_deq_bits_start_byte}; // @[MemLoader.scala:28:31, :124:60] wire [4:0] _len_to_write_T_1 = _len_to_write_T[4:0]; // @[MemLoader.scala:124:60] wire [5:0] len_to_write = {1'h0, _len_to_write_T_1} + 6'h1; // @[MemLoader.scala:124:{60,102}] wire [6:0] wrap_len_index_wide = _idx_T + {1'h0, len_to_write}; // @[MemLoader.scala:116:34, :124:102, :126:47] wire [6:0] _GEN_33 = wrap_len_index_wide % 7'h20; // @[MemLoader.scala:126:47, :127:48] wire [5:0] wrap_len_index_end = _GEN_33[5:0]; // @[MemLoader.scala:127:48] wire wrapped = |(wrap_len_index_wide[6:5]); // @[MemLoader.scala:126:47, :128:37] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] wire _all_queues_ready_T = _Queue64_UInt8_io_enq_ready & _Queue64_UInt8_1_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue64_UInt8_2_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue64_UInt8_3_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue64_UInt8_4_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue64_UInt8_5_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue64_UInt8_6_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue64_UInt8_7_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue64_UInt8_8_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue64_UInt8_9_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue64_UInt8_10_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue64_UInt8_11_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue64_UInt8_12_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue64_UInt8_13_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue64_UInt8_14_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue64_UInt8_15_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue64_UInt8_16_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue64_UInt8_17_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue64_UInt8_18_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue64_UInt8_19_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue64_UInt8_20_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue64_UInt8_21_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue64_UInt8_22_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue64_UInt8_23_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue64_UInt8_24_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue64_UInt8_25_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue64_UInt8_26_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue64_UInt8_27_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue64_UInt8_28_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue64_UInt8_29_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue64_UInt8_30_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire all_queues_ready = _all_queues_ready_T_29 & _Queue64_UInt8_31_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _load_info_queue_io_deq_ready_T = io_l2helperUser_resp_valid_0 & all_queues_ready; // @[Misc.scala:26:53] assign _io_l2helperUser_resp_ready_T = _load_info_queue_io_deq_valid & all_queues_ready; // @[Misc.scala:26:53] assign io_l2helperUser_resp_ready_0 = _io_l2helperUser_resp_ready_T; // @[Misc.scala:26:53] wire _resp_fire_allqueues_T = io_l2helperUser_resp_valid_0 & _load_info_queue_io_deq_valid; // @[Misc.scala:29:18] wire resp_fire_allqueues = _resp_fire_allqueues_T & all_queues_ready; // @[Misc.scala:29:18] wire _GEN_34 = write_start_index == 6'h0; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T; // @[MemLoader.scala:151:41] assign _use_this_queue_T = _GEN_34; // @[MemLoader.scala:151:41] wire _use_this_queue_T_3; // @[MemLoader.scala:152:41] assign _use_this_queue_T_3 = _GEN_34; // @[MemLoader.scala:151:41, :152:41] wire _use_this_queue_T_1 = |wrap_len_index_end; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_2 = _use_this_queue_T | _use_this_queue_T_1; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_4 = |wrap_len_index_end; // @[MemLoader.scala:127:48, :151:77, :152:77] wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_35 = write_start_index < 6'h2; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_6; // @[MemLoader.scala:151:41] assign _use_this_queue_T_6 = _GEN_35; // @[MemLoader.scala:151:41] wire _use_this_queue_T_9; // @[MemLoader.scala:152:41] assign _use_this_queue_T_9 = _GEN_35; // @[MemLoader.scala:151:41, :152:41] wire _use_this_queue_T_7 = |(wrap_len_index_end[5:1]); // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_8 = _use_this_queue_T_6 | _use_this_queue_T_7; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_10 = |(wrap_len_index_end[5:1]); // @[MemLoader.scala:127:48, :151:77, :152:77] wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_36 = write_start_index < 6'h3; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_12; // @[MemLoader.scala:151:41] assign _use_this_queue_T_12 = _GEN_36; // @[MemLoader.scala:151:41] wire _use_this_queue_T_15; // @[MemLoader.scala:152:41] assign _use_this_queue_T_15 = _GEN_36; // @[MemLoader.scala:151:41, :152:41] wire _GEN_37 = wrap_len_index_end > 6'h2; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_13; // @[MemLoader.scala:151:77] assign _use_this_queue_T_13 = _GEN_37; // @[MemLoader.scala:151:77] wire _use_this_queue_T_16; // @[MemLoader.scala:152:77] assign _use_this_queue_T_16 = _GEN_37; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_14 = _use_this_queue_T_12 | _use_this_queue_T_13; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_38 = write_start_index < 6'h4; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_18; // @[MemLoader.scala:151:41] assign _use_this_queue_T_18 = _GEN_38; // @[MemLoader.scala:151:41] wire _use_this_queue_T_21; // @[MemLoader.scala:152:41] assign _use_this_queue_T_21 = _GEN_38; // @[MemLoader.scala:151:41, :152:41] wire _use_this_queue_T_19 = |(wrap_len_index_end[5:2]); // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_20 = _use_this_queue_T_18 | _use_this_queue_T_19; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_22 = |(wrap_len_index_end[5:2]); // @[MemLoader.scala:127:48, :151:77, :152:77] wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_39 = write_start_index < 6'h5; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_24; // @[MemLoader.scala:151:41] assign _use_this_queue_T_24 = _GEN_39; // @[MemLoader.scala:151:41] wire _use_this_queue_T_27; // @[MemLoader.scala:152:41] assign _use_this_queue_T_27 = _GEN_39; // @[MemLoader.scala:151:41, :152:41] wire _GEN_40 = wrap_len_index_end > 6'h4; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_25; // @[MemLoader.scala:151:77] assign _use_this_queue_T_25 = _GEN_40; // @[MemLoader.scala:151:77] wire _use_this_queue_T_28; // @[MemLoader.scala:152:77] assign _use_this_queue_T_28 = _GEN_40; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_26 = _use_this_queue_T_24 | _use_this_queue_T_25; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_41 = write_start_index < 6'h6; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_30; // @[MemLoader.scala:151:41] assign _use_this_queue_T_30 = _GEN_41; // @[MemLoader.scala:151:41] wire _use_this_queue_T_33; // @[MemLoader.scala:152:41] assign _use_this_queue_T_33 = _GEN_41; // @[MemLoader.scala:151:41, :152:41] wire _GEN_42 = wrap_len_index_end > 6'h5; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_31; // @[MemLoader.scala:151:77] assign _use_this_queue_T_31 = _GEN_42; // @[MemLoader.scala:151:77] wire _use_this_queue_T_34; // @[MemLoader.scala:152:77] assign _use_this_queue_T_34 = _GEN_42; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_32 = _use_this_queue_T_30 | _use_this_queue_T_31; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_43 = write_start_index < 6'h7; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_36; // @[MemLoader.scala:151:41] assign _use_this_queue_T_36 = _GEN_43; // @[MemLoader.scala:151:41] wire _use_this_queue_T_39; // @[MemLoader.scala:152:41] assign _use_this_queue_T_39 = _GEN_43; // @[MemLoader.scala:151:41, :152:41] wire _GEN_44 = wrap_len_index_end > 6'h6; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_37; // @[MemLoader.scala:151:77] assign _use_this_queue_T_37 = _GEN_44; // @[MemLoader.scala:151:77] wire _use_this_queue_T_40; // @[MemLoader.scala:152:77] assign _use_this_queue_T_40 = _GEN_44; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_38 = _use_this_queue_T_36 | _use_this_queue_T_37; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_45 = write_start_index < 6'h8; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_42; // @[MemLoader.scala:151:41] assign _use_this_queue_T_42 = _GEN_45; // @[MemLoader.scala:151:41] wire _use_this_queue_T_45; // @[MemLoader.scala:152:41] assign _use_this_queue_T_45 = _GEN_45; // @[MemLoader.scala:151:41, :152:41] wire _use_this_queue_T_43 = |(wrap_len_index_end[5:3]); // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_44 = _use_this_queue_T_42 | _use_this_queue_T_43; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_46 = |(wrap_len_index_end[5:3]); // @[MemLoader.scala:127:48, :151:77, :152:77] wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_46 = write_start_index < 6'h9; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_48; // @[MemLoader.scala:151:41] assign _use_this_queue_T_48 = _GEN_46; // @[MemLoader.scala:151:41] wire _use_this_queue_T_51; // @[MemLoader.scala:152:41] assign _use_this_queue_T_51 = _GEN_46; // @[MemLoader.scala:151:41, :152:41] wire _GEN_47 = wrap_len_index_end > 6'h8; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_49; // @[MemLoader.scala:151:77] assign _use_this_queue_T_49 = _GEN_47; // @[MemLoader.scala:151:77] wire _use_this_queue_T_52; // @[MemLoader.scala:152:77] assign _use_this_queue_T_52 = _GEN_47; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_50 = _use_this_queue_T_48 | _use_this_queue_T_49; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_48 = write_start_index < 6'hA; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_54; // @[MemLoader.scala:151:41] assign _use_this_queue_T_54 = _GEN_48; // @[MemLoader.scala:151:41] wire _use_this_queue_T_57; // @[MemLoader.scala:152:41] assign _use_this_queue_T_57 = _GEN_48; // @[MemLoader.scala:151:41, :152:41] wire _GEN_49 = wrap_len_index_end > 6'h9; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_55; // @[MemLoader.scala:151:77] assign _use_this_queue_T_55 = _GEN_49; // @[MemLoader.scala:151:77] wire _use_this_queue_T_58; // @[MemLoader.scala:152:77] assign _use_this_queue_T_58 = _GEN_49; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_56 = _use_this_queue_T_54 | _use_this_queue_T_55; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_50 = write_start_index < 6'hB; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_60; // @[MemLoader.scala:151:41] assign _use_this_queue_T_60 = _GEN_50; // @[MemLoader.scala:151:41] wire _use_this_queue_T_63; // @[MemLoader.scala:152:41] assign _use_this_queue_T_63 = _GEN_50; // @[MemLoader.scala:151:41, :152:41] wire _GEN_51 = wrap_len_index_end > 6'hA; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_61; // @[MemLoader.scala:151:77] assign _use_this_queue_T_61 = _GEN_51; // @[MemLoader.scala:151:77] wire _use_this_queue_T_64; // @[MemLoader.scala:152:77] assign _use_this_queue_T_64 = _GEN_51; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_62 = _use_this_queue_T_60 | _use_this_queue_T_61; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_52 = write_start_index < 6'hC; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_66; // @[MemLoader.scala:151:41] assign _use_this_queue_T_66 = _GEN_52; // @[MemLoader.scala:151:41] wire _use_this_queue_T_69; // @[MemLoader.scala:152:41] assign _use_this_queue_T_69 = _GEN_52; // @[MemLoader.scala:151:41, :152:41] wire _GEN_53 = wrap_len_index_end > 6'hB; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_67; // @[MemLoader.scala:151:77] assign _use_this_queue_T_67 = _GEN_53; // @[MemLoader.scala:151:77] wire _use_this_queue_T_70; // @[MemLoader.scala:152:77] assign _use_this_queue_T_70 = _GEN_53; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_68 = _use_this_queue_T_66 | _use_this_queue_T_67; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_54 = write_start_index < 6'hD; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_72; // @[MemLoader.scala:151:41] assign _use_this_queue_T_72 = _GEN_54; // @[MemLoader.scala:151:41] wire _use_this_queue_T_75; // @[MemLoader.scala:152:41] assign _use_this_queue_T_75 = _GEN_54; // @[MemLoader.scala:151:41, :152:41] wire _GEN_55 = wrap_len_index_end > 6'hC; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_73; // @[MemLoader.scala:151:77] assign _use_this_queue_T_73 = _GEN_55; // @[MemLoader.scala:151:77] wire _use_this_queue_T_76; // @[MemLoader.scala:152:77] assign _use_this_queue_T_76 = _GEN_55; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_74 = _use_this_queue_T_72 | _use_this_queue_T_73; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_56 = write_start_index < 6'hE; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_78; // @[MemLoader.scala:151:41] assign _use_this_queue_T_78 = _GEN_56; // @[MemLoader.scala:151:41] wire _use_this_queue_T_81; // @[MemLoader.scala:152:41] assign _use_this_queue_T_81 = _GEN_56; // @[MemLoader.scala:151:41, :152:41] wire _GEN_57 = wrap_len_index_end > 6'hD; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_79; // @[MemLoader.scala:151:77] assign _use_this_queue_T_79 = _GEN_57; // @[MemLoader.scala:151:77] wire _use_this_queue_T_82; // @[MemLoader.scala:152:77] assign _use_this_queue_T_82 = _GEN_57; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_80 = _use_this_queue_T_78 | _use_this_queue_T_79; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_58 = write_start_index < 6'hF; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_84; // @[MemLoader.scala:151:41] assign _use_this_queue_T_84 = _GEN_58; // @[MemLoader.scala:151:41] wire _use_this_queue_T_87; // @[MemLoader.scala:152:41] assign _use_this_queue_T_87 = _GEN_58; // @[MemLoader.scala:151:41, :152:41] wire _GEN_59 = wrap_len_index_end > 6'hE; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_85; // @[MemLoader.scala:151:77] assign _use_this_queue_T_85 = _GEN_59; // @[MemLoader.scala:151:77] wire _use_this_queue_T_88; // @[MemLoader.scala:152:77] assign _use_this_queue_T_88 = _GEN_59; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_86 = _use_this_queue_T_84 | _use_this_queue_T_85; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_60 = write_start_index < 6'h10; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_90; // @[MemLoader.scala:151:41] assign _use_this_queue_T_90 = _GEN_60; // @[MemLoader.scala:151:41] wire _use_this_queue_T_93; // @[MemLoader.scala:152:41] assign _use_this_queue_T_93 = _GEN_60; // @[MemLoader.scala:151:41, :152:41] wire _use_this_queue_T_91 = |(wrap_len_index_end[5:4]); // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_92 = _use_this_queue_T_90 | _use_this_queue_T_91; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_94 = |(wrap_len_index_end[5:4]); // @[MemLoader.scala:127:48, :151:77, :152:77] wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_61 = write_start_index < 6'h11; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_96; // @[MemLoader.scala:151:41] assign _use_this_queue_T_96 = _GEN_61; // @[MemLoader.scala:151:41] wire _use_this_queue_T_99; // @[MemLoader.scala:152:41] assign _use_this_queue_T_99 = _GEN_61; // @[MemLoader.scala:151:41, :152:41] wire _GEN_62 = wrap_len_index_end > 6'h10; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_97; // @[MemLoader.scala:151:77] assign _use_this_queue_T_97 = _GEN_62; // @[MemLoader.scala:151:77] wire _use_this_queue_T_100; // @[MemLoader.scala:152:77] assign _use_this_queue_T_100 = _GEN_62; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_98 = _use_this_queue_T_96 | _use_this_queue_T_97; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_63 = write_start_index < 6'h12; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_102; // @[MemLoader.scala:151:41] assign _use_this_queue_T_102 = _GEN_63; // @[MemLoader.scala:151:41] wire _use_this_queue_T_105; // @[MemLoader.scala:152:41] assign _use_this_queue_T_105 = _GEN_63; // @[MemLoader.scala:151:41, :152:41] wire _GEN_64 = wrap_len_index_end > 6'h11; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_103; // @[MemLoader.scala:151:77] assign _use_this_queue_T_103 = _GEN_64; // @[MemLoader.scala:151:77] wire _use_this_queue_T_106; // @[MemLoader.scala:152:77] assign _use_this_queue_T_106 = _GEN_64; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_104 = _use_this_queue_T_102 | _use_this_queue_T_103; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_65 = write_start_index < 6'h13; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_108; // @[MemLoader.scala:151:41] assign _use_this_queue_T_108 = _GEN_65; // @[MemLoader.scala:151:41] wire _use_this_queue_T_111; // @[MemLoader.scala:152:41] assign _use_this_queue_T_111 = _GEN_65; // @[MemLoader.scala:151:41, :152:41] wire _GEN_66 = wrap_len_index_end > 6'h12; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_109; // @[MemLoader.scala:151:77] assign _use_this_queue_T_109 = _GEN_66; // @[MemLoader.scala:151:77] wire _use_this_queue_T_112; // @[MemLoader.scala:152:77] assign _use_this_queue_T_112 = _GEN_66; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_110 = _use_this_queue_T_108 | _use_this_queue_T_109; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_67 = write_start_index < 6'h14; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_114; // @[MemLoader.scala:151:41] assign _use_this_queue_T_114 = _GEN_67; // @[MemLoader.scala:151:41] wire _use_this_queue_T_117; // @[MemLoader.scala:152:41] assign _use_this_queue_T_117 = _GEN_67; // @[MemLoader.scala:151:41, :152:41] wire _GEN_68 = wrap_len_index_end > 6'h13; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_115; // @[MemLoader.scala:151:77] assign _use_this_queue_T_115 = _GEN_68; // @[MemLoader.scala:151:77] wire _use_this_queue_T_118; // @[MemLoader.scala:152:77] assign _use_this_queue_T_118 = _GEN_68; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_116 = _use_this_queue_T_114 | _use_this_queue_T_115; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_69 = write_start_index < 6'h15; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_120; // @[MemLoader.scala:151:41] assign _use_this_queue_T_120 = _GEN_69; // @[MemLoader.scala:151:41] wire _use_this_queue_T_123; // @[MemLoader.scala:152:41] assign _use_this_queue_T_123 = _GEN_69; // @[MemLoader.scala:151:41, :152:41] wire _GEN_70 = wrap_len_index_end > 6'h14; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_121; // @[MemLoader.scala:151:77] assign _use_this_queue_T_121 = _GEN_70; // @[MemLoader.scala:151:77] wire _use_this_queue_T_124; // @[MemLoader.scala:152:77] assign _use_this_queue_T_124 = _GEN_70; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_122 = _use_this_queue_T_120 | _use_this_queue_T_121; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_71 = write_start_index < 6'h16; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_126; // @[MemLoader.scala:151:41] assign _use_this_queue_T_126 = _GEN_71; // @[MemLoader.scala:151:41] wire _use_this_queue_T_129; // @[MemLoader.scala:152:41] assign _use_this_queue_T_129 = _GEN_71; // @[MemLoader.scala:151:41, :152:41] wire _GEN_72 = wrap_len_index_end > 6'h15; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_127; // @[MemLoader.scala:151:77] assign _use_this_queue_T_127 = _GEN_72; // @[MemLoader.scala:151:77] wire _use_this_queue_T_130; // @[MemLoader.scala:152:77] assign _use_this_queue_T_130 = _GEN_72; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_128 = _use_this_queue_T_126 | _use_this_queue_T_127; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_73 = write_start_index < 6'h17; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_132; // @[MemLoader.scala:151:41] assign _use_this_queue_T_132 = _GEN_73; // @[MemLoader.scala:151:41] wire _use_this_queue_T_135; // @[MemLoader.scala:152:41] assign _use_this_queue_T_135 = _GEN_73; // @[MemLoader.scala:151:41, :152:41] wire _GEN_74 = wrap_len_index_end > 6'h16; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_133; // @[MemLoader.scala:151:77] assign _use_this_queue_T_133 = _GEN_74; // @[MemLoader.scala:151:77] wire _use_this_queue_T_136; // @[MemLoader.scala:152:77] assign _use_this_queue_T_136 = _GEN_74; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_134 = _use_this_queue_T_132 | _use_this_queue_T_133; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_75 = write_start_index < 6'h18; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_138; // @[MemLoader.scala:151:41] assign _use_this_queue_T_138 = _GEN_75; // @[MemLoader.scala:151:41] wire _use_this_queue_T_141; // @[MemLoader.scala:152:41] assign _use_this_queue_T_141 = _GEN_75; // @[MemLoader.scala:151:41, :152:41] wire _GEN_76 = wrap_len_index_end > 6'h17; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_139; // @[MemLoader.scala:151:77] assign _use_this_queue_T_139 = _GEN_76; // @[MemLoader.scala:151:77] wire _use_this_queue_T_142; // @[MemLoader.scala:152:77] assign _use_this_queue_T_142 = _GEN_76; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_140 = _use_this_queue_T_138 | _use_this_queue_T_139; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_77 = write_start_index < 6'h19; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_144; // @[MemLoader.scala:151:41] assign _use_this_queue_T_144 = _GEN_77; // @[MemLoader.scala:151:41] wire _use_this_queue_T_147; // @[MemLoader.scala:152:41] assign _use_this_queue_T_147 = _GEN_77; // @[MemLoader.scala:151:41, :152:41] wire _GEN_78 = wrap_len_index_end > 6'h18; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_145; // @[MemLoader.scala:151:77] assign _use_this_queue_T_145 = _GEN_78; // @[MemLoader.scala:151:77] wire _use_this_queue_T_148; // @[MemLoader.scala:152:77] assign _use_this_queue_T_148 = _GEN_78; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_146 = _use_this_queue_T_144 | _use_this_queue_T_145; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_79 = write_start_index < 6'h1A; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_150; // @[MemLoader.scala:151:41] assign _use_this_queue_T_150 = _GEN_79; // @[MemLoader.scala:151:41] wire _use_this_queue_T_153; // @[MemLoader.scala:152:41] assign _use_this_queue_T_153 = _GEN_79; // @[MemLoader.scala:151:41, :152:41] wire _GEN_80 = wrap_len_index_end > 6'h19; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_151; // @[MemLoader.scala:151:77] assign _use_this_queue_T_151 = _GEN_80; // @[MemLoader.scala:151:77] wire _use_this_queue_T_154; // @[MemLoader.scala:152:77] assign _use_this_queue_T_154 = _GEN_80; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_152 = _use_this_queue_T_150 | _use_this_queue_T_151; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_81 = write_start_index < 6'h1B; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_156; // @[MemLoader.scala:151:41] assign _use_this_queue_T_156 = _GEN_81; // @[MemLoader.scala:151:41] wire _use_this_queue_T_159; // @[MemLoader.scala:152:41] assign _use_this_queue_T_159 = _GEN_81; // @[MemLoader.scala:151:41, :152:41] wire _GEN_82 = wrap_len_index_end > 6'h1A; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_157; // @[MemLoader.scala:151:77] assign _use_this_queue_T_157 = _GEN_82; // @[MemLoader.scala:151:77] wire _use_this_queue_T_160; // @[MemLoader.scala:152:77] assign _use_this_queue_T_160 = _GEN_82; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_158 = _use_this_queue_T_156 | _use_this_queue_T_157; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_83 = write_start_index < 6'h1C; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_162; // @[MemLoader.scala:151:41] assign _use_this_queue_T_162 = _GEN_83; // @[MemLoader.scala:151:41] wire _use_this_queue_T_165; // @[MemLoader.scala:152:41] assign _use_this_queue_T_165 = _GEN_83; // @[MemLoader.scala:151:41, :152:41] wire _GEN_84 = wrap_len_index_end > 6'h1B; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_163; // @[MemLoader.scala:151:77] assign _use_this_queue_T_163 = _GEN_84; // @[MemLoader.scala:151:77] wire _use_this_queue_T_166; // @[MemLoader.scala:152:77] assign _use_this_queue_T_166 = _GEN_84; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_164 = _use_this_queue_T_162 | _use_this_queue_T_163; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_85 = write_start_index < 6'h1D; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_168; // @[MemLoader.scala:151:41] assign _use_this_queue_T_168 = _GEN_85; // @[MemLoader.scala:151:41] wire _use_this_queue_T_171; // @[MemLoader.scala:152:41] assign _use_this_queue_T_171 = _GEN_85; // @[MemLoader.scala:151:41, :152:41] wire _GEN_86 = wrap_len_index_end > 6'h1C; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_169; // @[MemLoader.scala:151:77] assign _use_this_queue_T_169 = _GEN_86; // @[MemLoader.scala:151:77] wire _use_this_queue_T_172; // @[MemLoader.scala:152:77] assign _use_this_queue_T_172 = _GEN_86; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_170 = _use_this_queue_T_168 | _use_this_queue_T_169; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_87 = write_start_index < 6'h1E; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_174; // @[MemLoader.scala:151:41] assign _use_this_queue_T_174 = _GEN_87; // @[MemLoader.scala:151:41] wire _use_this_queue_T_177; // @[MemLoader.scala:152:41] assign _use_this_queue_T_177 = _GEN_87; // @[MemLoader.scala:151:41, :152:41] wire _GEN_88 = wrap_len_index_end > 6'h1D; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_175; // @[MemLoader.scala:151:77] assign _use_this_queue_T_175 = _GEN_88; // @[MemLoader.scala:151:77] wire _use_this_queue_T_178; // @[MemLoader.scala:152:77] assign _use_this_queue_T_178 = _GEN_88; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_176 = _use_this_queue_T_174 | _use_this_queue_T_175; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_89 = write_start_index < 6'h1F; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_180; // @[MemLoader.scala:151:41] assign _use_this_queue_T_180 = _GEN_89; // @[MemLoader.scala:151:41] wire _use_this_queue_T_183; // @[MemLoader.scala:152:41] assign _use_this_queue_T_183 = _GEN_89; // @[MemLoader.scala:151:41, :152:41] wire _GEN_90 = wrap_len_index_end > 6'h1E; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_181; // @[MemLoader.scala:151:77] assign _use_this_queue_T_181 = _GEN_90; // @[MemLoader.scala:151:77] wire _use_this_queue_T_184; // @[MemLoader.scala:152:77] assign _use_this_queue_T_184 = _GEN_90; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_182 = _use_this_queue_T_180 | _use_this_queue_T_181; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[MemLoader.scala:127:48, :151:77, :152:77] wire _use_this_queue_T_188 = _use_this_queue_T_186 | _use_this_queue_T_187; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[MemLoader.scala:105:34, :151:41, :152:41] wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_38; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_76 = {1'h0, loginfo_cycles_38} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_77 = _loginfo_cycles_T_76[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_39; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_78 = {1'h0, loginfo_cycles_39} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_79 = _loginfo_cycles_T_78[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_40; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_80 = {1'h0, loginfo_cycles_40} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_81 = _loginfo_cycles_T_80[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_41; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_82 = {1'h0, loginfo_cycles_41} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_83 = _loginfo_cycles_T_82[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_42; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_84 = {1'h0, loginfo_cycles_42} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_85 = _loginfo_cycles_T_84[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_43; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_86 = {1'h0, loginfo_cycles_43} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_87 = _loginfo_cycles_T_86[63:0]; // @[Util.scala:19:38] reg [5:0] read_start_index; // @[MemLoader.scala:163:33] reg [63:0] len_already_consumed; // @[MemLoader.scala:164:37] wire [7:0] remapVecData_0; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_1; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_2; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_3; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_4; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_5; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_6; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_7; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_8; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_9; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_10; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_11; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_12; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_13; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_14; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_15; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_16; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_17; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_18; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_19; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_20; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_21; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_22; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_23; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_24; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_25; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_26; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_27; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_28; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_29; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_30; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_31; // @[MemLoader.scala:166:26] wire remapVecValids_0; // @[MemLoader.scala:167:28] wire remapVecValids_1; // @[MemLoader.scala:167:28] wire remapVecValids_2; // @[MemLoader.scala:167:28] wire remapVecValids_3; // @[MemLoader.scala:167:28] wire remapVecValids_4; // @[MemLoader.scala:167:28] wire remapVecValids_5; // @[MemLoader.scala:167:28] wire remapVecValids_6; // @[MemLoader.scala:167:28] wire remapVecValids_7; // @[MemLoader.scala:167:28] wire remapVecValids_8; // @[MemLoader.scala:167:28] wire remapVecValids_9; // @[MemLoader.scala:167:28] wire remapVecValids_10; // @[MemLoader.scala:167:28] wire remapVecValids_11; // @[MemLoader.scala:167:28] wire remapVecValids_12; // @[MemLoader.scala:167:28] wire remapVecValids_13; // @[MemLoader.scala:167:28] wire remapVecValids_14; // @[MemLoader.scala:167:28] wire remapVecValids_15; // @[MemLoader.scala:167:28] wire remapVecValids_16; // @[MemLoader.scala:167:28] wire remapVecValids_17; // @[MemLoader.scala:167:28] wire remapVecValids_18; // @[MemLoader.scala:167:28] wire remapVecValids_19; // @[MemLoader.scala:167:28] wire remapVecValids_20; // @[MemLoader.scala:167:28] wire remapVecValids_21; // @[MemLoader.scala:167:28] wire remapVecValids_22; // @[MemLoader.scala:167:28] wire remapVecValids_23; // @[MemLoader.scala:167:28] wire remapVecValids_24; // @[MemLoader.scala:167:28] wire remapVecValids_25; // @[MemLoader.scala:167:28] wire remapVecValids_26; // @[MemLoader.scala:167:28] wire remapVecValids_27; // @[MemLoader.scala:167:28] wire remapVecValids_28; // @[MemLoader.scala:167:28] wire remapVecValids_29; // @[MemLoader.scala:167:28] wire remapVecValids_30; // @[MemLoader.scala:167:28] wire remapVecValids_31; // @[MemLoader.scala:167:28] wire _remapVecReadys_0_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_1_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_2_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_3_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_4_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_5_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_6_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_7_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_8_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_9_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_10_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_11_T_3; // @[MemLoader.scala:217:78] wire remapVecReadys_0; // @[MemLoader.scala:168:28] wire remapVecReadys_1; // @[MemLoader.scala:168:28] wire remapVecReadys_2; // @[MemLoader.scala:168:28] wire remapVecReadys_3; // @[MemLoader.scala:168:28] wire remapVecReadys_4; // @[MemLoader.scala:168:28] wire remapVecReadys_5; // @[MemLoader.scala:168:28] wire remapVecReadys_6; // @[MemLoader.scala:168:28] wire remapVecReadys_7; // @[MemLoader.scala:168:28] wire remapVecReadys_8; // @[MemLoader.scala:168:28] wire remapVecReadys_9; // @[MemLoader.scala:168:28] wire remapVecReadys_10; // @[MemLoader.scala:168:28] wire remapVecReadys_11; // @[MemLoader.scala:168:28] wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[MemLoader.scala:163:33, :177:33] wire [6:0] _GEN_91 = _remapindex_T % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex = _GEN_91[5:0]; // @[MemLoader.scala:177:54] wire _T_2330 = remapindex == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2331 = remapindex == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2332 = remapindex == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2333 = remapindex == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2334 = remapindex == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2335 = remapindex == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2336 = remapindex == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2337 = remapindex == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2338 = remapindex == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2339 = remapindex == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2340 = remapindex == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2341 = remapindex == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2342 = remapindex == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2343 = remapindex == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2344 = remapindex == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2345 = remapindex == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2346 = remapindex == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2347 = remapindex == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2348 = remapindex == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2349 = remapindex == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2350 = remapindex == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2351 = remapindex == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2352 = remapindex == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2353 = remapindex == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2354 = remapindex == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2355 = remapindex == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2356 = remapindex == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2357 = remapindex == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2358 = remapindex == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2359 = remapindex == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2360 = remapindex == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2361 = remapindex == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_0 = _T_2361 ? _Queue64_UInt8_31_io_deq_bits : _T_2360 ? _Queue64_UInt8_30_io_deq_bits : _T_2359 ? _Queue64_UInt8_29_io_deq_bits : _T_2358 ? _Queue64_UInt8_28_io_deq_bits : _T_2357 ? _Queue64_UInt8_27_io_deq_bits : _T_2356 ? _Queue64_UInt8_26_io_deq_bits : _T_2355 ? _Queue64_UInt8_25_io_deq_bits : _T_2354 ? _Queue64_UInt8_24_io_deq_bits : _T_2353 ? _Queue64_UInt8_23_io_deq_bits : _T_2352 ? _Queue64_UInt8_22_io_deq_bits : _T_2351 ? _Queue64_UInt8_21_io_deq_bits : _T_2350 ? _Queue64_UInt8_20_io_deq_bits : _T_2349 ? _Queue64_UInt8_19_io_deq_bits : _T_2348 ? _Queue64_UInt8_18_io_deq_bits : _T_2347 ? _Queue64_UInt8_17_io_deq_bits : _T_2346 ? _Queue64_UInt8_16_io_deq_bits : _T_2345 ? _Queue64_UInt8_15_io_deq_bits : _T_2344 ? _Queue64_UInt8_14_io_deq_bits : _T_2343 ? _Queue64_UInt8_13_io_deq_bits : _T_2342 ? _Queue64_UInt8_12_io_deq_bits : _T_2341 ? _Queue64_UInt8_11_io_deq_bits : _T_2340 ? _Queue64_UInt8_10_io_deq_bits : _T_2339 ? _Queue64_UInt8_9_io_deq_bits : _T_2338 ? _Queue64_UInt8_8_io_deq_bits : _T_2337 ? _Queue64_UInt8_7_io_deq_bits : _T_2336 ? _Queue64_UInt8_6_io_deq_bits : _T_2335 ? _Queue64_UInt8_5_io_deq_bits : _T_2334 ? _Queue64_UInt8_4_io_deq_bits : _T_2333 ? _Queue64_UInt8_3_io_deq_bits : _T_2332 ? _Queue64_UInt8_2_io_deq_bits : _T_2331 ? _Queue64_UInt8_1_io_deq_bits : _T_2330 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_0 = _T_2361 ? _Queue64_UInt8_31_io_deq_valid : _T_2360 ? _Queue64_UInt8_30_io_deq_valid : _T_2359 ? _Queue64_UInt8_29_io_deq_valid : _T_2358 ? _Queue64_UInt8_28_io_deq_valid : _T_2357 ? _Queue64_UInt8_27_io_deq_valid : _T_2356 ? _Queue64_UInt8_26_io_deq_valid : _T_2355 ? _Queue64_UInt8_25_io_deq_valid : _T_2354 ? _Queue64_UInt8_24_io_deq_valid : _T_2353 ? _Queue64_UInt8_23_io_deq_valid : _T_2352 ? _Queue64_UInt8_22_io_deq_valid : _T_2351 ? _Queue64_UInt8_21_io_deq_valid : _T_2350 ? _Queue64_UInt8_20_io_deq_valid : _T_2349 ? _Queue64_UInt8_19_io_deq_valid : _T_2348 ? _Queue64_UInt8_18_io_deq_valid : _T_2347 ? _Queue64_UInt8_17_io_deq_valid : _T_2346 ? _Queue64_UInt8_16_io_deq_valid : _T_2345 ? _Queue64_UInt8_15_io_deq_valid : _T_2344 ? _Queue64_UInt8_14_io_deq_valid : _T_2343 ? _Queue64_UInt8_13_io_deq_valid : _T_2342 ? _Queue64_UInt8_12_io_deq_valid : _T_2341 ? _Queue64_UInt8_11_io_deq_valid : _T_2340 ? _Queue64_UInt8_10_io_deq_valid : _T_2339 ? _Queue64_UInt8_9_io_deq_valid : _T_2338 ? _Queue64_UInt8_8_io_deq_valid : _T_2337 ? _Queue64_UInt8_7_io_deq_valid : _T_2336 ? _Queue64_UInt8_6_io_deq_valid : _T_2335 ? _Queue64_UInt8_5_io_deq_valid : _T_2334 ? _Queue64_UInt8_4_io_deq_valid : _T_2333 ? _Queue64_UInt8_3_io_deq_valid : _T_2332 ? _Queue64_UInt8_2_io_deq_valid : _T_2331 ? _Queue64_UInt8_1_io_deq_valid : _T_2330 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[MemLoader.scala:177:33] wire [6:0] _GEN_92 = _remapindex_T_1 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_1 = _GEN_92[5:0]; // @[MemLoader.scala:177:54] wire _T_2362 = remapindex_1 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2363 = remapindex_1 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2364 = remapindex_1 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2365 = remapindex_1 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2366 = remapindex_1 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2367 = remapindex_1 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2368 = remapindex_1 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2369 = remapindex_1 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2370 = remapindex_1 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2371 = remapindex_1 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2372 = remapindex_1 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2373 = remapindex_1 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2374 = remapindex_1 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2375 = remapindex_1 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2376 = remapindex_1 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2377 = remapindex_1 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2378 = remapindex_1 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2379 = remapindex_1 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2380 = remapindex_1 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2381 = remapindex_1 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2382 = remapindex_1 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2383 = remapindex_1 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2384 = remapindex_1 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2385 = remapindex_1 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2386 = remapindex_1 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2387 = remapindex_1 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2388 = remapindex_1 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2389 = remapindex_1 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2390 = remapindex_1 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2391 = remapindex_1 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2392 = remapindex_1 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2393 = remapindex_1 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_1 = _T_2393 ? _Queue64_UInt8_31_io_deq_bits : _T_2392 ? _Queue64_UInt8_30_io_deq_bits : _T_2391 ? _Queue64_UInt8_29_io_deq_bits : _T_2390 ? _Queue64_UInt8_28_io_deq_bits : _T_2389 ? _Queue64_UInt8_27_io_deq_bits : _T_2388 ? _Queue64_UInt8_26_io_deq_bits : _T_2387 ? _Queue64_UInt8_25_io_deq_bits : _T_2386 ? _Queue64_UInt8_24_io_deq_bits : _T_2385 ? _Queue64_UInt8_23_io_deq_bits : _T_2384 ? _Queue64_UInt8_22_io_deq_bits : _T_2383 ? _Queue64_UInt8_21_io_deq_bits : _T_2382 ? _Queue64_UInt8_20_io_deq_bits : _T_2381 ? _Queue64_UInt8_19_io_deq_bits : _T_2380 ? _Queue64_UInt8_18_io_deq_bits : _T_2379 ? _Queue64_UInt8_17_io_deq_bits : _T_2378 ? _Queue64_UInt8_16_io_deq_bits : _T_2377 ? _Queue64_UInt8_15_io_deq_bits : _T_2376 ? _Queue64_UInt8_14_io_deq_bits : _T_2375 ? _Queue64_UInt8_13_io_deq_bits : _T_2374 ? _Queue64_UInt8_12_io_deq_bits : _T_2373 ? _Queue64_UInt8_11_io_deq_bits : _T_2372 ? _Queue64_UInt8_10_io_deq_bits : _T_2371 ? _Queue64_UInt8_9_io_deq_bits : _T_2370 ? _Queue64_UInt8_8_io_deq_bits : _T_2369 ? _Queue64_UInt8_7_io_deq_bits : _T_2368 ? _Queue64_UInt8_6_io_deq_bits : _T_2367 ? _Queue64_UInt8_5_io_deq_bits : _T_2366 ? _Queue64_UInt8_4_io_deq_bits : _T_2365 ? _Queue64_UInt8_3_io_deq_bits : _T_2364 ? _Queue64_UInt8_2_io_deq_bits : _T_2363 ? _Queue64_UInt8_1_io_deq_bits : _T_2362 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_1 = _T_2393 ? _Queue64_UInt8_31_io_deq_valid : _T_2392 ? _Queue64_UInt8_30_io_deq_valid : _T_2391 ? _Queue64_UInt8_29_io_deq_valid : _T_2390 ? _Queue64_UInt8_28_io_deq_valid : _T_2389 ? _Queue64_UInt8_27_io_deq_valid : _T_2388 ? _Queue64_UInt8_26_io_deq_valid : _T_2387 ? _Queue64_UInt8_25_io_deq_valid : _T_2386 ? _Queue64_UInt8_24_io_deq_valid : _T_2385 ? _Queue64_UInt8_23_io_deq_valid : _T_2384 ? _Queue64_UInt8_22_io_deq_valid : _T_2383 ? _Queue64_UInt8_21_io_deq_valid : _T_2382 ? _Queue64_UInt8_20_io_deq_valid : _T_2381 ? _Queue64_UInt8_19_io_deq_valid : _T_2380 ? _Queue64_UInt8_18_io_deq_valid : _T_2379 ? _Queue64_UInt8_17_io_deq_valid : _T_2378 ? _Queue64_UInt8_16_io_deq_valid : _T_2377 ? _Queue64_UInt8_15_io_deq_valid : _T_2376 ? _Queue64_UInt8_14_io_deq_valid : _T_2375 ? _Queue64_UInt8_13_io_deq_valid : _T_2374 ? _Queue64_UInt8_12_io_deq_valid : _T_2373 ? _Queue64_UInt8_11_io_deq_valid : _T_2372 ? _Queue64_UInt8_10_io_deq_valid : _T_2371 ? _Queue64_UInt8_9_io_deq_valid : _T_2370 ? _Queue64_UInt8_8_io_deq_valid : _T_2369 ? _Queue64_UInt8_7_io_deq_valid : _T_2368 ? _Queue64_UInt8_6_io_deq_valid : _T_2367 ? _Queue64_UInt8_5_io_deq_valid : _T_2366 ? _Queue64_UInt8_4_io_deq_valid : _T_2365 ? _Queue64_UInt8_3_io_deq_valid : _T_2364 ? _Queue64_UInt8_2_io_deq_valid : _T_2363 ? _Queue64_UInt8_1_io_deq_valid : _T_2362 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[MemLoader.scala:177:33] wire [6:0] _GEN_93 = _remapindex_T_2 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_2 = _GEN_93[5:0]; // @[MemLoader.scala:177:54] wire _T_2394 = remapindex_2 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2395 = remapindex_2 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2396 = remapindex_2 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2397 = remapindex_2 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2398 = remapindex_2 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2399 = remapindex_2 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2400 = remapindex_2 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2401 = remapindex_2 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2402 = remapindex_2 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2403 = remapindex_2 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2404 = remapindex_2 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2405 = remapindex_2 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2406 = remapindex_2 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2407 = remapindex_2 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2408 = remapindex_2 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2409 = remapindex_2 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2410 = remapindex_2 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2411 = remapindex_2 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2412 = remapindex_2 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2413 = remapindex_2 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2414 = remapindex_2 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2415 = remapindex_2 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2416 = remapindex_2 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2417 = remapindex_2 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2418 = remapindex_2 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2419 = remapindex_2 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2420 = remapindex_2 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2421 = remapindex_2 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2422 = remapindex_2 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2423 = remapindex_2 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2424 = remapindex_2 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2425 = remapindex_2 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_2 = _T_2425 ? _Queue64_UInt8_31_io_deq_bits : _T_2424 ? _Queue64_UInt8_30_io_deq_bits : _T_2423 ? _Queue64_UInt8_29_io_deq_bits : _T_2422 ? _Queue64_UInt8_28_io_deq_bits : _T_2421 ? _Queue64_UInt8_27_io_deq_bits : _T_2420 ? _Queue64_UInt8_26_io_deq_bits : _T_2419 ? _Queue64_UInt8_25_io_deq_bits : _T_2418 ? _Queue64_UInt8_24_io_deq_bits : _T_2417 ? _Queue64_UInt8_23_io_deq_bits : _T_2416 ? _Queue64_UInt8_22_io_deq_bits : _T_2415 ? _Queue64_UInt8_21_io_deq_bits : _T_2414 ? _Queue64_UInt8_20_io_deq_bits : _T_2413 ? _Queue64_UInt8_19_io_deq_bits : _T_2412 ? _Queue64_UInt8_18_io_deq_bits : _T_2411 ? _Queue64_UInt8_17_io_deq_bits : _T_2410 ? _Queue64_UInt8_16_io_deq_bits : _T_2409 ? _Queue64_UInt8_15_io_deq_bits : _T_2408 ? _Queue64_UInt8_14_io_deq_bits : _T_2407 ? _Queue64_UInt8_13_io_deq_bits : _T_2406 ? _Queue64_UInt8_12_io_deq_bits : _T_2405 ? _Queue64_UInt8_11_io_deq_bits : _T_2404 ? _Queue64_UInt8_10_io_deq_bits : _T_2403 ? _Queue64_UInt8_9_io_deq_bits : _T_2402 ? _Queue64_UInt8_8_io_deq_bits : _T_2401 ? _Queue64_UInt8_7_io_deq_bits : _T_2400 ? _Queue64_UInt8_6_io_deq_bits : _T_2399 ? _Queue64_UInt8_5_io_deq_bits : _T_2398 ? _Queue64_UInt8_4_io_deq_bits : _T_2397 ? _Queue64_UInt8_3_io_deq_bits : _T_2396 ? _Queue64_UInt8_2_io_deq_bits : _T_2395 ? _Queue64_UInt8_1_io_deq_bits : _T_2394 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_2 = _T_2425 ? _Queue64_UInt8_31_io_deq_valid : _T_2424 ? _Queue64_UInt8_30_io_deq_valid : _T_2423 ? _Queue64_UInt8_29_io_deq_valid : _T_2422 ? _Queue64_UInt8_28_io_deq_valid : _T_2421 ? _Queue64_UInt8_27_io_deq_valid : _T_2420 ? _Queue64_UInt8_26_io_deq_valid : _T_2419 ? _Queue64_UInt8_25_io_deq_valid : _T_2418 ? _Queue64_UInt8_24_io_deq_valid : _T_2417 ? _Queue64_UInt8_23_io_deq_valid : _T_2416 ? _Queue64_UInt8_22_io_deq_valid : _T_2415 ? _Queue64_UInt8_21_io_deq_valid : _T_2414 ? _Queue64_UInt8_20_io_deq_valid : _T_2413 ? _Queue64_UInt8_19_io_deq_valid : _T_2412 ? _Queue64_UInt8_18_io_deq_valid : _T_2411 ? _Queue64_UInt8_17_io_deq_valid : _T_2410 ? _Queue64_UInt8_16_io_deq_valid : _T_2409 ? _Queue64_UInt8_15_io_deq_valid : _T_2408 ? _Queue64_UInt8_14_io_deq_valid : _T_2407 ? _Queue64_UInt8_13_io_deq_valid : _T_2406 ? _Queue64_UInt8_12_io_deq_valid : _T_2405 ? _Queue64_UInt8_11_io_deq_valid : _T_2404 ? _Queue64_UInt8_10_io_deq_valid : _T_2403 ? _Queue64_UInt8_9_io_deq_valid : _T_2402 ? _Queue64_UInt8_8_io_deq_valid : _T_2401 ? _Queue64_UInt8_7_io_deq_valid : _T_2400 ? _Queue64_UInt8_6_io_deq_valid : _T_2399 ? _Queue64_UInt8_5_io_deq_valid : _T_2398 ? _Queue64_UInt8_4_io_deq_valid : _T_2397 ? _Queue64_UInt8_3_io_deq_valid : _T_2396 ? _Queue64_UInt8_2_io_deq_valid : _T_2395 ? _Queue64_UInt8_1_io_deq_valid : _T_2394 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[MemLoader.scala:177:33] wire [6:0] _GEN_94 = _remapindex_T_3 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_3 = _GEN_94[5:0]; // @[MemLoader.scala:177:54] wire _T_2426 = remapindex_3 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2427 = remapindex_3 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2428 = remapindex_3 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2429 = remapindex_3 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2430 = remapindex_3 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2431 = remapindex_3 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2432 = remapindex_3 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2433 = remapindex_3 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2434 = remapindex_3 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2435 = remapindex_3 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2436 = remapindex_3 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2437 = remapindex_3 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2438 = remapindex_3 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2439 = remapindex_3 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2440 = remapindex_3 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2441 = remapindex_3 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2442 = remapindex_3 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2443 = remapindex_3 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2444 = remapindex_3 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2445 = remapindex_3 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2446 = remapindex_3 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2447 = remapindex_3 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2448 = remapindex_3 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2449 = remapindex_3 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2450 = remapindex_3 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2451 = remapindex_3 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2452 = remapindex_3 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2453 = remapindex_3 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2454 = remapindex_3 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2455 = remapindex_3 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2456 = remapindex_3 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2457 = remapindex_3 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_3 = _T_2457 ? _Queue64_UInt8_31_io_deq_bits : _T_2456 ? _Queue64_UInt8_30_io_deq_bits : _T_2455 ? _Queue64_UInt8_29_io_deq_bits : _T_2454 ? _Queue64_UInt8_28_io_deq_bits : _T_2453 ? _Queue64_UInt8_27_io_deq_bits : _T_2452 ? _Queue64_UInt8_26_io_deq_bits : _T_2451 ? _Queue64_UInt8_25_io_deq_bits : _T_2450 ? _Queue64_UInt8_24_io_deq_bits : _T_2449 ? _Queue64_UInt8_23_io_deq_bits : _T_2448 ? _Queue64_UInt8_22_io_deq_bits : _T_2447 ? _Queue64_UInt8_21_io_deq_bits : _T_2446 ? _Queue64_UInt8_20_io_deq_bits : _T_2445 ? _Queue64_UInt8_19_io_deq_bits : _T_2444 ? _Queue64_UInt8_18_io_deq_bits : _T_2443 ? _Queue64_UInt8_17_io_deq_bits : _T_2442 ? _Queue64_UInt8_16_io_deq_bits : _T_2441 ? _Queue64_UInt8_15_io_deq_bits : _T_2440 ? _Queue64_UInt8_14_io_deq_bits : _T_2439 ? _Queue64_UInt8_13_io_deq_bits : _T_2438 ? _Queue64_UInt8_12_io_deq_bits : _T_2437 ? _Queue64_UInt8_11_io_deq_bits : _T_2436 ? _Queue64_UInt8_10_io_deq_bits : _T_2435 ? _Queue64_UInt8_9_io_deq_bits : _T_2434 ? _Queue64_UInt8_8_io_deq_bits : _T_2433 ? _Queue64_UInt8_7_io_deq_bits : _T_2432 ? _Queue64_UInt8_6_io_deq_bits : _T_2431 ? _Queue64_UInt8_5_io_deq_bits : _T_2430 ? _Queue64_UInt8_4_io_deq_bits : _T_2429 ? _Queue64_UInt8_3_io_deq_bits : _T_2428 ? _Queue64_UInt8_2_io_deq_bits : _T_2427 ? _Queue64_UInt8_1_io_deq_bits : _T_2426 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_3 = _T_2457 ? _Queue64_UInt8_31_io_deq_valid : _T_2456 ? _Queue64_UInt8_30_io_deq_valid : _T_2455 ? _Queue64_UInt8_29_io_deq_valid : _T_2454 ? _Queue64_UInt8_28_io_deq_valid : _T_2453 ? _Queue64_UInt8_27_io_deq_valid : _T_2452 ? _Queue64_UInt8_26_io_deq_valid : _T_2451 ? _Queue64_UInt8_25_io_deq_valid : _T_2450 ? _Queue64_UInt8_24_io_deq_valid : _T_2449 ? _Queue64_UInt8_23_io_deq_valid : _T_2448 ? _Queue64_UInt8_22_io_deq_valid : _T_2447 ? _Queue64_UInt8_21_io_deq_valid : _T_2446 ? _Queue64_UInt8_20_io_deq_valid : _T_2445 ? _Queue64_UInt8_19_io_deq_valid : _T_2444 ? _Queue64_UInt8_18_io_deq_valid : _T_2443 ? _Queue64_UInt8_17_io_deq_valid : _T_2442 ? _Queue64_UInt8_16_io_deq_valid : _T_2441 ? _Queue64_UInt8_15_io_deq_valid : _T_2440 ? _Queue64_UInt8_14_io_deq_valid : _T_2439 ? _Queue64_UInt8_13_io_deq_valid : _T_2438 ? _Queue64_UInt8_12_io_deq_valid : _T_2437 ? _Queue64_UInt8_11_io_deq_valid : _T_2436 ? _Queue64_UInt8_10_io_deq_valid : _T_2435 ? _Queue64_UInt8_9_io_deq_valid : _T_2434 ? _Queue64_UInt8_8_io_deq_valid : _T_2433 ? _Queue64_UInt8_7_io_deq_valid : _T_2432 ? _Queue64_UInt8_6_io_deq_valid : _T_2431 ? _Queue64_UInt8_5_io_deq_valid : _T_2430 ? _Queue64_UInt8_4_io_deq_valid : _T_2429 ? _Queue64_UInt8_3_io_deq_valid : _T_2428 ? _Queue64_UInt8_2_io_deq_valid : _T_2427 ? _Queue64_UInt8_1_io_deq_valid : _T_2426 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[MemLoader.scala:177:33] wire [6:0] _GEN_95 = _remapindex_T_4 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_4 = _GEN_95[5:0]; // @[MemLoader.scala:177:54] wire _T_2458 = remapindex_4 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2459 = remapindex_4 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2460 = remapindex_4 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2461 = remapindex_4 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2462 = remapindex_4 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2463 = remapindex_4 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2464 = remapindex_4 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2465 = remapindex_4 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2466 = remapindex_4 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2467 = remapindex_4 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2468 = remapindex_4 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2469 = remapindex_4 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2470 = remapindex_4 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2471 = remapindex_4 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2472 = remapindex_4 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2473 = remapindex_4 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2474 = remapindex_4 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2475 = remapindex_4 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2476 = remapindex_4 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2477 = remapindex_4 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2478 = remapindex_4 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2479 = remapindex_4 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2480 = remapindex_4 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2481 = remapindex_4 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2482 = remapindex_4 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2483 = remapindex_4 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2484 = remapindex_4 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2485 = remapindex_4 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2486 = remapindex_4 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2487 = remapindex_4 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2488 = remapindex_4 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2489 = remapindex_4 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_4 = _T_2489 ? _Queue64_UInt8_31_io_deq_bits : _T_2488 ? _Queue64_UInt8_30_io_deq_bits : _T_2487 ? _Queue64_UInt8_29_io_deq_bits : _T_2486 ? _Queue64_UInt8_28_io_deq_bits : _T_2485 ? _Queue64_UInt8_27_io_deq_bits : _T_2484 ? _Queue64_UInt8_26_io_deq_bits : _T_2483 ? _Queue64_UInt8_25_io_deq_bits : _T_2482 ? _Queue64_UInt8_24_io_deq_bits : _T_2481 ? _Queue64_UInt8_23_io_deq_bits : _T_2480 ? _Queue64_UInt8_22_io_deq_bits : _T_2479 ? _Queue64_UInt8_21_io_deq_bits : _T_2478 ? _Queue64_UInt8_20_io_deq_bits : _T_2477 ? _Queue64_UInt8_19_io_deq_bits : _T_2476 ? _Queue64_UInt8_18_io_deq_bits : _T_2475 ? _Queue64_UInt8_17_io_deq_bits : _T_2474 ? _Queue64_UInt8_16_io_deq_bits : _T_2473 ? _Queue64_UInt8_15_io_deq_bits : _T_2472 ? _Queue64_UInt8_14_io_deq_bits : _T_2471 ? _Queue64_UInt8_13_io_deq_bits : _T_2470 ? _Queue64_UInt8_12_io_deq_bits : _T_2469 ? _Queue64_UInt8_11_io_deq_bits : _T_2468 ? _Queue64_UInt8_10_io_deq_bits : _T_2467 ? _Queue64_UInt8_9_io_deq_bits : _T_2466 ? _Queue64_UInt8_8_io_deq_bits : _T_2465 ? _Queue64_UInt8_7_io_deq_bits : _T_2464 ? _Queue64_UInt8_6_io_deq_bits : _T_2463 ? _Queue64_UInt8_5_io_deq_bits : _T_2462 ? _Queue64_UInt8_4_io_deq_bits : _T_2461 ? _Queue64_UInt8_3_io_deq_bits : _T_2460 ? _Queue64_UInt8_2_io_deq_bits : _T_2459 ? _Queue64_UInt8_1_io_deq_bits : _T_2458 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_4 = _T_2489 ? _Queue64_UInt8_31_io_deq_valid : _T_2488 ? _Queue64_UInt8_30_io_deq_valid : _T_2487 ? _Queue64_UInt8_29_io_deq_valid : _T_2486 ? _Queue64_UInt8_28_io_deq_valid : _T_2485 ? _Queue64_UInt8_27_io_deq_valid : _T_2484 ? _Queue64_UInt8_26_io_deq_valid : _T_2483 ? _Queue64_UInt8_25_io_deq_valid : _T_2482 ? _Queue64_UInt8_24_io_deq_valid : _T_2481 ? _Queue64_UInt8_23_io_deq_valid : _T_2480 ? _Queue64_UInt8_22_io_deq_valid : _T_2479 ? _Queue64_UInt8_21_io_deq_valid : _T_2478 ? _Queue64_UInt8_20_io_deq_valid : _T_2477 ? _Queue64_UInt8_19_io_deq_valid : _T_2476 ? _Queue64_UInt8_18_io_deq_valid : _T_2475 ? _Queue64_UInt8_17_io_deq_valid : _T_2474 ? _Queue64_UInt8_16_io_deq_valid : _T_2473 ? _Queue64_UInt8_15_io_deq_valid : _T_2472 ? _Queue64_UInt8_14_io_deq_valid : _T_2471 ? _Queue64_UInt8_13_io_deq_valid : _T_2470 ? _Queue64_UInt8_12_io_deq_valid : _T_2469 ? _Queue64_UInt8_11_io_deq_valid : _T_2468 ? _Queue64_UInt8_10_io_deq_valid : _T_2467 ? _Queue64_UInt8_9_io_deq_valid : _T_2466 ? _Queue64_UInt8_8_io_deq_valid : _T_2465 ? _Queue64_UInt8_7_io_deq_valid : _T_2464 ? _Queue64_UInt8_6_io_deq_valid : _T_2463 ? _Queue64_UInt8_5_io_deq_valid : _T_2462 ? _Queue64_UInt8_4_io_deq_valid : _T_2461 ? _Queue64_UInt8_3_io_deq_valid : _T_2460 ? _Queue64_UInt8_2_io_deq_valid : _T_2459 ? _Queue64_UInt8_1_io_deq_valid : _T_2458 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[MemLoader.scala:177:33] wire [6:0] _GEN_96 = _remapindex_T_5 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_5 = _GEN_96[5:0]; // @[MemLoader.scala:177:54] wire _T_2490 = remapindex_5 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2491 = remapindex_5 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2492 = remapindex_5 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2493 = remapindex_5 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2494 = remapindex_5 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2495 = remapindex_5 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2496 = remapindex_5 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2497 = remapindex_5 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2498 = remapindex_5 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2499 = remapindex_5 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2500 = remapindex_5 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2501 = remapindex_5 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2502 = remapindex_5 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2503 = remapindex_5 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2504 = remapindex_5 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2505 = remapindex_5 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2506 = remapindex_5 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2507 = remapindex_5 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2508 = remapindex_5 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2509 = remapindex_5 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2510 = remapindex_5 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2511 = remapindex_5 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2512 = remapindex_5 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2513 = remapindex_5 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2514 = remapindex_5 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2515 = remapindex_5 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2516 = remapindex_5 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2517 = remapindex_5 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2518 = remapindex_5 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2519 = remapindex_5 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2520 = remapindex_5 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2521 = remapindex_5 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_5 = _T_2521 ? _Queue64_UInt8_31_io_deq_bits : _T_2520 ? _Queue64_UInt8_30_io_deq_bits : _T_2519 ? _Queue64_UInt8_29_io_deq_bits : _T_2518 ? _Queue64_UInt8_28_io_deq_bits : _T_2517 ? _Queue64_UInt8_27_io_deq_bits : _T_2516 ? _Queue64_UInt8_26_io_deq_bits : _T_2515 ? _Queue64_UInt8_25_io_deq_bits : _T_2514 ? _Queue64_UInt8_24_io_deq_bits : _T_2513 ? _Queue64_UInt8_23_io_deq_bits : _T_2512 ? _Queue64_UInt8_22_io_deq_bits : _T_2511 ? _Queue64_UInt8_21_io_deq_bits : _T_2510 ? _Queue64_UInt8_20_io_deq_bits : _T_2509 ? _Queue64_UInt8_19_io_deq_bits : _T_2508 ? _Queue64_UInt8_18_io_deq_bits : _T_2507 ? _Queue64_UInt8_17_io_deq_bits : _T_2506 ? _Queue64_UInt8_16_io_deq_bits : _T_2505 ? _Queue64_UInt8_15_io_deq_bits : _T_2504 ? _Queue64_UInt8_14_io_deq_bits : _T_2503 ? _Queue64_UInt8_13_io_deq_bits : _T_2502 ? _Queue64_UInt8_12_io_deq_bits : _T_2501 ? _Queue64_UInt8_11_io_deq_bits : _T_2500 ? _Queue64_UInt8_10_io_deq_bits : _T_2499 ? _Queue64_UInt8_9_io_deq_bits : _T_2498 ? _Queue64_UInt8_8_io_deq_bits : _T_2497 ? _Queue64_UInt8_7_io_deq_bits : _T_2496 ? _Queue64_UInt8_6_io_deq_bits : _T_2495 ? _Queue64_UInt8_5_io_deq_bits : _T_2494 ? _Queue64_UInt8_4_io_deq_bits : _T_2493 ? _Queue64_UInt8_3_io_deq_bits : _T_2492 ? _Queue64_UInt8_2_io_deq_bits : _T_2491 ? _Queue64_UInt8_1_io_deq_bits : _T_2490 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_5 = _T_2521 ? _Queue64_UInt8_31_io_deq_valid : _T_2520 ? _Queue64_UInt8_30_io_deq_valid : _T_2519 ? _Queue64_UInt8_29_io_deq_valid : _T_2518 ? _Queue64_UInt8_28_io_deq_valid : _T_2517 ? _Queue64_UInt8_27_io_deq_valid : _T_2516 ? _Queue64_UInt8_26_io_deq_valid : _T_2515 ? _Queue64_UInt8_25_io_deq_valid : _T_2514 ? _Queue64_UInt8_24_io_deq_valid : _T_2513 ? _Queue64_UInt8_23_io_deq_valid : _T_2512 ? _Queue64_UInt8_22_io_deq_valid : _T_2511 ? _Queue64_UInt8_21_io_deq_valid : _T_2510 ? _Queue64_UInt8_20_io_deq_valid : _T_2509 ? _Queue64_UInt8_19_io_deq_valid : _T_2508 ? _Queue64_UInt8_18_io_deq_valid : _T_2507 ? _Queue64_UInt8_17_io_deq_valid : _T_2506 ? _Queue64_UInt8_16_io_deq_valid : _T_2505 ? _Queue64_UInt8_15_io_deq_valid : _T_2504 ? _Queue64_UInt8_14_io_deq_valid : _T_2503 ? _Queue64_UInt8_13_io_deq_valid : _T_2502 ? _Queue64_UInt8_12_io_deq_valid : _T_2501 ? _Queue64_UInt8_11_io_deq_valid : _T_2500 ? _Queue64_UInt8_10_io_deq_valid : _T_2499 ? _Queue64_UInt8_9_io_deq_valid : _T_2498 ? _Queue64_UInt8_8_io_deq_valid : _T_2497 ? _Queue64_UInt8_7_io_deq_valid : _T_2496 ? _Queue64_UInt8_6_io_deq_valid : _T_2495 ? _Queue64_UInt8_5_io_deq_valid : _T_2494 ? _Queue64_UInt8_4_io_deq_valid : _T_2493 ? _Queue64_UInt8_3_io_deq_valid : _T_2492 ? _Queue64_UInt8_2_io_deq_valid : _T_2491 ? _Queue64_UInt8_1_io_deq_valid : _T_2490 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[MemLoader.scala:177:33] wire [6:0] _GEN_97 = _remapindex_T_6 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_6 = _GEN_97[5:0]; // @[MemLoader.scala:177:54] wire _T_2522 = remapindex_6 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2523 = remapindex_6 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2524 = remapindex_6 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2525 = remapindex_6 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2526 = remapindex_6 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2527 = remapindex_6 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2528 = remapindex_6 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2529 = remapindex_6 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2530 = remapindex_6 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2531 = remapindex_6 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2532 = remapindex_6 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2533 = remapindex_6 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2534 = remapindex_6 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2535 = remapindex_6 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2536 = remapindex_6 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2537 = remapindex_6 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2538 = remapindex_6 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2539 = remapindex_6 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2540 = remapindex_6 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2541 = remapindex_6 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2542 = remapindex_6 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2543 = remapindex_6 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2544 = remapindex_6 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2545 = remapindex_6 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2546 = remapindex_6 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2547 = remapindex_6 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2548 = remapindex_6 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2549 = remapindex_6 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2550 = remapindex_6 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2551 = remapindex_6 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2552 = remapindex_6 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2553 = remapindex_6 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_6 = _T_2553 ? _Queue64_UInt8_31_io_deq_bits : _T_2552 ? _Queue64_UInt8_30_io_deq_bits : _T_2551 ? _Queue64_UInt8_29_io_deq_bits : _T_2550 ? _Queue64_UInt8_28_io_deq_bits : _T_2549 ? _Queue64_UInt8_27_io_deq_bits : _T_2548 ? _Queue64_UInt8_26_io_deq_bits : _T_2547 ? _Queue64_UInt8_25_io_deq_bits : _T_2546 ? _Queue64_UInt8_24_io_deq_bits : _T_2545 ? _Queue64_UInt8_23_io_deq_bits : _T_2544 ? _Queue64_UInt8_22_io_deq_bits : _T_2543 ? _Queue64_UInt8_21_io_deq_bits : _T_2542 ? _Queue64_UInt8_20_io_deq_bits : _T_2541 ? _Queue64_UInt8_19_io_deq_bits : _T_2540 ? _Queue64_UInt8_18_io_deq_bits : _T_2539 ? _Queue64_UInt8_17_io_deq_bits : _T_2538 ? _Queue64_UInt8_16_io_deq_bits : _T_2537 ? _Queue64_UInt8_15_io_deq_bits : _T_2536 ? _Queue64_UInt8_14_io_deq_bits : _T_2535 ? _Queue64_UInt8_13_io_deq_bits : _T_2534 ? _Queue64_UInt8_12_io_deq_bits : _T_2533 ? _Queue64_UInt8_11_io_deq_bits : _T_2532 ? _Queue64_UInt8_10_io_deq_bits : _T_2531 ? _Queue64_UInt8_9_io_deq_bits : _T_2530 ? _Queue64_UInt8_8_io_deq_bits : _T_2529 ? _Queue64_UInt8_7_io_deq_bits : _T_2528 ? _Queue64_UInt8_6_io_deq_bits : _T_2527 ? _Queue64_UInt8_5_io_deq_bits : _T_2526 ? _Queue64_UInt8_4_io_deq_bits : _T_2525 ? _Queue64_UInt8_3_io_deq_bits : _T_2524 ? _Queue64_UInt8_2_io_deq_bits : _T_2523 ? _Queue64_UInt8_1_io_deq_bits : _T_2522 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_6 = _T_2553 ? _Queue64_UInt8_31_io_deq_valid : _T_2552 ? _Queue64_UInt8_30_io_deq_valid : _T_2551 ? _Queue64_UInt8_29_io_deq_valid : _T_2550 ? _Queue64_UInt8_28_io_deq_valid : _T_2549 ? _Queue64_UInt8_27_io_deq_valid : _T_2548 ? _Queue64_UInt8_26_io_deq_valid : _T_2547 ? _Queue64_UInt8_25_io_deq_valid : _T_2546 ? _Queue64_UInt8_24_io_deq_valid : _T_2545 ? _Queue64_UInt8_23_io_deq_valid : _T_2544 ? _Queue64_UInt8_22_io_deq_valid : _T_2543 ? _Queue64_UInt8_21_io_deq_valid : _T_2542 ? _Queue64_UInt8_20_io_deq_valid : _T_2541 ? _Queue64_UInt8_19_io_deq_valid : _T_2540 ? _Queue64_UInt8_18_io_deq_valid : _T_2539 ? _Queue64_UInt8_17_io_deq_valid : _T_2538 ? _Queue64_UInt8_16_io_deq_valid : _T_2537 ? _Queue64_UInt8_15_io_deq_valid : _T_2536 ? _Queue64_UInt8_14_io_deq_valid : _T_2535 ? _Queue64_UInt8_13_io_deq_valid : _T_2534 ? _Queue64_UInt8_12_io_deq_valid : _T_2533 ? _Queue64_UInt8_11_io_deq_valid : _T_2532 ? _Queue64_UInt8_10_io_deq_valid : _T_2531 ? _Queue64_UInt8_9_io_deq_valid : _T_2530 ? _Queue64_UInt8_8_io_deq_valid : _T_2529 ? _Queue64_UInt8_7_io_deq_valid : _T_2528 ? _Queue64_UInt8_6_io_deq_valid : _T_2527 ? _Queue64_UInt8_5_io_deq_valid : _T_2526 ? _Queue64_UInt8_4_io_deq_valid : _T_2525 ? _Queue64_UInt8_3_io_deq_valid : _T_2524 ? _Queue64_UInt8_2_io_deq_valid : _T_2523 ? _Queue64_UInt8_1_io_deq_valid : _T_2522 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[MemLoader.scala:177:33] wire [6:0] _GEN_98 = _remapindex_T_7 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_7 = _GEN_98[5:0]; // @[MemLoader.scala:177:54] wire _T_2554 = remapindex_7 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2555 = remapindex_7 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2556 = remapindex_7 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2557 = remapindex_7 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2558 = remapindex_7 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2559 = remapindex_7 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2560 = remapindex_7 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2561 = remapindex_7 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2562 = remapindex_7 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2563 = remapindex_7 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2564 = remapindex_7 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2565 = remapindex_7 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2566 = remapindex_7 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2567 = remapindex_7 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2568 = remapindex_7 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2569 = remapindex_7 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2570 = remapindex_7 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2571 = remapindex_7 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2572 = remapindex_7 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2573 = remapindex_7 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2574 = remapindex_7 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2575 = remapindex_7 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2576 = remapindex_7 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2577 = remapindex_7 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2578 = remapindex_7 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2579 = remapindex_7 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2580 = remapindex_7 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2581 = remapindex_7 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2582 = remapindex_7 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2583 = remapindex_7 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2584 = remapindex_7 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2585 = remapindex_7 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_7 = _T_2585 ? _Queue64_UInt8_31_io_deq_bits : _T_2584 ? _Queue64_UInt8_30_io_deq_bits : _T_2583 ? _Queue64_UInt8_29_io_deq_bits : _T_2582 ? _Queue64_UInt8_28_io_deq_bits : _T_2581 ? _Queue64_UInt8_27_io_deq_bits : _T_2580 ? _Queue64_UInt8_26_io_deq_bits : _T_2579 ? _Queue64_UInt8_25_io_deq_bits : _T_2578 ? _Queue64_UInt8_24_io_deq_bits : _T_2577 ? _Queue64_UInt8_23_io_deq_bits : _T_2576 ? _Queue64_UInt8_22_io_deq_bits : _T_2575 ? _Queue64_UInt8_21_io_deq_bits : _T_2574 ? _Queue64_UInt8_20_io_deq_bits : _T_2573 ? _Queue64_UInt8_19_io_deq_bits : _T_2572 ? _Queue64_UInt8_18_io_deq_bits : _T_2571 ? _Queue64_UInt8_17_io_deq_bits : _T_2570 ? _Queue64_UInt8_16_io_deq_bits : _T_2569 ? _Queue64_UInt8_15_io_deq_bits : _T_2568 ? _Queue64_UInt8_14_io_deq_bits : _T_2567 ? _Queue64_UInt8_13_io_deq_bits : _T_2566 ? _Queue64_UInt8_12_io_deq_bits : _T_2565 ? _Queue64_UInt8_11_io_deq_bits : _T_2564 ? _Queue64_UInt8_10_io_deq_bits : _T_2563 ? _Queue64_UInt8_9_io_deq_bits : _T_2562 ? _Queue64_UInt8_8_io_deq_bits : _T_2561 ? _Queue64_UInt8_7_io_deq_bits : _T_2560 ? _Queue64_UInt8_6_io_deq_bits : _T_2559 ? _Queue64_UInt8_5_io_deq_bits : _T_2558 ? _Queue64_UInt8_4_io_deq_bits : _T_2557 ? _Queue64_UInt8_3_io_deq_bits : _T_2556 ? _Queue64_UInt8_2_io_deq_bits : _T_2555 ? _Queue64_UInt8_1_io_deq_bits : _T_2554 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_7 = _T_2585 ? _Queue64_UInt8_31_io_deq_valid : _T_2584 ? _Queue64_UInt8_30_io_deq_valid : _T_2583 ? _Queue64_UInt8_29_io_deq_valid : _T_2582 ? _Queue64_UInt8_28_io_deq_valid : _T_2581 ? _Queue64_UInt8_27_io_deq_valid : _T_2580 ? _Queue64_UInt8_26_io_deq_valid : _T_2579 ? _Queue64_UInt8_25_io_deq_valid : _T_2578 ? _Queue64_UInt8_24_io_deq_valid : _T_2577 ? _Queue64_UInt8_23_io_deq_valid : _T_2576 ? _Queue64_UInt8_22_io_deq_valid : _T_2575 ? _Queue64_UInt8_21_io_deq_valid : _T_2574 ? _Queue64_UInt8_20_io_deq_valid : _T_2573 ? _Queue64_UInt8_19_io_deq_valid : _T_2572 ? _Queue64_UInt8_18_io_deq_valid : _T_2571 ? _Queue64_UInt8_17_io_deq_valid : _T_2570 ? _Queue64_UInt8_16_io_deq_valid : _T_2569 ? _Queue64_UInt8_15_io_deq_valid : _T_2568 ? _Queue64_UInt8_14_io_deq_valid : _T_2567 ? _Queue64_UInt8_13_io_deq_valid : _T_2566 ? _Queue64_UInt8_12_io_deq_valid : _T_2565 ? _Queue64_UInt8_11_io_deq_valid : _T_2564 ? _Queue64_UInt8_10_io_deq_valid : _T_2563 ? _Queue64_UInt8_9_io_deq_valid : _T_2562 ? _Queue64_UInt8_8_io_deq_valid : _T_2561 ? _Queue64_UInt8_7_io_deq_valid : _T_2560 ? _Queue64_UInt8_6_io_deq_valid : _T_2559 ? _Queue64_UInt8_5_io_deq_valid : _T_2558 ? _Queue64_UInt8_4_io_deq_valid : _T_2557 ? _Queue64_UInt8_3_io_deq_valid : _T_2556 ? _Queue64_UInt8_2_io_deq_valid : _T_2555 ? _Queue64_UInt8_1_io_deq_valid : _T_2554 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[MemLoader.scala:177:33] wire [6:0] _GEN_99 = _remapindex_T_8 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_8 = _GEN_99[5:0]; // @[MemLoader.scala:177:54] wire _T_2586 = remapindex_8 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2587 = remapindex_8 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2588 = remapindex_8 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2589 = remapindex_8 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2590 = remapindex_8 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2591 = remapindex_8 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2592 = remapindex_8 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2593 = remapindex_8 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2594 = remapindex_8 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2595 = remapindex_8 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2596 = remapindex_8 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2597 = remapindex_8 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2598 = remapindex_8 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2599 = remapindex_8 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2600 = remapindex_8 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2601 = remapindex_8 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2602 = remapindex_8 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2603 = remapindex_8 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2604 = remapindex_8 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2605 = remapindex_8 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2606 = remapindex_8 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2607 = remapindex_8 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2608 = remapindex_8 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2609 = remapindex_8 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2610 = remapindex_8 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2611 = remapindex_8 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2612 = remapindex_8 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2613 = remapindex_8 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2614 = remapindex_8 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2615 = remapindex_8 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2616 = remapindex_8 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2617 = remapindex_8 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_8 = _T_2617 ? _Queue64_UInt8_31_io_deq_bits : _T_2616 ? _Queue64_UInt8_30_io_deq_bits : _T_2615 ? _Queue64_UInt8_29_io_deq_bits : _T_2614 ? _Queue64_UInt8_28_io_deq_bits : _T_2613 ? _Queue64_UInt8_27_io_deq_bits : _T_2612 ? _Queue64_UInt8_26_io_deq_bits : _T_2611 ? _Queue64_UInt8_25_io_deq_bits : _T_2610 ? _Queue64_UInt8_24_io_deq_bits : _T_2609 ? _Queue64_UInt8_23_io_deq_bits : _T_2608 ? _Queue64_UInt8_22_io_deq_bits : _T_2607 ? _Queue64_UInt8_21_io_deq_bits : _T_2606 ? _Queue64_UInt8_20_io_deq_bits : _T_2605 ? _Queue64_UInt8_19_io_deq_bits : _T_2604 ? _Queue64_UInt8_18_io_deq_bits : _T_2603 ? _Queue64_UInt8_17_io_deq_bits : _T_2602 ? _Queue64_UInt8_16_io_deq_bits : _T_2601 ? _Queue64_UInt8_15_io_deq_bits : _T_2600 ? _Queue64_UInt8_14_io_deq_bits : _T_2599 ? _Queue64_UInt8_13_io_deq_bits : _T_2598 ? _Queue64_UInt8_12_io_deq_bits : _T_2597 ? _Queue64_UInt8_11_io_deq_bits : _T_2596 ? _Queue64_UInt8_10_io_deq_bits : _T_2595 ? _Queue64_UInt8_9_io_deq_bits : _T_2594 ? _Queue64_UInt8_8_io_deq_bits : _T_2593 ? _Queue64_UInt8_7_io_deq_bits : _T_2592 ? _Queue64_UInt8_6_io_deq_bits : _T_2591 ? _Queue64_UInt8_5_io_deq_bits : _T_2590 ? _Queue64_UInt8_4_io_deq_bits : _T_2589 ? _Queue64_UInt8_3_io_deq_bits : _T_2588 ? _Queue64_UInt8_2_io_deq_bits : _T_2587 ? _Queue64_UInt8_1_io_deq_bits : _T_2586 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_8 = _T_2617 ? _Queue64_UInt8_31_io_deq_valid : _T_2616 ? _Queue64_UInt8_30_io_deq_valid : _T_2615 ? _Queue64_UInt8_29_io_deq_valid : _T_2614 ? _Queue64_UInt8_28_io_deq_valid : _T_2613 ? _Queue64_UInt8_27_io_deq_valid : _T_2612 ? _Queue64_UInt8_26_io_deq_valid : _T_2611 ? _Queue64_UInt8_25_io_deq_valid : _T_2610 ? _Queue64_UInt8_24_io_deq_valid : _T_2609 ? _Queue64_UInt8_23_io_deq_valid : _T_2608 ? _Queue64_UInt8_22_io_deq_valid : _T_2607 ? _Queue64_UInt8_21_io_deq_valid : _T_2606 ? _Queue64_UInt8_20_io_deq_valid : _T_2605 ? _Queue64_UInt8_19_io_deq_valid : _T_2604 ? _Queue64_UInt8_18_io_deq_valid : _T_2603 ? _Queue64_UInt8_17_io_deq_valid : _T_2602 ? _Queue64_UInt8_16_io_deq_valid : _T_2601 ? _Queue64_UInt8_15_io_deq_valid : _T_2600 ? _Queue64_UInt8_14_io_deq_valid : _T_2599 ? _Queue64_UInt8_13_io_deq_valid : _T_2598 ? _Queue64_UInt8_12_io_deq_valid : _T_2597 ? _Queue64_UInt8_11_io_deq_valid : _T_2596 ? _Queue64_UInt8_10_io_deq_valid : _T_2595 ? _Queue64_UInt8_9_io_deq_valid : _T_2594 ? _Queue64_UInt8_8_io_deq_valid : _T_2593 ? _Queue64_UInt8_7_io_deq_valid : _T_2592 ? _Queue64_UInt8_6_io_deq_valid : _T_2591 ? _Queue64_UInt8_5_io_deq_valid : _T_2590 ? _Queue64_UInt8_4_io_deq_valid : _T_2589 ? _Queue64_UInt8_3_io_deq_valid : _T_2588 ? _Queue64_UInt8_2_io_deq_valid : _T_2587 ? _Queue64_UInt8_1_io_deq_valid : _T_2586 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[MemLoader.scala:177:33] wire [6:0] _GEN_100 = _remapindex_T_9 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_9 = _GEN_100[5:0]; // @[MemLoader.scala:177:54] wire _T_2618 = remapindex_9 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2619 = remapindex_9 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2620 = remapindex_9 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2621 = remapindex_9 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2622 = remapindex_9 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2623 = remapindex_9 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2624 = remapindex_9 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2625 = remapindex_9 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2626 = remapindex_9 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2627 = remapindex_9 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2628 = remapindex_9 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2629 = remapindex_9 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2630 = remapindex_9 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2631 = remapindex_9 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2632 = remapindex_9 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2633 = remapindex_9 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2634 = remapindex_9 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2635 = remapindex_9 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2636 = remapindex_9 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2637 = remapindex_9 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2638 = remapindex_9 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2639 = remapindex_9 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2640 = remapindex_9 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2641 = remapindex_9 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2642 = remapindex_9 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2643 = remapindex_9 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2644 = remapindex_9 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2645 = remapindex_9 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2646 = remapindex_9 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2647 = remapindex_9 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2648 = remapindex_9 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2649 = remapindex_9 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_9 = _T_2649 ? _Queue64_UInt8_31_io_deq_bits : _T_2648 ? _Queue64_UInt8_30_io_deq_bits : _T_2647 ? _Queue64_UInt8_29_io_deq_bits : _T_2646 ? _Queue64_UInt8_28_io_deq_bits : _T_2645 ? _Queue64_UInt8_27_io_deq_bits : _T_2644 ? _Queue64_UInt8_26_io_deq_bits : _T_2643 ? _Queue64_UInt8_25_io_deq_bits : _T_2642 ? _Queue64_UInt8_24_io_deq_bits : _T_2641 ? _Queue64_UInt8_23_io_deq_bits : _T_2640 ? _Queue64_UInt8_22_io_deq_bits : _T_2639 ? _Queue64_UInt8_21_io_deq_bits : _T_2638 ? _Queue64_UInt8_20_io_deq_bits : _T_2637 ? _Queue64_UInt8_19_io_deq_bits : _T_2636 ? _Queue64_UInt8_18_io_deq_bits : _T_2635 ? _Queue64_UInt8_17_io_deq_bits : _T_2634 ? _Queue64_UInt8_16_io_deq_bits : _T_2633 ? _Queue64_UInt8_15_io_deq_bits : _T_2632 ? _Queue64_UInt8_14_io_deq_bits : _T_2631 ? _Queue64_UInt8_13_io_deq_bits : _T_2630 ? _Queue64_UInt8_12_io_deq_bits : _T_2629 ? _Queue64_UInt8_11_io_deq_bits : _T_2628 ? _Queue64_UInt8_10_io_deq_bits : _T_2627 ? _Queue64_UInt8_9_io_deq_bits : _T_2626 ? _Queue64_UInt8_8_io_deq_bits : _T_2625 ? _Queue64_UInt8_7_io_deq_bits : _T_2624 ? _Queue64_UInt8_6_io_deq_bits : _T_2623 ? _Queue64_UInt8_5_io_deq_bits : _T_2622 ? _Queue64_UInt8_4_io_deq_bits : _T_2621 ? _Queue64_UInt8_3_io_deq_bits : _T_2620 ? _Queue64_UInt8_2_io_deq_bits : _T_2619 ? _Queue64_UInt8_1_io_deq_bits : _T_2618 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_9 = _T_2649 ? _Queue64_UInt8_31_io_deq_valid : _T_2648 ? _Queue64_UInt8_30_io_deq_valid : _T_2647 ? _Queue64_UInt8_29_io_deq_valid : _T_2646 ? _Queue64_UInt8_28_io_deq_valid : _T_2645 ? _Queue64_UInt8_27_io_deq_valid : _T_2644 ? _Queue64_UInt8_26_io_deq_valid : _T_2643 ? _Queue64_UInt8_25_io_deq_valid : _T_2642 ? _Queue64_UInt8_24_io_deq_valid : _T_2641 ? _Queue64_UInt8_23_io_deq_valid : _T_2640 ? _Queue64_UInt8_22_io_deq_valid : _T_2639 ? _Queue64_UInt8_21_io_deq_valid : _T_2638 ? _Queue64_UInt8_20_io_deq_valid : _T_2637 ? _Queue64_UInt8_19_io_deq_valid : _T_2636 ? _Queue64_UInt8_18_io_deq_valid : _T_2635 ? _Queue64_UInt8_17_io_deq_valid : _T_2634 ? _Queue64_UInt8_16_io_deq_valid : _T_2633 ? _Queue64_UInt8_15_io_deq_valid : _T_2632 ? _Queue64_UInt8_14_io_deq_valid : _T_2631 ? _Queue64_UInt8_13_io_deq_valid : _T_2630 ? _Queue64_UInt8_12_io_deq_valid : _T_2629 ? _Queue64_UInt8_11_io_deq_valid : _T_2628 ? _Queue64_UInt8_10_io_deq_valid : _T_2627 ? _Queue64_UInt8_9_io_deq_valid : _T_2626 ? _Queue64_UInt8_8_io_deq_valid : _T_2625 ? _Queue64_UInt8_7_io_deq_valid : _T_2624 ? _Queue64_UInt8_6_io_deq_valid : _T_2623 ? _Queue64_UInt8_5_io_deq_valid : _T_2622 ? _Queue64_UInt8_4_io_deq_valid : _T_2621 ? _Queue64_UInt8_3_io_deq_valid : _T_2620 ? _Queue64_UInt8_2_io_deq_valid : _T_2619 ? _Queue64_UInt8_1_io_deq_valid : _T_2618 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[MemLoader.scala:177:33] wire [6:0] _GEN_101 = _remapindex_T_10 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_10 = _GEN_101[5:0]; // @[MemLoader.scala:177:54] wire _T_2650 = remapindex_10 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2651 = remapindex_10 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2652 = remapindex_10 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2653 = remapindex_10 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2654 = remapindex_10 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2655 = remapindex_10 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2656 = remapindex_10 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2657 = remapindex_10 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2658 = remapindex_10 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2659 = remapindex_10 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2660 = remapindex_10 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2661 = remapindex_10 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2662 = remapindex_10 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2663 = remapindex_10 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2664 = remapindex_10 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2665 = remapindex_10 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2666 = remapindex_10 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2667 = remapindex_10 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2668 = remapindex_10 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2669 = remapindex_10 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2670 = remapindex_10 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2671 = remapindex_10 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2672 = remapindex_10 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2673 = remapindex_10 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2674 = remapindex_10 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2675 = remapindex_10 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2676 = remapindex_10 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2677 = remapindex_10 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2678 = remapindex_10 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2679 = remapindex_10 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2680 = remapindex_10 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2681 = remapindex_10 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_10 = _T_2681 ? _Queue64_UInt8_31_io_deq_bits : _T_2680 ? _Queue64_UInt8_30_io_deq_bits : _T_2679 ? _Queue64_UInt8_29_io_deq_bits : _T_2678 ? _Queue64_UInt8_28_io_deq_bits : _T_2677 ? _Queue64_UInt8_27_io_deq_bits : _T_2676 ? _Queue64_UInt8_26_io_deq_bits : _T_2675 ? _Queue64_UInt8_25_io_deq_bits : _T_2674 ? _Queue64_UInt8_24_io_deq_bits : _T_2673 ? _Queue64_UInt8_23_io_deq_bits : _T_2672 ? _Queue64_UInt8_22_io_deq_bits : _T_2671 ? _Queue64_UInt8_21_io_deq_bits : _T_2670 ? _Queue64_UInt8_20_io_deq_bits : _T_2669 ? _Queue64_UInt8_19_io_deq_bits : _T_2668 ? _Queue64_UInt8_18_io_deq_bits : _T_2667 ? _Queue64_UInt8_17_io_deq_bits : _T_2666 ? _Queue64_UInt8_16_io_deq_bits : _T_2665 ? _Queue64_UInt8_15_io_deq_bits : _T_2664 ? _Queue64_UInt8_14_io_deq_bits : _T_2663 ? _Queue64_UInt8_13_io_deq_bits : _T_2662 ? _Queue64_UInt8_12_io_deq_bits : _T_2661 ? _Queue64_UInt8_11_io_deq_bits : _T_2660 ? _Queue64_UInt8_10_io_deq_bits : _T_2659 ? _Queue64_UInt8_9_io_deq_bits : _T_2658 ? _Queue64_UInt8_8_io_deq_bits : _T_2657 ? _Queue64_UInt8_7_io_deq_bits : _T_2656 ? _Queue64_UInt8_6_io_deq_bits : _T_2655 ? _Queue64_UInt8_5_io_deq_bits : _T_2654 ? _Queue64_UInt8_4_io_deq_bits : _T_2653 ? _Queue64_UInt8_3_io_deq_bits : _T_2652 ? _Queue64_UInt8_2_io_deq_bits : _T_2651 ? _Queue64_UInt8_1_io_deq_bits : _T_2650 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_10 = _T_2681 ? _Queue64_UInt8_31_io_deq_valid : _T_2680 ? _Queue64_UInt8_30_io_deq_valid : _T_2679 ? _Queue64_UInt8_29_io_deq_valid : _T_2678 ? _Queue64_UInt8_28_io_deq_valid : _T_2677 ? _Queue64_UInt8_27_io_deq_valid : _T_2676 ? _Queue64_UInt8_26_io_deq_valid : _T_2675 ? _Queue64_UInt8_25_io_deq_valid : _T_2674 ? _Queue64_UInt8_24_io_deq_valid : _T_2673 ? _Queue64_UInt8_23_io_deq_valid : _T_2672 ? _Queue64_UInt8_22_io_deq_valid : _T_2671 ? _Queue64_UInt8_21_io_deq_valid : _T_2670 ? _Queue64_UInt8_20_io_deq_valid : _T_2669 ? _Queue64_UInt8_19_io_deq_valid : _T_2668 ? _Queue64_UInt8_18_io_deq_valid : _T_2667 ? _Queue64_UInt8_17_io_deq_valid : _T_2666 ? _Queue64_UInt8_16_io_deq_valid : _T_2665 ? _Queue64_UInt8_15_io_deq_valid : _T_2664 ? _Queue64_UInt8_14_io_deq_valid : _T_2663 ? _Queue64_UInt8_13_io_deq_valid : _T_2662 ? _Queue64_UInt8_12_io_deq_valid : _T_2661 ? _Queue64_UInt8_11_io_deq_valid : _T_2660 ? _Queue64_UInt8_10_io_deq_valid : _T_2659 ? _Queue64_UInt8_9_io_deq_valid : _T_2658 ? _Queue64_UInt8_8_io_deq_valid : _T_2657 ? _Queue64_UInt8_7_io_deq_valid : _T_2656 ? _Queue64_UInt8_6_io_deq_valid : _T_2655 ? _Queue64_UInt8_5_io_deq_valid : _T_2654 ? _Queue64_UInt8_4_io_deq_valid : _T_2653 ? _Queue64_UInt8_3_io_deq_valid : _T_2652 ? _Queue64_UInt8_2_io_deq_valid : _T_2651 ? _Queue64_UInt8_1_io_deq_valid : _T_2650 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[MemLoader.scala:177:33] wire [6:0] _GEN_102 = _remapindex_T_11 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_11 = _GEN_102[5:0]; // @[MemLoader.scala:177:54] wire _T_2682 = remapindex_11 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2683 = remapindex_11 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2684 = remapindex_11 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2685 = remapindex_11 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2686 = remapindex_11 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2687 = remapindex_11 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2688 = remapindex_11 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2689 = remapindex_11 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2690 = remapindex_11 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2691 = remapindex_11 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2692 = remapindex_11 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2693 = remapindex_11 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2694 = remapindex_11 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2695 = remapindex_11 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2696 = remapindex_11 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2697 = remapindex_11 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2698 = remapindex_11 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2699 = remapindex_11 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2700 = remapindex_11 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2701 = remapindex_11 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2702 = remapindex_11 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2703 = remapindex_11 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2704 = remapindex_11 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2705 = remapindex_11 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2706 = remapindex_11 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2707 = remapindex_11 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2708 = remapindex_11 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2709 = remapindex_11 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2710 = remapindex_11 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2711 = remapindex_11 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2712 = remapindex_11 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2713 = remapindex_11 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_11 = _T_2713 ? _Queue64_UInt8_31_io_deq_bits : _T_2712 ? _Queue64_UInt8_30_io_deq_bits : _T_2711 ? _Queue64_UInt8_29_io_deq_bits : _T_2710 ? _Queue64_UInt8_28_io_deq_bits : _T_2709 ? _Queue64_UInt8_27_io_deq_bits : _T_2708 ? _Queue64_UInt8_26_io_deq_bits : _T_2707 ? _Queue64_UInt8_25_io_deq_bits : _T_2706 ? _Queue64_UInt8_24_io_deq_bits : _T_2705 ? _Queue64_UInt8_23_io_deq_bits : _T_2704 ? _Queue64_UInt8_22_io_deq_bits : _T_2703 ? _Queue64_UInt8_21_io_deq_bits : _T_2702 ? _Queue64_UInt8_20_io_deq_bits : _T_2701 ? _Queue64_UInt8_19_io_deq_bits : _T_2700 ? _Queue64_UInt8_18_io_deq_bits : _T_2699 ? _Queue64_UInt8_17_io_deq_bits : _T_2698 ? _Queue64_UInt8_16_io_deq_bits : _T_2697 ? _Queue64_UInt8_15_io_deq_bits : _T_2696 ? _Queue64_UInt8_14_io_deq_bits : _T_2695 ? _Queue64_UInt8_13_io_deq_bits : _T_2694 ? _Queue64_UInt8_12_io_deq_bits : _T_2693 ? _Queue64_UInt8_11_io_deq_bits : _T_2692 ? _Queue64_UInt8_10_io_deq_bits : _T_2691 ? _Queue64_UInt8_9_io_deq_bits : _T_2690 ? _Queue64_UInt8_8_io_deq_bits : _T_2689 ? _Queue64_UInt8_7_io_deq_bits : _T_2688 ? _Queue64_UInt8_6_io_deq_bits : _T_2687 ? _Queue64_UInt8_5_io_deq_bits : _T_2686 ? _Queue64_UInt8_4_io_deq_bits : _T_2685 ? _Queue64_UInt8_3_io_deq_bits : _T_2684 ? _Queue64_UInt8_2_io_deq_bits : _T_2683 ? _Queue64_UInt8_1_io_deq_bits : _T_2682 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_11 = _T_2713 ? _Queue64_UInt8_31_io_deq_valid : _T_2712 ? _Queue64_UInt8_30_io_deq_valid : _T_2711 ? _Queue64_UInt8_29_io_deq_valid : _T_2710 ? _Queue64_UInt8_28_io_deq_valid : _T_2709 ? _Queue64_UInt8_27_io_deq_valid : _T_2708 ? _Queue64_UInt8_26_io_deq_valid : _T_2707 ? _Queue64_UInt8_25_io_deq_valid : _T_2706 ? _Queue64_UInt8_24_io_deq_valid : _T_2705 ? _Queue64_UInt8_23_io_deq_valid : _T_2704 ? _Queue64_UInt8_22_io_deq_valid : _T_2703 ? _Queue64_UInt8_21_io_deq_valid : _T_2702 ? _Queue64_UInt8_20_io_deq_valid : _T_2701 ? _Queue64_UInt8_19_io_deq_valid : _T_2700 ? _Queue64_UInt8_18_io_deq_valid : _T_2699 ? _Queue64_UInt8_17_io_deq_valid : _T_2698 ? _Queue64_UInt8_16_io_deq_valid : _T_2697 ? _Queue64_UInt8_15_io_deq_valid : _T_2696 ? _Queue64_UInt8_14_io_deq_valid : _T_2695 ? _Queue64_UInt8_13_io_deq_valid : _T_2694 ? _Queue64_UInt8_12_io_deq_valid : _T_2693 ? _Queue64_UInt8_11_io_deq_valid : _T_2692 ? _Queue64_UInt8_10_io_deq_valid : _T_2691 ? _Queue64_UInt8_9_io_deq_valid : _T_2690 ? _Queue64_UInt8_8_io_deq_valid : _T_2689 ? _Queue64_UInt8_7_io_deq_valid : _T_2688 ? _Queue64_UInt8_6_io_deq_valid : _T_2687 ? _Queue64_UInt8_5_io_deq_valid : _T_2686 ? _Queue64_UInt8_4_io_deq_valid : _T_2685 ? _Queue64_UInt8_3_io_deq_valid : _T_2684 ? _Queue64_UInt8_2_io_deq_valid : _T_2683 ? _Queue64_UInt8_1_io_deq_valid : _T_2682 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _GEN_103 = _remapindex_T + 7'hC; // @[MemLoader.scala:177:33] wire [6:0] _remapindex_T_12; // @[MemLoader.scala:177:33] assign _remapindex_T_12 = _GEN_103; // @[MemLoader.scala:177:33] wire [6:0] _read_start_index_T; // @[MemLoader.scala:221:43] assign _read_start_index_T = _GEN_103; // @[MemLoader.scala:177:33, :221:43] wire [6:0] _GEN_104 = _remapindex_T_12 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_12 = _GEN_104[5:0]; // @[MemLoader.scala:177:54] wire _T_2714 = remapindex_12 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2715 = remapindex_12 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2716 = remapindex_12 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2717 = remapindex_12 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2718 = remapindex_12 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2719 = remapindex_12 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2720 = remapindex_12 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2721 = remapindex_12 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2722 = remapindex_12 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2723 = remapindex_12 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2724 = remapindex_12 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2725 = remapindex_12 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2726 = remapindex_12 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2727 = remapindex_12 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2728 = remapindex_12 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2729 = remapindex_12 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2730 = remapindex_12 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2731 = remapindex_12 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2732 = remapindex_12 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2733 = remapindex_12 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2734 = remapindex_12 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2735 = remapindex_12 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2736 = remapindex_12 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2737 = remapindex_12 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2738 = remapindex_12 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2739 = remapindex_12 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2740 = remapindex_12 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2741 = remapindex_12 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2742 = remapindex_12 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2743 = remapindex_12 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2744 = remapindex_12 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2745 = remapindex_12 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_12 = _T_2745 ? _Queue64_UInt8_31_io_deq_bits : _T_2744 ? _Queue64_UInt8_30_io_deq_bits : _T_2743 ? _Queue64_UInt8_29_io_deq_bits : _T_2742 ? _Queue64_UInt8_28_io_deq_bits : _T_2741 ? _Queue64_UInt8_27_io_deq_bits : _T_2740 ? _Queue64_UInt8_26_io_deq_bits : _T_2739 ? _Queue64_UInt8_25_io_deq_bits : _T_2738 ? _Queue64_UInt8_24_io_deq_bits : _T_2737 ? _Queue64_UInt8_23_io_deq_bits : _T_2736 ? _Queue64_UInt8_22_io_deq_bits : _T_2735 ? _Queue64_UInt8_21_io_deq_bits : _T_2734 ? _Queue64_UInt8_20_io_deq_bits : _T_2733 ? _Queue64_UInt8_19_io_deq_bits : _T_2732 ? _Queue64_UInt8_18_io_deq_bits : _T_2731 ? _Queue64_UInt8_17_io_deq_bits : _T_2730 ? _Queue64_UInt8_16_io_deq_bits : _T_2729 ? _Queue64_UInt8_15_io_deq_bits : _T_2728 ? _Queue64_UInt8_14_io_deq_bits : _T_2727 ? _Queue64_UInt8_13_io_deq_bits : _T_2726 ? _Queue64_UInt8_12_io_deq_bits : _T_2725 ? _Queue64_UInt8_11_io_deq_bits : _T_2724 ? _Queue64_UInt8_10_io_deq_bits : _T_2723 ? _Queue64_UInt8_9_io_deq_bits : _T_2722 ? _Queue64_UInt8_8_io_deq_bits : _T_2721 ? _Queue64_UInt8_7_io_deq_bits : _T_2720 ? _Queue64_UInt8_6_io_deq_bits : _T_2719 ? _Queue64_UInt8_5_io_deq_bits : _T_2718 ? _Queue64_UInt8_4_io_deq_bits : _T_2717 ? _Queue64_UInt8_3_io_deq_bits : _T_2716 ? _Queue64_UInt8_2_io_deq_bits : _T_2715 ? _Queue64_UInt8_1_io_deq_bits : _T_2714 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_12 = _T_2745 ? _Queue64_UInt8_31_io_deq_valid : _T_2744 ? _Queue64_UInt8_30_io_deq_valid : _T_2743 ? _Queue64_UInt8_29_io_deq_valid : _T_2742 ? _Queue64_UInt8_28_io_deq_valid : _T_2741 ? _Queue64_UInt8_27_io_deq_valid : _T_2740 ? _Queue64_UInt8_26_io_deq_valid : _T_2739 ? _Queue64_UInt8_25_io_deq_valid : _T_2738 ? _Queue64_UInt8_24_io_deq_valid : _T_2737 ? _Queue64_UInt8_23_io_deq_valid : _T_2736 ? _Queue64_UInt8_22_io_deq_valid : _T_2735 ? _Queue64_UInt8_21_io_deq_valid : _T_2734 ? _Queue64_UInt8_20_io_deq_valid : _T_2733 ? _Queue64_UInt8_19_io_deq_valid : _T_2732 ? _Queue64_UInt8_18_io_deq_valid : _T_2731 ? _Queue64_UInt8_17_io_deq_valid : _T_2730 ? _Queue64_UInt8_16_io_deq_valid : _T_2729 ? _Queue64_UInt8_15_io_deq_valid : _T_2728 ? _Queue64_UInt8_14_io_deq_valid : _T_2727 ? _Queue64_UInt8_13_io_deq_valid : _T_2726 ? _Queue64_UInt8_12_io_deq_valid : _T_2725 ? _Queue64_UInt8_11_io_deq_valid : _T_2724 ? _Queue64_UInt8_10_io_deq_valid : _T_2723 ? _Queue64_UInt8_9_io_deq_valid : _T_2722 ? _Queue64_UInt8_8_io_deq_valid : _T_2721 ? _Queue64_UInt8_7_io_deq_valid : _T_2720 ? _Queue64_UInt8_6_io_deq_valid : _T_2719 ? _Queue64_UInt8_5_io_deq_valid : _T_2718 ? _Queue64_UInt8_4_io_deq_valid : _T_2717 ? _Queue64_UInt8_3_io_deq_valid : _T_2716 ? _Queue64_UInt8_2_io_deq_valid : _T_2715 ? _Queue64_UInt8_1_io_deq_valid : _T_2714 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[MemLoader.scala:177:33] wire [6:0] _GEN_105 = _remapindex_T_13 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_13 = _GEN_105[5:0]; // @[MemLoader.scala:177:54] wire _T_2746 = remapindex_13 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2747 = remapindex_13 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2748 = remapindex_13 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2749 = remapindex_13 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2750 = remapindex_13 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2751 = remapindex_13 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2752 = remapindex_13 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2753 = remapindex_13 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2754 = remapindex_13 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2755 = remapindex_13 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2756 = remapindex_13 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2757 = remapindex_13 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2758 = remapindex_13 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2759 = remapindex_13 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2760 = remapindex_13 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2761 = remapindex_13 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2762 = remapindex_13 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2763 = remapindex_13 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2764 = remapindex_13 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2765 = remapindex_13 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2766 = remapindex_13 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2767 = remapindex_13 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2768 = remapindex_13 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2769 = remapindex_13 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2770 = remapindex_13 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2771 = remapindex_13 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2772 = remapindex_13 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2773 = remapindex_13 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2774 = remapindex_13 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2775 = remapindex_13 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2776 = remapindex_13 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2777 = remapindex_13 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_13 = _T_2777 ? _Queue64_UInt8_31_io_deq_bits : _T_2776 ? _Queue64_UInt8_30_io_deq_bits : _T_2775 ? _Queue64_UInt8_29_io_deq_bits : _T_2774 ? _Queue64_UInt8_28_io_deq_bits : _T_2773 ? _Queue64_UInt8_27_io_deq_bits : _T_2772 ? _Queue64_UInt8_26_io_deq_bits : _T_2771 ? _Queue64_UInt8_25_io_deq_bits : _T_2770 ? _Queue64_UInt8_24_io_deq_bits : _T_2769 ? _Queue64_UInt8_23_io_deq_bits : _T_2768 ? _Queue64_UInt8_22_io_deq_bits : _T_2767 ? _Queue64_UInt8_21_io_deq_bits : _T_2766 ? _Queue64_UInt8_20_io_deq_bits : _T_2765 ? _Queue64_UInt8_19_io_deq_bits : _T_2764 ? _Queue64_UInt8_18_io_deq_bits : _T_2763 ? _Queue64_UInt8_17_io_deq_bits : _T_2762 ? _Queue64_UInt8_16_io_deq_bits : _T_2761 ? _Queue64_UInt8_15_io_deq_bits : _T_2760 ? _Queue64_UInt8_14_io_deq_bits : _T_2759 ? _Queue64_UInt8_13_io_deq_bits : _T_2758 ? _Queue64_UInt8_12_io_deq_bits : _T_2757 ? _Queue64_UInt8_11_io_deq_bits : _T_2756 ? _Queue64_UInt8_10_io_deq_bits : _T_2755 ? _Queue64_UInt8_9_io_deq_bits : _T_2754 ? _Queue64_UInt8_8_io_deq_bits : _T_2753 ? _Queue64_UInt8_7_io_deq_bits : _T_2752 ? _Queue64_UInt8_6_io_deq_bits : _T_2751 ? _Queue64_UInt8_5_io_deq_bits : _T_2750 ? _Queue64_UInt8_4_io_deq_bits : _T_2749 ? _Queue64_UInt8_3_io_deq_bits : _T_2748 ? _Queue64_UInt8_2_io_deq_bits : _T_2747 ? _Queue64_UInt8_1_io_deq_bits : _T_2746 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_13 = _T_2777 ? _Queue64_UInt8_31_io_deq_valid : _T_2776 ? _Queue64_UInt8_30_io_deq_valid : _T_2775 ? _Queue64_UInt8_29_io_deq_valid : _T_2774 ? _Queue64_UInt8_28_io_deq_valid : _T_2773 ? _Queue64_UInt8_27_io_deq_valid : _T_2772 ? _Queue64_UInt8_26_io_deq_valid : _T_2771 ? _Queue64_UInt8_25_io_deq_valid : _T_2770 ? _Queue64_UInt8_24_io_deq_valid : _T_2769 ? _Queue64_UInt8_23_io_deq_valid : _T_2768 ? _Queue64_UInt8_22_io_deq_valid : _T_2767 ? _Queue64_UInt8_21_io_deq_valid : _T_2766 ? _Queue64_UInt8_20_io_deq_valid : _T_2765 ? _Queue64_UInt8_19_io_deq_valid : _T_2764 ? _Queue64_UInt8_18_io_deq_valid : _T_2763 ? _Queue64_UInt8_17_io_deq_valid : _T_2762 ? _Queue64_UInt8_16_io_deq_valid : _T_2761 ? _Queue64_UInt8_15_io_deq_valid : _T_2760 ? _Queue64_UInt8_14_io_deq_valid : _T_2759 ? _Queue64_UInt8_13_io_deq_valid : _T_2758 ? _Queue64_UInt8_12_io_deq_valid : _T_2757 ? _Queue64_UInt8_11_io_deq_valid : _T_2756 ? _Queue64_UInt8_10_io_deq_valid : _T_2755 ? _Queue64_UInt8_9_io_deq_valid : _T_2754 ? _Queue64_UInt8_8_io_deq_valid : _T_2753 ? _Queue64_UInt8_7_io_deq_valid : _T_2752 ? _Queue64_UInt8_6_io_deq_valid : _T_2751 ? _Queue64_UInt8_5_io_deq_valid : _T_2750 ? _Queue64_UInt8_4_io_deq_valid : _T_2749 ? _Queue64_UInt8_3_io_deq_valid : _T_2748 ? _Queue64_UInt8_2_io_deq_valid : _T_2747 ? _Queue64_UInt8_1_io_deq_valid : _T_2746 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[MemLoader.scala:177:33] wire [6:0] _GEN_106 = _remapindex_T_14 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_14 = _GEN_106[5:0]; // @[MemLoader.scala:177:54] wire _T_2778 = remapindex_14 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2779 = remapindex_14 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2780 = remapindex_14 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2781 = remapindex_14 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2782 = remapindex_14 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2783 = remapindex_14 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2784 = remapindex_14 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2785 = remapindex_14 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2786 = remapindex_14 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2787 = remapindex_14 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2788 = remapindex_14 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2789 = remapindex_14 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2790 = remapindex_14 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2791 = remapindex_14 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2792 = remapindex_14 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2793 = remapindex_14 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2794 = remapindex_14 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2795 = remapindex_14 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2796 = remapindex_14 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2797 = remapindex_14 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2798 = remapindex_14 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2799 = remapindex_14 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2800 = remapindex_14 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2801 = remapindex_14 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2802 = remapindex_14 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2803 = remapindex_14 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2804 = remapindex_14 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2805 = remapindex_14 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2806 = remapindex_14 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2807 = remapindex_14 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2808 = remapindex_14 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2809 = remapindex_14 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_14 = _T_2809 ? _Queue64_UInt8_31_io_deq_bits : _T_2808 ? _Queue64_UInt8_30_io_deq_bits : _T_2807 ? _Queue64_UInt8_29_io_deq_bits : _T_2806 ? _Queue64_UInt8_28_io_deq_bits : _T_2805 ? _Queue64_UInt8_27_io_deq_bits : _T_2804 ? _Queue64_UInt8_26_io_deq_bits : _T_2803 ? _Queue64_UInt8_25_io_deq_bits : _T_2802 ? _Queue64_UInt8_24_io_deq_bits : _T_2801 ? _Queue64_UInt8_23_io_deq_bits : _T_2800 ? _Queue64_UInt8_22_io_deq_bits : _T_2799 ? _Queue64_UInt8_21_io_deq_bits : _T_2798 ? _Queue64_UInt8_20_io_deq_bits : _T_2797 ? _Queue64_UInt8_19_io_deq_bits : _T_2796 ? _Queue64_UInt8_18_io_deq_bits : _T_2795 ? _Queue64_UInt8_17_io_deq_bits : _T_2794 ? _Queue64_UInt8_16_io_deq_bits : _T_2793 ? _Queue64_UInt8_15_io_deq_bits : _T_2792 ? _Queue64_UInt8_14_io_deq_bits : _T_2791 ? _Queue64_UInt8_13_io_deq_bits : _T_2790 ? _Queue64_UInt8_12_io_deq_bits : _T_2789 ? _Queue64_UInt8_11_io_deq_bits : _T_2788 ? _Queue64_UInt8_10_io_deq_bits : _T_2787 ? _Queue64_UInt8_9_io_deq_bits : _T_2786 ? _Queue64_UInt8_8_io_deq_bits : _T_2785 ? _Queue64_UInt8_7_io_deq_bits : _T_2784 ? _Queue64_UInt8_6_io_deq_bits : _T_2783 ? _Queue64_UInt8_5_io_deq_bits : _T_2782 ? _Queue64_UInt8_4_io_deq_bits : _T_2781 ? _Queue64_UInt8_3_io_deq_bits : _T_2780 ? _Queue64_UInt8_2_io_deq_bits : _T_2779 ? _Queue64_UInt8_1_io_deq_bits : _T_2778 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_14 = _T_2809 ? _Queue64_UInt8_31_io_deq_valid : _T_2808 ? _Queue64_UInt8_30_io_deq_valid : _T_2807 ? _Queue64_UInt8_29_io_deq_valid : _T_2806 ? _Queue64_UInt8_28_io_deq_valid : _T_2805 ? _Queue64_UInt8_27_io_deq_valid : _T_2804 ? _Queue64_UInt8_26_io_deq_valid : _T_2803 ? _Queue64_UInt8_25_io_deq_valid : _T_2802 ? _Queue64_UInt8_24_io_deq_valid : _T_2801 ? _Queue64_UInt8_23_io_deq_valid : _T_2800 ? _Queue64_UInt8_22_io_deq_valid : _T_2799 ? _Queue64_UInt8_21_io_deq_valid : _T_2798 ? _Queue64_UInt8_20_io_deq_valid : _T_2797 ? _Queue64_UInt8_19_io_deq_valid : _T_2796 ? _Queue64_UInt8_18_io_deq_valid : _T_2795 ? _Queue64_UInt8_17_io_deq_valid : _T_2794 ? _Queue64_UInt8_16_io_deq_valid : _T_2793 ? _Queue64_UInt8_15_io_deq_valid : _T_2792 ? _Queue64_UInt8_14_io_deq_valid : _T_2791 ? _Queue64_UInt8_13_io_deq_valid : _T_2790 ? _Queue64_UInt8_12_io_deq_valid : _T_2789 ? _Queue64_UInt8_11_io_deq_valid : _T_2788 ? _Queue64_UInt8_10_io_deq_valid : _T_2787 ? _Queue64_UInt8_9_io_deq_valid : _T_2786 ? _Queue64_UInt8_8_io_deq_valid : _T_2785 ? _Queue64_UInt8_7_io_deq_valid : _T_2784 ? _Queue64_UInt8_6_io_deq_valid : _T_2783 ? _Queue64_UInt8_5_io_deq_valid : _T_2782 ? _Queue64_UInt8_4_io_deq_valid : _T_2781 ? _Queue64_UInt8_3_io_deq_valid : _T_2780 ? _Queue64_UInt8_2_io_deq_valid : _T_2779 ? _Queue64_UInt8_1_io_deq_valid : _T_2778 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[MemLoader.scala:177:33] wire [6:0] _GEN_107 = _remapindex_T_15 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_15 = _GEN_107[5:0]; // @[MemLoader.scala:177:54] wire _T_2810 = remapindex_15 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2811 = remapindex_15 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2812 = remapindex_15 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2813 = remapindex_15 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2814 = remapindex_15 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2815 = remapindex_15 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2816 = remapindex_15 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2817 = remapindex_15 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2818 = remapindex_15 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2819 = remapindex_15 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2820 = remapindex_15 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2821 = remapindex_15 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2822 = remapindex_15 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2823 = remapindex_15 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2824 = remapindex_15 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2825 = remapindex_15 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2826 = remapindex_15 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2827 = remapindex_15 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2828 = remapindex_15 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2829 = remapindex_15 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2830 = remapindex_15 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2831 = remapindex_15 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2832 = remapindex_15 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2833 = remapindex_15 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2834 = remapindex_15 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2835 = remapindex_15 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2836 = remapindex_15 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2837 = remapindex_15 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2838 = remapindex_15 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2839 = remapindex_15 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2840 = remapindex_15 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2841 = remapindex_15 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_15 = _T_2841 ? _Queue64_UInt8_31_io_deq_bits : _T_2840 ? _Queue64_UInt8_30_io_deq_bits : _T_2839 ? _Queue64_UInt8_29_io_deq_bits : _T_2838 ? _Queue64_UInt8_28_io_deq_bits : _T_2837 ? _Queue64_UInt8_27_io_deq_bits : _T_2836 ? _Queue64_UInt8_26_io_deq_bits : _T_2835 ? _Queue64_UInt8_25_io_deq_bits : _T_2834 ? _Queue64_UInt8_24_io_deq_bits : _T_2833 ? _Queue64_UInt8_23_io_deq_bits : _T_2832 ? _Queue64_UInt8_22_io_deq_bits : _T_2831 ? _Queue64_UInt8_21_io_deq_bits : _T_2830 ? _Queue64_UInt8_20_io_deq_bits : _T_2829 ? _Queue64_UInt8_19_io_deq_bits : _T_2828 ? _Queue64_UInt8_18_io_deq_bits : _T_2827 ? _Queue64_UInt8_17_io_deq_bits : _T_2826 ? _Queue64_UInt8_16_io_deq_bits : _T_2825 ? _Queue64_UInt8_15_io_deq_bits : _T_2824 ? _Queue64_UInt8_14_io_deq_bits : _T_2823 ? _Queue64_UInt8_13_io_deq_bits : _T_2822 ? _Queue64_UInt8_12_io_deq_bits : _T_2821 ? _Queue64_UInt8_11_io_deq_bits : _T_2820 ? _Queue64_UInt8_10_io_deq_bits : _T_2819 ? _Queue64_UInt8_9_io_deq_bits : _T_2818 ? _Queue64_UInt8_8_io_deq_bits : _T_2817 ? _Queue64_UInt8_7_io_deq_bits : _T_2816 ? _Queue64_UInt8_6_io_deq_bits : _T_2815 ? _Queue64_UInt8_5_io_deq_bits : _T_2814 ? _Queue64_UInt8_4_io_deq_bits : _T_2813 ? _Queue64_UInt8_3_io_deq_bits : _T_2812 ? _Queue64_UInt8_2_io_deq_bits : _T_2811 ? _Queue64_UInt8_1_io_deq_bits : _T_2810 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_15 = _T_2841 ? _Queue64_UInt8_31_io_deq_valid : _T_2840 ? _Queue64_UInt8_30_io_deq_valid : _T_2839 ? _Queue64_UInt8_29_io_deq_valid : _T_2838 ? _Queue64_UInt8_28_io_deq_valid : _T_2837 ? _Queue64_UInt8_27_io_deq_valid : _T_2836 ? _Queue64_UInt8_26_io_deq_valid : _T_2835 ? _Queue64_UInt8_25_io_deq_valid : _T_2834 ? _Queue64_UInt8_24_io_deq_valid : _T_2833 ? _Queue64_UInt8_23_io_deq_valid : _T_2832 ? _Queue64_UInt8_22_io_deq_valid : _T_2831 ? _Queue64_UInt8_21_io_deq_valid : _T_2830 ? _Queue64_UInt8_20_io_deq_valid : _T_2829 ? _Queue64_UInt8_19_io_deq_valid : _T_2828 ? _Queue64_UInt8_18_io_deq_valid : _T_2827 ? _Queue64_UInt8_17_io_deq_valid : _T_2826 ? _Queue64_UInt8_16_io_deq_valid : _T_2825 ? _Queue64_UInt8_15_io_deq_valid : _T_2824 ? _Queue64_UInt8_14_io_deq_valid : _T_2823 ? _Queue64_UInt8_13_io_deq_valid : _T_2822 ? _Queue64_UInt8_12_io_deq_valid : _T_2821 ? _Queue64_UInt8_11_io_deq_valid : _T_2820 ? _Queue64_UInt8_10_io_deq_valid : _T_2819 ? _Queue64_UInt8_9_io_deq_valid : _T_2818 ? _Queue64_UInt8_8_io_deq_valid : _T_2817 ? _Queue64_UInt8_7_io_deq_valid : _T_2816 ? _Queue64_UInt8_6_io_deq_valid : _T_2815 ? _Queue64_UInt8_5_io_deq_valid : _T_2814 ? _Queue64_UInt8_4_io_deq_valid : _T_2813 ? _Queue64_UInt8_3_io_deq_valid : _T_2812 ? _Queue64_UInt8_2_io_deq_valid : _T_2811 ? _Queue64_UInt8_1_io_deq_valid : _T_2810 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[MemLoader.scala:177:33] wire [6:0] _GEN_108 = _remapindex_T_16 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_16 = _GEN_108[5:0]; // @[MemLoader.scala:177:54] wire _T_2842 = remapindex_16 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2843 = remapindex_16 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2844 = remapindex_16 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2845 = remapindex_16 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2846 = remapindex_16 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2847 = remapindex_16 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2848 = remapindex_16 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2849 = remapindex_16 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2850 = remapindex_16 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2851 = remapindex_16 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2852 = remapindex_16 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2853 = remapindex_16 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2854 = remapindex_16 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2855 = remapindex_16 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2856 = remapindex_16 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2857 = remapindex_16 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2858 = remapindex_16 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2859 = remapindex_16 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2860 = remapindex_16 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2861 = remapindex_16 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2862 = remapindex_16 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2863 = remapindex_16 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2864 = remapindex_16 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2865 = remapindex_16 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2866 = remapindex_16 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2867 = remapindex_16 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2868 = remapindex_16 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2869 = remapindex_16 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2870 = remapindex_16 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2871 = remapindex_16 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2872 = remapindex_16 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2873 = remapindex_16 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_16 = _T_2873 ? _Queue64_UInt8_31_io_deq_bits : _T_2872 ? _Queue64_UInt8_30_io_deq_bits : _T_2871 ? _Queue64_UInt8_29_io_deq_bits : _T_2870 ? _Queue64_UInt8_28_io_deq_bits : _T_2869 ? _Queue64_UInt8_27_io_deq_bits : _T_2868 ? _Queue64_UInt8_26_io_deq_bits : _T_2867 ? _Queue64_UInt8_25_io_deq_bits : _T_2866 ? _Queue64_UInt8_24_io_deq_bits : _T_2865 ? _Queue64_UInt8_23_io_deq_bits : _T_2864 ? _Queue64_UInt8_22_io_deq_bits : _T_2863 ? _Queue64_UInt8_21_io_deq_bits : _T_2862 ? _Queue64_UInt8_20_io_deq_bits : _T_2861 ? _Queue64_UInt8_19_io_deq_bits : _T_2860 ? _Queue64_UInt8_18_io_deq_bits : _T_2859 ? _Queue64_UInt8_17_io_deq_bits : _T_2858 ? _Queue64_UInt8_16_io_deq_bits : _T_2857 ? _Queue64_UInt8_15_io_deq_bits : _T_2856 ? _Queue64_UInt8_14_io_deq_bits : _T_2855 ? _Queue64_UInt8_13_io_deq_bits : _T_2854 ? _Queue64_UInt8_12_io_deq_bits : _T_2853 ? _Queue64_UInt8_11_io_deq_bits : _T_2852 ? _Queue64_UInt8_10_io_deq_bits : _T_2851 ? _Queue64_UInt8_9_io_deq_bits : _T_2850 ? _Queue64_UInt8_8_io_deq_bits : _T_2849 ? _Queue64_UInt8_7_io_deq_bits : _T_2848 ? _Queue64_UInt8_6_io_deq_bits : _T_2847 ? _Queue64_UInt8_5_io_deq_bits : _T_2846 ? _Queue64_UInt8_4_io_deq_bits : _T_2845 ? _Queue64_UInt8_3_io_deq_bits : _T_2844 ? _Queue64_UInt8_2_io_deq_bits : _T_2843 ? _Queue64_UInt8_1_io_deq_bits : _T_2842 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_16 = _T_2873 ? _Queue64_UInt8_31_io_deq_valid : _T_2872 ? _Queue64_UInt8_30_io_deq_valid : _T_2871 ? _Queue64_UInt8_29_io_deq_valid : _T_2870 ? _Queue64_UInt8_28_io_deq_valid : _T_2869 ? _Queue64_UInt8_27_io_deq_valid : _T_2868 ? _Queue64_UInt8_26_io_deq_valid : _T_2867 ? _Queue64_UInt8_25_io_deq_valid : _T_2866 ? _Queue64_UInt8_24_io_deq_valid : _T_2865 ? _Queue64_UInt8_23_io_deq_valid : _T_2864 ? _Queue64_UInt8_22_io_deq_valid : _T_2863 ? _Queue64_UInt8_21_io_deq_valid : _T_2862 ? _Queue64_UInt8_20_io_deq_valid : _T_2861 ? _Queue64_UInt8_19_io_deq_valid : _T_2860 ? _Queue64_UInt8_18_io_deq_valid : _T_2859 ? _Queue64_UInt8_17_io_deq_valid : _T_2858 ? _Queue64_UInt8_16_io_deq_valid : _T_2857 ? _Queue64_UInt8_15_io_deq_valid : _T_2856 ? _Queue64_UInt8_14_io_deq_valid : _T_2855 ? _Queue64_UInt8_13_io_deq_valid : _T_2854 ? _Queue64_UInt8_12_io_deq_valid : _T_2853 ? _Queue64_UInt8_11_io_deq_valid : _T_2852 ? _Queue64_UInt8_10_io_deq_valid : _T_2851 ? _Queue64_UInt8_9_io_deq_valid : _T_2850 ? _Queue64_UInt8_8_io_deq_valid : _T_2849 ? _Queue64_UInt8_7_io_deq_valid : _T_2848 ? _Queue64_UInt8_6_io_deq_valid : _T_2847 ? _Queue64_UInt8_5_io_deq_valid : _T_2846 ? _Queue64_UInt8_4_io_deq_valid : _T_2845 ? _Queue64_UInt8_3_io_deq_valid : _T_2844 ? _Queue64_UInt8_2_io_deq_valid : _T_2843 ? _Queue64_UInt8_1_io_deq_valid : _T_2842 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[MemLoader.scala:177:33] wire [6:0] _GEN_109 = _remapindex_T_17 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_17 = _GEN_109[5:0]; // @[MemLoader.scala:177:54] wire _T_2874 = remapindex_17 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2875 = remapindex_17 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2876 = remapindex_17 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2877 = remapindex_17 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2878 = remapindex_17 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2879 = remapindex_17 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2880 = remapindex_17 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2881 = remapindex_17 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2882 = remapindex_17 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2883 = remapindex_17 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2884 = remapindex_17 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2885 = remapindex_17 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2886 = remapindex_17 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2887 = remapindex_17 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2888 = remapindex_17 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2889 = remapindex_17 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2890 = remapindex_17 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2891 = remapindex_17 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2892 = remapindex_17 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2893 = remapindex_17 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2894 = remapindex_17 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2895 = remapindex_17 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2896 = remapindex_17 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2897 = remapindex_17 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2898 = remapindex_17 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2899 = remapindex_17 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2900 = remapindex_17 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2901 = remapindex_17 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2902 = remapindex_17 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2903 = remapindex_17 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2904 = remapindex_17 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2905 = remapindex_17 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_17 = _T_2905 ? _Queue64_UInt8_31_io_deq_bits : _T_2904 ? _Queue64_UInt8_30_io_deq_bits : _T_2903 ? _Queue64_UInt8_29_io_deq_bits : _T_2902 ? _Queue64_UInt8_28_io_deq_bits : _T_2901 ? _Queue64_UInt8_27_io_deq_bits : _T_2900 ? _Queue64_UInt8_26_io_deq_bits : _T_2899 ? _Queue64_UInt8_25_io_deq_bits : _T_2898 ? _Queue64_UInt8_24_io_deq_bits : _T_2897 ? _Queue64_UInt8_23_io_deq_bits : _T_2896 ? _Queue64_UInt8_22_io_deq_bits : _T_2895 ? _Queue64_UInt8_21_io_deq_bits : _T_2894 ? _Queue64_UInt8_20_io_deq_bits : _T_2893 ? _Queue64_UInt8_19_io_deq_bits : _T_2892 ? _Queue64_UInt8_18_io_deq_bits : _T_2891 ? _Queue64_UInt8_17_io_deq_bits : _T_2890 ? _Queue64_UInt8_16_io_deq_bits : _T_2889 ? _Queue64_UInt8_15_io_deq_bits : _T_2888 ? _Queue64_UInt8_14_io_deq_bits : _T_2887 ? _Queue64_UInt8_13_io_deq_bits : _T_2886 ? _Queue64_UInt8_12_io_deq_bits : _T_2885 ? _Queue64_UInt8_11_io_deq_bits : _T_2884 ? _Queue64_UInt8_10_io_deq_bits : _T_2883 ? _Queue64_UInt8_9_io_deq_bits : _T_2882 ? _Queue64_UInt8_8_io_deq_bits : _T_2881 ? _Queue64_UInt8_7_io_deq_bits : _T_2880 ? _Queue64_UInt8_6_io_deq_bits : _T_2879 ? _Queue64_UInt8_5_io_deq_bits : _T_2878 ? _Queue64_UInt8_4_io_deq_bits : _T_2877 ? _Queue64_UInt8_3_io_deq_bits : _T_2876 ? _Queue64_UInt8_2_io_deq_bits : _T_2875 ? _Queue64_UInt8_1_io_deq_bits : _T_2874 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_17 = _T_2905 ? _Queue64_UInt8_31_io_deq_valid : _T_2904 ? _Queue64_UInt8_30_io_deq_valid : _T_2903 ? _Queue64_UInt8_29_io_deq_valid : _T_2902 ? _Queue64_UInt8_28_io_deq_valid : _T_2901 ? _Queue64_UInt8_27_io_deq_valid : _T_2900 ? _Queue64_UInt8_26_io_deq_valid : _T_2899 ? _Queue64_UInt8_25_io_deq_valid : _T_2898 ? _Queue64_UInt8_24_io_deq_valid : _T_2897 ? _Queue64_UInt8_23_io_deq_valid : _T_2896 ? _Queue64_UInt8_22_io_deq_valid : _T_2895 ? _Queue64_UInt8_21_io_deq_valid : _T_2894 ? _Queue64_UInt8_20_io_deq_valid : _T_2893 ? _Queue64_UInt8_19_io_deq_valid : _T_2892 ? _Queue64_UInt8_18_io_deq_valid : _T_2891 ? _Queue64_UInt8_17_io_deq_valid : _T_2890 ? _Queue64_UInt8_16_io_deq_valid : _T_2889 ? _Queue64_UInt8_15_io_deq_valid : _T_2888 ? _Queue64_UInt8_14_io_deq_valid : _T_2887 ? _Queue64_UInt8_13_io_deq_valid : _T_2886 ? _Queue64_UInt8_12_io_deq_valid : _T_2885 ? _Queue64_UInt8_11_io_deq_valid : _T_2884 ? _Queue64_UInt8_10_io_deq_valid : _T_2883 ? _Queue64_UInt8_9_io_deq_valid : _T_2882 ? _Queue64_UInt8_8_io_deq_valid : _T_2881 ? _Queue64_UInt8_7_io_deq_valid : _T_2880 ? _Queue64_UInt8_6_io_deq_valid : _T_2879 ? _Queue64_UInt8_5_io_deq_valid : _T_2878 ? _Queue64_UInt8_4_io_deq_valid : _T_2877 ? _Queue64_UInt8_3_io_deq_valid : _T_2876 ? _Queue64_UInt8_2_io_deq_valid : _T_2875 ? _Queue64_UInt8_1_io_deq_valid : _T_2874 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[MemLoader.scala:177:33] wire [6:0] _GEN_110 = _remapindex_T_18 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_18 = _GEN_110[5:0]; // @[MemLoader.scala:177:54] wire _T_2906 = remapindex_18 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2907 = remapindex_18 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2908 = remapindex_18 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2909 = remapindex_18 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2910 = remapindex_18 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2911 = remapindex_18 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2912 = remapindex_18 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2913 = remapindex_18 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2914 = remapindex_18 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2915 = remapindex_18 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2916 = remapindex_18 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2917 = remapindex_18 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2918 = remapindex_18 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2919 = remapindex_18 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2920 = remapindex_18 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2921 = remapindex_18 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2922 = remapindex_18 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2923 = remapindex_18 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2924 = remapindex_18 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2925 = remapindex_18 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2926 = remapindex_18 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2927 = remapindex_18 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2928 = remapindex_18 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2929 = remapindex_18 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2930 = remapindex_18 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2931 = remapindex_18 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2932 = remapindex_18 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2933 = remapindex_18 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2934 = remapindex_18 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2935 = remapindex_18 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2936 = remapindex_18 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2937 = remapindex_18 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_18 = _T_2937 ? _Queue64_UInt8_31_io_deq_bits : _T_2936 ? _Queue64_UInt8_30_io_deq_bits : _T_2935 ? _Queue64_UInt8_29_io_deq_bits : _T_2934 ? _Queue64_UInt8_28_io_deq_bits : _T_2933 ? _Queue64_UInt8_27_io_deq_bits : _T_2932 ? _Queue64_UInt8_26_io_deq_bits : _T_2931 ? _Queue64_UInt8_25_io_deq_bits : _T_2930 ? _Queue64_UInt8_24_io_deq_bits : _T_2929 ? _Queue64_UInt8_23_io_deq_bits : _T_2928 ? _Queue64_UInt8_22_io_deq_bits : _T_2927 ? _Queue64_UInt8_21_io_deq_bits : _T_2926 ? _Queue64_UInt8_20_io_deq_bits : _T_2925 ? _Queue64_UInt8_19_io_deq_bits : _T_2924 ? _Queue64_UInt8_18_io_deq_bits : _T_2923 ? _Queue64_UInt8_17_io_deq_bits : _T_2922 ? _Queue64_UInt8_16_io_deq_bits : _T_2921 ? _Queue64_UInt8_15_io_deq_bits : _T_2920 ? _Queue64_UInt8_14_io_deq_bits : _T_2919 ? _Queue64_UInt8_13_io_deq_bits : _T_2918 ? _Queue64_UInt8_12_io_deq_bits : _T_2917 ? _Queue64_UInt8_11_io_deq_bits : _T_2916 ? _Queue64_UInt8_10_io_deq_bits : _T_2915 ? _Queue64_UInt8_9_io_deq_bits : _T_2914 ? _Queue64_UInt8_8_io_deq_bits : _T_2913 ? _Queue64_UInt8_7_io_deq_bits : _T_2912 ? _Queue64_UInt8_6_io_deq_bits : _T_2911 ? _Queue64_UInt8_5_io_deq_bits : _T_2910 ? _Queue64_UInt8_4_io_deq_bits : _T_2909 ? _Queue64_UInt8_3_io_deq_bits : _T_2908 ? _Queue64_UInt8_2_io_deq_bits : _T_2907 ? _Queue64_UInt8_1_io_deq_bits : _T_2906 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_18 = _T_2937 ? _Queue64_UInt8_31_io_deq_valid : _T_2936 ? _Queue64_UInt8_30_io_deq_valid : _T_2935 ? _Queue64_UInt8_29_io_deq_valid : _T_2934 ? _Queue64_UInt8_28_io_deq_valid : _T_2933 ? _Queue64_UInt8_27_io_deq_valid : _T_2932 ? _Queue64_UInt8_26_io_deq_valid : _T_2931 ? _Queue64_UInt8_25_io_deq_valid : _T_2930 ? _Queue64_UInt8_24_io_deq_valid : _T_2929 ? _Queue64_UInt8_23_io_deq_valid : _T_2928 ? _Queue64_UInt8_22_io_deq_valid : _T_2927 ? _Queue64_UInt8_21_io_deq_valid : _T_2926 ? _Queue64_UInt8_20_io_deq_valid : _T_2925 ? _Queue64_UInt8_19_io_deq_valid : _T_2924 ? _Queue64_UInt8_18_io_deq_valid : _T_2923 ? _Queue64_UInt8_17_io_deq_valid : _T_2922 ? _Queue64_UInt8_16_io_deq_valid : _T_2921 ? _Queue64_UInt8_15_io_deq_valid : _T_2920 ? _Queue64_UInt8_14_io_deq_valid : _T_2919 ? _Queue64_UInt8_13_io_deq_valid : _T_2918 ? _Queue64_UInt8_12_io_deq_valid : _T_2917 ? _Queue64_UInt8_11_io_deq_valid : _T_2916 ? _Queue64_UInt8_10_io_deq_valid : _T_2915 ? _Queue64_UInt8_9_io_deq_valid : _T_2914 ? _Queue64_UInt8_8_io_deq_valid : _T_2913 ? _Queue64_UInt8_7_io_deq_valid : _T_2912 ? _Queue64_UInt8_6_io_deq_valid : _T_2911 ? _Queue64_UInt8_5_io_deq_valid : _T_2910 ? _Queue64_UInt8_4_io_deq_valid : _T_2909 ? _Queue64_UInt8_3_io_deq_valid : _T_2908 ? _Queue64_UInt8_2_io_deq_valid : _T_2907 ? _Queue64_UInt8_1_io_deq_valid : _T_2906 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[MemLoader.scala:177:33] wire [6:0] _GEN_111 = _remapindex_T_19 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_19 = _GEN_111[5:0]; // @[MemLoader.scala:177:54] wire _T_2938 = remapindex_19 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2939 = remapindex_19 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2940 = remapindex_19 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2941 = remapindex_19 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2942 = remapindex_19 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2943 = remapindex_19 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2944 = remapindex_19 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2945 = remapindex_19 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2946 = remapindex_19 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2947 = remapindex_19 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2948 = remapindex_19 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2949 = remapindex_19 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2950 = remapindex_19 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2951 = remapindex_19 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2952 = remapindex_19 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2953 = remapindex_19 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2954 = remapindex_19 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2955 = remapindex_19 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2956 = remapindex_19 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2957 = remapindex_19 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2958 = remapindex_19 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2959 = remapindex_19 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2960 = remapindex_19 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2961 = remapindex_19 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2962 = remapindex_19 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2963 = remapindex_19 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2964 = remapindex_19 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2965 = remapindex_19 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2966 = remapindex_19 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2967 = remapindex_19 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2968 = remapindex_19 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2969 = remapindex_19 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_19 = _T_2969 ? _Queue64_UInt8_31_io_deq_bits : _T_2968 ? _Queue64_UInt8_30_io_deq_bits : _T_2967 ? _Queue64_UInt8_29_io_deq_bits : _T_2966 ? _Queue64_UInt8_28_io_deq_bits : _T_2965 ? _Queue64_UInt8_27_io_deq_bits : _T_2964 ? _Queue64_UInt8_26_io_deq_bits : _T_2963 ? _Queue64_UInt8_25_io_deq_bits : _T_2962 ? _Queue64_UInt8_24_io_deq_bits : _T_2961 ? _Queue64_UInt8_23_io_deq_bits : _T_2960 ? _Queue64_UInt8_22_io_deq_bits : _T_2959 ? _Queue64_UInt8_21_io_deq_bits : _T_2958 ? _Queue64_UInt8_20_io_deq_bits : _T_2957 ? _Queue64_UInt8_19_io_deq_bits : _T_2956 ? _Queue64_UInt8_18_io_deq_bits : _T_2955 ? _Queue64_UInt8_17_io_deq_bits : _T_2954 ? _Queue64_UInt8_16_io_deq_bits : _T_2953 ? _Queue64_UInt8_15_io_deq_bits : _T_2952 ? _Queue64_UInt8_14_io_deq_bits : _T_2951 ? _Queue64_UInt8_13_io_deq_bits : _T_2950 ? _Queue64_UInt8_12_io_deq_bits : _T_2949 ? _Queue64_UInt8_11_io_deq_bits : _T_2948 ? _Queue64_UInt8_10_io_deq_bits : _T_2947 ? _Queue64_UInt8_9_io_deq_bits : _T_2946 ? _Queue64_UInt8_8_io_deq_bits : _T_2945 ? _Queue64_UInt8_7_io_deq_bits : _T_2944 ? _Queue64_UInt8_6_io_deq_bits : _T_2943 ? _Queue64_UInt8_5_io_deq_bits : _T_2942 ? _Queue64_UInt8_4_io_deq_bits : _T_2941 ? _Queue64_UInt8_3_io_deq_bits : _T_2940 ? _Queue64_UInt8_2_io_deq_bits : _T_2939 ? _Queue64_UInt8_1_io_deq_bits : _T_2938 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_19 = _T_2969 ? _Queue64_UInt8_31_io_deq_valid : _T_2968 ? _Queue64_UInt8_30_io_deq_valid : _T_2967 ? _Queue64_UInt8_29_io_deq_valid : _T_2966 ? _Queue64_UInt8_28_io_deq_valid : _T_2965 ? _Queue64_UInt8_27_io_deq_valid : _T_2964 ? _Queue64_UInt8_26_io_deq_valid : _T_2963 ? _Queue64_UInt8_25_io_deq_valid : _T_2962 ? _Queue64_UInt8_24_io_deq_valid : _T_2961 ? _Queue64_UInt8_23_io_deq_valid : _T_2960 ? _Queue64_UInt8_22_io_deq_valid : _T_2959 ? _Queue64_UInt8_21_io_deq_valid : _T_2958 ? _Queue64_UInt8_20_io_deq_valid : _T_2957 ? _Queue64_UInt8_19_io_deq_valid : _T_2956 ? _Queue64_UInt8_18_io_deq_valid : _T_2955 ? _Queue64_UInt8_17_io_deq_valid : _T_2954 ? _Queue64_UInt8_16_io_deq_valid : _T_2953 ? _Queue64_UInt8_15_io_deq_valid : _T_2952 ? _Queue64_UInt8_14_io_deq_valid : _T_2951 ? _Queue64_UInt8_13_io_deq_valid : _T_2950 ? _Queue64_UInt8_12_io_deq_valid : _T_2949 ? _Queue64_UInt8_11_io_deq_valid : _T_2948 ? _Queue64_UInt8_10_io_deq_valid : _T_2947 ? _Queue64_UInt8_9_io_deq_valid : _T_2946 ? _Queue64_UInt8_8_io_deq_valid : _T_2945 ? _Queue64_UInt8_7_io_deq_valid : _T_2944 ? _Queue64_UInt8_6_io_deq_valid : _T_2943 ? _Queue64_UInt8_5_io_deq_valid : _T_2942 ? _Queue64_UInt8_4_io_deq_valid : _T_2941 ? _Queue64_UInt8_3_io_deq_valid : _T_2940 ? _Queue64_UInt8_2_io_deq_valid : _T_2939 ? _Queue64_UInt8_1_io_deq_valid : _T_2938 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[MemLoader.scala:177:33] wire [6:0] _GEN_112 = _remapindex_T_20 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_20 = _GEN_112[5:0]; // @[MemLoader.scala:177:54] wire _T_2970 = remapindex_20 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2971 = remapindex_20 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2972 = remapindex_20 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2973 = remapindex_20 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2974 = remapindex_20 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2975 = remapindex_20 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2976 = remapindex_20 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2977 = remapindex_20 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2978 = remapindex_20 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2979 = remapindex_20 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2980 = remapindex_20 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2981 = remapindex_20 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2982 = remapindex_20 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2983 = remapindex_20 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2984 = remapindex_20 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2985 = remapindex_20 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2986 = remapindex_20 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2987 = remapindex_20 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2988 = remapindex_20 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2989 = remapindex_20 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2990 = remapindex_20 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2991 = remapindex_20 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2992 = remapindex_20 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2993 = remapindex_20 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2994 = remapindex_20 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2995 = remapindex_20 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2996 = remapindex_20 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2997 = remapindex_20 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2998 = remapindex_20 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2999 = remapindex_20 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3000 = remapindex_20 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3001 = remapindex_20 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_20 = _T_3001 ? _Queue64_UInt8_31_io_deq_bits : _T_3000 ? _Queue64_UInt8_30_io_deq_bits : _T_2999 ? _Queue64_UInt8_29_io_deq_bits : _T_2998 ? _Queue64_UInt8_28_io_deq_bits : _T_2997 ? _Queue64_UInt8_27_io_deq_bits : _T_2996 ? _Queue64_UInt8_26_io_deq_bits : _T_2995 ? _Queue64_UInt8_25_io_deq_bits : _T_2994 ? _Queue64_UInt8_24_io_deq_bits : _T_2993 ? _Queue64_UInt8_23_io_deq_bits : _T_2992 ? _Queue64_UInt8_22_io_deq_bits : _T_2991 ? _Queue64_UInt8_21_io_deq_bits : _T_2990 ? _Queue64_UInt8_20_io_deq_bits : _T_2989 ? _Queue64_UInt8_19_io_deq_bits : _T_2988 ? _Queue64_UInt8_18_io_deq_bits : _T_2987 ? _Queue64_UInt8_17_io_deq_bits : _T_2986 ? _Queue64_UInt8_16_io_deq_bits : _T_2985 ? _Queue64_UInt8_15_io_deq_bits : _T_2984 ? _Queue64_UInt8_14_io_deq_bits : _T_2983 ? _Queue64_UInt8_13_io_deq_bits : _T_2982 ? _Queue64_UInt8_12_io_deq_bits : _T_2981 ? _Queue64_UInt8_11_io_deq_bits : _T_2980 ? _Queue64_UInt8_10_io_deq_bits : _T_2979 ? _Queue64_UInt8_9_io_deq_bits : _T_2978 ? _Queue64_UInt8_8_io_deq_bits : _T_2977 ? _Queue64_UInt8_7_io_deq_bits : _T_2976 ? _Queue64_UInt8_6_io_deq_bits : _T_2975 ? _Queue64_UInt8_5_io_deq_bits : _T_2974 ? _Queue64_UInt8_4_io_deq_bits : _T_2973 ? _Queue64_UInt8_3_io_deq_bits : _T_2972 ? _Queue64_UInt8_2_io_deq_bits : _T_2971 ? _Queue64_UInt8_1_io_deq_bits : _T_2970 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_20 = _T_3001 ? _Queue64_UInt8_31_io_deq_valid : _T_3000 ? _Queue64_UInt8_30_io_deq_valid : _T_2999 ? _Queue64_UInt8_29_io_deq_valid : _T_2998 ? _Queue64_UInt8_28_io_deq_valid : _T_2997 ? _Queue64_UInt8_27_io_deq_valid : _T_2996 ? _Queue64_UInt8_26_io_deq_valid : _T_2995 ? _Queue64_UInt8_25_io_deq_valid : _T_2994 ? _Queue64_UInt8_24_io_deq_valid : _T_2993 ? _Queue64_UInt8_23_io_deq_valid : _T_2992 ? _Queue64_UInt8_22_io_deq_valid : _T_2991 ? _Queue64_UInt8_21_io_deq_valid : _T_2990 ? _Queue64_UInt8_20_io_deq_valid : _T_2989 ? _Queue64_UInt8_19_io_deq_valid : _T_2988 ? _Queue64_UInt8_18_io_deq_valid : _T_2987 ? _Queue64_UInt8_17_io_deq_valid : _T_2986 ? _Queue64_UInt8_16_io_deq_valid : _T_2985 ? _Queue64_UInt8_15_io_deq_valid : _T_2984 ? _Queue64_UInt8_14_io_deq_valid : _T_2983 ? _Queue64_UInt8_13_io_deq_valid : _T_2982 ? _Queue64_UInt8_12_io_deq_valid : _T_2981 ? _Queue64_UInt8_11_io_deq_valid : _T_2980 ? _Queue64_UInt8_10_io_deq_valid : _T_2979 ? _Queue64_UInt8_9_io_deq_valid : _T_2978 ? _Queue64_UInt8_8_io_deq_valid : _T_2977 ? _Queue64_UInt8_7_io_deq_valid : _T_2976 ? _Queue64_UInt8_6_io_deq_valid : _T_2975 ? _Queue64_UInt8_5_io_deq_valid : _T_2974 ? _Queue64_UInt8_4_io_deq_valid : _T_2973 ? _Queue64_UInt8_3_io_deq_valid : _T_2972 ? _Queue64_UInt8_2_io_deq_valid : _T_2971 ? _Queue64_UInt8_1_io_deq_valid : _T_2970 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[MemLoader.scala:177:33] wire [6:0] _GEN_113 = _remapindex_T_21 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_21 = _GEN_113[5:0]; // @[MemLoader.scala:177:54] wire _T_3002 = remapindex_21 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3003 = remapindex_21 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3004 = remapindex_21 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3005 = remapindex_21 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3006 = remapindex_21 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3007 = remapindex_21 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3008 = remapindex_21 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3009 = remapindex_21 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3010 = remapindex_21 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3011 = remapindex_21 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3012 = remapindex_21 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3013 = remapindex_21 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3014 = remapindex_21 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3015 = remapindex_21 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3016 = remapindex_21 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3017 = remapindex_21 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3018 = remapindex_21 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3019 = remapindex_21 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3020 = remapindex_21 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3021 = remapindex_21 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3022 = remapindex_21 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3023 = remapindex_21 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3024 = remapindex_21 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3025 = remapindex_21 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3026 = remapindex_21 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3027 = remapindex_21 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3028 = remapindex_21 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3029 = remapindex_21 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3030 = remapindex_21 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3031 = remapindex_21 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3032 = remapindex_21 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3033 = remapindex_21 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_21 = _T_3033 ? _Queue64_UInt8_31_io_deq_bits : _T_3032 ? _Queue64_UInt8_30_io_deq_bits : _T_3031 ? _Queue64_UInt8_29_io_deq_bits : _T_3030 ? _Queue64_UInt8_28_io_deq_bits : _T_3029 ? _Queue64_UInt8_27_io_deq_bits : _T_3028 ? _Queue64_UInt8_26_io_deq_bits : _T_3027 ? _Queue64_UInt8_25_io_deq_bits : _T_3026 ? _Queue64_UInt8_24_io_deq_bits : _T_3025 ? _Queue64_UInt8_23_io_deq_bits : _T_3024 ? _Queue64_UInt8_22_io_deq_bits : _T_3023 ? _Queue64_UInt8_21_io_deq_bits : _T_3022 ? _Queue64_UInt8_20_io_deq_bits : _T_3021 ? _Queue64_UInt8_19_io_deq_bits : _T_3020 ? _Queue64_UInt8_18_io_deq_bits : _T_3019 ? _Queue64_UInt8_17_io_deq_bits : _T_3018 ? _Queue64_UInt8_16_io_deq_bits : _T_3017 ? _Queue64_UInt8_15_io_deq_bits : _T_3016 ? _Queue64_UInt8_14_io_deq_bits : _T_3015 ? _Queue64_UInt8_13_io_deq_bits : _T_3014 ? _Queue64_UInt8_12_io_deq_bits : _T_3013 ? _Queue64_UInt8_11_io_deq_bits : _T_3012 ? _Queue64_UInt8_10_io_deq_bits : _T_3011 ? _Queue64_UInt8_9_io_deq_bits : _T_3010 ? _Queue64_UInt8_8_io_deq_bits : _T_3009 ? _Queue64_UInt8_7_io_deq_bits : _T_3008 ? _Queue64_UInt8_6_io_deq_bits : _T_3007 ? _Queue64_UInt8_5_io_deq_bits : _T_3006 ? _Queue64_UInt8_4_io_deq_bits : _T_3005 ? _Queue64_UInt8_3_io_deq_bits : _T_3004 ? _Queue64_UInt8_2_io_deq_bits : _T_3003 ? _Queue64_UInt8_1_io_deq_bits : _T_3002 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_21 = _T_3033 ? _Queue64_UInt8_31_io_deq_valid : _T_3032 ? _Queue64_UInt8_30_io_deq_valid : _T_3031 ? _Queue64_UInt8_29_io_deq_valid : _T_3030 ? _Queue64_UInt8_28_io_deq_valid : _T_3029 ? _Queue64_UInt8_27_io_deq_valid : _T_3028 ? _Queue64_UInt8_26_io_deq_valid : _T_3027 ? _Queue64_UInt8_25_io_deq_valid : _T_3026 ? _Queue64_UInt8_24_io_deq_valid : _T_3025 ? _Queue64_UInt8_23_io_deq_valid : _T_3024 ? _Queue64_UInt8_22_io_deq_valid : _T_3023 ? _Queue64_UInt8_21_io_deq_valid : _T_3022 ? _Queue64_UInt8_20_io_deq_valid : _T_3021 ? _Queue64_UInt8_19_io_deq_valid : _T_3020 ? _Queue64_UInt8_18_io_deq_valid : _T_3019 ? _Queue64_UInt8_17_io_deq_valid : _T_3018 ? _Queue64_UInt8_16_io_deq_valid : _T_3017 ? _Queue64_UInt8_15_io_deq_valid : _T_3016 ? _Queue64_UInt8_14_io_deq_valid : _T_3015 ? _Queue64_UInt8_13_io_deq_valid : _T_3014 ? _Queue64_UInt8_12_io_deq_valid : _T_3013 ? _Queue64_UInt8_11_io_deq_valid : _T_3012 ? _Queue64_UInt8_10_io_deq_valid : _T_3011 ? _Queue64_UInt8_9_io_deq_valid : _T_3010 ? _Queue64_UInt8_8_io_deq_valid : _T_3009 ? _Queue64_UInt8_7_io_deq_valid : _T_3008 ? _Queue64_UInt8_6_io_deq_valid : _T_3007 ? _Queue64_UInt8_5_io_deq_valid : _T_3006 ? _Queue64_UInt8_4_io_deq_valid : _T_3005 ? _Queue64_UInt8_3_io_deq_valid : _T_3004 ? _Queue64_UInt8_2_io_deq_valid : _T_3003 ? _Queue64_UInt8_1_io_deq_valid : _T_3002 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[MemLoader.scala:177:33] wire [6:0] _GEN_114 = _remapindex_T_22 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_22 = _GEN_114[5:0]; // @[MemLoader.scala:177:54] wire _T_3034 = remapindex_22 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3035 = remapindex_22 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3036 = remapindex_22 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3037 = remapindex_22 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3038 = remapindex_22 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3039 = remapindex_22 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3040 = remapindex_22 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3041 = remapindex_22 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3042 = remapindex_22 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3043 = remapindex_22 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3044 = remapindex_22 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3045 = remapindex_22 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3046 = remapindex_22 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3047 = remapindex_22 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3048 = remapindex_22 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3049 = remapindex_22 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3050 = remapindex_22 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3051 = remapindex_22 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3052 = remapindex_22 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3053 = remapindex_22 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3054 = remapindex_22 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3055 = remapindex_22 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3056 = remapindex_22 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3057 = remapindex_22 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3058 = remapindex_22 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3059 = remapindex_22 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3060 = remapindex_22 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3061 = remapindex_22 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3062 = remapindex_22 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3063 = remapindex_22 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3064 = remapindex_22 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3065 = remapindex_22 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_22 = _T_3065 ? _Queue64_UInt8_31_io_deq_bits : _T_3064 ? _Queue64_UInt8_30_io_deq_bits : _T_3063 ? _Queue64_UInt8_29_io_deq_bits : _T_3062 ? _Queue64_UInt8_28_io_deq_bits : _T_3061 ? _Queue64_UInt8_27_io_deq_bits : _T_3060 ? _Queue64_UInt8_26_io_deq_bits : _T_3059 ? _Queue64_UInt8_25_io_deq_bits : _T_3058 ? _Queue64_UInt8_24_io_deq_bits : _T_3057 ? _Queue64_UInt8_23_io_deq_bits : _T_3056 ? _Queue64_UInt8_22_io_deq_bits : _T_3055 ? _Queue64_UInt8_21_io_deq_bits : _T_3054 ? _Queue64_UInt8_20_io_deq_bits : _T_3053 ? _Queue64_UInt8_19_io_deq_bits : _T_3052 ? _Queue64_UInt8_18_io_deq_bits : _T_3051 ? _Queue64_UInt8_17_io_deq_bits : _T_3050 ? _Queue64_UInt8_16_io_deq_bits : _T_3049 ? _Queue64_UInt8_15_io_deq_bits : _T_3048 ? _Queue64_UInt8_14_io_deq_bits : _T_3047 ? _Queue64_UInt8_13_io_deq_bits : _T_3046 ? _Queue64_UInt8_12_io_deq_bits : _T_3045 ? _Queue64_UInt8_11_io_deq_bits : _T_3044 ? _Queue64_UInt8_10_io_deq_bits : _T_3043 ? _Queue64_UInt8_9_io_deq_bits : _T_3042 ? _Queue64_UInt8_8_io_deq_bits : _T_3041 ? _Queue64_UInt8_7_io_deq_bits : _T_3040 ? _Queue64_UInt8_6_io_deq_bits : _T_3039 ? _Queue64_UInt8_5_io_deq_bits : _T_3038 ? _Queue64_UInt8_4_io_deq_bits : _T_3037 ? _Queue64_UInt8_3_io_deq_bits : _T_3036 ? _Queue64_UInt8_2_io_deq_bits : _T_3035 ? _Queue64_UInt8_1_io_deq_bits : _T_3034 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_22 = _T_3065 ? _Queue64_UInt8_31_io_deq_valid : _T_3064 ? _Queue64_UInt8_30_io_deq_valid : _T_3063 ? _Queue64_UInt8_29_io_deq_valid : _T_3062 ? _Queue64_UInt8_28_io_deq_valid : _T_3061 ? _Queue64_UInt8_27_io_deq_valid : _T_3060 ? _Queue64_UInt8_26_io_deq_valid : _T_3059 ? _Queue64_UInt8_25_io_deq_valid : _T_3058 ? _Queue64_UInt8_24_io_deq_valid : _T_3057 ? _Queue64_UInt8_23_io_deq_valid : _T_3056 ? _Queue64_UInt8_22_io_deq_valid : _T_3055 ? _Queue64_UInt8_21_io_deq_valid : _T_3054 ? _Queue64_UInt8_20_io_deq_valid : _T_3053 ? _Queue64_UInt8_19_io_deq_valid : _T_3052 ? _Queue64_UInt8_18_io_deq_valid : _T_3051 ? _Queue64_UInt8_17_io_deq_valid : _T_3050 ? _Queue64_UInt8_16_io_deq_valid : _T_3049 ? _Queue64_UInt8_15_io_deq_valid : _T_3048 ? _Queue64_UInt8_14_io_deq_valid : _T_3047 ? _Queue64_UInt8_13_io_deq_valid : _T_3046 ? _Queue64_UInt8_12_io_deq_valid : _T_3045 ? _Queue64_UInt8_11_io_deq_valid : _T_3044 ? _Queue64_UInt8_10_io_deq_valid : _T_3043 ? _Queue64_UInt8_9_io_deq_valid : _T_3042 ? _Queue64_UInt8_8_io_deq_valid : _T_3041 ? _Queue64_UInt8_7_io_deq_valid : _T_3040 ? _Queue64_UInt8_6_io_deq_valid : _T_3039 ? _Queue64_UInt8_5_io_deq_valid : _T_3038 ? _Queue64_UInt8_4_io_deq_valid : _T_3037 ? _Queue64_UInt8_3_io_deq_valid : _T_3036 ? _Queue64_UInt8_2_io_deq_valid : _T_3035 ? _Queue64_UInt8_1_io_deq_valid : _T_3034 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[MemLoader.scala:177:33] wire [6:0] _GEN_115 = _remapindex_T_23 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_23 = _GEN_115[5:0]; // @[MemLoader.scala:177:54] wire _T_3066 = remapindex_23 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3067 = remapindex_23 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3068 = remapindex_23 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3069 = remapindex_23 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3070 = remapindex_23 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3071 = remapindex_23 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3072 = remapindex_23 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3073 = remapindex_23 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3074 = remapindex_23 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3075 = remapindex_23 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3076 = remapindex_23 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3077 = remapindex_23 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3078 = remapindex_23 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3079 = remapindex_23 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3080 = remapindex_23 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3081 = remapindex_23 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3082 = remapindex_23 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3083 = remapindex_23 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3084 = remapindex_23 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3085 = remapindex_23 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3086 = remapindex_23 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3087 = remapindex_23 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3088 = remapindex_23 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3089 = remapindex_23 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3090 = remapindex_23 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3091 = remapindex_23 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3092 = remapindex_23 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3093 = remapindex_23 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3094 = remapindex_23 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3095 = remapindex_23 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3096 = remapindex_23 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3097 = remapindex_23 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_23 = _T_3097 ? _Queue64_UInt8_31_io_deq_bits : _T_3096 ? _Queue64_UInt8_30_io_deq_bits : _T_3095 ? _Queue64_UInt8_29_io_deq_bits : _T_3094 ? _Queue64_UInt8_28_io_deq_bits : _T_3093 ? _Queue64_UInt8_27_io_deq_bits : _T_3092 ? _Queue64_UInt8_26_io_deq_bits : _T_3091 ? _Queue64_UInt8_25_io_deq_bits : _T_3090 ? _Queue64_UInt8_24_io_deq_bits : _T_3089 ? _Queue64_UInt8_23_io_deq_bits : _T_3088 ? _Queue64_UInt8_22_io_deq_bits : _T_3087 ? _Queue64_UInt8_21_io_deq_bits : _T_3086 ? _Queue64_UInt8_20_io_deq_bits : _T_3085 ? _Queue64_UInt8_19_io_deq_bits : _T_3084 ? _Queue64_UInt8_18_io_deq_bits : _T_3083 ? _Queue64_UInt8_17_io_deq_bits : _T_3082 ? _Queue64_UInt8_16_io_deq_bits : _T_3081 ? _Queue64_UInt8_15_io_deq_bits : _T_3080 ? _Queue64_UInt8_14_io_deq_bits : _T_3079 ? _Queue64_UInt8_13_io_deq_bits : _T_3078 ? _Queue64_UInt8_12_io_deq_bits : _T_3077 ? _Queue64_UInt8_11_io_deq_bits : _T_3076 ? _Queue64_UInt8_10_io_deq_bits : _T_3075 ? _Queue64_UInt8_9_io_deq_bits : _T_3074 ? _Queue64_UInt8_8_io_deq_bits : _T_3073 ? _Queue64_UInt8_7_io_deq_bits : _T_3072 ? _Queue64_UInt8_6_io_deq_bits : _T_3071 ? _Queue64_UInt8_5_io_deq_bits : _T_3070 ? _Queue64_UInt8_4_io_deq_bits : _T_3069 ? _Queue64_UInt8_3_io_deq_bits : _T_3068 ? _Queue64_UInt8_2_io_deq_bits : _T_3067 ? _Queue64_UInt8_1_io_deq_bits : _T_3066 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_23 = _T_3097 ? _Queue64_UInt8_31_io_deq_valid : _T_3096 ? _Queue64_UInt8_30_io_deq_valid : _T_3095 ? _Queue64_UInt8_29_io_deq_valid : _T_3094 ? _Queue64_UInt8_28_io_deq_valid : _T_3093 ? _Queue64_UInt8_27_io_deq_valid : _T_3092 ? _Queue64_UInt8_26_io_deq_valid : _T_3091 ? _Queue64_UInt8_25_io_deq_valid : _T_3090 ? _Queue64_UInt8_24_io_deq_valid : _T_3089 ? _Queue64_UInt8_23_io_deq_valid : _T_3088 ? _Queue64_UInt8_22_io_deq_valid : _T_3087 ? _Queue64_UInt8_21_io_deq_valid : _T_3086 ? _Queue64_UInt8_20_io_deq_valid : _T_3085 ? _Queue64_UInt8_19_io_deq_valid : _T_3084 ? _Queue64_UInt8_18_io_deq_valid : _T_3083 ? _Queue64_UInt8_17_io_deq_valid : _T_3082 ? _Queue64_UInt8_16_io_deq_valid : _T_3081 ? _Queue64_UInt8_15_io_deq_valid : _T_3080 ? _Queue64_UInt8_14_io_deq_valid : _T_3079 ? _Queue64_UInt8_13_io_deq_valid : _T_3078 ? _Queue64_UInt8_12_io_deq_valid : _T_3077 ? _Queue64_UInt8_11_io_deq_valid : _T_3076 ? _Queue64_UInt8_10_io_deq_valid : _T_3075 ? _Queue64_UInt8_9_io_deq_valid : _T_3074 ? _Queue64_UInt8_8_io_deq_valid : _T_3073 ? _Queue64_UInt8_7_io_deq_valid : _T_3072 ? _Queue64_UInt8_6_io_deq_valid : _T_3071 ? _Queue64_UInt8_5_io_deq_valid : _T_3070 ? _Queue64_UInt8_4_io_deq_valid : _T_3069 ? _Queue64_UInt8_3_io_deq_valid : _T_3068 ? _Queue64_UInt8_2_io_deq_valid : _T_3067 ? _Queue64_UInt8_1_io_deq_valid : _T_3066 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[MemLoader.scala:177:33] wire [6:0] _GEN_116 = _remapindex_T_24 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_24 = _GEN_116[5:0]; // @[MemLoader.scala:177:54] wire _T_3098 = remapindex_24 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3099 = remapindex_24 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3100 = remapindex_24 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3101 = remapindex_24 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3102 = remapindex_24 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3103 = remapindex_24 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3104 = remapindex_24 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3105 = remapindex_24 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3106 = remapindex_24 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3107 = remapindex_24 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3108 = remapindex_24 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3109 = remapindex_24 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3110 = remapindex_24 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3111 = remapindex_24 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3112 = remapindex_24 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3113 = remapindex_24 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3114 = remapindex_24 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3115 = remapindex_24 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3116 = remapindex_24 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3117 = remapindex_24 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3118 = remapindex_24 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3119 = remapindex_24 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3120 = remapindex_24 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3121 = remapindex_24 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3122 = remapindex_24 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3123 = remapindex_24 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3124 = remapindex_24 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3125 = remapindex_24 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3126 = remapindex_24 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3127 = remapindex_24 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3128 = remapindex_24 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3129 = remapindex_24 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_24 = _T_3129 ? _Queue64_UInt8_31_io_deq_bits : _T_3128 ? _Queue64_UInt8_30_io_deq_bits : _T_3127 ? _Queue64_UInt8_29_io_deq_bits : _T_3126 ? _Queue64_UInt8_28_io_deq_bits : _T_3125 ? _Queue64_UInt8_27_io_deq_bits : _T_3124 ? _Queue64_UInt8_26_io_deq_bits : _T_3123 ? _Queue64_UInt8_25_io_deq_bits : _T_3122 ? _Queue64_UInt8_24_io_deq_bits : _T_3121 ? _Queue64_UInt8_23_io_deq_bits : _T_3120 ? _Queue64_UInt8_22_io_deq_bits : _T_3119 ? _Queue64_UInt8_21_io_deq_bits : _T_3118 ? _Queue64_UInt8_20_io_deq_bits : _T_3117 ? _Queue64_UInt8_19_io_deq_bits : _T_3116 ? _Queue64_UInt8_18_io_deq_bits : _T_3115 ? _Queue64_UInt8_17_io_deq_bits : _T_3114 ? _Queue64_UInt8_16_io_deq_bits : _T_3113 ? _Queue64_UInt8_15_io_deq_bits : _T_3112 ? _Queue64_UInt8_14_io_deq_bits : _T_3111 ? _Queue64_UInt8_13_io_deq_bits : _T_3110 ? _Queue64_UInt8_12_io_deq_bits : _T_3109 ? _Queue64_UInt8_11_io_deq_bits : _T_3108 ? _Queue64_UInt8_10_io_deq_bits : _T_3107 ? _Queue64_UInt8_9_io_deq_bits : _T_3106 ? _Queue64_UInt8_8_io_deq_bits : _T_3105 ? _Queue64_UInt8_7_io_deq_bits : _T_3104 ? _Queue64_UInt8_6_io_deq_bits : _T_3103 ? _Queue64_UInt8_5_io_deq_bits : _T_3102 ? _Queue64_UInt8_4_io_deq_bits : _T_3101 ? _Queue64_UInt8_3_io_deq_bits : _T_3100 ? _Queue64_UInt8_2_io_deq_bits : _T_3099 ? _Queue64_UInt8_1_io_deq_bits : _T_3098 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_24 = _T_3129 ? _Queue64_UInt8_31_io_deq_valid : _T_3128 ? _Queue64_UInt8_30_io_deq_valid : _T_3127 ? _Queue64_UInt8_29_io_deq_valid : _T_3126 ? _Queue64_UInt8_28_io_deq_valid : _T_3125 ? _Queue64_UInt8_27_io_deq_valid : _T_3124 ? _Queue64_UInt8_26_io_deq_valid : _T_3123 ? _Queue64_UInt8_25_io_deq_valid : _T_3122 ? _Queue64_UInt8_24_io_deq_valid : _T_3121 ? _Queue64_UInt8_23_io_deq_valid : _T_3120 ? _Queue64_UInt8_22_io_deq_valid : _T_3119 ? _Queue64_UInt8_21_io_deq_valid : _T_3118 ? _Queue64_UInt8_20_io_deq_valid : _T_3117 ? _Queue64_UInt8_19_io_deq_valid : _T_3116 ? _Queue64_UInt8_18_io_deq_valid : _T_3115 ? _Queue64_UInt8_17_io_deq_valid : _T_3114 ? _Queue64_UInt8_16_io_deq_valid : _T_3113 ? _Queue64_UInt8_15_io_deq_valid : _T_3112 ? _Queue64_UInt8_14_io_deq_valid : _T_3111 ? _Queue64_UInt8_13_io_deq_valid : _T_3110 ? _Queue64_UInt8_12_io_deq_valid : _T_3109 ? _Queue64_UInt8_11_io_deq_valid : _T_3108 ? _Queue64_UInt8_10_io_deq_valid : _T_3107 ? _Queue64_UInt8_9_io_deq_valid : _T_3106 ? _Queue64_UInt8_8_io_deq_valid : _T_3105 ? _Queue64_UInt8_7_io_deq_valid : _T_3104 ? _Queue64_UInt8_6_io_deq_valid : _T_3103 ? _Queue64_UInt8_5_io_deq_valid : _T_3102 ? _Queue64_UInt8_4_io_deq_valid : _T_3101 ? _Queue64_UInt8_3_io_deq_valid : _T_3100 ? _Queue64_UInt8_2_io_deq_valid : _T_3099 ? _Queue64_UInt8_1_io_deq_valid : _T_3098 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[MemLoader.scala:177:33] wire [6:0] _GEN_117 = _remapindex_T_25 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_25 = _GEN_117[5:0]; // @[MemLoader.scala:177:54] wire _T_3130 = remapindex_25 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3131 = remapindex_25 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3132 = remapindex_25 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3133 = remapindex_25 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3134 = remapindex_25 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3135 = remapindex_25 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3136 = remapindex_25 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3137 = remapindex_25 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3138 = remapindex_25 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3139 = remapindex_25 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3140 = remapindex_25 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3141 = remapindex_25 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3142 = remapindex_25 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3143 = remapindex_25 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3144 = remapindex_25 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3145 = remapindex_25 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3146 = remapindex_25 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3147 = remapindex_25 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3148 = remapindex_25 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3149 = remapindex_25 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3150 = remapindex_25 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3151 = remapindex_25 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3152 = remapindex_25 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3153 = remapindex_25 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3154 = remapindex_25 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3155 = remapindex_25 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3156 = remapindex_25 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3157 = remapindex_25 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3158 = remapindex_25 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3159 = remapindex_25 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3160 = remapindex_25 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3161 = remapindex_25 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_25 = _T_3161 ? _Queue64_UInt8_31_io_deq_bits : _T_3160 ? _Queue64_UInt8_30_io_deq_bits : _T_3159 ? _Queue64_UInt8_29_io_deq_bits : _T_3158 ? _Queue64_UInt8_28_io_deq_bits : _T_3157 ? _Queue64_UInt8_27_io_deq_bits : _T_3156 ? _Queue64_UInt8_26_io_deq_bits : _T_3155 ? _Queue64_UInt8_25_io_deq_bits : _T_3154 ? _Queue64_UInt8_24_io_deq_bits : _T_3153 ? _Queue64_UInt8_23_io_deq_bits : _T_3152 ? _Queue64_UInt8_22_io_deq_bits : _T_3151 ? _Queue64_UInt8_21_io_deq_bits : _T_3150 ? _Queue64_UInt8_20_io_deq_bits : _T_3149 ? _Queue64_UInt8_19_io_deq_bits : _T_3148 ? _Queue64_UInt8_18_io_deq_bits : _T_3147 ? _Queue64_UInt8_17_io_deq_bits : _T_3146 ? _Queue64_UInt8_16_io_deq_bits : _T_3145 ? _Queue64_UInt8_15_io_deq_bits : _T_3144 ? _Queue64_UInt8_14_io_deq_bits : _T_3143 ? _Queue64_UInt8_13_io_deq_bits : _T_3142 ? _Queue64_UInt8_12_io_deq_bits : _T_3141 ? _Queue64_UInt8_11_io_deq_bits : _T_3140 ? _Queue64_UInt8_10_io_deq_bits : _T_3139 ? _Queue64_UInt8_9_io_deq_bits : _T_3138 ? _Queue64_UInt8_8_io_deq_bits : _T_3137 ? _Queue64_UInt8_7_io_deq_bits : _T_3136 ? _Queue64_UInt8_6_io_deq_bits : _T_3135 ? _Queue64_UInt8_5_io_deq_bits : _T_3134 ? _Queue64_UInt8_4_io_deq_bits : _T_3133 ? _Queue64_UInt8_3_io_deq_bits : _T_3132 ? _Queue64_UInt8_2_io_deq_bits : _T_3131 ? _Queue64_UInt8_1_io_deq_bits : _T_3130 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_25 = _T_3161 ? _Queue64_UInt8_31_io_deq_valid : _T_3160 ? _Queue64_UInt8_30_io_deq_valid : _T_3159 ? _Queue64_UInt8_29_io_deq_valid : _T_3158 ? _Queue64_UInt8_28_io_deq_valid : _T_3157 ? _Queue64_UInt8_27_io_deq_valid : _T_3156 ? _Queue64_UInt8_26_io_deq_valid : _T_3155 ? _Queue64_UInt8_25_io_deq_valid : _T_3154 ? _Queue64_UInt8_24_io_deq_valid : _T_3153 ? _Queue64_UInt8_23_io_deq_valid : _T_3152 ? _Queue64_UInt8_22_io_deq_valid : _T_3151 ? _Queue64_UInt8_21_io_deq_valid : _T_3150 ? _Queue64_UInt8_20_io_deq_valid : _T_3149 ? _Queue64_UInt8_19_io_deq_valid : _T_3148 ? _Queue64_UInt8_18_io_deq_valid : _T_3147 ? _Queue64_UInt8_17_io_deq_valid : _T_3146 ? _Queue64_UInt8_16_io_deq_valid : _T_3145 ? _Queue64_UInt8_15_io_deq_valid : _T_3144 ? _Queue64_UInt8_14_io_deq_valid : _T_3143 ? _Queue64_UInt8_13_io_deq_valid : _T_3142 ? _Queue64_UInt8_12_io_deq_valid : _T_3141 ? _Queue64_UInt8_11_io_deq_valid : _T_3140 ? _Queue64_UInt8_10_io_deq_valid : _T_3139 ? _Queue64_UInt8_9_io_deq_valid : _T_3138 ? _Queue64_UInt8_8_io_deq_valid : _T_3137 ? _Queue64_UInt8_7_io_deq_valid : _T_3136 ? _Queue64_UInt8_6_io_deq_valid : _T_3135 ? _Queue64_UInt8_5_io_deq_valid : _T_3134 ? _Queue64_UInt8_4_io_deq_valid : _T_3133 ? _Queue64_UInt8_3_io_deq_valid : _T_3132 ? _Queue64_UInt8_2_io_deq_valid : _T_3131 ? _Queue64_UInt8_1_io_deq_valid : _T_3130 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[MemLoader.scala:177:33] wire [6:0] _GEN_118 = _remapindex_T_26 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_26 = _GEN_118[5:0]; // @[MemLoader.scala:177:54] wire _T_3162 = remapindex_26 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3163 = remapindex_26 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3164 = remapindex_26 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3165 = remapindex_26 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3166 = remapindex_26 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3167 = remapindex_26 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3168 = remapindex_26 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3169 = remapindex_26 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3170 = remapindex_26 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3171 = remapindex_26 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3172 = remapindex_26 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3173 = remapindex_26 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3174 = remapindex_26 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3175 = remapindex_26 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3176 = remapindex_26 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3177 = remapindex_26 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3178 = remapindex_26 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3179 = remapindex_26 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3180 = remapindex_26 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3181 = remapindex_26 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3182 = remapindex_26 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3183 = remapindex_26 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3184 = remapindex_26 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3185 = remapindex_26 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3186 = remapindex_26 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3187 = remapindex_26 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3188 = remapindex_26 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3189 = remapindex_26 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3190 = remapindex_26 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3191 = remapindex_26 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3192 = remapindex_26 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3193 = remapindex_26 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_26 = _T_3193 ? _Queue64_UInt8_31_io_deq_bits : _T_3192 ? _Queue64_UInt8_30_io_deq_bits : _T_3191 ? _Queue64_UInt8_29_io_deq_bits : _T_3190 ? _Queue64_UInt8_28_io_deq_bits : _T_3189 ? _Queue64_UInt8_27_io_deq_bits : _T_3188 ? _Queue64_UInt8_26_io_deq_bits : _T_3187 ? _Queue64_UInt8_25_io_deq_bits : _T_3186 ? _Queue64_UInt8_24_io_deq_bits : _T_3185 ? _Queue64_UInt8_23_io_deq_bits : _T_3184 ? _Queue64_UInt8_22_io_deq_bits : _T_3183 ? _Queue64_UInt8_21_io_deq_bits : _T_3182 ? _Queue64_UInt8_20_io_deq_bits : _T_3181 ? _Queue64_UInt8_19_io_deq_bits : _T_3180 ? _Queue64_UInt8_18_io_deq_bits : _T_3179 ? _Queue64_UInt8_17_io_deq_bits : _T_3178 ? _Queue64_UInt8_16_io_deq_bits : _T_3177 ? _Queue64_UInt8_15_io_deq_bits : _T_3176 ? _Queue64_UInt8_14_io_deq_bits : _T_3175 ? _Queue64_UInt8_13_io_deq_bits : _T_3174 ? _Queue64_UInt8_12_io_deq_bits : _T_3173 ? _Queue64_UInt8_11_io_deq_bits : _T_3172 ? _Queue64_UInt8_10_io_deq_bits : _T_3171 ? _Queue64_UInt8_9_io_deq_bits : _T_3170 ? _Queue64_UInt8_8_io_deq_bits : _T_3169 ? _Queue64_UInt8_7_io_deq_bits : _T_3168 ? _Queue64_UInt8_6_io_deq_bits : _T_3167 ? _Queue64_UInt8_5_io_deq_bits : _T_3166 ? _Queue64_UInt8_4_io_deq_bits : _T_3165 ? _Queue64_UInt8_3_io_deq_bits : _T_3164 ? _Queue64_UInt8_2_io_deq_bits : _T_3163 ? _Queue64_UInt8_1_io_deq_bits : _T_3162 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_26 = _T_3193 ? _Queue64_UInt8_31_io_deq_valid : _T_3192 ? _Queue64_UInt8_30_io_deq_valid : _T_3191 ? _Queue64_UInt8_29_io_deq_valid : _T_3190 ? _Queue64_UInt8_28_io_deq_valid : _T_3189 ? _Queue64_UInt8_27_io_deq_valid : _T_3188 ? _Queue64_UInt8_26_io_deq_valid : _T_3187 ? _Queue64_UInt8_25_io_deq_valid : _T_3186 ? _Queue64_UInt8_24_io_deq_valid : _T_3185 ? _Queue64_UInt8_23_io_deq_valid : _T_3184 ? _Queue64_UInt8_22_io_deq_valid : _T_3183 ? _Queue64_UInt8_21_io_deq_valid : _T_3182 ? _Queue64_UInt8_20_io_deq_valid : _T_3181 ? _Queue64_UInt8_19_io_deq_valid : _T_3180 ? _Queue64_UInt8_18_io_deq_valid : _T_3179 ? _Queue64_UInt8_17_io_deq_valid : _T_3178 ? _Queue64_UInt8_16_io_deq_valid : _T_3177 ? _Queue64_UInt8_15_io_deq_valid : _T_3176 ? _Queue64_UInt8_14_io_deq_valid : _T_3175 ? _Queue64_UInt8_13_io_deq_valid : _T_3174 ? _Queue64_UInt8_12_io_deq_valid : _T_3173 ? _Queue64_UInt8_11_io_deq_valid : _T_3172 ? _Queue64_UInt8_10_io_deq_valid : _T_3171 ? _Queue64_UInt8_9_io_deq_valid : _T_3170 ? _Queue64_UInt8_8_io_deq_valid : _T_3169 ? _Queue64_UInt8_7_io_deq_valid : _T_3168 ? _Queue64_UInt8_6_io_deq_valid : _T_3167 ? _Queue64_UInt8_5_io_deq_valid : _T_3166 ? _Queue64_UInt8_4_io_deq_valid : _T_3165 ? _Queue64_UInt8_3_io_deq_valid : _T_3164 ? _Queue64_UInt8_2_io_deq_valid : _T_3163 ? _Queue64_UInt8_1_io_deq_valid : _T_3162 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[MemLoader.scala:177:33] wire [6:0] _GEN_119 = _remapindex_T_27 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_27 = _GEN_119[5:0]; // @[MemLoader.scala:177:54] wire _T_3194 = remapindex_27 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3195 = remapindex_27 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3196 = remapindex_27 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3197 = remapindex_27 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3198 = remapindex_27 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3199 = remapindex_27 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3200 = remapindex_27 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3201 = remapindex_27 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3202 = remapindex_27 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3203 = remapindex_27 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3204 = remapindex_27 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3205 = remapindex_27 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3206 = remapindex_27 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3207 = remapindex_27 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3208 = remapindex_27 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3209 = remapindex_27 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3210 = remapindex_27 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3211 = remapindex_27 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3212 = remapindex_27 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3213 = remapindex_27 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3214 = remapindex_27 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3215 = remapindex_27 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3216 = remapindex_27 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3217 = remapindex_27 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3218 = remapindex_27 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3219 = remapindex_27 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3220 = remapindex_27 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3221 = remapindex_27 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3222 = remapindex_27 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3223 = remapindex_27 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3224 = remapindex_27 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3225 = remapindex_27 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_27 = _T_3225 ? _Queue64_UInt8_31_io_deq_bits : _T_3224 ? _Queue64_UInt8_30_io_deq_bits : _T_3223 ? _Queue64_UInt8_29_io_deq_bits : _T_3222 ? _Queue64_UInt8_28_io_deq_bits : _T_3221 ? _Queue64_UInt8_27_io_deq_bits : _T_3220 ? _Queue64_UInt8_26_io_deq_bits : _T_3219 ? _Queue64_UInt8_25_io_deq_bits : _T_3218 ? _Queue64_UInt8_24_io_deq_bits : _T_3217 ? _Queue64_UInt8_23_io_deq_bits : _T_3216 ? _Queue64_UInt8_22_io_deq_bits : _T_3215 ? _Queue64_UInt8_21_io_deq_bits : _T_3214 ? _Queue64_UInt8_20_io_deq_bits : _T_3213 ? _Queue64_UInt8_19_io_deq_bits : _T_3212 ? _Queue64_UInt8_18_io_deq_bits : _T_3211 ? _Queue64_UInt8_17_io_deq_bits : _T_3210 ? _Queue64_UInt8_16_io_deq_bits : _T_3209 ? _Queue64_UInt8_15_io_deq_bits : _T_3208 ? _Queue64_UInt8_14_io_deq_bits : _T_3207 ? _Queue64_UInt8_13_io_deq_bits : _T_3206 ? _Queue64_UInt8_12_io_deq_bits : _T_3205 ? _Queue64_UInt8_11_io_deq_bits : _T_3204 ? _Queue64_UInt8_10_io_deq_bits : _T_3203 ? _Queue64_UInt8_9_io_deq_bits : _T_3202 ? _Queue64_UInt8_8_io_deq_bits : _T_3201 ? _Queue64_UInt8_7_io_deq_bits : _T_3200 ? _Queue64_UInt8_6_io_deq_bits : _T_3199 ? _Queue64_UInt8_5_io_deq_bits : _T_3198 ? _Queue64_UInt8_4_io_deq_bits : _T_3197 ? _Queue64_UInt8_3_io_deq_bits : _T_3196 ? _Queue64_UInt8_2_io_deq_bits : _T_3195 ? _Queue64_UInt8_1_io_deq_bits : _T_3194 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_27 = _T_3225 ? _Queue64_UInt8_31_io_deq_valid : _T_3224 ? _Queue64_UInt8_30_io_deq_valid : _T_3223 ? _Queue64_UInt8_29_io_deq_valid : _T_3222 ? _Queue64_UInt8_28_io_deq_valid : _T_3221 ? _Queue64_UInt8_27_io_deq_valid : _T_3220 ? _Queue64_UInt8_26_io_deq_valid : _T_3219 ? _Queue64_UInt8_25_io_deq_valid : _T_3218 ? _Queue64_UInt8_24_io_deq_valid : _T_3217 ? _Queue64_UInt8_23_io_deq_valid : _T_3216 ? _Queue64_UInt8_22_io_deq_valid : _T_3215 ? _Queue64_UInt8_21_io_deq_valid : _T_3214 ? _Queue64_UInt8_20_io_deq_valid : _T_3213 ? _Queue64_UInt8_19_io_deq_valid : _T_3212 ? _Queue64_UInt8_18_io_deq_valid : _T_3211 ? _Queue64_UInt8_17_io_deq_valid : _T_3210 ? _Queue64_UInt8_16_io_deq_valid : _T_3209 ? _Queue64_UInt8_15_io_deq_valid : _T_3208 ? _Queue64_UInt8_14_io_deq_valid : _T_3207 ? _Queue64_UInt8_13_io_deq_valid : _T_3206 ? _Queue64_UInt8_12_io_deq_valid : _T_3205 ? _Queue64_UInt8_11_io_deq_valid : _T_3204 ? _Queue64_UInt8_10_io_deq_valid : _T_3203 ? _Queue64_UInt8_9_io_deq_valid : _T_3202 ? _Queue64_UInt8_8_io_deq_valid : _T_3201 ? _Queue64_UInt8_7_io_deq_valid : _T_3200 ? _Queue64_UInt8_6_io_deq_valid : _T_3199 ? _Queue64_UInt8_5_io_deq_valid : _T_3198 ? _Queue64_UInt8_4_io_deq_valid : _T_3197 ? _Queue64_UInt8_3_io_deq_valid : _T_3196 ? _Queue64_UInt8_2_io_deq_valid : _T_3195 ? _Queue64_UInt8_1_io_deq_valid : _T_3194 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[MemLoader.scala:177:33] wire [6:0] _GEN_120 = _remapindex_T_28 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_28 = _GEN_120[5:0]; // @[MemLoader.scala:177:54] wire _T_3226 = remapindex_28 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3227 = remapindex_28 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3228 = remapindex_28 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3229 = remapindex_28 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3230 = remapindex_28 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3231 = remapindex_28 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3232 = remapindex_28 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3233 = remapindex_28 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3234 = remapindex_28 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3235 = remapindex_28 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3236 = remapindex_28 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3237 = remapindex_28 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3238 = remapindex_28 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3239 = remapindex_28 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3240 = remapindex_28 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3241 = remapindex_28 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3242 = remapindex_28 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3243 = remapindex_28 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3244 = remapindex_28 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3245 = remapindex_28 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3246 = remapindex_28 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3247 = remapindex_28 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3248 = remapindex_28 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3249 = remapindex_28 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3250 = remapindex_28 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3251 = remapindex_28 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3252 = remapindex_28 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3253 = remapindex_28 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3254 = remapindex_28 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3255 = remapindex_28 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3256 = remapindex_28 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3257 = remapindex_28 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_28 = _T_3257 ? _Queue64_UInt8_31_io_deq_bits : _T_3256 ? _Queue64_UInt8_30_io_deq_bits : _T_3255 ? _Queue64_UInt8_29_io_deq_bits : _T_3254 ? _Queue64_UInt8_28_io_deq_bits : _T_3253 ? _Queue64_UInt8_27_io_deq_bits : _T_3252 ? _Queue64_UInt8_26_io_deq_bits : _T_3251 ? _Queue64_UInt8_25_io_deq_bits : _T_3250 ? _Queue64_UInt8_24_io_deq_bits : _T_3249 ? _Queue64_UInt8_23_io_deq_bits : _T_3248 ? _Queue64_UInt8_22_io_deq_bits : _T_3247 ? _Queue64_UInt8_21_io_deq_bits : _T_3246 ? _Queue64_UInt8_20_io_deq_bits : _T_3245 ? _Queue64_UInt8_19_io_deq_bits : _T_3244 ? _Queue64_UInt8_18_io_deq_bits : _T_3243 ? _Queue64_UInt8_17_io_deq_bits : _T_3242 ? _Queue64_UInt8_16_io_deq_bits : _T_3241 ? _Queue64_UInt8_15_io_deq_bits : _T_3240 ? _Queue64_UInt8_14_io_deq_bits : _T_3239 ? _Queue64_UInt8_13_io_deq_bits : _T_3238 ? _Queue64_UInt8_12_io_deq_bits : _T_3237 ? _Queue64_UInt8_11_io_deq_bits : _T_3236 ? _Queue64_UInt8_10_io_deq_bits : _T_3235 ? _Queue64_UInt8_9_io_deq_bits : _T_3234 ? _Queue64_UInt8_8_io_deq_bits : _T_3233 ? _Queue64_UInt8_7_io_deq_bits : _T_3232 ? _Queue64_UInt8_6_io_deq_bits : _T_3231 ? _Queue64_UInt8_5_io_deq_bits : _T_3230 ? _Queue64_UInt8_4_io_deq_bits : _T_3229 ? _Queue64_UInt8_3_io_deq_bits : _T_3228 ? _Queue64_UInt8_2_io_deq_bits : _T_3227 ? _Queue64_UInt8_1_io_deq_bits : _T_3226 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_28 = _T_3257 ? _Queue64_UInt8_31_io_deq_valid : _T_3256 ? _Queue64_UInt8_30_io_deq_valid : _T_3255 ? _Queue64_UInt8_29_io_deq_valid : _T_3254 ? _Queue64_UInt8_28_io_deq_valid : _T_3253 ? _Queue64_UInt8_27_io_deq_valid : _T_3252 ? _Queue64_UInt8_26_io_deq_valid : _T_3251 ? _Queue64_UInt8_25_io_deq_valid : _T_3250 ? _Queue64_UInt8_24_io_deq_valid : _T_3249 ? _Queue64_UInt8_23_io_deq_valid : _T_3248 ? _Queue64_UInt8_22_io_deq_valid : _T_3247 ? _Queue64_UInt8_21_io_deq_valid : _T_3246 ? _Queue64_UInt8_20_io_deq_valid : _T_3245 ? _Queue64_UInt8_19_io_deq_valid : _T_3244 ? _Queue64_UInt8_18_io_deq_valid : _T_3243 ? _Queue64_UInt8_17_io_deq_valid : _T_3242 ? _Queue64_UInt8_16_io_deq_valid : _T_3241 ? _Queue64_UInt8_15_io_deq_valid : _T_3240 ? _Queue64_UInt8_14_io_deq_valid : _T_3239 ? _Queue64_UInt8_13_io_deq_valid : _T_3238 ? _Queue64_UInt8_12_io_deq_valid : _T_3237 ? _Queue64_UInt8_11_io_deq_valid : _T_3236 ? _Queue64_UInt8_10_io_deq_valid : _T_3235 ? _Queue64_UInt8_9_io_deq_valid : _T_3234 ? _Queue64_UInt8_8_io_deq_valid : _T_3233 ? _Queue64_UInt8_7_io_deq_valid : _T_3232 ? _Queue64_UInt8_6_io_deq_valid : _T_3231 ? _Queue64_UInt8_5_io_deq_valid : _T_3230 ? _Queue64_UInt8_4_io_deq_valid : _T_3229 ? _Queue64_UInt8_3_io_deq_valid : _T_3228 ? _Queue64_UInt8_2_io_deq_valid : _T_3227 ? _Queue64_UInt8_1_io_deq_valid : _T_3226 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[MemLoader.scala:177:33] wire [6:0] _GEN_121 = _remapindex_T_29 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_29 = _GEN_121[5:0]; // @[MemLoader.scala:177:54] wire _T_3258 = remapindex_29 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3259 = remapindex_29 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3260 = remapindex_29 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3261 = remapindex_29 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3262 = remapindex_29 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3263 = remapindex_29 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3264 = remapindex_29 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3265 = remapindex_29 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3266 = remapindex_29 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3267 = remapindex_29 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3268 = remapindex_29 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3269 = remapindex_29 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3270 = remapindex_29 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3271 = remapindex_29 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3272 = remapindex_29 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3273 = remapindex_29 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3274 = remapindex_29 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3275 = remapindex_29 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3276 = remapindex_29 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3277 = remapindex_29 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3278 = remapindex_29 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3279 = remapindex_29 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3280 = remapindex_29 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3281 = remapindex_29 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3282 = remapindex_29 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3283 = remapindex_29 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3284 = remapindex_29 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3285 = remapindex_29 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3286 = remapindex_29 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3287 = remapindex_29 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3288 = remapindex_29 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3289 = remapindex_29 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_29 = _T_3289 ? _Queue64_UInt8_31_io_deq_bits : _T_3288 ? _Queue64_UInt8_30_io_deq_bits : _T_3287 ? _Queue64_UInt8_29_io_deq_bits : _T_3286 ? _Queue64_UInt8_28_io_deq_bits : _T_3285 ? _Queue64_UInt8_27_io_deq_bits : _T_3284 ? _Queue64_UInt8_26_io_deq_bits : _T_3283 ? _Queue64_UInt8_25_io_deq_bits : _T_3282 ? _Queue64_UInt8_24_io_deq_bits : _T_3281 ? _Queue64_UInt8_23_io_deq_bits : _T_3280 ? _Queue64_UInt8_22_io_deq_bits : _T_3279 ? _Queue64_UInt8_21_io_deq_bits : _T_3278 ? _Queue64_UInt8_20_io_deq_bits : _T_3277 ? _Queue64_UInt8_19_io_deq_bits : _T_3276 ? _Queue64_UInt8_18_io_deq_bits : _T_3275 ? _Queue64_UInt8_17_io_deq_bits : _T_3274 ? _Queue64_UInt8_16_io_deq_bits : _T_3273 ? _Queue64_UInt8_15_io_deq_bits : _T_3272 ? _Queue64_UInt8_14_io_deq_bits : _T_3271 ? _Queue64_UInt8_13_io_deq_bits : _T_3270 ? _Queue64_UInt8_12_io_deq_bits : _T_3269 ? _Queue64_UInt8_11_io_deq_bits : _T_3268 ? _Queue64_UInt8_10_io_deq_bits : _T_3267 ? _Queue64_UInt8_9_io_deq_bits : _T_3266 ? _Queue64_UInt8_8_io_deq_bits : _T_3265 ? _Queue64_UInt8_7_io_deq_bits : _T_3264 ? _Queue64_UInt8_6_io_deq_bits : _T_3263 ? _Queue64_UInt8_5_io_deq_bits : _T_3262 ? _Queue64_UInt8_4_io_deq_bits : _T_3261 ? _Queue64_UInt8_3_io_deq_bits : _T_3260 ? _Queue64_UInt8_2_io_deq_bits : _T_3259 ? _Queue64_UInt8_1_io_deq_bits : _T_3258 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_29 = _T_3289 ? _Queue64_UInt8_31_io_deq_valid : _T_3288 ? _Queue64_UInt8_30_io_deq_valid : _T_3287 ? _Queue64_UInt8_29_io_deq_valid : _T_3286 ? _Queue64_UInt8_28_io_deq_valid : _T_3285 ? _Queue64_UInt8_27_io_deq_valid : _T_3284 ? _Queue64_UInt8_26_io_deq_valid : _T_3283 ? _Queue64_UInt8_25_io_deq_valid : _T_3282 ? _Queue64_UInt8_24_io_deq_valid : _T_3281 ? _Queue64_UInt8_23_io_deq_valid : _T_3280 ? _Queue64_UInt8_22_io_deq_valid : _T_3279 ? _Queue64_UInt8_21_io_deq_valid : _T_3278 ? _Queue64_UInt8_20_io_deq_valid : _T_3277 ? _Queue64_UInt8_19_io_deq_valid : _T_3276 ? _Queue64_UInt8_18_io_deq_valid : _T_3275 ? _Queue64_UInt8_17_io_deq_valid : _T_3274 ? _Queue64_UInt8_16_io_deq_valid : _T_3273 ? _Queue64_UInt8_15_io_deq_valid : _T_3272 ? _Queue64_UInt8_14_io_deq_valid : _T_3271 ? _Queue64_UInt8_13_io_deq_valid : _T_3270 ? _Queue64_UInt8_12_io_deq_valid : _T_3269 ? _Queue64_UInt8_11_io_deq_valid : _T_3268 ? _Queue64_UInt8_10_io_deq_valid : _T_3267 ? _Queue64_UInt8_9_io_deq_valid : _T_3266 ? _Queue64_UInt8_8_io_deq_valid : _T_3265 ? _Queue64_UInt8_7_io_deq_valid : _T_3264 ? _Queue64_UInt8_6_io_deq_valid : _T_3263 ? _Queue64_UInt8_5_io_deq_valid : _T_3262 ? _Queue64_UInt8_4_io_deq_valid : _T_3261 ? _Queue64_UInt8_3_io_deq_valid : _T_3260 ? _Queue64_UInt8_2_io_deq_valid : _T_3259 ? _Queue64_UInt8_1_io_deq_valid : _T_3258 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[MemLoader.scala:177:33] wire [6:0] _GEN_122 = _remapindex_T_30 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_30 = _GEN_122[5:0]; // @[MemLoader.scala:177:54] wire _T_3290 = remapindex_30 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3291 = remapindex_30 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3292 = remapindex_30 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3293 = remapindex_30 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3294 = remapindex_30 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3295 = remapindex_30 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3296 = remapindex_30 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3297 = remapindex_30 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3298 = remapindex_30 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3299 = remapindex_30 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3300 = remapindex_30 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3301 = remapindex_30 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3302 = remapindex_30 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3303 = remapindex_30 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3304 = remapindex_30 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3305 = remapindex_30 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3306 = remapindex_30 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3307 = remapindex_30 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3308 = remapindex_30 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3309 = remapindex_30 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3310 = remapindex_30 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3311 = remapindex_30 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3312 = remapindex_30 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3313 = remapindex_30 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3314 = remapindex_30 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3315 = remapindex_30 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3316 = remapindex_30 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3317 = remapindex_30 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3318 = remapindex_30 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3319 = remapindex_30 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3320 = remapindex_30 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3321 = remapindex_30 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_30 = _T_3321 ? _Queue64_UInt8_31_io_deq_bits : _T_3320 ? _Queue64_UInt8_30_io_deq_bits : _T_3319 ? _Queue64_UInt8_29_io_deq_bits : _T_3318 ? _Queue64_UInt8_28_io_deq_bits : _T_3317 ? _Queue64_UInt8_27_io_deq_bits : _T_3316 ? _Queue64_UInt8_26_io_deq_bits : _T_3315 ? _Queue64_UInt8_25_io_deq_bits : _T_3314 ? _Queue64_UInt8_24_io_deq_bits : _T_3313 ? _Queue64_UInt8_23_io_deq_bits : _T_3312 ? _Queue64_UInt8_22_io_deq_bits : _T_3311 ? _Queue64_UInt8_21_io_deq_bits : _T_3310 ? _Queue64_UInt8_20_io_deq_bits : _T_3309 ? _Queue64_UInt8_19_io_deq_bits : _T_3308 ? _Queue64_UInt8_18_io_deq_bits : _T_3307 ? _Queue64_UInt8_17_io_deq_bits : _T_3306 ? _Queue64_UInt8_16_io_deq_bits : _T_3305 ? _Queue64_UInt8_15_io_deq_bits : _T_3304 ? _Queue64_UInt8_14_io_deq_bits : _T_3303 ? _Queue64_UInt8_13_io_deq_bits : _T_3302 ? _Queue64_UInt8_12_io_deq_bits : _T_3301 ? _Queue64_UInt8_11_io_deq_bits : _T_3300 ? _Queue64_UInt8_10_io_deq_bits : _T_3299 ? _Queue64_UInt8_9_io_deq_bits : _T_3298 ? _Queue64_UInt8_8_io_deq_bits : _T_3297 ? _Queue64_UInt8_7_io_deq_bits : _T_3296 ? _Queue64_UInt8_6_io_deq_bits : _T_3295 ? _Queue64_UInt8_5_io_deq_bits : _T_3294 ? _Queue64_UInt8_4_io_deq_bits : _T_3293 ? _Queue64_UInt8_3_io_deq_bits : _T_3292 ? _Queue64_UInt8_2_io_deq_bits : _T_3291 ? _Queue64_UInt8_1_io_deq_bits : _T_3290 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_30 = _T_3321 ? _Queue64_UInt8_31_io_deq_valid : _T_3320 ? _Queue64_UInt8_30_io_deq_valid : _T_3319 ? _Queue64_UInt8_29_io_deq_valid : _T_3318 ? _Queue64_UInt8_28_io_deq_valid : _T_3317 ? _Queue64_UInt8_27_io_deq_valid : _T_3316 ? _Queue64_UInt8_26_io_deq_valid : _T_3315 ? _Queue64_UInt8_25_io_deq_valid : _T_3314 ? _Queue64_UInt8_24_io_deq_valid : _T_3313 ? _Queue64_UInt8_23_io_deq_valid : _T_3312 ? _Queue64_UInt8_22_io_deq_valid : _T_3311 ? _Queue64_UInt8_21_io_deq_valid : _T_3310 ? _Queue64_UInt8_20_io_deq_valid : _T_3309 ? _Queue64_UInt8_19_io_deq_valid : _T_3308 ? _Queue64_UInt8_18_io_deq_valid : _T_3307 ? _Queue64_UInt8_17_io_deq_valid : _T_3306 ? _Queue64_UInt8_16_io_deq_valid : _T_3305 ? _Queue64_UInt8_15_io_deq_valid : _T_3304 ? _Queue64_UInt8_14_io_deq_valid : _T_3303 ? _Queue64_UInt8_13_io_deq_valid : _T_3302 ? _Queue64_UInt8_12_io_deq_valid : _T_3301 ? _Queue64_UInt8_11_io_deq_valid : _T_3300 ? _Queue64_UInt8_10_io_deq_valid : _T_3299 ? _Queue64_UInt8_9_io_deq_valid : _T_3298 ? _Queue64_UInt8_8_io_deq_valid : _T_3297 ? _Queue64_UInt8_7_io_deq_valid : _T_3296 ? _Queue64_UInt8_6_io_deq_valid : _T_3295 ? _Queue64_UInt8_5_io_deq_valid : _T_3294 ? _Queue64_UInt8_4_io_deq_valid : _T_3293 ? _Queue64_UInt8_3_io_deq_valid : _T_3292 ? _Queue64_UInt8_2_io_deq_valid : _T_3291 ? _Queue64_UInt8_1_io_deq_valid : _T_3290 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[MemLoader.scala:177:33] wire [6:0] _GEN_123 = _remapindex_T_31 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_31 = _GEN_123[5:0]; // @[MemLoader.scala:177:54] wire _T_3322 = remapindex_31 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3323 = remapindex_31 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3324 = remapindex_31 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3325 = remapindex_31 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3326 = remapindex_31 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3327 = remapindex_31 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3328 = remapindex_31 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3329 = remapindex_31 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3330 = remapindex_31 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3331 = remapindex_31 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3332 = remapindex_31 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3333 = remapindex_31 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3334 = remapindex_31 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3335 = remapindex_31 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3336 = remapindex_31 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3337 = remapindex_31 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3338 = remapindex_31 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3339 = remapindex_31 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3340 = remapindex_31 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3341 = remapindex_31 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3342 = remapindex_31 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3343 = remapindex_31 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3344 = remapindex_31 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3345 = remapindex_31 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3346 = remapindex_31 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3347 = remapindex_31 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3348 = remapindex_31 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3349 = remapindex_31 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3350 = remapindex_31 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3351 = remapindex_31 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3352 = remapindex_31 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3353 = remapindex_31 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_31 = _T_3353 ? _Queue64_UInt8_31_io_deq_bits : _T_3352 ? _Queue64_UInt8_30_io_deq_bits : _T_3351 ? _Queue64_UInt8_29_io_deq_bits : _T_3350 ? _Queue64_UInt8_28_io_deq_bits : _T_3349 ? _Queue64_UInt8_27_io_deq_bits : _T_3348 ? _Queue64_UInt8_26_io_deq_bits : _T_3347 ? _Queue64_UInt8_25_io_deq_bits : _T_3346 ? _Queue64_UInt8_24_io_deq_bits : _T_3345 ? _Queue64_UInt8_23_io_deq_bits : _T_3344 ? _Queue64_UInt8_22_io_deq_bits : _T_3343 ? _Queue64_UInt8_21_io_deq_bits : _T_3342 ? _Queue64_UInt8_20_io_deq_bits : _T_3341 ? _Queue64_UInt8_19_io_deq_bits : _T_3340 ? _Queue64_UInt8_18_io_deq_bits : _T_3339 ? _Queue64_UInt8_17_io_deq_bits : _T_3338 ? _Queue64_UInt8_16_io_deq_bits : _T_3337 ? _Queue64_UInt8_15_io_deq_bits : _T_3336 ? _Queue64_UInt8_14_io_deq_bits : _T_3335 ? _Queue64_UInt8_13_io_deq_bits : _T_3334 ? _Queue64_UInt8_12_io_deq_bits : _T_3333 ? _Queue64_UInt8_11_io_deq_bits : _T_3332 ? _Queue64_UInt8_10_io_deq_bits : _T_3331 ? _Queue64_UInt8_9_io_deq_bits : _T_3330 ? _Queue64_UInt8_8_io_deq_bits : _T_3329 ? _Queue64_UInt8_7_io_deq_bits : _T_3328 ? _Queue64_UInt8_6_io_deq_bits : _T_3327 ? _Queue64_UInt8_5_io_deq_bits : _T_3326 ? _Queue64_UInt8_4_io_deq_bits : _T_3325 ? _Queue64_UInt8_3_io_deq_bits : _T_3324 ? _Queue64_UInt8_2_io_deq_bits : _T_3323 ? _Queue64_UInt8_1_io_deq_bits : _T_3322 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_31 = _T_3353 ? _Queue64_UInt8_31_io_deq_valid : _T_3352 ? _Queue64_UInt8_30_io_deq_valid : _T_3351 ? _Queue64_UInt8_29_io_deq_valid : _T_3350 ? _Queue64_UInt8_28_io_deq_valid : _T_3349 ? _Queue64_UInt8_27_io_deq_valid : _T_3348 ? _Queue64_UInt8_26_io_deq_valid : _T_3347 ? _Queue64_UInt8_25_io_deq_valid : _T_3346 ? _Queue64_UInt8_24_io_deq_valid : _T_3345 ? _Queue64_UInt8_23_io_deq_valid : _T_3344 ? _Queue64_UInt8_22_io_deq_valid : _T_3343 ? _Queue64_UInt8_21_io_deq_valid : _T_3342 ? _Queue64_UInt8_20_io_deq_valid : _T_3341 ? _Queue64_UInt8_19_io_deq_valid : _T_3340 ? _Queue64_UInt8_18_io_deq_valid : _T_3339 ? _Queue64_UInt8_17_io_deq_valid : _T_3338 ? _Queue64_UInt8_16_io_deq_valid : _T_3337 ? _Queue64_UInt8_15_io_deq_valid : _T_3336 ? _Queue64_UInt8_14_io_deq_valid : _T_3335 ? _Queue64_UInt8_13_io_deq_valid : _T_3334 ? _Queue64_UInt8_12_io_deq_valid : _T_3333 ? _Queue64_UInt8_11_io_deq_valid : _T_3332 ? _Queue64_UInt8_10_io_deq_valid : _T_3331 ? _Queue64_UInt8_9_io_deq_valid : _T_3330 ? _Queue64_UInt8_8_io_deq_valid : _T_3329 ? _Queue64_UInt8_7_io_deq_valid : _T_3328 ? _Queue64_UInt8_6_io_deq_valid : _T_3327 ? _Queue64_UInt8_5_io_deq_valid : _T_3326 ? _Queue64_UInt8_4_io_deq_valid : _T_3325 ? _Queue64_UInt8_3_io_deq_valid : _T_3324 ? _Queue64_UInt8_2_io_deq_valid : _T_3323 ? _Queue64_UInt8_1_io_deq_valid : _T_3322 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [15:0] io_consumer_output_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[MemLoader.scala:166:26, :186:33] wire [15:0] io_consumer_output_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[MemLoader.scala:166:26, :186:33] wire [31:0] io_consumer_output_data_lo_lo_lo = {io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo}; // @[MemLoader.scala:186:33] wire [15:0] io_consumer_output_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[MemLoader.scala:166:26, :186:33] wire [15:0] io_consumer_output_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[MemLoader.scala:166:26, :186:33] wire [31:0] io_consumer_output_data_lo_lo_hi = {io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo}; // @[MemLoader.scala:186:33] wire [63:0] io_consumer_output_data_lo_lo = {io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo}; // @[MemLoader.scala:186:33] wire [15:0] io_consumer_output_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[MemLoader.scala:166:26, :186:33] wire [15:0] io_consumer_output_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[MemLoader.scala:166:26, :186:33] wire [31:0] io_consumer_output_data_lo_hi_lo = {io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo}; // @[MemLoader.scala:186:33] wire [15:0] io_consumer_output_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[MemLoader.scala:166:26, :186:33] wire [15:0] io_consumer_output_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[MemLoader.scala:166:26, :186:33] wire [31:0] io_consumer_output_data_lo_hi_hi = {io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo}; // @[MemLoader.scala:186:33] wire [63:0] io_consumer_output_data_lo_hi = {io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo}; // @[MemLoader.scala:186:33] wire [127:0] io_consumer_output_data_lo = {io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo}; // @[MemLoader.scala:186:33] wire [15:0] io_consumer_output_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[MemLoader.scala:166:26, :186:33] wire [15:0] io_consumer_output_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[MemLoader.scala:166:26, :186:33] wire [31:0] io_consumer_output_data_hi_lo_lo = {io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo}; // @[MemLoader.scala:186:33] wire [15:0] io_consumer_output_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[MemLoader.scala:166:26, :186:33] wire [15:0] io_consumer_output_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[MemLoader.scala:166:26, :186:33] wire [31:0] io_consumer_output_data_hi_lo_hi = {io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo}; // @[MemLoader.scala:186:33] wire [63:0] io_consumer_output_data_hi_lo = {io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo}; // @[MemLoader.scala:186:33] wire [15:0] io_consumer_output_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[MemLoader.scala:166:26, :186:33] wire [15:0] io_consumer_output_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[MemLoader.scala:166:26, :186:33] wire [31:0] io_consumer_output_data_hi_hi_lo = {io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo}; // @[MemLoader.scala:186:33] wire [15:0] io_consumer_output_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[MemLoader.scala:166:26, :186:33] wire [15:0] io_consumer_output_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[MemLoader.scala:166:26, :186:33] wire [31:0] io_consumer_output_data_hi_hi_hi = {io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo}; // @[MemLoader.scala:186:33] wire [63:0] io_consumer_output_data_hi_hi = {io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo}; // @[MemLoader.scala:186:33] wire [127:0] io_consumer_output_data_hi = {io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo}; // @[MemLoader.scala:186:33] assign _io_consumer_output_data_T = {io_consumer_output_data_hi, io_consumer_output_data_lo}; // @[MemLoader.scala:186:33] assign io_consumer_output_data_0 = _io_consumer_output_data_T; // @[MemLoader.scala:15:7, :186:33] wire [64:0] _GEN_124 = {1'h0, len_already_consumed}; // @[MemLoader.scala:164:37, :189:40] wire [64:0] _GEN_125 = _GEN_124 + 65'hC; // @[MemLoader.scala:189:40] wire [64:0] _buf_last_T; // @[MemLoader.scala:189:40] assign _buf_last_T = _GEN_125; // @[MemLoader.scala:189:40] wire [64:0] _len_already_consumed_T; // @[MemLoader.scala:230:52] assign _len_already_consumed_T = _GEN_125; // @[MemLoader.scala:189:40, :230:52] wire [63:0] _buf_last_T_1 = _buf_last_T[63:0]; // @[MemLoader.scala:189:40] wire buf_last = _buf_last_T_1 == _buf_info_queue_io_deq_bits_len_bytes; // @[MemLoader.scala:26:30, :189:{40,75}] wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[MemLoader.scala:167:28, :190:60] wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[MemLoader.scala:167:28, :190:60] wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[MemLoader.scala:167:28, :190:60] wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[MemLoader.scala:167:28, :190:60] wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[MemLoader.scala:167:28, :190:60] wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[MemLoader.scala:167:28, :190:60] wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[MemLoader.scala:167:28, :190:60] wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[MemLoader.scala:167:28, :190:60] wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[MemLoader.scala:167:28, :190:60] wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[MemLoader.scala:167:28, :190:60] wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[MemLoader.scala:167:28, :190:60] wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[MemLoader.scala:167:28, :190:60] wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[MemLoader.scala:167:28, :190:60] wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[MemLoader.scala:167:28, :190:60] wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[MemLoader.scala:167:28, :190:60] wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[MemLoader.scala:167:28, :190:60] wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[MemLoader.scala:167:28, :190:60] wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[MemLoader.scala:167:28, :190:60] wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[MemLoader.scala:167:28, :190:60] wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[MemLoader.scala:167:28, :190:60] wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[MemLoader.scala:167:28, :190:60] wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[MemLoader.scala:167:28, :190:60] wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[MemLoader.scala:167:28, :190:60] wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[MemLoader.scala:167:28, :190:60] wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[MemLoader.scala:167:28, :190:60] wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[MemLoader.scala:167:28, :190:60] wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[MemLoader.scala:167:28, :190:60] wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[MemLoader.scala:167:28, :190:60] wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[MemLoader.scala:167:28, :190:60] wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[MemLoader.scala:167:28, :190:60] wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[MemLoader.scala:167:28, :190:60] wire [64:0] _unconsumed_bytes_so_far_T = {1'h0, _buf_info_queue_io_deq_bits_len_bytes} - _GEN_124; // @[MemLoader.scala:26:30, :189:40, :191:70] wire [63:0] unconsumed_bytes_so_far = _unconsumed_bytes_so_far_T[63:0]; // @[MemLoader.scala:191:70] wire _enough_data_T = |(unconsumed_bytes_so_far[63:5]); // @[MemLoader.scala:191:70, :193:49] wire _enough_data_T_1 = count_valids == 32'h20; // @[MemLoader.scala:190:60, :194:38] wire _enough_data_T_2 = {32'h0, count_valids} >= unconsumed_bytes_so_far; // @[MemLoader.scala:190:60, :191:70, :195:38] wire enough_data = _enough_data_T ? _enough_data_T_1 : _enough_data_T_2; // @[MemLoader.scala:193:{24,49}, :194:38, :195:38] wire _io_consumer_available_output_bytes_T = |(unconsumed_bytes_so_far[63:5]); // @[MemLoader.scala:191:70, :193:49, :197:69] wire [63:0] _io_consumer_available_output_bytes_T_1 = _io_consumer_available_output_bytes_T ? 64'h20 : unconsumed_bytes_so_far; // @[MemLoader.scala:191:70, :197:{44,69}] assign io_consumer_available_output_bytes_0 = _io_consumer_available_output_bytes_T_1[5:0]; // @[MemLoader.scala:15:7, :197:{38,44}] assign _io_consumer_output_last_chunk_T = unconsumed_bytes_so_far < 64'h21; // @[MemLoader.scala:191:70, :201:61] assign io_consumer_output_last_chunk_0 = _io_consumer_output_last_chunk_T; // @[MemLoader.scala:15:7, :201:61] wire _T_3362 = io_consumer_output_ready_0 & _buf_info_queue_io_deq_valid; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_1 = _T_3362; // @[Misc.scala:29:18] reg [63:0] loginfo_cycles_44; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_88 = {1'h0, loginfo_cycles_44} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_89 = _loginfo_cycles_T_88[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_170( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_180 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundRawFNToRecFN_e8_s24_12( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_12 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_detectTininess (io_detectTininess_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SRAM.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes} import freechips.rocketchip.resources.{Device, DeviceRegName, DiplomaticSRAM, HasJustOneSeqMem} import freechips.rocketchip.util.{CanHaveErrors, ECCParams, property, SECDEDCode} import freechips.rocketchip.util.DataToAugmentedData import freechips.rocketchip.util.BooleanToAugmentedBoolean class TLRAMErrors(val params: ECCParams, val addrBits: Int) extends Bundle with CanHaveErrors { val correctable = (params.code.canCorrect && params.notifyErrors).option(Valid(UInt(addrBits.W))) val uncorrectable = (params.code.canDetect && params.notifyErrors).option(Valid(UInt(addrBits.W))) } class TLRAM( address: AddressSet, cacheable: Boolean = true, executable: Boolean = true, atomics: Boolean = false, beatBytes: Int = 4, ecc: ECCParams = ECCParams(), sramReg: Boolean = false, // drive SRAM data output directly into a register => 1 cycle longer response val devName: Option[String] = None, val dtsCompat: Option[Seq[String]] = None, val devOverride: Option[Device with DeviceRegName] = None )(implicit p: Parameters) extends DiplomaticSRAM(address, beatBytes, devName, dtsCompat, devOverride) { val eccBytes = ecc.bytes val code = ecc.code require (eccBytes >= 1 && isPow2(eccBytes)) require (beatBytes >= 1 && isPow2(beatBytes)) require (eccBytes <= beatBytes, s"TLRAM eccBytes (${eccBytes}) > beatBytes (${beatBytes}). Use a WidthWidget=>Fragmenter=>SRAM if you need high density and narrow ECC; it will do bursts efficiently") val node = TLManagerNode(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = List(address), resources = resources, regionType = if (cacheable) RegionType.UNCACHED else RegionType.IDEMPOTENT, executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), supportsArithmetic = if (atomics) TransferSizes(1, beatBytes) else TransferSizes.none, supportsLogical = if (atomics) TransferSizes(1, beatBytes) else TransferSizes.none, fifoId = Some(0)).v2copy(name=devName)), // requests are handled in order beatBytes = beatBytes, minLatency = 1))) // no bypass needed for this device val notifyNode = ecc.notifyErrors.option(BundleBridgeSource(() => new TLRAMErrors(ecc, log2Ceil(address.max)).cloneType)) private val outer = this lazy val module = new Impl class Impl extends LazyModuleImp(this) with HasJustOneSeqMem { val (in, edge) = node.in(0) val indexBits = (outer.address.mask & ~(beatBytes-1)).bitCount val width = code.width(eccBytes*8) val lanes = beatBytes/eccBytes val mem = makeSinglePortedByteWriteSeqMem( size = BigInt(1) << indexBits, lanes = lanes, bits = width) val eccCode = Some(ecc.code) val address = outer.address val laneDataBits = eccBytes * 8 /* This block has a three-stage pipeline * Stage A is the combinational request from TileLink A channel * Stage R corresponds to an accepted request * Stage D registers the result of an SRAM read (if any) * * The TileLink D channel response comes from * - stage D for corected reads or AMOs * - stage R for everything else * - However, to increase maximum operating frequency, the * stage R responses can be configured to come from stage D * * For sub-ECC granule writes and atomic operations: * - stage A sets up the read for the old data value * - stage R is used to gather the result from SRAM to registers * - stage D corrects ECC, applies the ALU, and sets up SRAM write * * For super-ECC granule writes: * - stage A sets up the write * * For reads: * - stage A sets up the read * - stage R drives the uncorrected data with valid based on ECC validity * - stage D sets up the correction, if any * * When stage D needs to perform a write (AMO, sub-ECC write, or ECC correction): * - there is a WaW or WaR hazard vs. the operation in stage R * - for sub-ECC writes and atomics, we ensure stage R has a bubble * - for ECC correction, we cause stage R to be replayed (and reject stage A twice) * - there is a structural hazard competing with stage A for SRAM access * - stage D always wins (stage A is rejected) * - on ECC correction, there is a structural hazard competing with stage R for the response channel * - stage D always wins (stage R is replayed) */ // D stage registers from R val d_full = RegInit(false.B) val d_respond = Reg(Bool()) val d_opcode = Reg(UInt(3.W)) val d_param = Reg(UInt(3.W)) val d_size = Reg(UInt(edge.bundle.sizeBits.W)) val d_source = Reg(UInt(edge.bundle.sourceBits.W)) val d_read = Reg(Bool()) val d_atomic = Reg(Bool()) val d_sublane = Reg(Bool()) val d_address = Reg(UInt(edge.bundle.addressBits.W)) val d_mask = Reg(UInt(beatBytes.W)) val d_rmw_data = Reg(UInt((8*beatBytes).W)) val d_poison = Reg(Bool()) val d_raw_data = Reg(Vec(lanes, Bits(width.W))) // R stage registers from A val r_full = RegInit(false.B) val r_opcode = Reg(UInt(3.W)) val r_param = Reg(UInt(3.W)) val r_size = Reg(UInt(edge.bundle.sizeBits.W)) val r_source = Reg(UInt(edge.bundle.sourceBits.W)) val r_read = Reg(Bool()) val r_atomic = Reg(Bool()) val r_sublane = Reg(Bool()) val r_address = Reg(UInt(edge.bundle.addressBits.W)) val r_mask = Reg(UInt(beatBytes.W)) val r_rmw_data = Reg(UInt((8*beatBytes).W)) val r_poison = Reg(Bool()) val r_raw_data = Wire(Vec(lanes, Bits(width.W))) // Decode raw SRAM output val d_decoded = d_raw_data.map(lane => code.decode(lane)) val d_corrected = Cat(d_decoded.map(_.corrected).reverse) val d_uncorrected = Cat(d_decoded.map(_.uncorrected).reverse) val d_correctable = d_decoded.map(_.correctable) val d_uncorrectable = d_decoded.map(_.uncorrectable) val d_need_fix = d_correctable.reduce(_ || _) val d_lanes = Cat(Seq.tabulate(lanes) { i => d_mask(eccBytes*(i+1)-1, eccBytes*i).orR }.reverse) val d_lane_error = Cat(d_uncorrectable.reverse) & d_lanes val d_error = d_lane_error.orR val r_decoded = r_raw_data.map(lane => code.decode(lane)) val r_corrected = Cat(r_decoded.map(_.corrected).reverse) val r_uncorrected = Cat(r_decoded.map(_.uncorrected).reverse) val r_correctable = r_decoded.map(_.correctable) val r_uncorrectable = r_decoded.map(_.uncorrectable) val r_need_fix = r_correctable.reduce(_ || _) val r_lanes = Cat(Seq.tabulate(lanes) { i => r_mask(eccBytes*(i+1)-1, eccBytes*i).orR }.reverse) val r_lane_error = Cat(r_uncorrectable.reverse) & r_lanes val r_error = r_lane_error.orR // Out-of-band notification of any faults notifyNode.foreach { nnode => nnode.bundle.correctable.foreach { c => c.valid := d_need_fix && d_full && (d_atomic || d_read || d_sublane) c.bits := d_address } nnode.bundle.uncorrectable.foreach { u => u.valid := d_error && d_full && (d_atomic || d_read || d_sublane) u.bits := d_address } } // What does D-stage want to write-back? // Make an ALU if we need one val d_updated = if (atomics) { val alu = Module(new Atomics(edge.bundle)) alu.io.write := false.B alu.io.a.opcode := d_opcode alu.io.a.param := d_param alu.io.a.size := d_size alu.io.a.source := 0.U alu.io.a.address := 0.U alu.io.a.data := d_rmw_data alu.io.a.mask := d_mask alu.io.a.corrupt := false.B alu.io.data_in := d_corrected alu.io.data_out } else { Cat(Seq.tabulate(beatBytes) { i => val upd = d_mask(i) && !d_read val rmw = d_rmw_data (8*(i+1)-1, 8*i) val fix = d_corrected(8*(i+1)-1, 8*i) // safe to use, because D-stage write-back always wins arbitration Mux(upd, rmw, fix) }.reverse) } // Stage D always wins control of the response channel val d_win = d_full && d_respond val d_mux = if (sramReg) true.B else d_win val out_aad = Mux(d_mux, d_read || d_atomic, r_read || r_atomic) in.d.bits.opcode := Mux(out_aad, TLMessages.AccessAckData, TLMessages.AccessAck) in.d.bits.param := 0.U in.d.bits.size := Mux(d_mux, d_size, r_size) in.d.bits.source := Mux(d_mux, d_source, r_source) in.d.bits.sink := 0.U in.d.bits.denied := false.B in.d.bits.data := Mux(d_mux, d_corrected, r_uncorrected) in.d.bits.corrupt := Mux(d_mux, d_error, r_error) && out_aad val mem_active_valid = Seq(property.CoverBoolean(in.d.valid, Seq("mem_active"))) val data_error = Seq( property.CoverBoolean(!d_need_fix && !d_error , Seq("no_data_error")), property.CoverBoolean(d_need_fix && !in.d.bits.corrupt, Seq("data_correctable_error_not_reported")), property.CoverBoolean(d_error && in.d.bits.corrupt, Seq("data_uncorrectable_error_reported"))) val error_cross_covers = new property.CrossProperty(Seq(mem_active_valid, data_error), Seq(), "Ecc Covers") property.cover(error_cross_covers) // Does the D stage want to perform a write? // It's important this reduce to false.B when eccBytes=1 && atomics=false && canCorrect=false val d_wb = d_full && (d_sublane || d_atomic || (d_read && d_need_fix)) // Formulate an R response unless there is a data output fix to perform // It's important this reduce to false.B for sramReg and true.B for !code.canCorrect val r_respond = !sramReg.B && (!r_need_fix || !(r_read || r_atomic)) // Resolve WaW and WaR hazard when D performs an update (only happens on ECC correction) // It's important this reduce to false.B unless code.canDetect val r_replay = RegNext(r_full && d_full && d_read && d_need_fix) // r_full && d_wb => read ecc fault (we insert a buble for atomic/sublane) assert (!(r_full && d_wb) || (d_full && d_read && d_need_fix)) // Pipeline control in.d.valid := (d_full && d_respond) || (r_full && r_respond && !d_wb && !r_replay) val d_ready = !d_respond || in.d.ready val r_ready = !d_wb && !r_replay && (!d_full || d_ready) && (!r_respond || (!d_win && in.d.ready)) in.a.ready := !(d_full && d_wb) && (!r_full || r_ready) && (!r_full || !(r_atomic || r_sublane)) // ignore sublane if it is a read or mask is all set val a_read = in.a.bits.opcode === TLMessages.Get val a_sublane = if (eccBytes == 1) false.B else ~a_read && (((in.a.bits.opcode === TLMessages.PutPartialData) && (~in.a.bits.mask.andR)) || in.a.bits.size < log2Ceil(eccBytes).U) val a_atomic = if (!atomics) false.B else in.a.bits.opcode === TLMessages.ArithmeticData || in.a.bits.opcode === TLMessages.LogicalData // Forward pipeline stage from R to D when (d_ready) { d_full := false.B } when (r_full && r_ready) { d_full := true.B d_respond := !r_respond d_opcode := r_opcode d_param := r_param d_size := r_size d_source := r_source d_read := r_read d_atomic := r_atomic d_sublane := r_sublane d_address := r_address d_mask := r_mask d_rmw_data := r_rmw_data d_poison := r_poison d_raw_data := r_raw_data } // Forward pipeline stage from A to R when (r_ready) { r_full := false.B } when (in.a.fire) { r_full := true.B r_sublane := a_sublane r_opcode := in.a.bits.opcode r_param := in.a.bits.param r_size := in.a.bits.size r_source := in.a.bits.source r_read := a_read r_atomic := a_atomic r_sublane := a_sublane r_address := in.a.bits.address r_poison := in.a.bits.corrupt r_mask := in.a.bits.mask when (!a_read) { r_rmw_data := in.a.bits.data } } // Split data into eccBytes-sized chunks: val a_data = VecInit(Seq.tabulate(lanes) { i => in.a.bits.data(eccBytes*8*(i+1)-1, eccBytes*8*i) }) val r_data = VecInit(Seq.tabulate(lanes) { i => r_rmw_data(eccBytes*8*(i+1)-1, eccBytes*8*i) }) val d_data = VecInit(Seq.tabulate(lanes) { i => d_updated(8*eccBytes*(i+1)-1, 8*eccBytes*i) }) // Which data chunks get poisoned val a_poisonv = VecInit(Seq.fill(lanes) { in.a.bits.corrupt }) val r_poisonv = VecInit(Seq.fill(lanes) { r_poison }) val d_poisonv = VecInit(Seq.tabulate(lanes) { i => val upd = d_mask(eccBytes*(i+1)-1, eccBytes*i) (!upd.andR && d_uncorrectable(i)) || d_poison // sub-lane writes should not correct uncorrectable }) val a_lanes = Cat(Seq.tabulate(lanes) { i => in.a.bits.mask(eccBytes*(i+1)-1, eccBytes*i).orR }.reverse) // SRAM arbitration val a_fire = in.a.fire val a_ren = a_read || a_atomic || a_sublane val r_ren = r_read || r_atomic || r_sublane val wen = d_wb || Mux(r_replay, !r_ren, a_fire && !a_ren) val ren = !wen && (a_fire || r_replay) // help Chisel infer a RW-port val addr = Mux(d_wb, d_address, Mux(r_replay, r_address, in.a.bits.address)) val sel = Mux(d_wb, d_lanes, Mux(r_replay, r_lanes, a_lanes)) val dat = Mux(d_wb, d_data, Mux(r_replay, r_data, a_data)) val poison = Mux(d_wb, d_poisonv, Mux(r_replay, r_poisonv, a_poisonv)) val coded = VecInit((dat zip poison) map { case (d, p) => if (code.canDetect) code.encode(d, p) else code.encode(d) }) val index = Cat(mask.zip((addr >> log2Ceil(beatBytes)).asBools).filter(_._1).map(_._2).reverse) r_raw_data := mem.read(index, ren) holdUnless RegNext(ren) when (wen) { mem.write(index, coded, sel.asBools) } // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B } } object TLRAM { def apply( address: AddressSet, cacheable: Boolean = true, executable: Boolean = true, atomics: Boolean = false, beatBytes: Int = 4, ecc: ECCParams = ECCParams(), sramReg: Boolean = false, devName: Option[String] = None, )(implicit p: Parameters): TLInwardNode = { val ram = LazyModule(new TLRAM(address, cacheable, executable, atomics, beatBytes, ecc, sramReg, devName)) ram.node } } // Synthesizable unit testing import freechips.rocketchip.unittest._ class TLRAMSimple(ramBeatBytes: Int, sramReg: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("SRAMSimple")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes, sramReg = sramReg)) ram.node := TLDelayer(0.25) := model.node := fuzz.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMSimpleTest(ramBeatBytes: Int, sramReg: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMSimple(ramBeatBytes, sramReg, txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLRAMECC(ramBeatBytes: Int, eccBytes: Int, sramReg: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("SRAMSimple")) val ram = LazyModule(new TLRAM( AddressSet(0x0, 0x3ff), atomics = true, beatBytes = ramBeatBytes, ecc = ECCParams(bytes = eccBytes, code = new SECDEDCode), sramReg = sramReg)) ram.node := TLDelayer(0.25) := model.node := fuzz.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMECCTest(ramBeatBytes: Int, eccBytes: Int, sramReg: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMECC(ramBeatBytes, eccBytes, sramReg, txns)).module) dut.io.start := io.start io.finished := dut.io.finished } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }
module TLRAM_ScratchpadBank( // @[SRAM.scala:63:9] input clock, // @[SRAM.scala:63:9] input reset, // @[SRAM.scala:63:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire [63:0] _mem_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire auto_in_a_valid_0 = auto_in_a_valid; // @[SRAM.scala:63:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[SRAM.scala:63:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[SRAM.scala:63:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[SRAM.scala:63:9] wire [7:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[SRAM.scala:63:9] wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[SRAM.scala:63:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[SRAM.scala:63:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[SRAM.scala:63:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[SRAM.scala:63:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[SRAM.scala:63:9] wire auto_in_d_bits_sink = 1'h0; // @[SRAM.scala:63:9] wire auto_in_d_bits_denied = 1'h0; // @[SRAM.scala:63:9] wire auto_in_d_bits_corrupt = 1'h0; // @[SRAM.scala:63:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _d_need_fix_T = 1'h0; // @[SRAM.scala:148:50] wire _d_need_fix_T_1 = 1'h0; // @[SRAM.scala:148:50] wire _d_need_fix_T_2 = 1'h0; // @[SRAM.scala:148:50] wire _d_need_fix_T_3 = 1'h0; // @[SRAM.scala:148:50] wire _d_need_fix_T_4 = 1'h0; // @[SRAM.scala:148:50] wire _d_need_fix_T_5 = 1'h0; // @[SRAM.scala:148:50] wire d_need_fix = 1'h0; // @[SRAM.scala:148:50] wire d_error = 1'h0; // @[SRAM.scala:151:40] wire _r_need_fix_T = 1'h0; // @[SRAM.scala:158:50] wire _r_need_fix_T_1 = 1'h0; // @[SRAM.scala:158:50] wire _r_need_fix_T_2 = 1'h0; // @[SRAM.scala:158:50] wire _r_need_fix_T_3 = 1'h0; // @[SRAM.scala:158:50] wire _r_need_fix_T_4 = 1'h0; // @[SRAM.scala:158:50] wire _r_need_fix_T_5 = 1'h0; // @[SRAM.scala:158:50] wire r_need_fix = 1'h0; // @[SRAM.scala:158:50] wire r_error = 1'h0; // @[SRAM.scala:161:40] wire d_win = 1'h0; // @[SRAM.scala:200:24] wire _nodeIn_d_bits_corrupt_T = 1'h0; // @[SRAM.scala:210:29] wire _nodeIn_d_bits_corrupt_T_1 = 1'h0; // @[SRAM.scala:210:55] wire _d_wb_T_1 = 1'h0; // @[SRAM.scala:223:60] wire _r_replay_T_2 = 1'h0; // @[SRAM.scala:229:55] wire _nodeIn_d_valid_T = 1'h0; // @[SRAM.scala:234:27] wire _r_ready_T_6 = 1'h0; // @[SRAM.scala:236:66] wire _nodeIn_a_ready_T_6 = 1'h0; // @[SRAM.scala:237:87] wire _d_respond_T = 1'h0; // @[SRAM.scala:253:21] wire _d_poisonv_T_2 = 1'h0; // @[SRAM.scala:296:18] wire _d_poisonv_T_6 = 1'h0; // @[SRAM.scala:296:18] wire _d_poisonv_T_10 = 1'h0; // @[SRAM.scala:296:18] wire _d_poisonv_T_14 = 1'h0; // @[SRAM.scala:296:18] wire _d_poisonv_T_18 = 1'h0; // @[SRAM.scala:296:18] wire _d_poisonv_T_22 = 1'h0; // @[SRAM.scala:296:18] wire _d_poisonv_T_26 = 1'h0; // @[SRAM.scala:296:18] wire _d_poisonv_T_30 = 1'h0; // @[SRAM.scala:296:18] wire _r_respond_T = 1'h1; // @[SRAM.scala:226:21] wire _r_respond_T_1 = 1'h1; // @[SRAM.scala:226:36] wire _r_respond_T_4 = 1'h1; // @[SRAM.scala:226:48] wire r_respond = 1'h1; // @[SRAM.scala:226:32] wire _nodeIn_d_valid_T_4 = 1'h1; // @[SRAM.scala:234:77] wire _d_ready_T = 1'h1; // @[SRAM.scala:235:19] wire d_ready = 1'h1; // @[SRAM.scala:235:30] wire _r_ready_T_1 = 1'h1; // @[SRAM.scala:236:28] wire _r_ready_T_4 = 1'h1; // @[SRAM.scala:236:50] wire _r_ready_T_7 = 1'h1; // @[SRAM.scala:236:81] wire _nodeIn_a_ready_T_7 = 1'h1; // @[SRAM.scala:237:76] wire _nodeIn_a_ready_T_8 = 1'h1; // @[SRAM.scala:237:73] wire [1:0] auto_in_d_bits_param = 2'h0; // @[SRAM.scala:63:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] d_lane_error_lo_lo = 2'h0; // @[SRAM.scala:150:30] wire [1:0] d_lane_error_lo_hi = 2'h0; // @[SRAM.scala:150:30] wire [1:0] d_lane_error_hi_lo = 2'h0; // @[SRAM.scala:150:30] wire [1:0] d_lane_error_hi_hi = 2'h0; // @[SRAM.scala:150:30] wire [1:0] r_lane_error_lo_lo = 2'h0; // @[SRAM.scala:160:30] wire [1:0] r_lane_error_lo_hi = 2'h0; // @[SRAM.scala:160:30] wire [1:0] r_lane_error_hi_lo = 2'h0; // @[SRAM.scala:160:30] wire [1:0] r_lane_error_hi_hi = 2'h0; // @[SRAM.scala:160:30] wire [7:0] _d_lane_error_T = 8'h0; // @[SRAM.scala:150:30] wire [7:0] d_lane_error = 8'h0; // @[SRAM.scala:150:56] wire [7:0] _r_lane_error_T = 8'h0; // @[SRAM.scala:160:30] wire [7:0] r_lane_error = 8'h0; // @[SRAM.scala:160:56] wire [3:0] d_lane_error_lo = 4'h0; // @[SRAM.scala:150:30] wire [3:0] d_lane_error_hi = 4'h0; // @[SRAM.scala:150:30] wire [3:0] r_lane_error_lo = 4'h0; // @[SRAM.scala:160:30] wire [3:0] r_lane_error_hi = 4'h0; // @[SRAM.scala:160:30] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[SRAM.scala:63:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[SRAM.scala:63:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[SRAM.scala:63:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[SRAM.scala:63:9] wire [7:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[SRAM.scala:63:9] wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[SRAM.scala:63:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[SRAM.scala:63:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[SRAM.scala:63:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[SRAM.scala:63:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[SRAM.scala:63:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_in_a_ready_0; // @[SRAM.scala:63:9] wire [2:0] auto_in_d_bits_opcode_0; // @[SRAM.scala:63:9] wire [1:0] auto_in_d_bits_size_0; // @[SRAM.scala:63:9] wire [7:0] auto_in_d_bits_source_0; // @[SRAM.scala:63:9] wire [63:0] auto_in_d_bits_data_0; // @[SRAM.scala:63:9] wire auto_in_d_valid_0; // @[SRAM.scala:63:9] wire _nodeIn_a_ready_T_9; // @[SRAM.scala:237:61] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[SRAM.scala:63:9] wire [27:0] _addr_T = nodeIn_a_bits_address; // @[SRAM.scala:308:42] wire a_poisonv_0 = nodeIn_a_bits_corrupt; // @[SRAM.scala:292:28] wire a_poisonv_1 = nodeIn_a_bits_corrupt; // @[SRAM.scala:292:28] wire a_poisonv_2 = nodeIn_a_bits_corrupt; // @[SRAM.scala:292:28] wire a_poisonv_3 = nodeIn_a_bits_corrupt; // @[SRAM.scala:292:28] wire a_poisonv_4 = nodeIn_a_bits_corrupt; // @[SRAM.scala:292:28] wire a_poisonv_5 = nodeIn_a_bits_corrupt; // @[SRAM.scala:292:28] wire a_poisonv_6 = nodeIn_a_bits_corrupt; // @[SRAM.scala:292:28] wire a_poisonv_7 = nodeIn_a_bits_corrupt; // @[SRAM.scala:292:28] wire _nodeIn_d_valid_T_6; // @[SRAM.scala:234:41] wire _r_ready_T_8 = nodeIn_d_ready; // @[SRAM.scala:236:88] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[SRAM.scala:63:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[SRAM.scala:63:9] wire [1:0] _nodeIn_d_bits_size_T; // @[SRAM.scala:205:29] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[SRAM.scala:63:9] wire [7:0] _nodeIn_d_bits_source_T; // @[SRAM.scala:206:29] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[SRAM.scala:63:9] wire [63:0] _nodeIn_d_bits_data_T; // @[SRAM.scala:209:29] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[SRAM.scala:63:9] wire wen; // @[SRAM.scala:305:20] wire ren; // @[SRAM.scala:306:20] wire [7:0] coded_0; // @[SRAM.scala:312:25] wire [7:0] coded_1; // @[SRAM.scala:312:25] wire [7:0] coded_2; // @[SRAM.scala:312:25] wire [7:0] coded_3; // @[SRAM.scala:312:25] wire [7:0] coded_4; // @[SRAM.scala:312:25] wire [7:0] coded_5; // @[SRAM.scala:312:25] wire [7:0] coded_6; // @[SRAM.scala:312:25] wire [7:0] coded_7; // @[SRAM.scala:312:25] reg d_full; // @[SRAM.scala:112:30] reg [2:0] d_opcode; // @[SRAM.scala:114:26] reg [2:0] d_param; // @[SRAM.scala:115:26] reg [1:0] d_size; // @[SRAM.scala:116:26] reg [7:0] d_source; // @[SRAM.scala:117:26] reg d_read; // @[SRAM.scala:118:26] reg d_atomic; // @[SRAM.scala:119:26] reg d_sublane; // @[SRAM.scala:120:26] reg [27:0] d_address; // @[SRAM.scala:121:26] reg [7:0] d_mask; // @[SRAM.scala:122:26] reg [63:0] d_rmw_data; // @[SRAM.scala:123:26] reg d_poison; // @[SRAM.scala:124:26] wire _d_poisonv_T_3 = d_poison; // @[SRAM.scala:124:26, :296:41] wire _d_poisonv_T_7 = d_poison; // @[SRAM.scala:124:26, :296:41] wire _d_poisonv_T_11 = d_poison; // @[SRAM.scala:124:26, :296:41] wire _d_poisonv_T_15 = d_poison; // @[SRAM.scala:124:26, :296:41] wire _d_poisonv_T_19 = d_poison; // @[SRAM.scala:124:26, :296:41] wire _d_poisonv_T_23 = d_poison; // @[SRAM.scala:124:26, :296:41] wire _d_poisonv_T_27 = d_poison; // @[SRAM.scala:124:26, :296:41] wire _d_poisonv_T_31 = d_poison; // @[SRAM.scala:124:26, :296:41] reg [7:0] d_raw_data_0; // @[SRAM.scala:125:26] reg [7:0] d_raw_data_1; // @[SRAM.scala:125:26] reg [7:0] d_raw_data_2; // @[SRAM.scala:125:26] reg [7:0] d_raw_data_3; // @[SRAM.scala:125:26] reg [7:0] d_raw_data_4; // @[SRAM.scala:125:26] reg [7:0] d_raw_data_5; // @[SRAM.scala:125:26] reg [7:0] d_raw_data_6; // @[SRAM.scala:125:26] reg [7:0] d_raw_data_7; // @[SRAM.scala:125:26] reg r_full; // @[SRAM.scala:128:30] wire _nodeIn_d_valid_T_1 = r_full; // @[SRAM.scala:128:30, :234:52] reg [2:0] r_opcode; // @[SRAM.scala:129:26] reg [2:0] r_param; // @[SRAM.scala:130:26] reg [1:0] r_size; // @[SRAM.scala:131:26] assign _nodeIn_d_bits_size_T = r_size; // @[SRAM.scala:131:26, :205:29] reg [7:0] r_source; // @[SRAM.scala:132:26] assign _nodeIn_d_bits_source_T = r_source; // @[SRAM.scala:132:26, :206:29] reg r_read; // @[SRAM.scala:133:26] wire _out_aad_T_1 = r_read; // @[SRAM.scala:133:26, :202:57] wire _r_respond_T_2 = r_read; // @[SRAM.scala:133:26, :226:60] wire _r_ren_T = r_read; // @[SRAM.scala:133:26, :304:24] reg [27:0] r_address; // @[SRAM.scala:136:26] reg [7:0] r_mask; // @[SRAM.scala:137:26] reg [63:0] r_rmw_data; // @[SRAM.scala:138:26] reg r_poison; // @[SRAM.scala:139:26] wire r_poisonv_0 = r_poison; // @[SRAM.scala:139:26, :293:28] wire r_poisonv_1 = r_poison; // @[SRAM.scala:139:26, :293:28] wire r_poisonv_2 = r_poison; // @[SRAM.scala:139:26, :293:28] wire r_poisonv_3 = r_poison; // @[SRAM.scala:139:26, :293:28] wire r_poisonv_4 = r_poison; // @[SRAM.scala:139:26, :293:28] wire r_poisonv_5 = r_poison; // @[SRAM.scala:139:26, :293:28] wire r_poisonv_6 = r_poison; // @[SRAM.scala:139:26, :293:28] wire r_poisonv_7 = r_poison; // @[SRAM.scala:139:26, :293:28] wire [7:0] r_raw_data_0; // @[SRAM.scala:140:27] wire [7:0] r_raw_data_1; // @[SRAM.scala:140:27] wire [7:0] r_raw_data_2; // @[SRAM.scala:140:27] wire [7:0] r_raw_data_3; // @[SRAM.scala:140:27] wire [7:0] r_raw_data_4; // @[SRAM.scala:140:27] wire [7:0] r_raw_data_5; // @[SRAM.scala:140:27] wire [7:0] r_raw_data_6; // @[SRAM.scala:140:27] wire [7:0] r_raw_data_7; // @[SRAM.scala:140:27] wire [15:0] _GEN = {d_raw_data_1, d_raw_data_0}; // @[SRAM.scala:125:26, :144:30] wire [15:0] d_corrected_lo_lo; // @[SRAM.scala:144:30] assign d_corrected_lo_lo = _GEN; // @[SRAM.scala:144:30] wire [15:0] d_uncorrected_lo_lo; // @[SRAM.scala:145:30] assign d_uncorrected_lo_lo = _GEN; // @[SRAM.scala:144:30, :145:30] wire [15:0] _GEN_0 = {d_raw_data_3, d_raw_data_2}; // @[SRAM.scala:125:26, :144:30] wire [15:0] d_corrected_lo_hi; // @[SRAM.scala:144:30] assign d_corrected_lo_hi = _GEN_0; // @[SRAM.scala:144:30] wire [15:0] d_uncorrected_lo_hi; // @[SRAM.scala:145:30] assign d_uncorrected_lo_hi = _GEN_0; // @[SRAM.scala:144:30, :145:30] wire [31:0] d_corrected_lo = {d_corrected_lo_hi, d_corrected_lo_lo}; // @[SRAM.scala:144:30] wire [15:0] _GEN_1 = {d_raw_data_5, d_raw_data_4}; // @[SRAM.scala:125:26, :144:30] wire [15:0] d_corrected_hi_lo; // @[SRAM.scala:144:30] assign d_corrected_hi_lo = _GEN_1; // @[SRAM.scala:144:30] wire [15:0] d_uncorrected_hi_lo; // @[SRAM.scala:145:30] assign d_uncorrected_hi_lo = _GEN_1; // @[SRAM.scala:144:30, :145:30] wire [15:0] _GEN_2 = {d_raw_data_7, d_raw_data_6}; // @[SRAM.scala:125:26, :144:30] wire [15:0] d_corrected_hi_hi; // @[SRAM.scala:144:30] assign d_corrected_hi_hi = _GEN_2; // @[SRAM.scala:144:30] wire [15:0] d_uncorrected_hi_hi; // @[SRAM.scala:145:30] assign d_uncorrected_hi_hi = _GEN_2; // @[SRAM.scala:144:30, :145:30] wire [31:0] d_corrected_hi = {d_corrected_hi_hi, d_corrected_hi_lo}; // @[SRAM.scala:144:30] wire [63:0] d_corrected = {d_corrected_hi, d_corrected_lo}; // @[SRAM.scala:144:30] wire [31:0] d_uncorrected_lo = {d_uncorrected_lo_hi, d_uncorrected_lo_lo}; // @[SRAM.scala:145:30] wire [31:0] d_uncorrected_hi = {d_uncorrected_hi_hi, d_uncorrected_hi_lo}; // @[SRAM.scala:145:30] wire [63:0] d_uncorrected = {d_uncorrected_hi, d_uncorrected_lo}; // @[SRAM.scala:145:30] wire _d_lanes_T = d_mask[0]; // @[SRAM.scala:122:26, :149:64] wire _d_updated_upd_T = d_mask[0]; // @[SRAM.scala:122:26, :149:64, :192:25] wire d_poisonv_upd = d_mask[0]; // @[SRAM.scala:122:26, :149:64, :295:23] wire _d_lanes_T_1 = _d_lanes_T; // @[SRAM.scala:149:{64,95}] wire _d_lanes_T_2 = d_mask[1]; // @[SRAM.scala:122:26, :149:64] wire _d_updated_upd_T_2 = d_mask[1]; // @[SRAM.scala:122:26, :149:64, :192:25] wire d_poisonv_upd_1 = d_mask[1]; // @[SRAM.scala:122:26, :149:64, :295:23] wire _d_lanes_T_3 = _d_lanes_T_2; // @[SRAM.scala:149:{64,95}] wire _d_lanes_T_4 = d_mask[2]; // @[SRAM.scala:122:26, :149:64] wire _d_updated_upd_T_4 = d_mask[2]; // @[SRAM.scala:122:26, :149:64, :192:25] wire d_poisonv_upd_2 = d_mask[2]; // @[SRAM.scala:122:26, :149:64, :295:23] wire _d_lanes_T_5 = _d_lanes_T_4; // @[SRAM.scala:149:{64,95}] wire _d_lanes_T_6 = d_mask[3]; // @[SRAM.scala:122:26, :149:64] wire _d_updated_upd_T_6 = d_mask[3]; // @[SRAM.scala:122:26, :149:64, :192:25] wire d_poisonv_upd_3 = d_mask[3]; // @[SRAM.scala:122:26, :149:64, :295:23] wire _d_lanes_T_7 = _d_lanes_T_6; // @[SRAM.scala:149:{64,95}] wire _d_lanes_T_8 = d_mask[4]; // @[SRAM.scala:122:26, :149:64] wire _d_updated_upd_T_8 = d_mask[4]; // @[SRAM.scala:122:26, :149:64, :192:25] wire d_poisonv_upd_4 = d_mask[4]; // @[SRAM.scala:122:26, :149:64, :295:23] wire _d_lanes_T_9 = _d_lanes_T_8; // @[SRAM.scala:149:{64,95}] wire _d_lanes_T_10 = d_mask[5]; // @[SRAM.scala:122:26, :149:64] wire _d_updated_upd_T_10 = d_mask[5]; // @[SRAM.scala:122:26, :149:64, :192:25] wire d_poisonv_upd_5 = d_mask[5]; // @[SRAM.scala:122:26, :149:64, :295:23] wire _d_lanes_T_11 = _d_lanes_T_10; // @[SRAM.scala:149:{64,95}] wire _d_lanes_T_12 = d_mask[6]; // @[SRAM.scala:122:26, :149:64] wire _d_updated_upd_T_12 = d_mask[6]; // @[SRAM.scala:122:26, :149:64, :192:25] wire d_poisonv_upd_6 = d_mask[6]; // @[SRAM.scala:122:26, :149:64, :295:23] wire _d_lanes_T_13 = _d_lanes_T_12; // @[SRAM.scala:149:{64,95}] wire _d_lanes_T_14 = d_mask[7]; // @[SRAM.scala:122:26, :149:64] wire _d_updated_upd_T_14 = d_mask[7]; // @[SRAM.scala:122:26, :149:64, :192:25] wire d_poisonv_upd_7 = d_mask[7]; // @[SRAM.scala:122:26, :149:64, :295:23] wire _d_lanes_T_15 = _d_lanes_T_14; // @[SRAM.scala:149:{64,95}] wire [1:0] d_lanes_lo_lo = {_d_lanes_T_3, _d_lanes_T_1}; // @[SRAM.scala:149:{30,95}] wire [1:0] d_lanes_lo_hi = {_d_lanes_T_7, _d_lanes_T_5}; // @[SRAM.scala:149:{30,95}] wire [3:0] d_lanes_lo = {d_lanes_lo_hi, d_lanes_lo_lo}; // @[SRAM.scala:149:30] wire [1:0] d_lanes_hi_lo = {_d_lanes_T_11, _d_lanes_T_9}; // @[SRAM.scala:149:{30,95}] wire [1:0] d_lanes_hi_hi = {_d_lanes_T_15, _d_lanes_T_13}; // @[SRAM.scala:149:{30,95}] wire [3:0] d_lanes_hi = {d_lanes_hi_hi, d_lanes_hi_lo}; // @[SRAM.scala:149:30] wire [7:0] d_lanes = {d_lanes_hi, d_lanes_lo}; // @[SRAM.scala:149:30] wire [15:0] _GEN_3 = {r_raw_data_1, r_raw_data_0}; // @[SRAM.scala:140:27, :154:30] wire [15:0] r_corrected_lo_lo; // @[SRAM.scala:154:30] assign r_corrected_lo_lo = _GEN_3; // @[SRAM.scala:154:30] wire [15:0] r_uncorrected_lo_lo; // @[SRAM.scala:155:30] assign r_uncorrected_lo_lo = _GEN_3; // @[SRAM.scala:154:30, :155:30] wire [15:0] _GEN_4 = {r_raw_data_3, r_raw_data_2}; // @[SRAM.scala:140:27, :154:30] wire [15:0] r_corrected_lo_hi; // @[SRAM.scala:154:30] assign r_corrected_lo_hi = _GEN_4; // @[SRAM.scala:154:30] wire [15:0] r_uncorrected_lo_hi; // @[SRAM.scala:155:30] assign r_uncorrected_lo_hi = _GEN_4; // @[SRAM.scala:154:30, :155:30] wire [31:0] r_corrected_lo = {r_corrected_lo_hi, r_corrected_lo_lo}; // @[SRAM.scala:154:30] wire [15:0] _GEN_5 = {r_raw_data_5, r_raw_data_4}; // @[SRAM.scala:140:27, :154:30] wire [15:0] r_corrected_hi_lo; // @[SRAM.scala:154:30] assign r_corrected_hi_lo = _GEN_5; // @[SRAM.scala:154:30] wire [15:0] r_uncorrected_hi_lo; // @[SRAM.scala:155:30] assign r_uncorrected_hi_lo = _GEN_5; // @[SRAM.scala:154:30, :155:30] wire [15:0] _GEN_6 = {r_raw_data_7, r_raw_data_6}; // @[SRAM.scala:140:27, :154:30] wire [15:0] r_corrected_hi_hi; // @[SRAM.scala:154:30] assign r_corrected_hi_hi = _GEN_6; // @[SRAM.scala:154:30] wire [15:0] r_uncorrected_hi_hi; // @[SRAM.scala:155:30] assign r_uncorrected_hi_hi = _GEN_6; // @[SRAM.scala:154:30, :155:30] wire [31:0] r_corrected_hi = {r_corrected_hi_hi, r_corrected_hi_lo}; // @[SRAM.scala:154:30] wire [63:0] r_corrected = {r_corrected_hi, r_corrected_lo}; // @[SRAM.scala:154:30] wire [31:0] r_uncorrected_lo = {r_uncorrected_lo_hi, r_uncorrected_lo_lo}; // @[SRAM.scala:155:30] wire [31:0] r_uncorrected_hi = {r_uncorrected_hi_hi, r_uncorrected_hi_lo}; // @[SRAM.scala:155:30] wire [63:0] r_uncorrected = {r_uncorrected_hi, r_uncorrected_lo}; // @[SRAM.scala:155:30] assign _nodeIn_d_bits_data_T = r_uncorrected; // @[SRAM.scala:155:30, :209:29] wire _r_lanes_T = r_mask[0]; // @[SRAM.scala:137:26, :159:64] wire _r_lanes_T_1 = _r_lanes_T; // @[SRAM.scala:159:{64,95}] wire _r_lanes_T_2 = r_mask[1]; // @[SRAM.scala:137:26, :159:64] wire _r_lanes_T_3 = _r_lanes_T_2; // @[SRAM.scala:159:{64,95}] wire _r_lanes_T_4 = r_mask[2]; // @[SRAM.scala:137:26, :159:64] wire _r_lanes_T_5 = _r_lanes_T_4; // @[SRAM.scala:159:{64,95}] wire _r_lanes_T_6 = r_mask[3]; // @[SRAM.scala:137:26, :159:64] wire _r_lanes_T_7 = _r_lanes_T_6; // @[SRAM.scala:159:{64,95}] wire _r_lanes_T_8 = r_mask[4]; // @[SRAM.scala:137:26, :159:64] wire _r_lanes_T_9 = _r_lanes_T_8; // @[SRAM.scala:159:{64,95}] wire _r_lanes_T_10 = r_mask[5]; // @[SRAM.scala:137:26, :159:64] wire _r_lanes_T_11 = _r_lanes_T_10; // @[SRAM.scala:159:{64,95}] wire _r_lanes_T_12 = r_mask[6]; // @[SRAM.scala:137:26, :159:64] wire _r_lanes_T_13 = _r_lanes_T_12; // @[SRAM.scala:159:{64,95}] wire _r_lanes_T_14 = r_mask[7]; // @[SRAM.scala:137:26, :159:64] wire _r_lanes_T_15 = _r_lanes_T_14; // @[SRAM.scala:159:{64,95}] wire [1:0] r_lanes_lo_lo = {_r_lanes_T_3, _r_lanes_T_1}; // @[SRAM.scala:159:{30,95}] wire [1:0] r_lanes_lo_hi = {_r_lanes_T_7, _r_lanes_T_5}; // @[SRAM.scala:159:{30,95}] wire [3:0] r_lanes_lo = {r_lanes_lo_hi, r_lanes_lo_lo}; // @[SRAM.scala:159:30] wire [1:0] r_lanes_hi_lo = {_r_lanes_T_11, _r_lanes_T_9}; // @[SRAM.scala:159:{30,95}] wire [1:0] r_lanes_hi_hi = {_r_lanes_T_15, _r_lanes_T_13}; // @[SRAM.scala:159:{30,95}] wire [3:0] r_lanes_hi = {r_lanes_hi_hi, r_lanes_hi_lo}; // @[SRAM.scala:159:30] wire [7:0] r_lanes = {r_lanes_hi, r_lanes_lo}; // @[SRAM.scala:159:30] wire _d_updated_upd_T_1 = ~d_read; // @[SRAM.scala:118:26, :192:32] wire d_updated_upd = _d_updated_upd_T & _d_updated_upd_T_1; // @[SRAM.scala:192:{25,29,32}] wire [7:0] d_updated_rmw = d_rmw_data[7:0]; // @[SRAM.scala:123:26, :193:30] wire [7:0] d_updated_fix = d_corrected[7:0]; // @[SRAM.scala:144:30, :194:30] wire [7:0] _d_updated_T = d_updated_upd ? d_updated_rmw : d_updated_fix; // @[SRAM.scala:192:29, :193:30, :194:30, :195:12] wire _d_updated_upd_T_3 = ~d_read; // @[SRAM.scala:118:26, :192:32] wire d_updated_upd_1 = _d_updated_upd_T_2 & _d_updated_upd_T_3; // @[SRAM.scala:192:{25,29,32}] wire [7:0] d_updated_rmw_1 = d_rmw_data[15:8]; // @[SRAM.scala:123:26, :193:30] wire [7:0] d_updated_fix_1 = d_corrected[15:8]; // @[SRAM.scala:144:30, :194:30] wire [7:0] _d_updated_T_1 = d_updated_upd_1 ? d_updated_rmw_1 : d_updated_fix_1; // @[SRAM.scala:192:29, :193:30, :194:30, :195:12] wire _d_updated_upd_T_5 = ~d_read; // @[SRAM.scala:118:26, :192:32] wire d_updated_upd_2 = _d_updated_upd_T_4 & _d_updated_upd_T_5; // @[SRAM.scala:192:{25,29,32}] wire [7:0] d_updated_rmw_2 = d_rmw_data[23:16]; // @[SRAM.scala:123:26, :193:30] wire [7:0] d_updated_fix_2 = d_corrected[23:16]; // @[SRAM.scala:144:30, :194:30] wire [7:0] _d_updated_T_2 = d_updated_upd_2 ? d_updated_rmw_2 : d_updated_fix_2; // @[SRAM.scala:192:29, :193:30, :194:30, :195:12] wire _d_updated_upd_T_7 = ~d_read; // @[SRAM.scala:118:26, :192:32] wire d_updated_upd_3 = _d_updated_upd_T_6 & _d_updated_upd_T_7; // @[SRAM.scala:192:{25,29,32}] wire [7:0] d_updated_rmw_3 = d_rmw_data[31:24]; // @[SRAM.scala:123:26, :193:30] wire [7:0] d_updated_fix_3 = d_corrected[31:24]; // @[SRAM.scala:144:30, :194:30] wire [7:0] _d_updated_T_3 = d_updated_upd_3 ? d_updated_rmw_3 : d_updated_fix_3; // @[SRAM.scala:192:29, :193:30, :194:30, :195:12] wire _d_updated_upd_T_9 = ~d_read; // @[SRAM.scala:118:26, :192:32] wire d_updated_upd_4 = _d_updated_upd_T_8 & _d_updated_upd_T_9; // @[SRAM.scala:192:{25,29,32}] wire [7:0] d_updated_rmw_4 = d_rmw_data[39:32]; // @[SRAM.scala:123:26, :193:30] wire [7:0] d_updated_fix_4 = d_corrected[39:32]; // @[SRAM.scala:144:30, :194:30] wire [7:0] _d_updated_T_4 = d_updated_upd_4 ? d_updated_rmw_4 : d_updated_fix_4; // @[SRAM.scala:192:29, :193:30, :194:30, :195:12] wire _d_updated_upd_T_11 = ~d_read; // @[SRAM.scala:118:26, :192:32] wire d_updated_upd_5 = _d_updated_upd_T_10 & _d_updated_upd_T_11; // @[SRAM.scala:192:{25,29,32}] wire [7:0] d_updated_rmw_5 = d_rmw_data[47:40]; // @[SRAM.scala:123:26, :193:30] wire [7:0] d_updated_fix_5 = d_corrected[47:40]; // @[SRAM.scala:144:30, :194:30] wire [7:0] _d_updated_T_5 = d_updated_upd_5 ? d_updated_rmw_5 : d_updated_fix_5; // @[SRAM.scala:192:29, :193:30, :194:30, :195:12] wire _d_updated_upd_T_13 = ~d_read; // @[SRAM.scala:118:26, :192:32] wire d_updated_upd_6 = _d_updated_upd_T_12 & _d_updated_upd_T_13; // @[SRAM.scala:192:{25,29,32}] wire [7:0] d_updated_rmw_6 = d_rmw_data[55:48]; // @[SRAM.scala:123:26, :193:30] wire [7:0] d_updated_fix_6 = d_corrected[55:48]; // @[SRAM.scala:144:30, :194:30] wire [7:0] _d_updated_T_6 = d_updated_upd_6 ? d_updated_rmw_6 : d_updated_fix_6; // @[SRAM.scala:192:29, :193:30, :194:30, :195:12] wire _d_updated_upd_T_15 = ~d_read; // @[SRAM.scala:118:26, :192:32] wire d_updated_upd_7 = _d_updated_upd_T_14 & _d_updated_upd_T_15; // @[SRAM.scala:192:{25,29,32}] wire [7:0] d_updated_rmw_7 = d_rmw_data[63:56]; // @[SRAM.scala:123:26, :193:30] wire [7:0] d_updated_fix_7 = d_corrected[63:56]; // @[SRAM.scala:144:30, :194:30] wire [7:0] _d_updated_T_7 = d_updated_upd_7 ? d_updated_rmw_7 : d_updated_fix_7; // @[SRAM.scala:192:29, :193:30, :194:30, :195:12] wire [15:0] d_updated_lo_lo = {_d_updated_T_1, _d_updated_T}; // @[SRAM.scala:191:10, :195:12] wire [15:0] d_updated_lo_hi = {_d_updated_T_3, _d_updated_T_2}; // @[SRAM.scala:191:10, :195:12] wire [31:0] d_updated_lo = {d_updated_lo_hi, d_updated_lo_lo}; // @[SRAM.scala:191:10] wire [15:0] d_updated_hi_lo = {_d_updated_T_5, _d_updated_T_4}; // @[SRAM.scala:191:10, :195:12] wire [15:0] d_updated_hi_hi = {_d_updated_T_7, _d_updated_T_6}; // @[SRAM.scala:191:10, :195:12] wire [31:0] d_updated_hi = {d_updated_hi_hi, d_updated_hi_lo}; // @[SRAM.scala:191:10] wire [63:0] d_updated = {d_updated_hi, d_updated_lo}; // @[SRAM.scala:191:10] wire _out_aad_T = d_read | d_atomic; // @[SRAM.scala:118:26, :119:26, :202:37] wire out_aad = _out_aad_T_1; // @[SRAM.scala:202:{22,57}] wire _nodeIn_d_bits_opcode_T = out_aad; // @[SRAM.scala:202:22, :203:29] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[SRAM.scala:203:{23,29}] assign nodeIn_d_bits_size = _nodeIn_d_bits_size_T; // @[SRAM.scala:205:29] assign nodeIn_d_bits_source = _nodeIn_d_bits_source_T; // @[SRAM.scala:206:29] assign nodeIn_d_bits_data = _nodeIn_d_bits_data_T; // @[SRAM.scala:209:29] wire _d_wb_T = d_sublane | d_atomic; // @[SRAM.scala:119:26, :120:26, :223:37] wire _d_wb_T_2 = _d_wb_T; // @[SRAM.scala:223:{37,49}] wire d_wb = d_full & _d_wb_T_2; // @[SRAM.scala:112:30, :223:{23,49}] wire _r_respond_T_3 = ~_r_respond_T_2; // @[SRAM.scala:226:{51,60}] wire _r_replay_T = r_full & d_full; // @[SRAM.scala:112:30, :128:30, :229:35] wire _r_replay_T_1 = _r_replay_T & d_read; // @[SRAM.scala:118:26, :229:{35,45}]
Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 */ val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2*maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready || drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) || out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied || out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full || !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full || in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLFragmenter_Debug( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [9:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [11:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9] wire [9:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Fragmenter.scala:92:9] wire [13:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36] wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50] wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50] wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84] wire [1:0] _limit_T_1 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_3 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_5 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_7 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_9 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] limit = 2'h3; // @[Fragmenter.scala:288:49] wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59] wire find_0 = 1'h1; // @[Parameters.scala:616:12] wire [12:0] _find_T_2 = 13'h0; // @[Parameters.scala:137:46] wire [12:0] _find_T_3 = 13'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [9:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [11:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [9:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Fragmenter.scala:92:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [13:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [1:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [13:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_ready_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [9:0] auto_anon_in_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [13:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Fragmenter.scala:92:9] assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Fragmenter.scala:92:9] wire [9:0] _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9] wire [13:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9] wire [11:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dsizeOH_shiftAmount = anonOut_d_bits_size; // @[OneHot.scala:64:49] assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire [2:0] dFragnum = anonOut_d_bits_source[2:0]; // @[Fragmenter.scala:204:41] wire [2:0] acknum_fragment = dFragnum; // @[Fragmenter.scala:204:41, :212:40] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala:204:41, :206:30] wire _drop_T_1 = dLast; // @[Fragmenter.scala:206:30, :234:37] wire [3:0] _dsizeOH_T = 4'h1 << dsizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] dsizeOH = _dsizeOH_T; // @[OneHot.scala:65:{12,27}] wire [5:0] _dsizeOH1_T = 6'h7 << anonOut_d_bits_size; // @[package.scala:243:71] wire [2:0] _dsizeOH1_T_1 = _dsizeOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1; // @[package.scala:243:{46,76}] wire dHasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] dFirst_acknum = acknum_fragment; // @[Fragmenter.scala:212:40, :215:45] wire _ack_decrement_T = dsizeOH[3]; // @[OneHot.scala:65:27] wire ack_decrement = dHasData | _ack_decrement_T; // @[Fragmenter.scala:216:{32,56}] wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala:204:41, :218:47] wire [5:0] _dFirst_size_T_1 = {_dFirst_size_T[5:3], _dFirst_size_T[2:0] | dsizeOH1}; // @[package.scala:243:46] wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala:241:35] wire [6:0] _dFirst_size_T_3 = {_dFirst_size_T_2[6:1], 1'h1}; // @[package.scala:241:{35,40}] wire [6:0] _dFirst_size_T_4 = {1'h0, _dFirst_size_T_1}; // @[package.scala:241:53] wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala:241:{49,53}] wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala:241:{40,47,49}] wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala:30:18] wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala:31:18] wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi} | dFirst_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28] wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _dFirst_size_T_11 = _dFirst_size_T_10[1]; // @[OneHot.scala:32:28] wire [1:0] _dFirst_size_T_12 = {_dFirst_size_T_9, _dFirst_size_T_11}; // @[OneHot.scala:32:{10,14}] wire [2:0] dFirst_size = {_dFirst_size_T_7, _dFirst_size_T_12}; // @[OneHot.scala:32:{10,14}] wire [3:0] _acknum_T = {1'h0, acknum} - {3'h0, ack_decrement}; // @[Fragmenter.scala:201:29, :216:32, :221:55] wire [2:0] _acknum_T_1 = _acknum_T[2:0]; // @[Fragmenter.scala:221:55] wire [2:0] _acknum_T_2 = dFirst ? dFirst_acknum : _acknum_T_1; // @[Fragmenter.scala:205:29, :215:45, :221:{24,55}] wire _dToggle_T = anonOut_d_bits_source[3]; // @[Fragmenter.scala:224:41] wire _drop_T = ~dHasData; // @[Fragmenter.scala:234:20] wire _drop_T_2 = ~_drop_T_1; // @[Fragmenter.scala:234:{33,37}] wire drop = _drop_T & _drop_T_2; // @[Fragmenter.scala:234:{20,30,33}] assign _anonOut_d_ready_T = anonIn_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35] assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] wire _anonIn_d_valid_T = ~drop; // @[Fragmenter.scala:234:30, :236:39] assign _anonIn_d_valid_T_1 = anonOut_d_valid & _anonIn_d_valid_T; // @[Fragmenter.scala:236:{36,39}] assign anonIn_d_valid = _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign _anonIn_d_bits_source_T = anonOut_d_bits_source[13:4]; // @[Fragmenter.scala:238:47] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign _anonIn_d_bits_size_T = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] assign anonIn_d_bits_size = _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] wire [11:0] _find_T; // @[Parameters.scala:137:31] wire [12:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}] wire _limit_T = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49] wire _aFrag_T = _repeater_io_deq_bits_size[2]; // @[Fragmenter.scala:274:30, :297:31] wire [2:0] aFrag = _aFrag_T ? 3'h3 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}] wire [9:0] _aFragOH1_T = 10'h7 << aFrag; // @[package.scala:243:71] wire [2:0] _aFragOH1_T_1 = _aFragOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}] wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30] wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] aMask = aHasData ? 3'h0 : aFragOH1; // @[package.scala:243:46] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] _old_gennum1_T = aOrigOH1[5:3]; // @[package.scala:243:46] wire [3:0] _old_gennum1_T_1 = {1'h0, gennum} - 4'h1; // @[Fragmenter.scala:303:29, :305:79] wire [2:0] _old_gennum1_T_2 = _old_gennum1_T_1[2:0]; // @[Fragmenter.scala:305:79] wire [2:0] old_gennum1 = aFirst ? _old_gennum1_T : _old_gennum1_T_2; // @[Fragmenter.scala:304:29, :305:{30,48,79}] wire [2:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40] wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28] wire [2:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}] wire [2:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}] wire [2:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}] wire [2:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}] wire [2:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}] wire aLast = ~(|aFragnum); // @[Fragmenter.scala:307:24, :308:30] reg aToggle_r; // @[Fragmenter.scala:309:54] wire _aToggle_T = aFirst ? dToggle : aToggle_r; // @[Fragmenter.scala:203:30, :304:29, :309:{27,54}] wire aToggle = ~_aToggle_T; // @[Fragmenter.scala:309:{23,27}] wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31] wire _repeater_io_repeat_T_1 = |aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53] wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}] wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala:305:30, :316:65] wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T | _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}] wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:3], _anonOut_a_bits_address_T_2[2:0] | aFragOH1}; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:3], 3'h7}; // @[Fragmenter.scala:316:{100,111}] wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}] assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[11:6], _repeater_io_deq_bits_address[5:0] | _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}] assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] wire [10:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, aToggle}; // @[Fragmenter.scala:274:30, :309:23, :317:33] assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, aFragnum}; // @[Fragmenter.scala:307:24, :317:33] assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25]
Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired || fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module Router_58( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [3:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [3:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [3:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [3:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [9:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [9:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_1_vc_sel_0_8; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_9; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_8; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_9; // @[Router.scala:136:32] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_8; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_9; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_8; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_9; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_8_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_9_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_8_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_9_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_8_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_9_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_8_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_9_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_1_to_10_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_credit_available_8; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_credit_available_9; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_channel_status_8_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_10_io_channel_status_9_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_credit_available_8; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_credit_available_9; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_channel_status_8_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_channel_status_9_occupied; // @[Router.scala:122:13] wire [3:0] _input_unit_1_from_10_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_10_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_10_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_10_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_10_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_10_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_10_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_10_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_10_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_10_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_10_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_10_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_10_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_10_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_3_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_3_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_3_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_3_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_3_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_3_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_3_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_3_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_3_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_3_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_3_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_3_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_3_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_3_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_3_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_10_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_161( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module MacUnit_157( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /** Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. */ class ClientMetadata extends Bundle { /** Actual state information stored in this bundle */ val state = UInt(ClientStates.width.W) /** Metadata equality */ def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /** Is the block's data present in this cache */ def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /** Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) */ private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /** Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). */ private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd || param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /** Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). */ def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /** Does a secondary miss on the block require another Acquire message */ def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /** Metadata change on a returned Grant */ def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /** Determine what state to go to based on Probe param */ private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /** Translate cache control cmds into Probe param */ private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /** Factories for ClientMetadata, including on reset */ object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways * (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) | wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /** @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined || nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined || nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits * nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBits*rowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /** Bundle definitions for HellaCache interfaces */ trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /** Base classes for Diplomatic TL2 HellaCaches */ abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM || cfg.blockBytes * cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated */ case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /** Mix-ins for constructing tiles that have a HellaCache */ trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /** Metadata array used for all HellaCaches */ class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst || (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst || (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst || io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst } File ECC.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR abstract class Decoding { def uncorrected: UInt def corrected: UInt def correctable: Bool def uncorrectable: Bool // If true, correctable should be ignored def error = correctable || uncorrectable } abstract class Code { def canDetect: Boolean def canCorrect: Boolean def width(w0: Int): Int /** Takes the unencoded width and returns a list of indices indicating which * bits of the encoded value will be used for ecc */ def eccIndices(width: Int): Seq[Int] /** Encode x to a codeword suitable for decode. * If poison is true, the decoded value will report uncorrectable * error despite uncorrected == corrected == x. */ def encode(x: UInt, poison: Bool = false.B): UInt def decode(x: UInt): Decoding /** Copy the bits in x to the right bit positions in an encoded word, * so that x === decode(swizzle(x)).uncorrected; but don't generate * the other code bits, so decode(swizzle(x)).error might be true. * For codes for which this operation is not trivial, throw an * UnsupportedOperationException. */ def swizzle(x: UInt): UInt } class IdentityCode extends Code { def canDetect = false def canCorrect = false def width(w0: Int) = w0 def eccIndices(width: Int) = Seq.empty[Int] def encode(x: UInt, poison: Bool = false.B) = { require (poison.isLit && poison.litValue == 0, "IdentityCode can not be poisoned") x } def swizzle(x: UInt) = x def decode(y: UInt) = new Decoding { def uncorrected = y def corrected = y def correctable = false.B def uncorrectable = false.B } } class ParityCode extends Code { def canDetect = true def canCorrect = false def width(w0: Int) = w0+1 def eccIndices(w0: Int) = Seq(w0) def encode(x: UInt, poison: Bool = false.B) = Cat(x.xorR ^ poison, x) def swizzle(x: UInt) = Cat(false.B, x) def decode(y: UInt) = new Decoding { val uncorrected = y(y.getWidth-2,0) val corrected = uncorrected val correctable = false.B val uncorrectable = y.xorR } } class SECCode extends Code { def canDetect = true def canCorrect = true // SEC codes may or may not be poisonous depending on the length // If the code is perfect, every non-codeword is correctable def poisonous(n: Int) = !isPow2(n+1) def width(k: Int) = { val m = log2Floor(k) + 1 k + m + (if((1 << m) < m+k+1) 1 else 0) } def eccIndices(w0: Int) = { (0 until width(w0)).collect { case i if i >= w0 => i } } def swizzle(x: UInt) = { val k = x.getWidth val n = width(k) Cat(0.U((n-k).W), x) } // An (n=16, k=11) Hamming code is naturally encoded as: // PPxPxxxPxxxxxxxP where P are parity bits and x are data // Indexes typically start at 1, because then the P are on powers of two // In systematic coding, you put all the data in the front: // xxxxxxxxxxxPPPPP // Indexes typically start at 0, because Computer Science // For sanity when reading SRAMs, you want systematic form. private def impl(n: Int, k: Int) = { require (n >= 3 && k >= 1 && !isPow2(n)) val hamm2sys = IndexedSeq.tabulate(n+1) { i => if (i == 0) { n /* undefined */ } else if (isPow2(i)) { k + log2Ceil(i) } else { i - 1 - log2Ceil(i) } } val sys2hamm = hamm2sys.zipWithIndex.sortBy(_._1).map(_._2).toIndexedSeq def syndrome(j: Int) = { val bit = 1 << j ("b" + Seq.tabulate(n) { i => if ((sys2hamm(i) & bit) != 0) "1" else "0" }.reverse.mkString).U } (hamm2sys, sys2hamm, syndrome _) } def encode(x: UInt, poison: Bool = false.B) = { val k = x.getWidth val n = width(k) val (_, _, syndrome) = impl(n, k) require ((poison.isLit && poison.litValue == 0) || poisonous(n), s"SEC code of length ${n} cannot be poisoned") /* By setting the entire syndrome on poison, the corrected bit falls off the end of the code */ val syndromeUInt = VecInit.tabulate(n-k) { j => (syndrome(j)(k-1, 0) & x).xorR ^ poison }.asUInt Cat(syndromeUInt, x) } def decode(y: UInt) = new Decoding { val n = y.getWidth val k = n - log2Ceil(n) val (_, sys2hamm, syndrome) = impl(n, k) val syndromeUInt = VecInit.tabulate(n-k) { j => (syndrome(j) & y).xorR }.asUInt val hammBadBitOH = UIntToOH(syndromeUInt, n+1) val sysBadBitOH = VecInit.tabulate(k) { i => hammBadBitOH(sys2hamm(i)) }.asUInt val uncorrected = y(k-1, 0) val corrected = uncorrected ^ sysBadBitOH val correctable = syndromeUInt.orR val uncorrectable = if (poisonous(n)) { syndromeUInt > n.U } else { false.B } } } class SECDEDCode extends Code { def canDetect = true def canCorrect = true private val sec = new SECCode private val par = new ParityCode def width(k: Int) = sec.width(k)+1 def eccIndices(w0: Int) = { (0 until width(w0)).collect { case i if i >= w0 => i } } def encode(x: UInt, poison: Bool = false.B) = { // toggling two bits ensures the error is uncorrectable // to ensure corrected == uncorrected, we pick one redundant // bit from SEC (the highest); correcting it does not affect // corrected == uncorrected. the second toggled bit is the // parity bit, which also does not appear in the decoding val toggle_lo = Cat(poison.asUInt, poison.asUInt) val toggle_hi = toggle_lo << (sec.width(x.getWidth)-1) par.encode(sec.encode(x)) ^ toggle_hi } def swizzle(x: UInt) = par.swizzle(sec.swizzle(x)) def decode(x: UInt) = new Decoding { val secdec = sec.decode(x(x.getWidth-2,0)) val pardec = par.decode(x) val uncorrected = secdec.uncorrected val corrected = secdec.corrected val correctable = pardec.uncorrectable val uncorrectable = !pardec.uncorrectable && secdec.correctable } } object ErrGen { // generate a 1-bit error with approximate probability 2^-f def apply(width: Int, f: Int): UInt = { require(width > 0 && f >= 0 && log2Up(width) + f <= 16) UIntToOH(LFSR(16)(log2Up(width)+f-1,0))(width-1,0) } def apply(x: UInt, f: Int): UInt = x ^ apply(x.getWidth, f) } trait CanHaveErrors extends Bundle { val correctable: Option[ValidIO[UInt]] val uncorrectable: Option[ValidIO[UInt]] } case class ECCParams( bytes: Int = 1, code: Code = new IdentityCode, notifyErrors: Boolean = false, ) object Code { def fromString(s: Option[String]): Code = fromString(s.getOrElse("none")) def fromString(s: String): Code = s.toLowerCase match { case "none" => new IdentityCode case "identity" => new IdentityCode case "parity" => new ParityCode case "sec" => new SECCode case "secded" => new SECDEDCode case _ => throw new IllegalArgumentException("Unknown ECC type") } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class ECCTest(k: Int, timeout: Int = 500000) extends UnitTest(timeout) { val code = new SECDEDCode val n = code.width(k) // Brute force the decode space val test = RegInit(0.U((n+1).W)) val last = test(n) test := test + !last io.finished := RegNext(last, false.B) // Confirm the decoding matches the encoding val decoded = code.decode(test(n-1, 0)) val recoded = code.encode(decoded.corrected) val distance = PopCount(recoded ^ test) // Count the cases val correct = RegInit(0.U(n.W)) val correctable = RegInit(0.U(n.W)) val uncorrectable = RegInit(0.U(n.W)) when (!last) { when (decoded.uncorrectable) { assert (distance >= 2.U) // uncorrectable uncorrectable := uncorrectable + 1.U } .elsewhen (decoded.correctable) { assert (distance(0)) // correctable => odd bit errors correctable := correctable + 1.U } .otherwise { assert (distance === 0.U) // correct assert (decoded.uncorrected === decoded.corrected) correct := correct + 1.U } } // Expected number of each case val nCodes = BigInt(1) << n val nCorrect = BigInt(1) << k val nCorrectable = nCodes / 2 val nUncorrectable = nCodes - nCorrectable - nCorrect when (last) { assert (correct === nCorrect.U) assert (correctable === nCorrectable.U) assert (uncorrectable === nUncorrectable.U) } } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File TLB.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps case object ASIdBits extends Field[Int](0) case object VMIdBits extends Field[Int](0) /** =SFENCE= * rs1 rs2 * {{{ * 0 0 -> flush All * 0 1 -> flush by ASID * 1 1 -> flush by ADDR * 1 0 -> flush by ADDR and ASID * }}} * {{{ * If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. * If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered. * If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces. * If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. * }}} */ class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) { val rs1 = Bool() val rs2 = Bool() val addr = UInt(vaddrBits.W) val asid = UInt((asIdBits max 1).W) // TODO zero-width val hv = Bool() val hg = Bool() } class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) { /** request address from CPU. */ val vaddr = UInt(vaddrBitsExtended.W) /** don't lookup TLB, bypass vaddr as paddr */ val passthrough = Bool() /** granularity */ val size = UInt(log2Ceil(lgMaxSize + 1).W) /** memory command. */ val cmd = Bits(M_SZ.W) val prv = UInt(PRV.SZ.W) /** virtualization mode */ val v = Bool() } class TLBExceptions extends Bundle { val ld = Bool() val st = Bool() val inst = Bool() } class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) { // lookup responses val miss = Bool() /** physical address */ val paddr = UInt(paddrBits.W) val gpa = UInt(vaddrBitsExtended.W) val gpa_is_pte = Bool() /** page fault exception */ val pf = new TLBExceptions /** guest page fault exception */ val gf = new TLBExceptions /** access exception */ val ae = new TLBExceptions /** misaligned access exception */ val ma = new TLBExceptions /** if this address is cacheable */ val cacheable = Bool() /** if caches must allocate this address */ val must_alloc = Bool() /** if this address is prefetchable for caches*/ val prefetchable = Bool() /** size/cmd of request that generated this response*/ val size = UInt(log2Ceil(lgMaxSize + 1).W) val cmd = UInt(M_SZ.W) } class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) { val ppn = UInt(ppnBits.W) /** pte.u user */ val u = Bool() /** pte.g global */ val g = Bool() /** access exception. * D$ -> PTW -> TLB AE * Alignment failed. */ val ae_ptw = Bool() val ae_final = Bool() val ae_stage2 = Bool() /** page fault */ val pf = Bool() /** guest page fault */ val gf = Bool() /** supervisor write */ val sw = Bool() /** supervisor execute */ val sx = Bool() /** supervisor read */ val sr = Bool() /** hypervisor write */ val hw = Bool() /** hypervisor excute */ val hx = Bool() /** hypervisor read */ val hr = Bool() /** prot_w */ val pw = Bool() /** prot_x */ val px = Bool() /** prot_r */ val pr = Bool() /** PutPartial */ val ppp = Bool() /** AMO logical */ val pal = Bool() /** AMO arithmetic */ val paa = Bool() /** get/put effects */ val eff = Bool() /** cacheable */ val c = Bool() /** fragmented_superpage support */ val fragmented_superpage = Bool() } /** basic cell for TLB data */ class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) { require(nSectors == 1 || !superpage) require(!superpageOnly || superpage) val level = UInt(log2Ceil(pgLevels).W) /** use vpn as tag */ val tag_vpn = UInt(vpnBits.W) /** tag in vitualization mode */ val tag_v = Bool() /** entry data */ val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W)) /** valid bit */ val valid = Vec(nSectors, Bool()) /** returns all entry data in this entry */ def entry_data = data.map(_.asTypeOf(new TLBEntryData)) /** returns the index of sector */ private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0) /** returns the entry data matched with this vpn*/ def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData)) /** returns whether a sector hits */ def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual) /** returns whether tag matches vpn */ def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual) /** returns hit signal */ def hit(vpn: UInt, virtual: Bool): Bool = { if (superpage && usingVM) { var tagMatch = valid.head && (tag_v === virtual) for (j <- 0 until pgLevels) { val base = (pgLevels - 1 - j) * pgLevelBits val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0) val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B tagMatch = tagMatch && (ignore || (tag_vpn ^ vpn)(base + n - 1, base) === 0.U) } tagMatch } else { val idx = sectorIdx(vpn) valid(idx) && sectorTagMatch(vpn, virtual) } } /** returns the ppn of the input TLBEntryData */ def ppn(vpn: UInt, data: TLBEntryData) = { val supervisorVPNBits = pgLevels * pgLevelBits if (superpage && usingVM) { var res = data.ppn >> pgLevelBits*(pgLevels - 1) for (j <- 1 until pgLevels) { val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B res = Cat(res, (Mux(ignore, vpn, 0.U) | data.ppn)(supervisorVPNBits - j*pgLevelBits - 1, supervisorVPNBits - (j + 1)*pgLevelBits)) } res } else { data.ppn } } /** does the refill * * find the target entry with vpn tag * and replace the target entry with the input entry data */ def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = { this.tag_vpn := vpn this.tag_v := virtual this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0) val idx = sectorIdx(vpn) valid(idx) := true.B data(idx) := entry.asUInt } def invalidate(): Unit = { valid.foreach(_ := false.B) } def invalidate(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual) { v := false.B } } def invalidateVPN(vpn: UInt, virtual: Bool): Unit = { if (superpage) { when (hit(vpn, virtual)) { invalidate() } } else { when (sectorTagMatch(vpn, virtual)) { for (((v, e), i) <- (valid zip entry_data).zipWithIndex) when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B } } } // For fragmented superpage mappings, we assume the worst (largest) // case, and zap entries whose most-significant VPNs match when (((tag_vpn ^ vpn) >> (pgLevelBits * (pgLevels - 1))) === 0.U) { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && e.fragmented_superpage) { v := false.B } } } def invalidateNonGlobal(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && !e.g) { v := false.B } } } /** TLB config * * @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]] * @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]] * @param nSectors the number of ways in a single PTE TLBEntry * @param nSuperpageEntries the number of SuperpageEntries */ case class TLBConfig( nSets: Int, nWays: Int, nSectors: Int = 4, nSuperpageEntries: Int = 4) /** =Overview= * [[TLB]] is a TLB template which contains PMA logic and PMP checker. * * TLB caches PTE and accelerates the address translation process. * When tlb miss happens, ask PTW(L2TLB) for Page Table Walk. * Perform PMP and PMA check during the translation and throw exception if there were any. * * ==Cache Structure== * - Sectored Entry (PTE) * - set-associative or direct-mapped * - nsets = [[TLBConfig.nSets]] * - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]] * - PTEEntry( sectors = [[TLBConfig.nSectors]] ) * - LRU(if set-associative) * * - Superpage Entry(superpage PTE) * - fully associative * - nsets = [[TLBConfig.nSuperpageEntries]] * - PTEEntry(sectors = 1) * - PseudoLRU * * - Special Entry(PTE across PMP) * - nsets = 1 * - PTEEntry(sectors = 1) * * ==Address structure== * {{{ * |vaddr | * |ppn/vpn | pgIndex | * | | | * | |nSets |nSector | |}}} * * ==State Machine== * {{{ * s_ready: ready to accept request from CPU. * s_request: when L1TLB(this) miss, send request to PTW(L2TLB), . * s_wait: wait for PTW to refill L1TLB. * s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}} * * ==PMP== * pmp check * - special_entry: always check * - other entry: check on refill * * ==Note== * PMA consume diplomacy parameter generate physical memory address checking logic * * Boom use Rocket ITLB, and its own DTLB. * * Accelerators:{{{ * sha3: DTLB * gemmini: DTLB * hwacha: DTLB*2+ITLB}}} * @param instruction true for ITLB, false for DTLB * @param lgMaxSize @todo seems granularity * @param cfg [[TLBConfig]] * @param edge collect SoC metadata. */ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { override def desiredName = if (instruction) "ITLB" else "DTLB" val io = IO(new Bundle { /** request from Core */ val req = Flipped(Decoupled(new TLBReq(lgMaxSize))) /** response to Core */ val resp = Output(new TLBResp(lgMaxSize)) /** SFence Input */ val sfence = Flipped(Valid(new SFenceReq)) /** IO to PTW */ val ptw = new TLBPTWIO /** suppress a TLB refill, one cycle after a miss */ val kill = Input(Bool()) }) io.ptw.customCSRs := DontCare val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits) /** index for sectored_Entry */ val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) /** TLB Entry */ val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false)))) /** Superpage Entry */ val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true))) /** Special Entry * * If PMP granularity is less than page size, thus need additional "special" entry manage PMP. */ val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false))) def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries def all_entries = ordinary_entries ++ special_entry def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) val state = RegInit(s_ready) // use vpn as refill_tag val r_refill_tag = Reg(UInt(vpnBits.W)) val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W)) val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W)) val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W))) val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W))) val r_vstage1_en = Reg(Bool()) val r_stage2_en = Reg(Bool()) val r_need_gpa = Reg(Bool()) val r_gpa_valid = Reg(Bool()) val r_gpa = Reg(UInt(vaddrBits.W)) val r_gpa_vpn = Reg(UInt(vpnBits.W)) val r_gpa_is_pte = Reg(Bool()) /** privilege mode */ val priv = io.req.bits.prv val priv_v = usingHypervisor.B && io.req.bits.v val priv_s = priv(0) // user mode and supervisor mode val priv_uses_vm = priv <= PRV.S.U val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1) /** VS-stage translation enable */ val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1) /** G-stage translation enable */ val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1) /** Enable Virtual Memory when: * 1. statically configured * 1. satp highest bits enabled * i. RV32: * - 0 -> Bare * - 1 -> SV32 * i. RV64: * - 0000 -> Bare * - 1000 -> SV39 * - 1001 -> SV48 * - 1010 -> SV57 * - 1011 -> SV64 * 1. In virtualization mode, vsatp highest bits enabled * 1. priv mode in U and S. * 1. in H & M mode, disable VM. * 1. no passthrough(micro-arch defined.) * * @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register * @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp) */ val vm_enabled = (stage1_en || stage2_en) && priv_uses_vm && !io.req.bits.passthrough // flush guest entries on vsatp.MODE Bare <-> SvXX transitions val v_entries_use_stage1 = RegInit(false.B) val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough // share a single physical memory attribute checker (unshare if critical path) val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0) /** refill signal */ val do_refill = usingVM.B && io.ptw.resp.valid /** sfence invalidate refill */ val invalidate_refill = state.isOneOf(s_request /* don't care */, s_wait_invalidate) || io.sfence.valid // PMP val mpu_ppn = Mux(do_refill, refill_ppn, Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits)) val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) val mpu_priv = Mux[UInt](usingVM.B && (do_refill || io.req.bits.passthrough /* PTW */), PRV.S.U, Cat(io.ptw.status.debug, priv)) val pmp = Module(new PMPChecker(lgMaxSize)) pmp.io.addr := mpu_physaddr pmp.io.size := io.req.bits.size pmp.io.pmp := (io.ptw.pmp: Seq[PMP]) pmp.io.prv := mpu_priv val pma = Module(new PMAChecker(edge.manager)(p)) pma.io.paddr := mpu_physaddr // todo: using DataScratchpad doesn't support cacheable. val cacheable = pma.io.resp.cacheable && (instruction || !usingDataScratchpad).B val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous // In M mode, if access DM address(debug module program buffer) val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B) val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w val prot_pp = pma.io.resp.pp val prot_al = pma.io.resp.al val prot_aa = pma.io.resp.aa val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x val prot_eff = pma.io.resp.eff // hit check val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v)) val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v)) val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v)) val real_hits = hitsVec.asUInt val hits = Cat(!vm_enabled, real_hits) // use ptw response to refill // permission bit arrays when (do_refill) { val pte = io.ptw.resp.bits.pte val refill_v = r_vstage1_en || r_stage2_en val newEntry = Wire(new TLBEntryData) newEntry.ppn := pte.ppn newEntry.c := cacheable newEntry.u := pte.u newEntry.g := pte.g && pte.v newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw newEntry.ae_final := io.ptw.resp.bits.ae_final newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en newEntry.pf := io.ptw.resp.bits.pf newEntry.gf := io.ptw.resp.bits.gf newEntry.hr := io.ptw.resp.bits.hr newEntry.hw := io.ptw.resp.bits.hw newEntry.hx := io.ptw.resp.bits.hx newEntry.sr := pte.sr() newEntry.sw := pte.sw() newEntry.sx := pte.sx() newEntry.pr := prot_r newEntry.pw := prot_w newEntry.px := prot_x newEntry.ppp := prot_pp newEntry.pal := prot_al newEntry.paa := prot_aa newEntry.eff := prot_eff newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage // refill special_entry when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) { special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)) }.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) { val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr) for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) { e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry) when (invalidate_refill) { e.invalidate() } } // refill sectored_hit }.otherwise { val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) { when (!r_sectored_hit.valid) { e.invalidate() } e.insert(r_refill_tag, refill_v, 0.U, newEntry) when (invalidate_refill) { e.invalidate() } } } r_gpa_valid := io.ptw.resp.bits.gpa.valid r_gpa := io.ptw.resp.bits.gpa.bits r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte } // get all entries data. val entries = all_entries.map(_.getData(vpn)) val normal_entries = entries.take(ordinary_entries.size) // parallel query PPN from [[all_entries]], if VM not enabled return VPN instead val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0)) val nPhysicalEntries = 1 + special_entry.size // generally PTW misaligned load exception. val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt) val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt) val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt) val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt) val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) // if in hypervisor/machine mode, cannot read/write user entries. // if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)" val priv_rw_ok = Mux(!priv_s || sum, entries.map(_.u).asUInt, 0.U) | Mux(priv_s, ~entries.map(_.u).asUInt, 0.U) // if in hypervisor/machine mode, other than user pages, all pages are executable. // if in superviosr/user mode, only user page can execute. val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt) val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) | entries.map(_.ae_stage2).asUInt) val mxr = io.ptw.status.mxr | Mux(priv_v, io.ptw.gstatus.mxr, false.B) // "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)" val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt | Mux(mxr, entries.map(_.sx).asUInt, 0.U))) | stage1_bypass) val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) | stage1_bypass) val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) | stage1_bypass) val stage2_bypass = Fill(entries.size, !stage2_en) val hr_array = Cat(true.B, entries.map(_.hr).asUInt | Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) | stage2_bypass) val hw_array = Cat(true.B, entries.map(_.hw).asUInt | stage2_bypass) val hx_array = Cat(true.B, entries.map(_.hx).asUInt | stage2_bypass) // These array is for each TLB entries. // user mode can read: PMA OK, TLB OK, AE OK val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array | final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array | final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array | final_ae_array) // put effect val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt) // cacheable val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt) // put partial val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt) // atomic arithmetic val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt) // atomic logic val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt) val ppp_array_if_cached = ppp_array | c_array val paa_array_if_cached = paa_array | (if(usingAtomicsInCache) c_array else 0.U) val pal_array_if_cached = pal_array | (if(usingAtomicsInCache) c_array else 0.U) val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt) // vaddr misaligned: vaddr[1:0]=b00 val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR def badVA(guestPA: Boolean): Bool = { val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels val extraBits = if (guestPA) hypervisorExtraAddrBits else 0 val signed = !guestPA val nPgLevelChoices = pgLevels - minPgLevels + 1 val minVAddrBits = pgIdxBits + minPgLevels * pgLevelBits + extraBits (for (i <- 0 until nPgLevelChoices) yield { val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U val maskedVAddr = io.req.bits.vaddr & mask additionalPgLevels === i.U && !(maskedVAddr === 0.U || signed.B && maskedVAddr === mask) }).orR } val bad_gpa = if (!usingHypervisor) false.B else vm_enabled && !stage1_en && badVA(true) val bad_va = if (!usingVM || (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B else vm_enabled && stage1_en && badVA(false) val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC) val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd) val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd) val cmd_put_partial = io.req.bits.cmd === M_PWR val cmd_read = isRead(io.req.bits.cmd) val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX val cmd_write = isWrite(io.req.bits.cmd) val cmd_write_perms = cmd_write || io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions val lrscAllowed = Mux((usingDataScratchpad || usingAtomicsOnlyForIO).B, 0.U, c_array) val ae_array = Mux(misaligned, eff_array, 0.U) | Mux(cmd_lrsc, ~lrscAllowed, 0.U) // access exception needs SoC information from PMA val ae_ld_array = Mux(cmd_read, ae_array | ~pr_array, 0.U) val ae_st_array = Mux(cmd_write_perms, ae_array | ~pw_array, 0.U) | Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) | Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) | Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U) val must_alloc_array = Mux(cmd_put_partial, ~ppp_array, 0.U) | Mux(cmd_amo_logical, ~pal_array, 0.U) | Mux(cmd_amo_arithmetic, ~paa_array, 0.U) | Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U) val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_inst_array = ((~x_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) | ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array | ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_inst_array = Mux(priv_v, (~hx_array | ptw_gf_array) & ~ptw_ae_array, 0.U) val gpa_hits = { val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array | gf_st_array val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) | Fill(all_entries.size, !vstage1_en) hit_mask | ~need_gpa_mask(all_entries.size-1, 0) } val tlb_hit_if_not_gpa_miss = real_hits.orR val tlb_hit = (real_hits & gpa_hits).orR // leads to s_request val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru") val superpage_plru = new PseudoLRU(superpage_entries.size) when (io.req.valid && vm_enabled) { // replace when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) } when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) } } // Superpages create the possibility that two entries in the TLB may match. // This corresponds to a software bug, but we can't return complete garbage; // we must return either the old translation or the new translation. This // isn't compatible with the Mux1H approach. So, flush the TLB and report // a miss on duplicate entries. val multipleHits = PopCountAtLeast(real_hits, 2) // only pull up req.ready when this is s_ready state. io.req.ready := state === s_ready // page fault io.resp.pf.ld := (bad_va && cmd_read) || (pf_ld_array & hits).orR io.resp.pf.st := (bad_va && cmd_write_perms) || (pf_st_array & hits).orR io.resp.pf.inst := bad_va || (pf_inst_array & hits).orR // guest page fault io.resp.gf.ld := (bad_gpa && cmd_read) || (gf_ld_array & hits).orR io.resp.gf.st := (bad_gpa && cmd_write_perms) || (gf_st_array & hits).orR io.resp.gf.inst := bad_gpa || (gf_inst_array & hits).orR // access exception io.resp.ae.ld := (ae_ld_array & hits).orR io.resp.ae.st := (ae_st_array & hits).orR io.resp.ae.inst := (~px_array & hits).orR // misaligned io.resp.ma.ld := misaligned && cmd_read io.resp.ma.st := misaligned && cmd_write io.resp.ma.inst := false.B // this is up to the pipeline to figure out io.resp.cacheable := (c_array & hits).orR io.resp.must_alloc := (must_alloc_array & hits).orR io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB || m.supportsHint).B io.resp.miss := do_refill || vsatp_mode_mismatch || tlb_miss || multipleHits io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) io.resp.size := io.req.bits.size io.resp.cmd := io.req.bits.cmd io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte io.resp.gpa := { val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits) val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0)) Cat(page, offset) } io.ptw.req.valid := state === s_request io.ptw.req.bits.valid := !io.kill io.ptw.req.bits.bits.addr := r_refill_tag io.ptw.req.bits.bits.vstage1 := r_vstage1_en io.ptw.req.bits.bits.stage2 := r_stage2_en io.ptw.req.bits.bits.need_gpa := r_need_gpa if (usingVM) { when(io.ptw.req.fire && io.ptw.req.bits.valid) { r_gpa_valid := false.B r_gpa_vpn := r_refill_tag } val sfence = io.sfence.valid // this is [[s_ready]] // handle miss/hit at the first cycle. // if miss, request PTW(L2TLB). when (io.req.fire && tlb_miss) { state := s_request r_refill_tag := vpn r_need_gpa := tlb_hit_if_not_gpa_miss r_vstage1_en := vstage1_en r_stage2_en := stage2_en r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way) r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx)) r_sectored_hit.valid := sector_hits.orR r_sectored_hit.bits := OHToUInt(sector_hits) r_superpage_hit.valid := superpage_hits.orR r_superpage_hit.bits := OHToUInt(superpage_hits) } // Handle SFENCE.VMA when send request to PTW. // SFENCE.VMA io.ptw.req.ready kill // ? ? 1 // 0 0 0 // 0 1 0 -> s_wait // 1 0 0 -> s_wait_invalidate // 1 0 0 -> s_ready when (state === s_request) { // SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle. when (sfence) { state := s_ready } // here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B) // fire -> s_wait when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) } // If CPU kills request(frontend.s2_redirect) when (io.kill) { state := s_ready } } // sfence in refill will results in invalidate when (state === s_wait && sfence) { state := s_wait_invalidate } // after CPU acquire response, go back to s_ready. when (io.ptw.resp.valid) { state := s_ready } // SFENCE processing logic. when (sfence) { assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn) for (e <- all_real_entries) { val hv = usingHypervisor.B && io.sfence.bits.hv val hg = usingHypervisor.B && io.sfence.bits.hg when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) } .elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) } .otherwise { e.invalidate(hv || hg) } } } when(io.req.fire && vsatp_mode_mismatch) { all_real_entries.foreach(_.invalidate(true.B)) v_entries_use_stage1 := vstage1_en } when (multipleHits || reset.asBool) { all_real_entries.foreach(_.invalidate()) } ccover(io.ptw.req.fire, "MISS", "TLB miss") ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy") ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill") ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB") ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID") ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line") ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID") ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc) /** Decides which entry to be replaced * * If there is a invalid entry, replace it with priorityencoder; * if not, replace the alt entry * * @return mask for TLBEntry replacement */ def replacementEntry(set: Seq[TLBEntry], alt: UInt) = { val valids = set.map(_.valid.orR).asUInt Mux(valids.andR, alt, PriorityEncoder(~valids)) } } File TLBPermissions.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined r: Bool, // readable w: Bool, // writeable x: Bool, // executable c: Bool, // cacheable a: Bool, // arithmetic ops l: Bool) // logical ops object TLBPageLookup { private case class TLBFixedPermissions( e: Boolean, // get-/put-effects r: Boolean, // readable w: Boolean, // writeable x: Boolean, // executable c: Boolean, // cacheable a: Boolean, // arithmetic ops l: Boolean) { // logical ops val useful = r || w || x || c || a || l } private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = { val permissions = managers.map { m => (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, r = m.supportsGet || m.supportsAcquireB, // if cached, never uses Get w = m.supportsPutFull || m.supportsAcquireT, // if cached, never uses Put x = m.executable, c = m.supportsAcquireB, a = m.supportsArithmetic, l = m.supportsLogical)) } permissions .filter(_._2.useful) // get rid of no-permission devices .groupBy(_._2) // group by permission type .mapValues(seq => AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions .toMap } // Unmapped memory is considered to be inhomogeneous def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = { require (isPow2(xLen) && xLen >= 8) require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8) require (isPow2(pageSize) && pageSize >= cacheBlockBytes) val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes) val allSizes = TransferSizes(1, maxRequestBytes) val amoSizes = TransferSizes(4, xLen/8) val permissions = managers.foreach { m => require (!m.supportsGet || m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}") require (!m.supportsPutFull || m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") require (!m.supportsPutPartial || m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}") require (!m.supportsAcquireB || m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}") require (!m.supportsAcquireT || m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers) .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = { val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) } val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList) // Find the minimal bits needed to distinguish between yes and no val decisionMask = AddressDecoder(Seq(yes, no)) def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct) val (yesf, nof) = (simplify(yes), simplify(no)) if (yesf.size < no.size) { (x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ || _) } else { (x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ || _) } } // Derive simplified property circuits (don't care when !homo) val rfn = lowCostProperty(_.r) val wfn = lowCostProperty(_.w) val xfn = lowCostProperty(_.x) val cfn = lowCostProperty(_.c) val afn = lowCostProperty(_.a) val lfn = lowCostProperty(_.l) val homo = AddressSet.unify(grouped.values.flatten.toList) (x: UInt) => TLBPermissions( homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ || _), r = rfn(x), w = wfn(x), x = xfn(x), c = cfn(x), a = afn(x), l = lfn(x)) } // Are all pageSize intervals of mapped regions homogeneous? def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = { groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize)) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /** PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss */ class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /** PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info */ class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /** ptw access exception */ val ae_ptw = Bool() /** final access exception */ val ae_final = Bool() /** page fault */ val pf = Bool() /** guest page fault */ val gf = Bool() /** hypervisor read */ val hr = Bool() /** hypervisor write */ val hw = Bool() /** hypervisor execute */ val hx = Bool() /** PTE to refill L1TLB * * source: L2TLB */ val pte = new PTE /** pte pglevel */ val level = UInt(log2Ceil(pgLevels).W) /** fragmented_superpage support */ val fragmented_superpage = Bool() /** homogeneous for both pma and pmp */ val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /** IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) */ class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /** PTW performance statistics */ class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /** Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core */ class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /** enable clock generated by ptw */ val clock_enabled = Output(Bool()) } /** PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format */ class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** global mapping */ val g = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() /** valid bit */ val v = Bool() /** return true if find a pointer to next level page table */ def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /** return true if find a leaf PTE */ def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a /** user read */ def ur(dummy: Int = 0) = sr() && u /** user write*/ def uw(dummy: Int = 0) = sw() && u /** user execute */ def ux(dummy: Int = 0) = sx() && u /** supervisor read */ def sr(dummy: Int = 0) = leaf() && r /** supervisor write */ def sw(dummy: Int = 0) = leaf() && w && d /** supervisor execute */ def sx(dummy: Int = 0) = leaf() && x /** full permission: writable and executable in user mode */ def isFullPerm(dummy: Int = 0) = uw() && ux() } /** L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format */ class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() } /** PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation */ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /** to n TLB */ val requestor = Flipped(Vec(n, new TLBPTWIO)) /** to HellaCache */ val mem = new HellaCacheIO /** to Core * * contains CSRs info and performance statistics */ val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /** Arbiter to arbite request from n TLB */ val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready || l2_refill_wire || arb.io.out.valid || io.dpath.sfence.valid || io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM || !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /** current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} */ val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /** tlb request */ val r_req = Reg(new PTWReq) /** current selected way in arbitor */ val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /** pte for 2-stage translation */ val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /** 2-stage translation both enable */ val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r || tmp.w || tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /** address send to mem for enquerry */ val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) * pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) | vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr */ val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) * pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBits*i), r_req.addr(((pgLevelBits*i) min vpnBits)-1, 0).padTo(pgLevelBits*i))) } /** PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation */ def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid | UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 || usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /** the valid vec for the selected set(including n ways) */ val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) | mask g(way) := Mux(r_pte.g, g(way) | mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) || s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid || (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req || state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit || (state =/= s_wait1) || resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor || pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous || pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final || !r_req.vstage1 || aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)*pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), aux_pte.ppn((pgLevels-i-1)*pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req || state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 || do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages || aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf || (pf && stage2) resp_hr := !stage2 || (!pf && !gf && pte.ur()) resp_hw := !stage2 || (!pf && !gf && pte.uw()) resp_hx := !stage2 || (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), r_req.addr(((pgLevels-i-1)*pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)*pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn */ private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /** use hgatp and vpn to construct a new ppn */ private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)*pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range */ private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)*pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW */ trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File DCache.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.amba.AMBAProt import freechips.rocketchip.diplomacy.{BufferParams} import freechips.rocketchip.prci.{ClockCrossingType, RationalCrossing, SynchronousCrossing, AsynchronousCrossing, CreditedCrossing} import freechips.rocketchip.tile.{CoreBundle, LookupByHartId} import freechips.rocketchip.tilelink.{TLFIFOFixer,ClientMetadata, TLBundleA, TLAtomics, TLBundleB, TLPermissions} import freechips.rocketchip.tilelink.TLMessages.{AccessAck, HintAck, AccessAckData, Grant, GrantData, ReleaseAck} import freechips.rocketchip.util.{CanHaveErrors, ClockGate, IdentityCode, ReplacementPolicy, DescribedSRAM, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps // TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits trait InlineInstance { self: chisel3.experimental.BaseModule => chisel3.experimental.annotate( new chisel3.experimental.ChiselAnnotation { def toFirrtl: firrtl.annotations.Annotation = firrtl.passes.InlineAnnotation(self.toNamed) } ) } class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p) with CanHaveErrors { val correctable = (cacheParams.tagCode.canCorrect || cacheParams.dataCode.canCorrect).option(Valid(UInt(paddrBits.W))) val uncorrectable = (cacheParams.tagCode.canDetect || cacheParams.dataCode.canDetect).option(Valid(UInt(paddrBits.W))) val bus = Valid(UInt(paddrBits.W)) } class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val addr = UInt(untagBits.W) val write = Bool() val wdata = UInt((encBits * rowBytes / eccBytes).W) val wordMask = UInt((rowBytes / subWordBytes).W) val eccMask = UInt((wordBytes / eccBytes).W) val way_en = UInt(nWays.W) } class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Valid(new DCacheDataReq)) val resp = Output(Vec(nWays, UInt((req.bits.wdata.getWidth).W))) }) require(rowBits % subWordBits == 0, "rowBits must be a multiple of subWordBits") val eccMask = if (eccBits == subWordBits) Seq(true.B) else io.req.bits.eccMask.asBools val wMask = if (nWays == 1) eccMask else (0 until nWays).flatMap(i => eccMask.map(_ && io.req.bits.way_en(i))) val wWords = io.req.bits.wdata.grouped(encBits * (subWordBits / eccBits)) val addr = io.req.bits.addr >> rowOffBits val data_arrays = Seq.tabulate(rowBits / subWordBits) { i => DescribedSRAM( name = s"${tileParams.baseName}_dcache_data_arrays_${i}", desc = "DCache Data Array", size = nSets * cacheBlockBytes / rowBytes, data = Vec(nWays * (subWordBits / eccBits), UInt(encBits.W)) ) } val rdata = for ((array , i) <- data_arrays.zipWithIndex) yield { val valid = io.req.valid && ((data_arrays.size == 1).B || io.req.bits.wordMask(i)) when (valid && io.req.bits.write) { val wMaskSlice = (0 until wMask.size).filter(j => i % (wordBits/subWordBits) == (j % (wordBytes/eccBytes)) / (subWordBytes/eccBytes)).map(wMask(_)) val wData = wWords(i).grouped(encBits) array.write(addr, VecInit((0 until nWays).flatMap(i => wData)), wMaskSlice) } val data = array.read(addr, valid && !io.req.bits.write) data.grouped(subWordBits / eccBits).map(_.asUInt).toSeq } (io.resp zip rdata.transpose).foreach { case (resp, data) => resp := data.asUInt } } class DCacheMetadataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val write = Bool() val addr = UInt(vaddrBitsExtended.W) val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val data = UInt(cacheParams.tagCode.width(new L1Metadata().getWidth).W) } class DCache(staticIdForMetadataUseOnly: Int, val crossing: ClockCrossingType)(implicit p: Parameters) extends HellaCache(staticIdForMetadataUseOnly)(p) { override lazy val module = new DCacheModule(this) } class DCacheTLBPort(implicit p: Parameters) extends CoreBundle()(p) { val req = Flipped(Decoupled(new TLBReq(coreDataBytes.log2))) val s1_resp = Output(new TLBResp(coreDataBytes.log2)) val s2_kill = Input(Bool()) } class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val tECC = cacheParams.tagCode val dECC = cacheParams.dataCode require(subWordBits % eccBits == 0, "subWordBits must be a multiple of eccBits") require(eccBytes == 1 || !dECC.isInstanceOf[IdentityCode]) require(cacheParams.silentDrop || cacheParams.acquireBeforeRelease, "!silentDrop requires acquireBeforeRelease") val usingRMW = eccBytes > 1 || usingAtomicsInCache val mmioOffset = outer.firstMMIO edge.manager.requireFifo(TLFIFOFixer.allVolatile) // TileLink pipelining MMIO requests val clock_en_reg = Reg(Bool()) io.cpu.clock_enabled := clock_en_reg val gated_clock = if (!cacheParams.clockGate) clock else ClockGate(clock, clock_en_reg, "dcache_clock_gate") class DCacheModuleImpl { // entering gated-clock domain val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages))) val pma_checker = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages)) with InlineInstance) // tags val replacer = ReplacementPolicy.fromString(cacheParams.replacementPolicy, nWays) /** Metadata Arbiter: * 0: Tag update on reset * 1: Tag update on ECC error * 2: Tag update on hit * 3: Tag update on refill * 4: Tag update on release * 5: Tag update on flush * 6: Tag update on probe * 7: Tag update on CPU request */ val metaArb = Module(new Arbiter(new DCacheMetadataReq, 8) with InlineInstance) val tag_array = DescribedSRAM( name = s"${tileParams.baseName}_dcache_tag_array", desc = "DCache Tag Array", size = nSets, data = Vec(nWays, chiselTypeOf(metaArb.io.out.bits.data)) ) // data val data = Module(new DCacheDataArray) /** Data Arbiter * 0: data from pending store buffer * 1: data from TL-D refill * 2: release to TL-A * 3: hit path to CPU */ val dataArb = Module(new Arbiter(new DCacheDataReq, 4) with InlineInstance) dataArb.io.in.tail.foreach(_.bits.wdata := dataArb.io.in.head.bits.wdata) // tie off write ports by default data.io.req.bits <> dataArb.io.out.bits data.io.req.valid := dataArb.io.out.valid dataArb.io.out.ready := true.B metaArb.io.out.ready := clock_en_reg val tl_out_a = Wire(chiselTypeOf(tl_out.a)) tl_out.a <> { val a_queue_depth = outer.crossing match { case RationalCrossing(_) => // TODO make this depend on the actual ratio? if (cacheParams.separateUncachedResp) (maxUncachedInFlight + 1) / 2 else 2 min maxUncachedInFlight-1 case SynchronousCrossing(BufferParams.none) => 1 // Need some buffering to guarantee livelock freedom case SynchronousCrossing(_) => 0 // Adequate buffering within the crossing case _: AsynchronousCrossing => 0 // Adequate buffering within the crossing case _: CreditedCrossing => 0 // Adequate buffering within the crossing } Queue(tl_out_a, a_queue_depth, flow = true) } val (tl_out_c, release_queue_empty) = if (cacheParams.acquireBeforeRelease) { val q = Module(new Queue(chiselTypeOf(tl_out.c.bits), cacheDataBeats, flow = true)) tl_out.c <> q.io.deq (q.io.enq, q.io.count === 0.U) } else { (tl_out.c, true.B) } val s1_valid = RegNext(io.cpu.req.fire, false.B) val s1_probe = RegNext(tl_out.b.fire, false.B) val probe_bits = RegEnable(tl_out.b.bits, tl_out.b.fire) // TODO has data now :( val s1_nack = WireDefault(false.B) val s1_valid_masked = s1_valid && !io.cpu.s1_kill val s1_valid_not_nacked = s1_valid && !s1_nack val s1_tlb_req_valid = RegNext(io.tlb_port.req.fire, false.B) val s2_tlb_req_valid = RegNext(s1_tlb_req_valid, false.B) val s0_clk_en = metaArb.io.out.valid && !metaArb.io.out.bits.write val s0_req = WireInit(io.cpu.req.bits) s0_req.addr := Cat(metaArb.io.out.bits.addr >> blockOffBits, io.cpu.req.bits.addr(blockOffBits-1,0)) s0_req.idx.foreach(_ := Cat(metaArb.io.out.bits.idx, s0_req.addr(blockOffBits-1, 0))) when (!metaArb.io.in(7).ready) { s0_req.phys := true.B } val s1_req = RegEnable(s0_req, s0_clk_en) val s1_vaddr = Cat(s1_req.idx.getOrElse(s1_req.addr) >> tagLSB, s1_req.addr(tagLSB-1, 0)) val s0_tlb_req = WireInit(io.tlb_port.req.bits) when (!io.tlb_port.req.fire) { s0_tlb_req.passthrough := s0_req.phys s0_tlb_req.vaddr := s0_req.addr s0_tlb_req.size := s0_req.size s0_tlb_req.cmd := s0_req.cmd s0_tlb_req.prv := s0_req.dprv s0_tlb_req.v := s0_req.dv } val s1_tlb_req = RegEnable(s0_tlb_req, s0_clk_en || io.tlb_port.req.valid) val s1_read = isRead(s1_req.cmd) val s1_write = isWrite(s1_req.cmd) val s1_readwrite = s1_read || s1_write val s1_sfence = s1_req.cmd === M_SFENCE || s1_req.cmd === M_HFENCEV || s1_req.cmd === M_HFENCEG val s1_flush_line = s1_req.cmd === M_FLUSH_ALL && s1_req.size(0) val s1_flush_valid = Reg(Bool()) val s1_waw_hazard = Wire(Bool()) val s_ready :: s_voluntary_writeback :: s_probe_rep_dirty :: s_probe_rep_clean :: s_probe_retry :: s_probe_rep_miss :: s_voluntary_write_meta :: s_probe_write_meta :: s_dummy :: s_voluntary_release :: Nil = Enum(10) val supports_flush = outer.flushOnFenceI || coreParams.haveCFlush val flushed = RegInit(true.B) val flushing = RegInit(false.B) val flushing_req = Reg(chiselTypeOf(s1_req)) val cached_grant_wait = RegInit(false.B) val resetting = RegInit(false.B) val flushCounter = RegInit((nSets * (nWays-1)).U(log2Ceil(nSets * nWays).W)) val release_ack_wait = RegInit(false.B) val release_ack_addr = Reg(UInt(paddrBits.W)) val release_state = RegInit(s_ready) val refill_way = Reg(UInt()) val any_pstore_valid = Wire(Bool()) val inWriteback = release_state.isOneOf(s_voluntary_writeback, s_probe_rep_dirty) val releaseWay = Wire(UInt()) io.cpu.req.ready := (release_state === s_ready) && !cached_grant_wait && !s1_nack // I/O MSHRs val uncachedInFlight = RegInit(VecInit(Seq.fill(maxUncachedInFlight)(false.B))) val uncachedReqs = Reg(Vec(maxUncachedInFlight, new HellaCacheReq)) val uncachedResp = WireInit(new HellaCacheReq, DontCare) // hit initiation path val s0_read = isRead(io.cpu.req.bits.cmd) dataArb.io.in(3).valid := io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits) dataArb.io.in(3).bits := dataArb.io.in(1).bits dataArb.io.in(3).bits.write := false.B dataArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.idx.getOrElse(io.cpu.req.bits.addr) >> tagLSB, io.cpu.req.bits.addr(tagLSB-1, 0)) dataArb.io.in(3).bits.wordMask := { val mask = (subWordBytes.log2 until rowOffBits).foldLeft(1.U) { case (in, i) => val upper_mask = Mux((i >= wordBytes.log2).B || io.cpu.req.bits.size <= i.U, 0.U, ((BigInt(1) << (1 << (i - subWordBytes.log2)))-1).U) val upper = Mux(io.cpu.req.bits.addr(i), in, 0.U) | upper_mask val lower = Mux(io.cpu.req.bits.addr(i), 0.U, in) upper ## lower } Fill(subWordBytes / eccBytes, mask) } dataArb.io.in(3).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(3).bits.way_en := ~0.U(nWays.W) when (!dataArb.io.in(3).ready && s0_read) { io.cpu.req.ready := false.B } val s1_did_read = RegEnable(dataArb.io.in(3).ready && (io.cpu.req.valid && needsRead(io.cpu.req.bits)), s0_clk_en) val s1_read_mask = RegEnable(dataArb.io.in(3).bits.wordMask, s0_clk_en) metaArb.io.in(7).valid := io.cpu.req.valid metaArb.io.in(7).bits.write := false.B metaArb.io.in(7).bits.idx := dataArb.io.in(3).bits.addr(idxMSB, idxLSB) metaArb.io.in(7).bits.addr := io.cpu.req.bits.addr metaArb.io.in(7).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(7).bits.data := metaArb.io.in(4).bits.data when (!metaArb.io.in(7).ready) { io.cpu.req.ready := false.B } // address translation val s1_cmd_uses_tlb = s1_readwrite || s1_flush_line || s1_req.cmd === M_WOK io.ptw <> tlb.io.ptw tlb.io.kill := io.cpu.s2_kill || s2_tlb_req_valid && io.tlb_port.s2_kill tlb.io.req.valid := s1_tlb_req_valid || s1_valid && !io.cpu.s1_kill && s1_cmd_uses_tlb tlb.io.req.bits := s1_tlb_req when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false.B } when (!s1_tlb_req_valid && s1_valid && s1_cmd_uses_tlb && tlb.io.resp.miss) { s1_nack := true.B } tlb.io.sfence.valid := s1_valid && !io.cpu.s1_kill && s1_sfence tlb.io.sfence.bits.rs1 := s1_req.size(0) tlb.io.sfence.bits.rs2 := s1_req.size(1) tlb.io.sfence.bits.asid := io.cpu.s1_data.data tlb.io.sfence.bits.addr := s1_req.addr tlb.io.sfence.bits.hv := s1_req.cmd === M_HFENCEV tlb.io.sfence.bits.hg := s1_req.cmd === M_HFENCEG io.tlb_port.req.ready := clock_en_reg io.tlb_port.s1_resp := tlb.io.resp when (s1_tlb_req_valid && s1_valid && !(s1_req.phys && s1_req.no_xcpt)) { s1_nack := true.B } pma_checker.io <> DontCare pma_checker.io.req.bits.passthrough := true.B pma_checker.io.req.bits.vaddr := s1_req.addr pma_checker.io.req.bits.size := s1_req.size pma_checker.io.req.bits.cmd := s1_req.cmd pma_checker.io.req.bits.prv := s1_req.dprv pma_checker.io.req.bits.v := s1_req.dv val s1_paddr = Cat(Mux(s1_tlb_req_valid, s1_req.addr(paddrBits-1, pgIdxBits), tlb.io.resp.paddr >> pgIdxBits), s1_req.addr(pgIdxBits-1, 0)) val s1_victim_way = Wire(UInt()) val (s1_hit_way, s1_hit_state, s1_meta) = if (usingDataScratchpad) { val baseAddr = p(LookupByHartId)(_.dcache.flatMap(_.scratch.map(_.U)), io_hartid.get) | io_mmio_address_prefix.get val inScratchpad = s1_paddr >= baseAddr && s1_paddr < baseAddr + (nSets * cacheBlockBytes).U val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset) val dummyMeta = L1Metadata(0.U, ClientMetadata.onReset) (inScratchpad, hitState, Seq(tECC.encode(dummyMeta.asUInt))) } else { val metaReq = metaArb.io.out val metaIdx = metaReq.bits.idx when (metaReq.valid && metaReq.bits.write) { val wmask = if (nWays == 1) Seq(true.B) else metaReq.bits.way_en.asBools tag_array.write(metaIdx, VecInit(Seq.fill(nWays)(metaReq.bits.data)), wmask) } val s1_meta = tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write) val s1_meta_uncorrected = s1_meta.map(tECC.decode(_).uncorrected.asTypeOf(new L1Metadata)) val s1_tag = s1_paddr >> tagLSB val s1_meta_hit_way = s1_meta_uncorrected.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt val s1_meta_hit_state = ( s1_meta_uncorrected.map(r => Mux(r.tag === s1_tag && !s1_flush_valid, r.coh.asUInt, 0.U)) .reduce (_|_)).asTypeOf(chiselTypeOf(ClientMetadata.onReset)) (s1_meta_hit_way, s1_meta_hit_state, s1_meta) } val s1_data_way = WireDefault(if (nWays == 1) 1.U else Mux(inWriteback, releaseWay, s1_hit_way)) val tl_d_data_encoded = Wire(chiselTypeOf(encodeData(tl_out.d.bits.data, false.B))) val s1_all_data_ways = VecInit(data.io.resp ++ (!cacheParams.separateUncachedResp).option(tl_d_data_encoded)) val s1_mask_xwr = new StoreGen(s1_req.size, s1_req.addr, 0.U, wordBytes).mask val s1_mask = Mux(s1_req.cmd === M_PWR, io.cpu.s1_data.mask, s1_mask_xwr) // for partial writes, s1_data.mask must be a subset of s1_mask_xwr assert(!(s1_valid_masked && s1_req.cmd === M_PWR) || (s1_mask_xwr | ~io.cpu.s1_data.mask).andR) val s2_valid = RegNext(s1_valid_masked && !s1_sfence, init=false.B) val s2_valid_no_xcpt = s2_valid && !io.cpu.s2_xcpt.asUInt.orR val s2_probe = RegNext(s1_probe, init=false.B) val releaseInFlight = s1_probe || s2_probe || release_state =/= s_ready val s2_not_nacked_in_s1 = RegNext(!s1_nack) val s2_valid_not_nacked_in_s1 = s2_valid && s2_not_nacked_in_s1 val s2_valid_masked = s2_valid_no_xcpt && s2_not_nacked_in_s1 val s2_valid_not_killed = s2_valid_masked && !io.cpu.s2_kill val s2_req = Reg(chiselTypeOf(io.cpu.req.bits)) val s2_cmd_flush_all = s2_req.cmd === M_FLUSH_ALL && !s2_req.size(0) val s2_cmd_flush_line = s2_req.cmd === M_FLUSH_ALL && s2_req.size(0) val s2_tlb_xcpt = Reg(chiselTypeOf(tlb.io.resp)) val s2_pma = Reg(chiselTypeOf(tlb.io.resp)) val s2_uncached_resp_addr = Reg(chiselTypeOf(s2_req.addr)) // should be DCE'd in synthesis when (s1_valid_not_nacked || s1_flush_valid) { s2_req := s1_req s2_req.addr := s1_paddr s2_tlb_xcpt := tlb.io.resp s2_pma := Mux(s1_tlb_req_valid, pma_checker.io.resp, tlb.io.resp) } val s2_vaddr = Cat(RegEnable(s1_vaddr, s1_valid_not_nacked || s1_flush_valid) >> tagLSB, s2_req.addr(tagLSB-1, 0)) val s2_read = isRead(s2_req.cmd) val s2_write = isWrite(s2_req.cmd) val s2_readwrite = s2_read || s2_write val s2_flush_valid_pre_tag_ecc = RegNext(s1_flush_valid) val s1_meta_decoded = s1_meta.map(tECC.decode(_)) val s1_meta_clk_en = s1_valid_not_nacked || s1_flush_valid || s1_probe val s2_meta_correctable_errors = s1_meta_decoded.map(m => RegEnable(m.correctable, s1_meta_clk_en)).asUInt val s2_meta_uncorrectable_errors = s1_meta_decoded.map(m => RegEnable(m.uncorrectable, s1_meta_clk_en)).asUInt val s2_meta_error_uncorrectable = s2_meta_uncorrectable_errors.orR val s2_meta_corrected = s1_meta_decoded.map(m => RegEnable(m.corrected, s1_meta_clk_en).asTypeOf(new L1Metadata)) val s2_meta_error = (s2_meta_uncorrectable_errors | s2_meta_correctable_errors).orR val s2_flush_valid = s2_flush_valid_pre_tag_ecc && !s2_meta_error val s2_data = { val wordsPerRow = rowBits / subWordBits val en = s1_valid || inWriteback || io.cpu.replay_next val word_en = Mux(inWriteback, Fill(wordsPerRow, 1.U), Mux(s1_did_read, s1_read_mask, 0.U)) val s1_way_words = s1_all_data_ways.map(_.grouped(dECC.width(eccBits) * (subWordBits / eccBits))) if (cacheParams.pipelineWayMux) { val s1_word_en = Mux(io.cpu.replay_next, 0.U, word_en) (for (i <- 0 until wordsPerRow) yield { val s2_way_en = RegEnable(Mux(s1_word_en(i), s1_data_way, 0.U), en) val s2_way_words = (0 until nWays).map(j => RegEnable(s1_way_words(j)(i), en && word_en(i))) (0 until nWays).map(j => Mux(s2_way_en(j), s2_way_words(j), 0.U)).reduce(_|_) }).asUInt } else { val s1_word_en = Mux(!io.cpu.replay_next, word_en, UIntToOH(uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)), wordsPerRow)) (for (i <- 0 until wordsPerRow) yield { RegEnable(Mux1H(Mux(s1_word_en(i), s1_data_way, 0.U), s1_way_words.map(_(i))), en) }).asUInt } } val s2_probe_way = RegEnable(s1_hit_way, s1_probe) val s2_probe_state = RegEnable(s1_hit_state, s1_probe) val s2_hit_way = RegEnable(s1_hit_way, s1_valid_not_nacked) val s2_hit_state = RegEnable(s1_hit_state, s1_valid_not_nacked || s1_flush_valid) val s2_waw_hazard = RegEnable(s1_waw_hazard, s1_valid_not_nacked) val s2_store_merge = Wire(Bool()) val s2_hit_valid = s2_hit_state.isValid() val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd) val s2_data_decoded = decodeData(s2_data) val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val s2_data_error = s2_data_decoded.map(_.error).orR val s2_data_error_uncorrectable = s2_data_decoded.map(_.uncorrectable).orR val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt val s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = s2_valid_masked && !s2_meta_error && s2_hit val s2_no_alloc_hazard = if (!usingVM || pgIdxBits >= untagBits) false.B else { // make sure that any in-flight non-allocating accesses are ordered before // any allocating accesses. this can only happen if aliasing is possible. val any_no_alloc_in_flight = Reg(Bool()) when (!uncachedInFlight.asUInt.orR) { any_no_alloc_in_flight := false.B } when (s2_valid && s2_req.no_alloc) { any_no_alloc_in_flight := true.B } val s1_need_check = any_no_alloc_in_flight || s2_valid && s2_req.no_alloc val concerns = (uncachedInFlight zip uncachedReqs) :+ (s2_valid && s2_req.no_alloc, s2_req) val s1_uncached_hits = concerns.map { c => val concern_wmask = new StoreGen(c._2.size, c._2.addr, 0.U, wordBytes).mask val addr_match = (c._2.addr ^ s1_paddr)(pgIdxBits+pgLevelBits-1, wordBytes.log2) === 0.U val mask_match = (concern_wmask & s1_mask_xwr).orR || c._2.cmd === M_PWR || s1_req.cmd === M_PWR val cmd_match = isWrite(c._2.cmd) || isWrite(s1_req.cmd) c._1 && s1_need_check && cmd_match && addr_match && mask_match } val s2_uncached_hits = RegEnable(s1_uncached_hits.asUInt, s1_valid_not_nacked) s2_uncached_hits.orR } val s2_valid_hit_pre_data_ecc_and_waw = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_readwrite && !s2_no_alloc_hazard val s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_cmd_flush_line val s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw && (!s2_waw_hazard || s2_store_merge) val s2_valid_data_error = s2_valid_hit_pre_data_ecc_and_waw && s2_data_error val s2_valid_hit = s2_valid_hit_pre_data_ecc && !s2_data_error val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_meta_error && !s2_hit val s2_uncached = !s2_pma.cacheable || s2_req.no_alloc && !s2_pma.must_alloc && !s2_hit_valid val s2_valid_cached_miss = s2_valid_miss && !s2_uncached && !uncachedInFlight.asUInt.orR dontTouch(s2_valid_cached_miss) val s2_want_victimize = (!usingDataScratchpad).B && (s2_valid_cached_miss || s2_valid_flush_line || s2_valid_data_error || s2_flush_valid) val s2_cannot_victimize = !s2_flush_valid && io.cpu.s2_kill val s2_victimize = s2_want_victimize && !s2_cannot_victimize val s2_valid_uncached_pending = s2_valid_miss && s2_uncached && !uncachedInFlight.asUInt.andR val s2_victim_way = UIntToOH(RegEnable(s1_victim_way, s1_valid_not_nacked || s1_flush_valid)) val s2_victim_or_hit_way = Mux(s2_hit_valid, s2_hit_way, s2_victim_way) val s2_victim_tag = Mux(s2_valid_data_error || s2_valid_flush_line, s2_req.addr(paddrBits-1, tagLSB), Mux1H(s2_victim_way, s2_meta_corrected).tag) val s2_victim_state = Mux(s2_hit_valid, s2_hit_state, Mux1H(s2_victim_way, s2_meta_corrected).coh) val (s2_prb_ack_data, s2_report_param, probeNewCoh)= s2_probe_state.onProbe(probe_bits.param) val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH) dontTouch(s2_victim_dirty) val s2_update_meta = s2_hit_state =/= s2_new_hit_state val s2_dont_nack_uncached = s2_valid_uncached_pending && tl_out_a.ready val s2_dont_nack_misc = s2_valid_masked && !s2_meta_error && (supports_flush.B && s2_cmd_flush_all && flushed && !flushing || supports_flush.B && s2_cmd_flush_line && !s2_hit || s2_req.cmd === M_WOK) io.cpu.s2_nack := s2_valid_no_xcpt && !s2_dont_nack_uncached && !s2_dont_nack_misc && !s2_valid_hit when (io.cpu.s2_nack || (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true.B } // tag updates on ECC errors val s2_first_meta_corrected = PriorityMux(s2_meta_correctable_errors, s2_meta_corrected) metaArb.io.in(1).valid := s2_meta_error && (s2_valid_masked || s2_flush_valid_pre_tag_ecc || s2_probe) metaArb.io.in(1).bits.write := true.B metaArb.io.in(1).bits.way_en := s2_meta_uncorrectable_errors | Mux(s2_meta_error_uncorrectable, 0.U, PriorityEncoderOH(s2_meta_correctable_errors)) metaArb.io.in(1).bits.idx := Mux(s2_probe, probeIdx(probe_bits), s2_vaddr(idxMSB, idxLSB)) metaArb.io.in(1).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(1).bits.idx << blockOffBits) metaArb.io.in(1).bits.data := tECC.encode { val new_meta = WireDefault(s2_first_meta_corrected) when (s2_meta_error_uncorrectable) { new_meta.coh := ClientMetadata.onReset } new_meta.asUInt } // tag updates on hit metaArb.io.in(2).valid := s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta metaArb.io.in(2).bits.write := !io.cpu.s2_kill metaArb.io.in(2).bits.way_en := s2_victim_or_hit_way metaArb.io.in(2).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(2).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(2).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_new_hit_state).asUInt) // load reservations and TL error reporting val s2_lr = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XLR val s2_sc = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XSC val lrscCount = RegInit(0.U) val lrscValid = lrscCount > lrscBackoff.U val lrscBackingOff = lrscCount > 0.U && !lrscValid val lrscAddr = Reg(UInt()) val lrscAddrMatch = lrscAddr === (s2_req.addr >> blockOffBits) val s2_sc_fail = s2_sc && !(lrscValid && lrscAddrMatch) when ((s2_valid_hit && s2_lr && !cached_grant_wait || s2_valid_cached_miss) && !io.cpu.s2_kill) { lrscCount := Mux(s2_hit, (lrscCycles - 1).U, 0.U) lrscAddr := s2_req.addr >> blockOffBits } when (lrscCount > 0.U) { lrscCount := lrscCount - 1.U } when (s2_valid_not_killed && lrscValid) { lrscCount := lrscBackoff.U } when (s1_probe) { lrscCount := 0.U } // don't perform data correction if it might clobber a recent store val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid || s2_valid) && usingDataScratchpad.B // pending store buffer val s2_valid_correct = s2_valid_hit_pre_data_ecc_and_waw && s2_correct && !io.cpu.s2_kill def s2_store_valid_pre_kill = s2_valid_hit && s2_write && !s2_sc_fail def s2_store_valid = s2_store_valid_pre_kill && !io.cpu.s2_kill val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write) val pstore1_addr = RegEnable(s1_vaddr, s1_valid_not_nacked && s1_write) val pstore1_data = RegEnable(io.cpu.s1_data.data, s1_valid_not_nacked && s1_write) val pstore1_way = RegEnable(s1_hit_way, s1_valid_not_nacked && s1_write) val pstore1_mask = RegEnable(s1_mask, s1_valid_not_nacked && s1_write) val pstore1_storegen_data = WireDefault(pstore1_data) val pstore1_rmw = usingRMW.B && RegEnable(needsRead(s1_req), s1_valid_not_nacked && s1_write) val pstore1_merge_likely = s2_valid_not_nacked_in_s1 && s2_write && s2_store_merge val pstore1_merge = s2_store_valid && s2_store_merge val pstore2_valid = RegInit(false.B) val pstore_drain_opportunistic = !(io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits)) && !(s1_valid && s1_waw_hazard) val pstore_drain_on_miss = releaseInFlight || RegNext(io.cpu.s2_nack) val pstore1_held = RegInit(false.B) val pstore1_valid_likely = s2_valid && s2_write || pstore1_held def pstore1_valid_not_rmw(s2_kill: Bool) = s2_valid_hit_pre_data_ecc && s2_write && !s2_kill || pstore1_held val pstore1_valid = s2_store_valid || pstore1_held any_pstore_valid := pstore1_held || pstore2_valid val pstore_drain_structural = pstore1_valid_likely && pstore2_valid && ((s1_valid && s1_write) || pstore1_rmw) assert(pstore1_rmw || pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid) ccover(pstore_drain_structural, "STORE_STRUCTURAL_HAZARD", "D$ read-modify-write structural hazard") ccover(pstore1_valid && pstore_drain_on_miss, "STORE_DRAIN_ON_MISS", "D$ store buffer drain on miss") ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") def should_pstore_drain(truly: Bool) = { val s2_kill = truly && io.cpu.s2_kill !pstore1_merge_likely && (usingRMW.B && pstore_drain_structural || (((pstore1_valid_not_rmw(s2_kill) && !pstore1_rmw) || pstore2_valid) && (pstore_drain_opportunistic || pstore_drain_on_miss))) } val pstore_drain = should_pstore_drain(true.B) pstore1_held := (s2_store_valid && !s2_store_merge || pstore1_held) && pstore2_valid && !pstore_drain val advance_pstore1 = (pstore1_valid || s2_valid_correct) && (pstore2_valid === pstore_drain) pstore2_valid := pstore2_valid && !pstore_drain || advance_pstore1 val pstore2_addr = RegEnable(Mux(s2_correct, s2_vaddr, pstore1_addr), advance_pstore1) val pstore2_way = RegEnable(Mux(s2_correct, s2_hit_way, pstore1_way), advance_pstore1) val pstore2_storegen_data = { for (i <- 0 until wordBytes) yield RegEnable(pstore1_storegen_data(8*(i+1)-1, 8*i), advance_pstore1 || pstore1_merge && pstore1_mask(i)) }.asUInt val pstore2_storegen_mask = { val mask = Reg(UInt(wordBytes.W)) when (advance_pstore1 || pstore1_merge) { val mergedMask = pstore1_mask | Mux(pstore1_merge, mask, 0.U) mask := ~Mux(s2_correct, 0.U, ~mergedMask) } mask } s2_store_merge := (if (eccBytes == 1) false.B else { ccover(pstore1_merge, "STORE_MERGED", "D$ store merged") // only merge stores to ECC granules that are already stored-to, to avoid // WAW hazards val wordMatch = (eccMask(pstore2_storegen_mask) | ~eccMask(pstore1_mask)).andR val idxMatch = s2_vaddr(untagBits-1, log2Ceil(wordBytes)) === pstore2_addr(untagBits-1, log2Ceil(wordBytes)) val tagMatch = (s2_hit_way & pstore2_way).orR pstore2_valid && wordMatch && idxMatch && tagMatch }) dataArb.io.in(0).valid := should_pstore_drain(false.B) dataArb.io.in(0).bits.write := pstore_drain dataArb.io.in(0).bits.addr := Mux(pstore2_valid, pstore2_addr, pstore1_addr) dataArb.io.in(0).bits.way_en := Mux(pstore2_valid, pstore2_way, pstore1_way) dataArb.io.in(0).bits.wdata := encodeData(Fill(rowWords, Mux(pstore2_valid, pstore2_storegen_data, pstore1_data)), false.B) dataArb.io.in(0).bits.wordMask := { val eccMask = dataArb.io.in(0).bits.eccMask.asBools.grouped(subWordBytes/eccBytes).map(_.orR).toSeq.asUInt val wordMask = UIntToOH(Mux(pstore2_valid, pstore2_addr, pstore1_addr).extract(rowOffBits-1, wordBytes.log2)) FillInterleaved(wordBytes/subWordBytes, wordMask) & Fill(rowBytes/wordBytes, eccMask) } dataArb.io.in(0).bits.eccMask := eccMask(Mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask)) // store->load RAW hazard detection def s1Depends(addr: UInt, mask: UInt) = addr(idxMSB, wordOffBits) === s1_vaddr(idxMSB, wordOffBits) && Mux(s1_write, (eccByteMask(mask) & eccByteMask(s1_mask_xwr)).orR, (mask & s1_mask_xwr).orR) val s1_hazard = (pstore1_valid_likely && s1Depends(pstore1_addr, pstore1_mask)) || (pstore2_valid && s1Depends(pstore2_addr, pstore2_storegen_mask)) val s1_raw_hazard = s1_read && s1_hazard s1_waw_hazard := (if (eccBytes == 1) false.B else { ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") s1_write && (s1_hazard || needsRead(s1_req) && !s1_did_read) }) when (s1_valid && s1_raw_hazard) { s1_nack := true.B } // performance hints to processor io.cpu.s2_nack_cause_raw := RegNext(s1_raw_hazard) || !(!s2_waw_hazard || s2_store_merge) // Prepare a TileLink request message that initiates a transaction val a_source = PriorityEncoder(~uncachedInFlight.asUInt << mmioOffset) // skip the MSHR val acquire_address = (s2_req.addr >> idxLSB) << idxLSB val access_address = s2_req.addr val a_size = s2_req.size val a_data = Fill(beatWords, pstore1_data) val a_mask = pstore1_mask << (access_address.extract(beatBytes.log2-1, wordBytes.log2) << 3) val get = edge.Get(a_source, access_address, a_size)._2 val put = edge.Put(a_source, access_address, a_size, a_data)._2 val putpartial = edge.Put(a_source, access_address, a_size, a_data, a_mask)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(s2_req.cmd, WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))))(Array( M_XA_SWAP -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert (!(tl_out_a.valid && s2_read && s2_write && s2_uncached)) WireDefault(new TLBundleA(edge.bundle), DontCare) } tl_out_a.valid := !io.cpu.s2_kill && (s2_valid_uncached_pending || (s2_valid_cached_miss && !(release_ack_wait && (s2_req.addr ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U) && (cacheParams.acquireBeforeRelease.B && !release_ack_wait && release_queue_empty || !s2_victim_dirty))) tl_out_a.bits := Mux(!s2_uncached, acquire(s2_vaddr, s2_req.addr, s2_grow_param), Mux(!s2_write, get, Mux(s2_req.cmd === M_PWR, putpartial, Mux(!s2_read, put, atomics)))) // Drive APROT Bits tl_out_a.bits.user.lift(AMBAProt).foreach { x => val user_bit_cacheable = s2_pma.cacheable x.privileged := s2_req.dprv === PRV.M.U || user_bit_cacheable // if the address is cacheable, enable outer caches x.bufferable := user_bit_cacheable x.modifiable := user_bit_cacheable x.readalloc := user_bit_cacheable x.writealloc := user_bit_cacheable // Following are always tied off x.fetch := false.B x.secure := true.B } // Set pending bits for outstanding TileLink transaction val a_sel = UIntToOH(a_source, maxUncachedInFlight+mmioOffset) >> mmioOffset when (tl_out_a.fire) { when (s2_uncached) { (a_sel.asBools zip (uncachedInFlight zip uncachedReqs)) foreach { case (s, (f, r)) => when (s) { f := true.B r := s2_req r.cmd := Mux(s2_write, Mux(s2_req.cmd === M_PWR, M_PWR, M_XWR), M_XRD) } } }.otherwise { cached_grant_wait := true.B refill_way := s2_victim_or_hit_way } } // grant val (d_first, d_last, d_done, d_address_inc) = edge.addr_inc(tl_out.d) val (d_opc, grantIsUncached, grantIsUncachedData) = { val uncachedGrantOpcodesSansData = Seq(AccessAck, HintAck) val uncachedGrantOpcodesWithData = Seq(AccessAckData) val uncachedGrantOpcodes = uncachedGrantOpcodesWithData ++ uncachedGrantOpcodesSansData val whole_opc = tl_out.d.bits.opcode if (usingDataScratchpad) { assert(!tl_out.d.valid || whole_opc.isOneOf(uncachedGrantOpcodes)) // the only valid TL-D messages are uncached, so we can do some pruning val opc = whole_opc(uncachedGrantOpcodes.map(_.getWidth).max - 1, 0) val data = DecodeLogic(opc, uncachedGrantOpcodesWithData, uncachedGrantOpcodesSansData) (opc, true.B, data) } else { (whole_opc, whole_opc.isOneOf(uncachedGrantOpcodes), whole_opc.isOneOf(uncachedGrantOpcodesWithData)) } } tl_d_data_encoded := encodeData(tl_out.d.bits.data, tl_out.d.bits.corrupt && !io.ptw.customCSRs.suppressCorruptOnGrantData && !grantIsUncached) val grantIsCached = d_opc.isOneOf(Grant, GrantData) val grantIsVoluntary = d_opc === ReleaseAck // Clears a different pending bit val grantIsRefill = d_opc === GrantData // Writes the data array val grantInProgress = RegInit(false.B) val blockProbeAfterGrantCount = RegInit(0.U) when (blockProbeAfterGrantCount > 0.U) { blockProbeAfterGrantCount := blockProbeAfterGrantCount - 1.U } val canAcceptCachedGrant = !release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release) tl_out.d.ready := Mux(grantIsCached, (!d_first || tl_out.e.ready) && canAcceptCachedGrant, true.B) val uncachedRespIdxOH = UIntToOH(tl_out.d.bits.source, maxUncachedInFlight+mmioOffset) >> mmioOffset uncachedResp := Mux1H(uncachedRespIdxOH, uncachedReqs) when (tl_out.d.fire) { when (grantIsCached) { grantInProgress := true.B assert(cached_grant_wait, "A GrantData was unexpected by the dcache.") when(d_last) { cached_grant_wait := false.B grantInProgress := false.B blockProbeAfterGrantCount := (blockProbeAfterGrantCycles - 1).U replacer.miss } } .elsewhen (grantIsUncached) { (uncachedRespIdxOH.asBools zip uncachedInFlight) foreach { case (s, f) => when (s && d_last) { assert(f, "An AccessAck was unexpected by the dcache.") // TODO must handle Ack coming back on same cycle! f := false.B } } when (grantIsUncachedData) { if (!cacheParams.separateUncachedResp) { if (!cacheParams.pipelineWayMux) s1_data_way := 1.U << nWays s2_req.cmd := M_XRD s2_req.size := uncachedResp.size s2_req.signed := uncachedResp.signed s2_req.tag := uncachedResp.tag s2_req.addr := { require(rowOffBits >= beatOffBits) val dontCareBits = s1_paddr >> rowOffBits << rowOffBits dontCareBits | uncachedResp.addr(beatOffBits-1, 0) } s2_uncached_resp_addr := uncachedResp.addr } } } .elsewhen (grantIsVoluntary) { assert(release_ack_wait, "A ReleaseAck was unexpected by the dcache.") // TODO should handle Ack coming back on same cycle! release_ack_wait := false.B } } // Finish TileLink transaction by issuing a GrantAck tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant tl_out.e.bits := edge.GrantAck(tl_out.d.bits) assert(tl_out.e.fire === (tl_out.d.fire && d_first && grantIsCached)) // data refill // note this ready-valid signaling ignores E-channel backpressure, which // benignly means the data RAM might occasionally be redundantly written dataArb.io.in(1).valid := tl_out.d.valid && grantIsRefill && canAcceptCachedGrant when (grantIsRefill && !dataArb.io.in(1).ready) { tl_out.e.valid := false.B tl_out.d.ready := false.B } if (!usingDataScratchpad) { dataArb.io.in(1).bits.write := true.B dataArb.io.in(1).bits.addr := (s2_vaddr >> idxLSB) << idxLSB | d_address_inc dataArb.io.in(1).bits.way_en := refill_way dataArb.io.in(1).bits.wdata := tl_d_data_encoded dataArb.io.in(1).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(1).bits.eccMask := ~0.U((wordBytes / eccBytes).W) } else { dataArb.io.in(1).bits := dataArb.io.in(0).bits } // tag updates on refill // ignore backpressure from metaArb, which can only be caused by tag ECC // errors on hit-under-miss. failing to write the new tag will leave the // line invalid, so we'll simply request the line again later. metaArb.io.in(3).valid := grantIsCached && d_done && !tl_out.d.bits.denied metaArb.io.in(3).bits.write := true.B metaArb.io.in(3).bits.way_en := refill_way metaArb.io.in(3).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(3).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_hit_state.onGrant(s2_req.cmd, tl_out.d.bits.param)).asUInt) if (!cacheParams.separateUncachedResp) { // don't accept uncached grants if there's a structural hazard on s2_data... val blockUncachedGrant = Reg(Bool()) blockUncachedGrant := dataArb.io.out.valid when (grantIsUncachedData && (blockUncachedGrant || s1_valid)) { tl_out.d.ready := false.B // ...but insert bubble to guarantee grant's eventual forward progress when (tl_out.d.valid) { io.cpu.req.ready := false.B dataArb.io.in(1).valid := true.B dataArb.io.in(1).bits.write := false.B blockUncachedGrant := !dataArb.io.in(1).ready } } } ccover(tl_out.d.valid && !tl_out.d.ready, "BLOCK_D", "D$ D-channel blocked") // Handle an incoming TileLink Probe message val block_probe_for_core_progress = blockProbeAfterGrantCount > 0.U || lrscValid val block_probe_for_pending_release_ack = release_ack_wait && (tl_out.b.bits.address ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U val block_probe_for_ordering = releaseInFlight || block_probe_for_pending_release_ack || grantInProgress metaArb.io.in(6).valid := tl_out.b.valid && (!block_probe_for_core_progress || lrscBackingOff) tl_out.b.ready := metaArb.io.in(6).ready && !(block_probe_for_core_progress || block_probe_for_ordering || s1_valid || s2_valid) metaArb.io.in(6).bits.write := false.B metaArb.io.in(6).bits.idx := probeIdx(tl_out.b.bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, tl_out.b.bits.address) metaArb.io.in(6).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(6).bits.data := metaArb.io.in(4).bits.data // replacement policy s1_victim_way := (if (replacer.perSet && nWays > 1) { val repl_array = Mem(nSets, UInt(replacer.nBits.W)) val s1_repl_idx = s1_req.addr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_idx = s2_vaddr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_state = Reg(UInt(replacer.nBits.W)) val s2_new_repl_state = replacer.get_next_state(s2_repl_state, OHToUInt(s2_hit_way)) val s2_repl_wen = s2_valid_masked && s2_hit_way.orR && s2_repl_state =/= s2_new_repl_state val s1_repl_state = Mux(s2_repl_wen && s2_repl_idx === s1_repl_idx, s2_new_repl_state, repl_array(s1_repl_idx)) when (s1_valid_not_nacked) { s2_repl_state := s1_repl_state } val waddr = Mux(resetting, flushCounter(idxBits-1, 0), s2_repl_idx) val wdata = Mux(resetting, 0.U, s2_new_repl_state) val wen = resetting || s2_repl_wen when (wen) { repl_array(waddr) := wdata } replacer.get_replace_way(s1_repl_state) } else { replacer.way }) // release val (c_first, c_last, releaseDone, c_count) = edge.count(tl_out_c) val releaseRejected = Wire(Bool()) val s1_release_data_valid = RegNext(dataArb.io.in(2).fire) val s2_release_data_valid = RegNext(s1_release_data_valid && !releaseRejected) releaseRejected := s2_release_data_valid && !tl_out_c.fire val releaseDataBeat = Cat(0.U, c_count) + Mux(releaseRejected, 0.U, s1_release_data_valid + Cat(0.U, s2_release_data_valid)) val nackResponseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = TLPermissions.NtoN) val cleanReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param) val dirtyReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param, data = 0.U) tl_out_c.valid := (s2_release_data_valid || (!cacheParams.silentDrop.B && release_state === s_voluntary_release)) && !(c_first && release_ack_wait) tl_out_c.bits := nackResponseMessage val newCoh = WireDefault(probeNewCoh) releaseWay := s2_probe_way if (!usingDataScratchpad) { when (s2_victimize) { assert(s2_valid_flush_line || s2_flush_valid || io.cpu.s2_nack) val discard_line = s2_valid_flush_line && s2_req.size(1) || s2_flush_valid && flushing_req.size(1) release_state := Mux(s2_victim_dirty && !discard_line, s_voluntary_writeback, Mux(!cacheParams.silentDrop.B && !release_ack_wait && release_queue_empty && s2_victim_state.isValid() && (s2_valid_flush_line || s2_flush_valid || s2_readwrite && !s2_hit_valid), s_voluntary_release, s_voluntary_write_meta)) probe_bits := addressToProbe(s2_vaddr, Cat(s2_victim_tag, s2_req.addr(tagLSB-1, idxLSB)) << idxLSB) } when (s2_probe) { val probeNack = WireDefault(true.B) when (s2_meta_error) { release_state := s_probe_retry }.elsewhen (s2_prb_ack_data) { release_state := s_probe_rep_dirty }.elsewhen (s2_probe_state.isValid()) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean) }.otherwise { tl_out_c.valid := true.B probeNack := !releaseDone release_state := Mux(releaseDone, s_ready, s_probe_rep_miss) } when (probeNack) { s1_nack := true.B } } when (release_state === s_probe_retry) { metaArb.io.in(6).valid := true.B metaArb.io.in(6).bits.idx := probeIdx(probe_bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, probe_bits.address) when (metaArb.io.in(6).ready) { release_state := s_ready s1_probe := true.B } } when (release_state === s_probe_rep_miss) { tl_out_c.valid := true.B when (releaseDone) { release_state := s_ready } } when (release_state === s_probe_rep_clean) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state === s_probe_rep_dirty) { tl_out_c.bits := dirtyReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release)) { when (release_state === s_voluntary_release) { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param)._2 }.otherwise { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param, data = 0.U)._2 } newCoh := voluntaryNewCoh releaseWay := s2_victim_or_hit_way when (releaseDone) { release_state := s_voluntary_write_meta } when (tl_out_c.fire && c_first) { release_ack_wait := true.B release_ack_addr := probe_bits.address } } tl_out_c.bits.source := probe_bits.source tl_out_c.bits.address := probe_bits.address tl_out_c.bits.data := s2_data_corrected tl_out_c.bits.corrupt := inWriteback && s2_data_error_uncorrectable } tl_out_c.bits.user.lift(AMBAProt).foreach { x => x.fetch := false.B x.secure := true.B x.privileged := true.B x.bufferable := true.B x.modifiable := true.B x.readalloc := true.B x.writealloc := true.B } dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles.U dataArb.io.in(2).bits := dataArb.io.in(1).bits dataArb.io.in(2).bits.write := false.B dataArb.io.in(2).bits.addr := (probeIdx(probe_bits) << blockOffBits) | (releaseDataBeat(log2Up(refillCycles)-1,0) << rowOffBits) dataArb.io.in(2).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(2).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(2).bits.way_en := ~0.U(nWays.W) metaArb.io.in(4).valid := release_state.isOneOf(s_voluntary_write_meta, s_probe_write_meta) metaArb.io.in(4).bits.write := true.B metaArb.io.in(4).bits.way_en := releaseWay metaArb.io.in(4).bits.idx := probeIdx(probe_bits) metaArb.io.in(4).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, probe_bits.address(idxMSB, 0)) metaArb.io.in(4).bits.data := tECC.encode(L1Metadata(tl_out_c.bits.address >> tagLSB, newCoh).asUInt) when (metaArb.io.in(4).fire) { release_state := s_ready } // cached response (io.cpu.resp.bits: Data).waiveAll :<>= (s2_req: Data).waiveAll io.cpu.resp.bits.has_data := s2_read io.cpu.resp.bits.replay := false.B io.cpu.s2_uncached := s2_uncached && !s2_hit io.cpu.s2_paddr := s2_req.addr io.cpu.s2_gpa := s2_tlb_xcpt.gpa io.cpu.s2_gpa_is_pte := s2_tlb_xcpt.gpa_is_pte // report whether there are any outstanding accesses. disregard any // slave-port accesses, since they don't affect local memory ordering. val s1_isSlavePortAccess = s1_req.no_xcpt val s2_isSlavePortAccess = s2_req.no_xcpt io.cpu.ordered := !(s1_valid && !s1_isSlavePortAccess || s2_valid && !s2_isSlavePortAccess || cached_grant_wait || uncachedInFlight.asUInt.orR) io.cpu.store_pending := (cached_grant_wait && isWrite(s2_req.cmd)) || uncachedInFlight.asUInt.orR val s1_xcpt_valid = tlb.io.req.valid && !s1_isSlavePortAccess && !s1_nack io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), s2_tlb_xcpt, 0.U.asTypeOf(s2_tlb_xcpt)) if (usingDataScratchpad) { assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC))) } else { ccover(tl_out.b.valid && !tl_out.b.ready, "BLOCK_B", "D$ B-channel blocked") } // uncached response val s1_uncached_data_word = { val word_idx = uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val words = tl_out.d.bits.data.grouped(wordBits) words(word_idx) } val s2_uncached_data_word = RegEnable(s1_uncached_data_word, io.cpu.replay_next) val doUncachedResp = RegNext(io.cpu.replay_next) io.cpu.resp.valid := (s2_valid_hit_pre_data_ecc || doUncachedResp) && !s2_data_error io.cpu.replay_next := tl_out.d.fire && grantIsUncachedData && !cacheParams.separateUncachedResp.B when (doUncachedResp) { assert(!s2_valid_hit) io.cpu.resp.bits.replay := true.B io.cpu.resp.bits.addr := s2_uncached_resp_addr } io.cpu.uncached_resp.map { resp => resp.valid := tl_out.d.valid && grantIsUncachedData resp.bits.tag := uncachedResp.tag resp.bits.size := uncachedResp.size resp.bits.signed := uncachedResp.signed resp.bits.data := new LoadGen(uncachedResp.size, uncachedResp.signed, uncachedResp.addr, s1_uncached_data_word, false.B, wordBytes).data resp.bits.data_raw := s1_uncached_data_word when (grantIsUncachedData && !resp.ready) { tl_out.d.ready := false.B } } // load data subword mux/sign extension val s2_data_word = (0 until rowBits by wordBits).map(i => s2_data_uncorrected(wordBits+i-1,i)).reduce(_|_) val s2_data_word_corrected = (0 until rowBits by wordBits).map(i => s2_data_corrected(wordBits+i-1,i)).reduce(_|_) val s2_data_word_possibly_uncached = Mux(cacheParams.pipelineWayMux.B && doUncachedResp, s2_uncached_data_word, 0.U) | s2_data_word val loadgen = new LoadGen(s2_req.size, s2_req.signed, s2_req.addr, s2_data_word_possibly_uncached, s2_sc, wordBytes) io.cpu.resp.bits.data := loadgen.data | s2_sc_fail io.cpu.resp.bits.data_word_bypass := loadgen.wordData io.cpu.resp.bits.data_raw := s2_data_word io.cpu.resp.bits.store_data := pstore1_data // AMOs if (usingRMW) { val amoalus = (0 until coreDataBits / xLen).map { i => val amoalu = Module(new AMOALU(xLen)) amoalu.io.mask := pstore1_mask >> (i * xBytes) amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR) amoalu.io.lhs := s2_data_word >> (i * xLen) amoalu.io.rhs := pstore1_data >> (i * xLen) amoalu } pstore1_storegen_data := (if (!usingDataScratchpad) amoalus.map(_.io.out).asUInt else { val mask = FillInterleaved(8, Mux(s2_correct, 0.U, pstore1_mask)) amoalus.map(_.io.out_unmasked).asUInt & mask | s2_data_word_corrected & ~mask }) } else if (!usingAtomics) { assert(!(s1_valid_masked && s1_read && s1_write), "unsupported D$ operation") } if (coreParams.useVector) { edge.manager.managers.foreach { m => // Statically ensure that no-allocate accesses are permitted. // We could consider turning some of these into dynamic PMA checks. require(!m.supportsAcquireB || m.supportsGet, "With a vector unit, cacheable memory must support Get") require(!m.supportsAcquireT || m.supportsPutPartial, "With a vector unit, cacheable memory must support PutPartial") } } // flushes if (!usingDataScratchpad) when (RegNext(reset.asBool)) { resetting := true.B } val flushCounterNext = flushCounter +& 1.U val flushDone = (flushCounterNext >> log2Ceil(nSets)) === nWays.U val flushCounterWrap = flushCounterNext(log2Ceil(nSets)-1, 0) ccover(s2_valid_masked && s2_cmd_flush_all && s2_meta_error, "TAG_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in tag array during cache flush") ccover(s2_valid_masked && s2_cmd_flush_all && s2_data_error, "DATA_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in data array during cache flush") s1_flush_valid := metaArb.io.in(5).fire && !s1_flush_valid && !s2_flush_valid_pre_tag_ecc && release_state === s_ready && !release_ack_wait metaArb.io.in(5).valid := flushing && !flushed metaArb.io.in(5).bits.write := false.B metaArb.io.in(5).bits.idx := flushCounter(idxBits-1, 0) metaArb.io.in(5).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(5).bits.idx << blockOffBits) metaArb.io.in(5).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data // Only flush D$ on FENCE.I if some cached executable regions are untracked. if (supports_flush) { when (s2_valid_masked && s2_cmd_flush_all) { when (!flushed && !io.cpu.s2_kill && !release_ack_wait && !uncachedInFlight.asUInt.orR) { flushing := true.B flushing_req := s2_req } } when (tl_out_a.fire && !s2_uncached) { flushed := false.B } when (flushing) { s1_victim_way := flushCounter >> log2Up(nSets) when (s2_flush_valid) { flushCounter := flushCounterNext when (flushDone) { flushed := true.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } when (flushed && release_state === s_ready && !release_ack_wait) { flushing := false.B } } } metaArb.io.in(0).valid := resetting metaArb.io.in(0).bits := metaArb.io.in(5).bits metaArb.io.in(0).bits.write := true.B metaArb.io.in(0).bits.way_en := ~0.U(nWays.W) metaArb.io.in(0).bits.data := tECC.encode(L1Metadata(0.U, ClientMetadata.onReset).asUInt) when (resetting) { flushCounter := flushCounterNext when (flushDone) { resetting := false.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } // gate the clock clock_en_reg := !cacheParams.clockGate.B || io.ptw.customCSRs.disableDCacheClockGate || io.cpu.keep_clock_enabled || metaArb.io.out.valid || // subsumes resetting || flushing s1_probe || s2_probe || s1_valid || s2_valid || io.tlb_port.req.valid || s1_tlb_req_valid || s2_tlb_req_valid || pstore1_held || pstore2_valid || release_state =/= s_ready || release_ack_wait || !release_queue_empty || !tlb.io.req.ready || cached_grant_wait || uncachedInFlight.asUInt.orR || lrscCount > 0.U || blockProbeAfterGrantCount > 0.U // performance events io.cpu.perf.acquire := edge.done(tl_out_a) io.cpu.perf.release := edge.done(tl_out_c) io.cpu.perf.grant := tl_out.d.valid && d_last io.cpu.perf.tlbMiss := io.ptw.req.fire io.cpu.perf.storeBufferEmptyAfterLoad := !( (s1_valid && s1_write) || ((s2_valid && s2_write && !s2_waw_hazard) || pstore1_held) || pstore2_valid) io.cpu.perf.storeBufferEmptyAfterStore := !( (s1_valid && s1_write) || (s2_valid && s2_write && pstore1_rmw) || ((s2_valid && s2_write && !s2_waw_hazard || pstore1_held) && pstore2_valid)) io.cpu.perf.canAcceptStoreThenLoad := !( ((s2_valid && s2_write && pstore1_rmw) && (s1_valid && s1_write && !s1_waw_hazard)) || (pstore2_valid && pstore1_valid_likely && (s1_valid && s1_write))) io.cpu.perf.canAcceptStoreThenRMW := io.cpu.perf.canAcceptStoreThenLoad && !pstore2_valid io.cpu.perf.canAcceptLoadThenLoad := !((s1_valid && s1_write && needsRead(s1_req)) && ((s2_valid && s2_write && !s2_waw_hazard || pstore1_held) || pstore2_valid)) io.cpu.perf.blocked := { // stop reporting blocked just before unblocking to avoid overly conservative stalling val beatsBeforeEnd = outer.crossing match { case SynchronousCrossing(_) => 2 case RationalCrossing(_) => 1 // assumes 1 < ratio <= 2; need more bookkeeping for optimal handling of >2 case _: AsynchronousCrossing => 1 // likewise case _: CreditedCrossing => 1 // likewise } val near_end_of_refill = if (cacheBlockBytes / beatBytes <= beatsBeforeEnd) tl_out.d.valid else { val refill_count = RegInit(0.U((cacheBlockBytes / beatBytes).log2.W)) when (tl_out.d.fire && grantIsRefill) { refill_count := refill_count + 1.U } refill_count >= (cacheBlockBytes / beatBytes - beatsBeforeEnd).U } cached_grant_wait && !near_end_of_refill } // report errors val (data_error, data_error_uncorrectable, data_error_addr) = if (usingDataScratchpad) (s2_valid_data_error, s2_data_error_uncorrectable, s2_req.addr) else { (RegNext(tl_out_c.fire && inWriteback && s2_data_error), RegNext(s2_data_error_uncorrectable), probe_bits.address) // This is stable for a cycle after tl_out_c.fire, so don't need a register } { val error_addr = Mux(metaArb.io.in(1).valid, Cat(s2_first_meta_corrected.tag, metaArb.io.in(1).bits.addr(tagLSB-1, idxLSB)), data_error_addr >> idxLSB) << idxLSB io.errors.uncorrectable.foreach { u => u.valid := metaArb.io.in(1).valid && s2_meta_error_uncorrectable || data_error && data_error_uncorrectable u.bits := error_addr } io.errors.correctable.foreach { c => c.valid := metaArb.io.in(1).valid || data_error c.bits := error_addr io.errors.uncorrectable.foreach { u => when (u.valid) { c.valid := false.B } } } io.errors.bus.valid := tl_out.d.fire && (tl_out.d.bits.denied || tl_out.d.bits.corrupt) io.errors.bus.bits := Mux(grantIsCached, s2_req.addr >> idxLSB << idxLSB, 0.U) ccoverNotScratchpad(io.errors.bus.valid && grantIsCached, "D_ERROR_CACHED", "D$ D-channel error, cached") ccover(io.errors.bus.valid && !grantIsCached, "D_ERROR_UNCACHED", "D$ D-channel error, uncached") } if (usingDataScratchpad) { val data_error_cover = Seq( property.CoverBoolean(!data_error, Seq("no_data_error")), property.CoverBoolean(data_error && !data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(data_error && data_error_uncorrectable, Seq("data_uncorrectable_error"))) val request_source = Seq( property.CoverBoolean(s2_isSlavePortAccess, Seq("from_TL")), property.CoverBoolean(!s2_isSlavePortAccess, Seq("from_CPU"))) property.cover(new property.CrossProperty( Seq(data_error_cover, request_source), Seq(), "MemorySystem;;Scratchpad Memory Bit Flip Cross Covers")) } else { val data_error_type = Seq( property.CoverBoolean(!s2_valid_data_error, Seq("no_data_error")), property.CoverBoolean(s2_valid_data_error && !s2_data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(s2_valid_data_error && s2_data_error_uncorrectable, Seq("data_uncorrectable_error"))) val data_error_dirty = Seq( property.CoverBoolean(!s2_victim_dirty, Seq("data_clean")), property.CoverBoolean(s2_victim_dirty, Seq("data_dirty"))) val request_source = if (supports_flush) { Seq( property.CoverBoolean(!flushing, Seq("access")), property.CoverBoolean(flushing, Seq("during_flush"))) } else { Seq(property.CoverBoolean(true.B, Seq("never_flush"))) } val tag_error_cover = Seq( property.CoverBoolean( !s2_meta_error, Seq("no_tag_error")), property.CoverBoolean( s2_meta_error && !s2_meta_error_uncorrectable, Seq("tag_correctable_error")), property.CoverBoolean( s2_meta_error && s2_meta_error_uncorrectable, Seq("tag_uncorrectable_error"))) property.cover(new property.CrossProperty( Seq(data_error_type, data_error_dirty, request_source, tag_error_cover), Seq(), "MemorySystem;;Cache Memory Bit Flip Cross Covers")) } } // leaving gated-clock domain val dcacheImpl = withClock (gated_clock) { new DCacheModuleImpl } def encodeData(x: UInt, poison: Bool) = x.grouped(eccBits).map(dECC.encode(_, if (dECC.canDetect) poison else false.B)).asUInt def dummyEncodeData(x: UInt) = x.grouped(eccBits).map(dECC.swizzle(_)).asUInt def decodeData(x: UInt) = x.grouped(dECC.width(eccBits)).map(dECC.decode(_)) def eccMask(byteMask: UInt) = byteMask.grouped(eccBytes).map(_.orR).asUInt def eccByteMask(byteMask: UInt) = FillInterleaved(eccBytes, eccMask(byteMask)) def likelyNeedsRead(req: HellaCacheReq) = { val res = !req.cmd.isOneOf(M_XWR, M_PFW) || req.size < log2Ceil(eccBytes).U assert(!needsRead(req) || res) res } def needsRead(req: HellaCacheReq) = isRead(req.cmd) || (isWrite(req.cmd) && (req.cmd === M_PWR || req.size < log2Ceil(eccBytes).U)) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"DCACHE_$label", "MemorySystem;;" + desc) def ccoverNotScratchpad(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (!usingDataScratchpad) ccover(cond, label, desc) require(!usingVM || tagLSB <= pgIdxBits, s"D$$ set size must not exceed ${1<<(pgIdxBits-10)} KiB; got ${(nSets * cacheBlockBytes)>>10} KiB") def tagLSB: Int = untagBits def probeIdx(b: TLBundleB): UInt = b.address(idxMSB, idxLSB) def addressToProbe(vaddr: UInt, paddr: UInt): TLBundleB = { val res = Wire(new TLBundleB(edge.bundle)) res :#= DontCare res.address := paddr res.source := (mmioOffset - 1).U res } def acquire(vaddr: UInt, paddr: UInt, param: UInt): TLBundleA = { if (!edge.manager.anySupportAcquireB) WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))) else edge.AcquireBlock(0.U, paddr >> lgCacheBlockBytes << lgCacheBlockBytes, lgCacheBlockBytes.U, param)._2 } } File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize*8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) | Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and || logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out | ~wmask & io.lhs io.out_unmasked := out }
module DCache_1( // @[DCache.scala:101:7] input clock, // @[DCache.scala:101:7] input reset, // @[DCache.scala:101:7] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output io_cpu_req_ready, // @[HellaCache.scala:243:14] input io_cpu_req_valid, // @[HellaCache.scala:243:14] input [39:0] io_cpu_req_bits_addr, // @[HellaCache.scala:243:14] input [6:0] io_cpu_req_bits_tag, // @[HellaCache.scala:243:14] input [4:0] io_cpu_req_bits_cmd, // @[HellaCache.scala:243:14] input [1:0] io_cpu_req_bits_size, // @[HellaCache.scala:243:14] input io_cpu_req_bits_signed, // @[HellaCache.scala:243:14] input [1:0] io_cpu_req_bits_dprv, // @[HellaCache.scala:243:14] input io_cpu_req_bits_dv, // @[HellaCache.scala:243:14] input io_cpu_req_bits_phys, // @[HellaCache.scala:243:14] input io_cpu_req_bits_no_resp, // @[HellaCache.scala:243:14] input io_cpu_s1_kill, // @[HellaCache.scala:243:14] input [63:0] io_cpu_s1_data_data, // @[HellaCache.scala:243:14] input [7:0] io_cpu_s1_data_mask, // @[HellaCache.scala:243:14] output io_cpu_s2_nack, // @[HellaCache.scala:243:14] output io_cpu_s2_nack_cause_raw, // @[HellaCache.scala:243:14] output io_cpu_s2_uncached, // @[HellaCache.scala:243:14] output [31:0] io_cpu_s2_paddr, // @[HellaCache.scala:243:14] output io_cpu_resp_valid, // @[HellaCache.scala:243:14] output [39:0] io_cpu_resp_bits_addr, // @[HellaCache.scala:243:14] output [6:0] io_cpu_resp_bits_tag, // @[HellaCache.scala:243:14] output [4:0] io_cpu_resp_bits_cmd, // @[HellaCache.scala:243:14] output [1:0] io_cpu_resp_bits_size, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_signed, // @[HellaCache.scala:243:14] output [1:0] io_cpu_resp_bits_dprv, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_dv, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data, // @[HellaCache.scala:243:14] output [7:0] io_cpu_resp_bits_mask, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_replay, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_has_data, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data_word_bypass, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data_raw, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_store_data, // @[HellaCache.scala:243:14] output io_cpu_replay_next, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ma_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ma_st, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_pf_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_pf_st, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ae_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ae_st, // @[HellaCache.scala:243:14] output [39:0] io_cpu_s2_gpa, // @[HellaCache.scala:243:14] output io_cpu_ordered, // @[HellaCache.scala:243:14] output io_cpu_store_pending, // @[HellaCache.scala:243:14] output io_cpu_perf_acquire, // @[HellaCache.scala:243:14] output io_cpu_perf_release, // @[HellaCache.scala:243:14] output io_cpu_perf_grant, // @[HellaCache.scala:243:14] output io_cpu_perf_tlbMiss, // @[HellaCache.scala:243:14] output io_cpu_perf_blocked, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptStoreThenLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptStoreThenRMW, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptLoadThenLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_storeBufferEmptyAfterLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_storeBufferEmptyAfterStore, // @[HellaCache.scala:243:14] input io_cpu_keep_clock_enabled, // @[HellaCache.scala:243:14] input io_ptw_req_ready, // @[HellaCache.scala:243:14] output io_ptw_req_valid, // @[HellaCache.scala:243:14] output [26:0] io_ptw_req_bits_bits_addr, // @[HellaCache.scala:243:14] output io_ptw_req_bits_bits_need_gpa, // @[HellaCache.scala:243:14] input io_ptw_resp_valid, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_ae_ptw, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_ae_final, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pf, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gf, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hr, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hw, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hx, // @[HellaCache.scala:243:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[HellaCache.scala:243:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[HellaCache.scala:243:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_d, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_a, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_g, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_u, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_x, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_w, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_r, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_v, // @[HellaCache.scala:243:14] input [1:0] io_ptw_resp_bits_level, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_homogeneous, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gpa_valid, // @[HellaCache.scala:243:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gpa_is_pte, // @[HellaCache.scala:243:14] input [3:0] io_ptw_ptbr_mode, // @[HellaCache.scala:243:14] input [43:0] io_ptw_ptbr_ppn, // @[HellaCache.scala:243:14] input io_ptw_status_debug, // @[HellaCache.scala:243:14] input io_ptw_status_cease, // @[HellaCache.scala:243:14] input io_ptw_status_wfi, // @[HellaCache.scala:243:14] input [31:0] io_ptw_status_isa, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_dprv, // @[HellaCache.scala:243:14] input io_ptw_status_dv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_prv, // @[HellaCache.scala:243:14] input io_ptw_status_v, // @[HellaCache.scala:243:14] input io_ptw_status_sd, // @[HellaCache.scala:243:14] input io_ptw_status_mpv, // @[HellaCache.scala:243:14] input io_ptw_status_gva, // @[HellaCache.scala:243:14] input io_ptw_status_tsr, // @[HellaCache.scala:243:14] input io_ptw_status_tw, // @[HellaCache.scala:243:14] input io_ptw_status_tvm, // @[HellaCache.scala:243:14] input io_ptw_status_mxr, // @[HellaCache.scala:243:14] input io_ptw_status_sum, // @[HellaCache.scala:243:14] input io_ptw_status_mprv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_fs, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_mpp, // @[HellaCache.scala:243:14] input io_ptw_status_spp, // @[HellaCache.scala:243:14] input io_ptw_status_mpie, // @[HellaCache.scala:243:14] input io_ptw_status_spie, // @[HellaCache.scala:243:14] input io_ptw_status_mie, // @[HellaCache.scala:243:14] input io_ptw_status_sie, // @[HellaCache.scala:243:14] input io_ptw_hstatus_spvp, // @[HellaCache.scala:243:14] input io_ptw_hstatus_spv, // @[HellaCache.scala:243:14] input io_ptw_hstatus_gva, // @[HellaCache.scala:243:14] input io_ptw_gstatus_debug, // @[HellaCache.scala:243:14] input io_ptw_gstatus_cease, // @[HellaCache.scala:243:14] input io_ptw_gstatus_wfi, // @[HellaCache.scala:243:14] input [31:0] io_ptw_gstatus_isa, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_dprv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_dv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_prv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_v, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sd, // @[HellaCache.scala:243:14] input [22:0] io_ptw_gstatus_zero2, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mpv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_gva, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mbe, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sbe, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_sxl, // @[HellaCache.scala:243:14] input [7:0] io_ptw_gstatus_zero1, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tsr, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tw, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tvm, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mxr, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sum, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mprv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_fs, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_mpp, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_vs, // @[HellaCache.scala:243:14] input io_ptw_gstatus_spp, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mpie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_ube, // @[HellaCache.scala:243:14] input io_ptw_gstatus_spie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_upie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_hie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_uie, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_0_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_0_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_1_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_1_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_2_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_2_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_3_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_3_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_4_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_4_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_5_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_5_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_6_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_6_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_7_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_7_mask, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_0_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_0_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_1_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_1_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_2_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_2_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_3_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_3_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[HellaCache.scala:243:14] ); wire [19:0] s2_meta_corrected_7_tag; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_7_coh_state; // @[DCache.scala:361:99] wire rockettile_dcache_tag_array_MPORT_en; // @[DCache.scala:310:27] wire s0_req_phys; // @[DCache.scala:192:24] wire [39:0] s0_req_addr; // @[DCache.scala:192:24] wire tl_out_a_valid; // @[DCache.scala:159:22] wire [127:0] tl_out_a_bits_data; // @[DCache.scala:159:22] wire [15:0] tl_out_a_bits_mask; // @[DCache.scala:159:22] wire [31:0] tl_out_a_bits_address; // @[DCache.scala:159:22] wire tl_out_a_bits_source; // @[DCache.scala:159:22] wire [3:0] tl_out_a_bits_size; // @[DCache.scala:159:22] wire [2:0] tl_out_a_bits_param; // @[DCache.scala:159:22] wire [2:0] tl_out_a_bits_opcode; // @[DCache.scala:159:22] wire [5:0] metaArb_io_out_bits_idx; // @[DCache.scala:135:28] wire metaArb_io_in_0_valid; // @[DCache.scala:135:28] wire [4:0] pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_req_bits_size; // @[DCache.scala:120:32] wire [175:0] _rockettile_dcache_tag_array_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire _lfsr_prng_io_out_0; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_1; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_2; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_3; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_4; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_5; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_6; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_7; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_8; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_9; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_10; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_11; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_12; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_13; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_14; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_15; // @[PRNG.scala:91:22] wire [19:0] _pma_checker_entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_checker_pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_eff; // @[TLB.scala:422:19] wire [19:0] _pma_checker_mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire _tlb_io_req_ready; // @[DCache.scala:119:19] wire _tlb_io_resp_miss; // @[DCache.scala:119:19] wire [31:0] _tlb_io_resp_paddr; // @[DCache.scala:119:19] wire [39:0] _tlb_io_resp_gpa; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_st; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_inst; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_st; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_inst; // @[DCache.scala:119:19] wire _tlb_io_resp_ma_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_ma_st; // @[DCache.scala:119:19] wire _tlb_io_resp_cacheable; // @[DCache.scala:119:19] wire _tlb_io_resp_must_alloc; // @[DCache.scala:119:19] wire _tlb_io_resp_prefetchable; // @[DCache.scala:119:19] wire [1:0] _tlb_io_resp_size; // @[DCache.scala:119:19] wire [4:0] _tlb_io_resp_cmd; // @[DCache.scala:119:19] wire auto_out_a_ready_0 = auto_out_a_ready; // @[DCache.scala:101:7] wire auto_out_b_valid_0 = auto_out_b_valid; // @[DCache.scala:101:7] wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[DCache.scala:101:7] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[DCache.scala:101:7] wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[DCache.scala:101:7] wire auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[DCache.scala:101:7] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[DCache.scala:101:7] wire [15:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[DCache.scala:101:7] wire [127:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[DCache.scala:101:7] wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[DCache.scala:101:7] wire auto_out_c_ready_0 = auto_out_c_ready; // @[DCache.scala:101:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[DCache.scala:101:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[DCache.scala:101:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[DCache.scala:101:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[DCache.scala:101:7] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[DCache.scala:101:7] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[DCache.scala:101:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[DCache.scala:101:7] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[DCache.scala:101:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[DCache.scala:101:7] wire auto_out_e_ready_0 = auto_out_e_ready; // @[DCache.scala:101:7] wire io_cpu_req_valid_0 = io_cpu_req_valid; // @[DCache.scala:101:7] wire [39:0] io_cpu_req_bits_addr_0 = io_cpu_req_bits_addr; // @[DCache.scala:101:7] wire [6:0] io_cpu_req_bits_tag_0 = io_cpu_req_bits_tag; // @[DCache.scala:101:7] wire [4:0] io_cpu_req_bits_cmd_0 = io_cpu_req_bits_cmd; // @[DCache.scala:101:7] wire [1:0] io_cpu_req_bits_size_0 = io_cpu_req_bits_size; // @[DCache.scala:101:7] wire io_cpu_req_bits_signed_0 = io_cpu_req_bits_signed; // @[DCache.scala:101:7] wire [1:0] io_cpu_req_bits_dprv_0 = io_cpu_req_bits_dprv; // @[DCache.scala:101:7] wire io_cpu_req_bits_dv_0 = io_cpu_req_bits_dv; // @[DCache.scala:101:7] wire io_cpu_req_bits_phys_0 = io_cpu_req_bits_phys; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_resp_0 = io_cpu_req_bits_no_resp; // @[DCache.scala:101:7] wire io_cpu_s1_kill_0 = io_cpu_s1_kill; // @[DCache.scala:101:7] wire [63:0] io_cpu_s1_data_data_0 = io_cpu_s1_data_data; // @[DCache.scala:101:7] wire [7:0] io_cpu_s1_data_mask_0 = io_cpu_s1_data_mask; // @[DCache.scala:101:7] wire io_cpu_keep_clock_enabled_0 = io_cpu_keep_clock_enabled; // @[DCache.scala:101:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[DCache.scala:101:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[DCache.scala:101:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[DCache.scala:101:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[DCache.scala:101:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[DCache.scala:101:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[DCache.scala:101:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[DCache.scala:101:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[DCache.scala:101:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[DCache.scala:101:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[DCache.scala:101:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[DCache.scala:101:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[DCache.scala:101:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[DCache.scala:101:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[DCache.scala:101:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[DCache.scala:101:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[DCache.scala:101:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[DCache.scala:101:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[DCache.scala:101:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[DCache.scala:101:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[DCache.scala:101:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[DCache.scala:101:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[DCache.scala:101:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[DCache.scala:101:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[DCache.scala:101:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[DCache.scala:101:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[DCache.scala:101:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[DCache.scala:101:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[DCache.scala:101:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[DCache.scala:101:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[DCache.scala:101:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[DCache.scala:101:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[DCache.scala:101:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[DCache.scala:101:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[DCache.scala:101:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[DCache.scala:101:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[DCache.scala:101:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[DCache.scala:101:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[DCache.scala:101:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[DCache.scala:101:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[DCache.scala:101:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[DCache.scala:101:7] wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[DCache.scala:101:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[DCache.scala:101:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[DCache.scala:101:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[DCache.scala:101:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[DCache.scala:101:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[DCache.scala:101:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[DCache.scala:101:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[DCache.scala:101:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[DCache.scala:101:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[DCache.scala:101:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[DCache.scala:101:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[DCache.scala:101:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[DCache.scala:101:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[DCache.scala:101:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[DCache.scala:101:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[DCache.scala:101:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[DCache.scala:101:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[DCache.scala:101:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[DCache.scala:101:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[DCache.scala:101:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[DCache.scala:101:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[DCache.scala:101:7] wire _dataArb_io_in_3_valid_T_55 = reset; // @[DCache.scala:1186:11] wire _pstore_drain_opportunistic_T_55 = reset; // @[DCache.scala:1186:11] wire auto_out_a_bits_corrupt = 1'h0; // @[DCache.scala:101:7] wire auto_out_c_bits_corrupt = 1'h0; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_alloc = 1'h0; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_xcpt = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_kill = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_gf_ld = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_gf_st = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_gpa_is_pte = 1'h0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_mbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_ube = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_upie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_hie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_uie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_valid = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_bits_passthrough = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_bits_v = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gpa_is_pte = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_ld = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_st = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_inst = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_inst = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s2_kill = 1'h0; // @[DCache.scala:101:7] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire pma_checker_io_req_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_miss = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gpa_is_pte = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_ld = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_st = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_inst = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_inst = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_rs1 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_rs2 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_asid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_hv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_hg = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_ready = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_need_gpa = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_ae_ptw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_ae_final = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pf = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gf = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hx = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_d = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_a = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_g = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_u = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_homogeneous = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gpa_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gpa_is_pte = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_debug = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_cease = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_wfi = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_dv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sd = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mpv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mxr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sum = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mprv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_spp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mpie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_ube = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_spie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_upie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_hie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_uie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_spvp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_spv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_debug = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_cease = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_wfi = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_dv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sd = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mpv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mxr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sum = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mprv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_spp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mpie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_ube = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_spie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_upie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_hie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_uie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_kill = 1'h0; // @[DCache.scala:120:32] wire pma_checker_priv_v = 1'h0; // @[TLB.scala:369:34] wire pma_checker__stage1_en_T = 1'h0; // @[TLB.scala:374:41] wire pma_checker_stage1_en = 1'h0; // @[TLB.scala:374:29] wire pma_checker__vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire pma_checker__vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire pma_checker_vstage1_en = 1'h0; // @[TLB.scala:376:48] wire pma_checker__stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire pma_checker__stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire pma_checker_stage2_en = 1'h0; // @[TLB.scala:378:48] wire pma_checker__vm_enabled_T = 1'h0; // @[TLB.scala:399:31] wire pma_checker__vm_enabled_T_1 = 1'h0; // @[TLB.scala:399:45] wire pma_checker__vm_enabled_T_2 = 1'h0; // @[TLB.scala:399:64] wire pma_checker_vm_enabled = 1'h0; // @[TLB.scala:399:61] wire pma_checker__vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire pma_checker__vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire pma_checker__vsatp_mode_mismatch_T_2 = 1'h0; // @[TLB.scala:403:81] wire pma_checker_vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire pma_checker_do_refill = 1'h0; // @[TLB.scala:408:29] wire pma_checker__invalidate_refill_T = 1'h0; // @[package.scala:16:47] wire pma_checker__invalidate_refill_T_1 = 1'h0; // @[package.scala:16:47] wire pma_checker__invalidate_refill_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker_invalidate_refill = 1'h0; // @[TLB.scala:410:88] wire pma_checker__mpu_ppn_T = 1'h0; // @[TLB.scala:413:32] wire pma_checker_prot_r = 1'h0; // @[TLB.scala:429:55] wire pma_checker_prot_w = 1'h0; // @[TLB.scala:430:55] wire pma_checker_prot_x = 1'h0; // @[TLB.scala:434:55] wire pma_checker__sector_hits_T = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_0 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_8 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_9 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_10 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_1 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_16 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_17 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_18 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_2 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_24 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_25 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_26 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_3 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_32 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_33 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_34 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_4 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_40 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_41 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_42 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_5 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_48 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_49 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_50 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_6 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_56 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_57 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_58 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_7 = 1'h0; // @[TLB.scala:172:55] wire pma_checker_superpage_hits_tagMatch = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_4 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_9 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_0 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_tagMatch_1 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_18 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_23 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_1 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_tagMatch_2 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_32 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_37 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_2 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_tagMatch_3 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_46 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_51 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_3 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_5 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_0 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_11 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_1 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_17 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_2 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_23 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_3 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_29 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_4 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_35 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_5 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_41 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_6 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_47 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_7 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_52 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_57 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_62 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_8 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_1 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_67 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_72 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_77 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_9 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_2 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_82 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_87 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_92 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_10 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_3 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_97 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_102 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_107 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_11 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_4 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_112 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_117 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_122 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_12 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_refill_v = 1'h0; // @[TLB.scala:448:33] wire pma_checker_newEntry_u = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_g = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_ptw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_final = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pf = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_gf = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sx = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hx = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_px = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire pma_checker__newEntry_g_T = 1'h0; // @[TLB.scala:453:25] wire pma_checker__newEntry_ae_stage2_T = 1'h0; // @[TLB.scala:456:53] wire pma_checker__newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire pma_checker__newEntry_sr_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sr_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sr_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sr_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sr_T_5 = 1'h0; // @[PTW.scala:149:35] wire pma_checker__newEntry_sw_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sw_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sw_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sw_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sw_T_5 = 1'h0; // @[PTW.scala:151:35] wire pma_checker__newEntry_sw_T_6 = 1'h0; // @[PTW.scala:151:40] wire pma_checker__newEntry_sx_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sx_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sx_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sx_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sx_T_5 = 1'h0; // @[PTW.scala:153:35] wire pma_checker__waddr_T = 1'h0; // @[TLB.scala:477:45] wire pma_checker__superpage_entries_0_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_1_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_2_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_3_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker_sum = 1'h0; // @[TLB.scala:510:16] wire pma_checker__mxr_T = 1'h0; // @[TLB.scala:518:36] wire pma_checker_mxr = 1'h0; // @[TLB.scala:518:31] wire pma_checker__bad_va_T = 1'h0; // @[TLB.scala:568:21] wire pma_checker_bad_va = 1'h0; // @[TLB.scala:568:34] wire pma_checker_cmd_readx = 1'h0; // @[TLB.scala:575:37] wire pma_checker__gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire pma_checker__gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire pma_checker__gpa_hits_hit_mask_T_1 = 1'h0; // @[TLB.scala:606:60] wire pma_checker_tlb_hit_if_not_gpa_miss = 1'h0; // @[TLB.scala:610:43] wire pma_checker_tlb_hit = 1'h0; // @[TLB.scala:611:40] wire pma_checker__tlb_miss_T_1 = 1'h0; // @[TLB.scala:613:29] wire pma_checker__tlb_miss_T_3 = 1'h0; // @[TLB.scala:613:53] wire pma_checker_tlb_miss = 1'h0; // @[TLB.scala:613:64] wire pma_checker__state_vec_0_set_left_older_T = 1'h0; // @[Replacement.scala:196:43] wire pma_checker__state_vec_0_set_left_older_T_1 = 1'h0; // @[Replacement.scala:196:43] wire pma_checker_state_vec_0_left_subtree_state_1 = 1'h0; // @[package.scala:163:13] wire pma_checker_state_vec_0_right_subtree_state_1 = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__state_vec_0_T_1 = 1'h0; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_2 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_vec_0_T_4 = 1'h0; // @[Replacement.scala:203:16] wire pma_checker__state_vec_0_T_5 = 1'h0; // @[Replacement.scala:207:62] wire pma_checker__state_vec_0_T_6 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_vec_0_set_left_older_T_2 = 1'h0; // @[Replacement.scala:196:43] wire pma_checker_state_vec_0_left_subtree_state_2 = 1'h0; // @[package.scala:163:13] wire pma_checker_state_vec_0_right_subtree_state_2 = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__state_vec_0_T_12 = 1'h0; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_13 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_vec_0_T_15 = 1'h0; // @[Replacement.scala:203:16] wire pma_checker__state_vec_0_T_16 = 1'h0; // @[Replacement.scala:207:62] wire pma_checker__state_vec_0_T_17 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_reg_set_left_older_T = 1'h0; // @[Replacement.scala:196:43] wire pma_checker_state_reg_left_subtree_state = 1'h0; // @[package.scala:163:13] wire pma_checker_state_reg_right_subtree_state = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__state_reg_T = 1'h0; // @[package.scala:163:13] wire pma_checker__state_reg_T_1 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_reg_T_3 = 1'h0; // @[Replacement.scala:203:16] wire pma_checker__state_reg_T_4 = 1'h0; // @[Replacement.scala:207:62] wire pma_checker__state_reg_T_5 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__multipleHits_T_2 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_4 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_1 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_5 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_1 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_7 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_2 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_8 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_9 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_11 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_3 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_13 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_4 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_14 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_2 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_3 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_16 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_1 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_4 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_17 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_18 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_2 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_5 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_19 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_20 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_1 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_23 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_6 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_25 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_7 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_26 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_5 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_6 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_28 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_3 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_8 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_29 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_30 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_2 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_33 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_9 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_34 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_7 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_leftOne_10 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_36 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_3 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_38 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_11 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_39 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_8 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_9 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_41 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_4 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_10 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_42 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_43 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_5 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_11 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_44 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_45 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_6 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_46 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_47 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_48 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits = 1'h0; // @[Misc.scala:183:49] wire pma_checker__io_resp_pf_ld_T = 1'h0; // @[TLB.scala:633:28] wire pma_checker__io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28] wire pma_checker__io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire pma_checker__io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire pma_checker__io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire pma_checker__io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire pma_checker__io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire pma_checker__io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire pma_checker__io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire pma_checker__io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire pma_checker__io_resp_miss_T = 1'h0; // @[TLB.scala:651:29] wire pma_checker__io_resp_miss_T_1 = 1'h0; // @[TLB.scala:651:52] wire pma_checker__io_resp_miss_T_2 = 1'h0; // @[TLB.scala:651:64] wire pma_checker__io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire pma_checker__io_ptw_req_valid_T = 1'h0; // @[TLB.scala:662:29] wire pma_checker_r_superpage_repl_addr_left_subtree_older = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_superpage_repl_addr_left_subtree_state = 1'h0; // @[package.scala:163:13] wire pma_checker_r_superpage_repl_addr_right_subtree_state = 1'h0; // @[Replacement.scala:245:38] wire pma_checker__r_superpage_repl_addr_T = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_superpage_repl_addr_T_1 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_superpage_repl_addr_T_2 = 1'h0; // @[Replacement.scala:250:16] wire pma_checker__r_superpage_repl_addr_T_4 = 1'h0; // @[TLB.scala:757:16] wire pma_checker_r_sectored_repl_addr_left_subtree_older = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_sectored_repl_addr_left_subtree_older_1 = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_sectored_repl_addr_left_subtree_state_1 = 1'h0; // @[package.scala:163:13] wire pma_checker_r_sectored_repl_addr_right_subtree_state_1 = 1'h0; // @[Replacement.scala:245:38] wire pma_checker__r_sectored_repl_addr_T = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_1 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_2 = 1'h0; // @[Replacement.scala:250:16] wire pma_checker_r_sectored_repl_addr_left_subtree_older_2 = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_sectored_repl_addr_left_subtree_state_2 = 1'h0; // @[package.scala:163:13] wire pma_checker_r_sectored_repl_addr_right_subtree_state_2 = 1'h0; // @[Replacement.scala:245:38] wire pma_checker__r_sectored_repl_addr_T_4 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_5 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_6 = 1'h0; // @[Replacement.scala:250:16] wire pma_checker__r_sectored_repl_addr_valids_T = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_3 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_4 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_5 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_6 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_7 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_8 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_9 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_10 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_11 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_12 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_13 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_14 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_15 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_16 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_17 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_18 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_19 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_20 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_21 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_22 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_23 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_T_10 = 1'h0; // @[TLB.scala:757:16] wire pma_checker__r_sectored_hit_valid_T = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_3 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_4 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_5 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_6 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_bits_T_1 = 1'h0; // @[OneHot.scala:32:14] wire pma_checker__r_sectored_hit_bits_T_3 = 1'h0; // @[OneHot.scala:32:14] wire pma_checker__r_sectored_hit_bits_T_5 = 1'h0; // @[CircuitMath.scala:28:8] wire pma_checker__r_superpage_hit_valid_T = 1'h0; // @[package.scala:81:59] wire pma_checker__r_superpage_hit_valid_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_superpage_hit_valid_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_superpage_hit_bits_T_1 = 1'h0; // @[OneHot.scala:32:14] wire pma_checker__r_superpage_hit_bits_T_3 = 1'h0; // @[CircuitMath.scala:28:8] wire pma_checker_hv = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_1 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_1 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_2 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_2 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_3 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_3 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_4 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_4 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_5 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_5 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_6 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_6 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_7 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_7 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_8 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_8 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_9 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_9 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_1 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_10 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_10 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_2 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_11 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_11 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_3 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_12 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_12 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_4 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire metaArb_io_in_1_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_5_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_5_bits_write = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_6_bits_write = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_7_bits_write = 1'h0; // @[DCache.scala:135:28] wire dataArb_io_in_2_bits_write = 1'h0; // @[DCache.scala:152:28] wire dataArb_io_in_3_bits_write = 1'h0; // @[DCache.scala:152:28] wire tl_out_a_bits_corrupt = 1'h0; // @[DCache.scala:159:22] wire nodeOut_a_deq_bits_corrupt = 1'h0; // @[Decoupled.scala:356:21] wire _s1_tlb_req_valid_T = 1'h0; // @[Decoupled.scala:51:35] wire s0_req_no_alloc = 1'h0; // @[DCache.scala:192:24] wire s0_req_no_xcpt = 1'h0; // @[DCache.scala:192:24] wire s1_waw_hazard = 1'h0; // @[DCache.scala:216:27] wire _uncachedInFlight_WIRE_0 = 1'h0; // @[DCache.scala:236:41] wire _dataArb_io_in_3_valid_res_T_4 = 1'h0; // @[DCache.scala:1185:58] wire _dataArb_io_in_3_valid_T_49 = 1'h0; // @[DCache.scala:1191:57] wire dataArb_io_in_3_bits_wordMask_mask_upper_mask = 1'h0; // @[DCache.scala:248:27] wire _s1_did_read_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _tlb_io_kill_T = 1'h0; // @[DCache.scala:272:53] wire _tlb_io_kill_T_1 = 1'h0; // @[DCache.scala:272:33] wire _s2_pma_T_gpa_is_pte = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_ld = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_st = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_inst = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_ma_inst = 1'h0; // @[DCache.scala:349:18] wire s2_meta_error_uncorrectable = 1'h0; // @[DCache.scala:360:66] wire s2_meta_error = 1'h0; // @[DCache.scala:362:83] wire s2_store_merge = 1'h0; // @[DCache.scala:388:28] wire _r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _s2_data_error_T = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_1 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_2 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_3 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_4 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_5 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_6 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_7 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_8 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_9 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_10 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_11 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_12 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_13 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_14 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_15 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_16 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_17 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_18 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_19 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_20 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_21 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_22 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_23 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_24 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_25 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_26 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_27 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_28 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_29 = 1'h0; // @[package.scala:81:59] wire s2_data_error = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_1 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_2 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_3 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_4 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_5 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_6 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_7 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_8 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_9 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_10 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_11 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_12 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_13 = 1'h0; // @[package.scala:81:59] wire s2_data_error_uncorrectable = 1'h0; // @[package.scala:81:59] wire s2_valid_data_error = 1'h0; // @[DCache.scala:421:63] wire s2_cannot_victimize = 1'h0; // @[DCache.scala:428:45] wire _r_T_73 = 1'h0; // @[Misc.scala:38:9] wire _r_T_77 = 1'h0; // @[Misc.scala:38:9] wire _r_T_81 = 1'h0; // @[Misc.scala:38:9] wire _r_T_119 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_121 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_137 = 1'h0; // @[Misc.scala:38:9] wire _r_T_141 = 1'h0; // @[Misc.scala:38:9] wire _r_T_145 = 1'h0; // @[Misc.scala:38:9] wire _s2_dont_nack_misc_T_2 = 1'h0; // @[DCache.scala:442:23] wire _s2_dont_nack_misc_T_3 = 1'h0; // @[DCache.scala:442:43] wire _s2_dont_nack_misc_T_5 = 1'h0; // @[DCache.scala:442:54] wire _s2_dont_nack_misc_T_6 = 1'h0; // @[DCache.scala:443:23] wire _s2_dont_nack_misc_T_8 = 1'h0; // @[DCache.scala:443:44] wire _s2_dont_nack_misc_T_9 = 1'h0; // @[DCache.scala:442:67] wire _s2_first_meta_corrected_T = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_1 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_2 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_3 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_4 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_5 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_6 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_7 = 1'h0; // @[Mux.scala:52:83] wire _metaArb_io_in_1_valid_T_2 = 1'h0; // @[DCache.scala:450:43] wire _metaArb_io_in_1_bits_way_en_T = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_1 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_2 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_3 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_4 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_5 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_6 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_7 = 1'h0; // @[OneHot.scala:85:71] wire _s2_correct_T_1 = 1'h0; // @[DCache.scala:487:34] wire _s2_correct_T_4 = 1'h0; // @[DCache.scala:487:55] wire s2_correct = 1'h0; // @[DCache.scala:487:97] wire _s2_valid_correct_T = 1'h0; // @[DCache.scala:489:60] wire s2_valid_correct = 1'h0; // @[DCache.scala:489:74] wire _pstore1_rmw_T_49 = 1'h0; // @[DCache.scala:1191:57] wire pstore1_merge_likely = 1'h0; // @[DCache.scala:499:68] wire pstore1_merge = 1'h0; // @[DCache.scala:500:38] wire _pstore_drain_opportunistic_res_T_4 = 1'h0; // @[DCache.scala:1185:58] wire _pstore_drain_opportunistic_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _pstore_drain_opportunistic_T_60 = 1'h0; // @[DCache.scala:502:106] wire pstore_drain_s2_kill = 1'h0; // @[DCache.scala:515:25] wire _pstore2_storegen_data_T_2 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_6 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_10 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_14 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_18 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_22 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_26 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_30 = 1'h0; // @[DCache.scala:528:95] wire dataArb_io_in_0_valid_s2_kill = 1'h0; // @[DCache.scala:515:25] wire _io_cpu_s2_nack_cause_raw_T_2 = 1'h0; // @[DCache.scala:574:57] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire get_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _put_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _put_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire put_corrupt = 1'h0; // @[Edges.scala:480:17] wire put_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _putpartial_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _putpartial_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire putpartial_corrupt = 1'h0; // @[Edges.scala:500:17] wire _atomics_WIRE_source = 1'h0; // @[DCache.scala:587:51] wire _atomics_WIRE_corrupt = 1'h0; // @[DCache.scala:587:51] wire _atomics_WIRE_1_source = 1'h0; // @[DCache.scala:587:38] wire _atomics_WIRE_1_corrupt = 1'h0; // @[DCache.scala:587:38] wire _atomics_legal_T_34 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_40 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_93 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_99 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_152 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_158 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_2 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_211 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_217 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_3 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_270 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_276 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_4 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_329 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_335 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_5 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_388 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_394 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_6 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_447 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_453 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_7 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_506 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_512 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_8 = 1'h0; // @[Misc.scala:206:21] wire _atomics_T_1_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_3_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_5_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_7_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_9_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_11_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_13_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_15_corrupt = 1'h0; // @[DCache.scala:587:81] wire atomics_corrupt = 1'h0; // @[DCache.scala:587:81] wire _tl_out_a_valid_T_8 = 1'h0; // @[DCache.scala:607:44] wire _tl_out_a_valid_T_9 = 1'h0; // @[DCache.scala:607:65] wire _tl_out_a_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _tl_out_a_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _tl_out_a_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire tl_out_a_bits_a_source = 1'h0; // @[Edges.scala:346:17] wire tl_out_a_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire tl_out_a_bits_a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _tl_out_a_bits_a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire tl_out_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _tl_out_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_T_6_corrupt = 1'h0; // @[DCache.scala:611:8] wire _tl_out_a_bits_T_7_corrupt = 1'h0; // @[DCache.scala:610:8] wire _tl_out_a_bits_T_8_corrupt = 1'h0; // @[DCache.scala:609:8] wire _tl_out_a_bits_T_9_corrupt = 1'h0; // @[DCache.scala:608:23] wire nackResponseMessage_corrupt = 1'h0; // @[Edges.scala:416:17] wire cleanReleaseMessage_corrupt = 1'h0; // @[Edges.scala:416:17] wire dirtyReleaseMessage_corrupt = 1'h0; // @[Edges.scala:433:17] wire _nodeOut_c_valid_T = 1'h0; // @[DCache.scala:810:48] wire _nodeOut_c_valid_T_2 = 1'h0; // @[DCache.scala:810:74] wire _discard_line_T_2 = 1'h0; // @[DCache.scala:818:102] wire _release_state_T_2 = 1'h0; // @[DCache.scala:820:28] wire _release_state_T_4 = 1'h0; // @[DCache.scala:820:54] wire _release_state_T_5 = 1'h0; // @[DCache.scala:820:75] wire _release_state_T_7 = 1'h0; // @[DCache.scala:820:98] wire _release_state_T_12 = 1'h0; // @[DCache.scala:820:127] wire probe_bits_res_source = 1'h0; // @[DCache.scala:1202:19] wire probe_bits_res_corrupt = 1'h0; // @[DCache.scala:1202:19] wire _nodeOut_c_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_c_bits_legal_T_1 = 1'h0; // @[Parameters.scala:137:31] wire _nodeOut_c_bits_legal_T_10 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_15 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_25 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_30 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_31 = 1'h0; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_32 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_legal = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_c_source = 1'h0; // @[Edges.scala:380:17] wire nodeOut_c_bits_c_corrupt = 1'h0; // @[Edges.scala:380:17] wire _nodeOut_c_bits_legal_T_34 = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_c_bits_legal_T_35 = 1'h0; // @[Parameters.scala:137:31] wire _nodeOut_c_bits_legal_T_44 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_49 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_52 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_59 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_64 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_65 = 1'h0; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_66 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_67 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_legal_1 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_c_1_source = 1'h0; // @[Edges.scala:396:17] wire nodeOut_c_bits_c_1_corrupt = 1'h0; // @[Edges.scala:396:17] wire _nodeOut_c_bits_corrupt_T = 1'h0; // @[DCache.scala:887:42] wire _io_cpu_s2_xcpt_WIRE_miss = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gpa_is_pte = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_cacheable = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_must_alloc = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_prefetchable = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_T_gpa_is_pte = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_ld = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_st = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_inst = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ma_inst = 1'h0; // @[DCache.scala:933:24] wire _s2_data_word_possibly_uncached_T = 1'h0; // @[DCache.scala:972:73] wire io_cpu_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_cpu_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_cpu_resp_bits_data_word_bypass_doZero = 1'h0; // @[AMOALU.scala:43:31] wire _s1_flush_valid_T = 1'h0; // @[Decoupled.scala:51:35] wire _s1_flush_valid_T_2 = 1'h0; // @[DCache.scala:1014:43] wire _s1_flush_valid_T_4 = 1'h0; // @[DCache.scala:1014:62] wire _s1_flush_valid_T_6 = 1'h0; // @[DCache.scala:1014:93] wire _s1_flush_valid_T_8 = 1'h0; // @[DCache.scala:1014:122] wire _metaArb_io_in_5_valid_T = 1'h0; // @[DCache.scala:1015:41] wire _metaArb_io_in_5_valid_T_1 = 1'h0; // @[DCache.scala:1015:38] wire _clock_en_reg_T_17 = 1'h0; // @[DCache.scala:1070:25] wire _io_cpu_perf_canAcceptLoadThenLoad_T_50 = 1'h0; // @[DCache.scala:1191:57] wire io_cpu_clock_enabled = 1'h1; // @[DCache.scala:101:7] wire io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:101:7] wire io_tlb_port_req_ready = 1'h1; // @[DCache.scala:101:7] wire pma_checker_io_req_ready = 1'h1; // @[DCache.scala:120:32] wire pma_checker_io_req_bits_passthrough = 1'h1; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:120:32] wire pma_checker__mpu_ppn_ignore_T = 1'h1; // @[TLB.scala:197:28] wire pma_checker_mpu_ppn_ignore = 1'h1; // @[TLB.scala:197:34] wire pma_checker__mpu_ppn_ignore_T_1 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_mpu_ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__mpu_priv_T = 1'h1; // @[TLB.scala:415:52] wire pma_checker__mpu_priv_T_1 = 1'h1; // @[TLB.scala:415:38] wire pma_checker__homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire pma_checker__deny_access_to_debug_T = 1'h1; // @[TLB.scala:428:39] wire pma_checker__sector_hits_T_6 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_14 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_22 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_30 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_38 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_46 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_54 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_62 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__superpage_hits_tagMatch_T = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_1 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_2 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__superpage_hits_tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_4 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_5 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__superpage_hits_tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_7 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_8 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__superpage_hits_tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_10 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_11 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_T_3 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_9 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_15 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_21 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_27 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_33 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_39 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_45 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_tagMatch_T = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_1 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_2 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_4 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_5 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_7 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_8 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_10 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_11 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_4 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_13 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_13 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_116 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_ignore_T_14 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_14 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_121 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hits_T = 1'h1; // @[TLB.scala:442:18] wire pma_checker__newEntry_sr_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__newEntry_sw_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__newEntry_sx_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__ppn_T = 1'h1; // @[TLB.scala:502:30] wire pma_checker__ppn_ignore_T = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_1 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_2 = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_3 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_4 = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_5 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_6 = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_7 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_8 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_8 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_9 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_9 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__stage1_bypass_T_1 = 1'h1; // @[TLB.scala:517:83] wire pma_checker__stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire pma_checker__bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire pma_checker__gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire pma_checker__tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire pma_checker__tlb_miss_T_2 = 1'h1; // @[TLB.scala:613:56] wire pma_checker__tlb_miss_T_4 = 1'h1; // @[TLB.scala:613:67] wire pma_checker_state_vec_0_set_left_older = 1'h1; // @[Replacement.scala:196:33] wire pma_checker_state_vec_0_set_left_older_1 = 1'h1; // @[Replacement.scala:196:33] wire pma_checker__state_vec_0_T_3 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_7 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_8 = 1'h1; // @[Replacement.scala:206:16] wire pma_checker_state_vec_0_set_left_older_2 = 1'h1; // @[Replacement.scala:196:33] wire pma_checker__state_vec_0_T_14 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_18 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_19 = 1'h1; // @[Replacement.scala:206:16] wire pma_checker_state_reg_set_left_older = 1'h1; // @[Replacement.scala:196:33] wire pma_checker__state_reg_T_2 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_reg_T_6 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_reg_T_7 = 1'h1; // @[Replacement.scala:206:16] wire pma_checker__io_req_ready_T = 1'h1; // @[TLB.scala:631:25] wire pma_checker__io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire pma_checker__io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire pma_checker__r_superpage_repl_addr_T_6 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_superpage_repl_addr_T_7 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_superpage_repl_addr_T_8 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_superpage_repl_addr_T_9 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_12 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_13 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_14 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_15 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_16 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_17 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_18 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_19 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__tagMatch_T = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_1 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_2 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_4 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_5 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_7 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_8 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_10 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_11 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_4 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_13 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_13 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__ignore_T_14 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_14 = 1'h1; // @[TLB.scala:182:34] wire metaArb_io_in_0_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_0_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_1_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_2_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_3_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_4_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_out_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire dataArb_io_in_0_ready = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_out_ready = 1'h1; // @[DCache.scala:152:28] wire dataArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire _dataArb_io_in_3_bits_wordMask_mask_upper_mask_T = 1'h1; // @[DCache.scala:248:76] wire _dataArb_io_in_3_bits_wordMask_mask_upper_mask_T_1 = 1'h1; // @[DCache.scala:248:52] wire _s2_valid_not_killed_T = 1'h1; // @[DCache.scala:338:48] wire _s2_flush_valid_T = 1'h1; // @[DCache.scala:363:54] wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T = 1'h1; // @[DCache.scala:397:74] wire _s2_valid_hit_pre_data_ecc_and_waw_T_1 = 1'h1; // @[DCache.scala:418:108] wire _s2_valid_hit_pre_data_ecc_T = 1'h1; // @[DCache.scala:420:73] wire _s2_valid_hit_pre_data_ecc_T_1 = 1'h1; // @[DCache.scala:420:88] wire _s2_valid_hit_T = 1'h1; // @[DCache.scala:422:51] wire _s2_valid_miss_T_1 = 1'h1; // @[DCache.scala:423:58] wire _s2_victimize_T = 1'h1; // @[DCache.scala:429:43] wire _r_T_117 = 1'h1; // @[Metadata.scala:140:24] wire _s2_dont_nack_misc_T = 1'h1; // @[DCache.scala:441:46] wire _s2_dont_nack_misc_T_4 = 1'h1; // @[DCache.scala:442:57] wire _metaArb_io_in_2_bits_write_T = 1'h1; // @[DCache.scala:463:34] wire _s2_valid_correct_T_1 = 1'h1; // @[DCache.scala:489:77] wire _pstore1_merge_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore_drain_opportunistic_T_61 = 1'h1; // @[DCache.scala:502:95] wire _pstore1_valid_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore_drain_T = 1'h1; // @[DCache.scala:516:5] wire _pstore_drain_T_3 = 1'h1; // @[DCache.scala:506:87] wire _pstore1_held_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore1_held_T_5 = 1'h1; // @[DCache.scala:521:38] wire _dataArb_io_in_0_valid_T = 1'h1; // @[DCache.scala:516:5] wire _dataArb_io_in_0_valid_T_3 = 1'h1; // @[DCache.scala:506:87] wire _io_cpu_s2_nack_cause_raw_T = 1'h1; // @[DCache.scala:574:59] wire _io_cpu_s2_nack_cause_raw_T_1 = 1'h1; // @[DCache.scala:574:74] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _putpartial_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _putpartial_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _putpartial_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _putpartial_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _putpartial_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _putpartial_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _putpartial_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _putpartial_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_41 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_42 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_43 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_44 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_59 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_60 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_61 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_62 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_100 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_101 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_102 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_103 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_118 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_119 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_120 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_121 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_159 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_160 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_161 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_162 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_177 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_178 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_179 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_180 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_218 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_219 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_220 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_221 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_236 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_237 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_238 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_239 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_277 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_278 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_279 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_280 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_295 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_296 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_297 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_298 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_336 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_337 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_338 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_339 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_354 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_355 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_356 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_357 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_395 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_396 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_397 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_398 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_413 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_414 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_415 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_416 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_454 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_455 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_456 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_457 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_472 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_473 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_474 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_475 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_513 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_514 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_515 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_516 = 1'h1; // @[Parameters.scala:684:29] wire _tl_out_a_valid_T = 1'h1; // @[DCache.scala:603:21] wire _tl_out_a_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _tl_out_a_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire tl_out_a_bits_a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire tl_out_a_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire tl_out_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire tl_out_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _nodeOut_c_bits_legal_T_5 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_16 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_17 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _nodeOut_c_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_c_bits_legal_T_39 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_50 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_51 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_53 = 1'h1; // @[Parameters.scala:91:44] wire _nodeOut_c_bits_legal_T_54 = 1'h1; // @[Parameters.scala:684:29] wire _io_cpu_ordered_T = 1'h1; // @[DCache.scala:929:35] wire _s1_xcpt_valid_T = 1'h1; // @[DCache.scala:932:43] wire _io_cpu_resp_valid_T_1 = 1'h1; // @[DCache.scala:949:73] wire _io_cpu_replay_next_T_2 = 1'h1; // @[DCache.scala:950:65] wire _clock_en_reg_T = 1'h1; // @[DCache.scala:1060:19] wire _clock_en_reg_T_2 = 1'h1; // @[DCache.scala:1060:44] wire _clock_en_reg_T_3 = 1'h1; // @[DCache.scala:1061:46] wire _clock_en_reg_T_4 = 1'h1; // @[DCache.scala:1062:31] wire _clock_en_reg_T_5 = 1'h1; // @[DCache.scala:1063:26] wire _clock_en_reg_T_6 = 1'h1; // @[DCache.scala:1064:14] wire _clock_en_reg_T_7 = 1'h1; // @[DCache.scala:1064:26] wire _clock_en_reg_T_8 = 1'h1; // @[DCache.scala:1065:14] wire _clock_en_reg_T_9 = 1'h1; // @[DCache.scala:1065:26] wire _clock_en_reg_T_10 = 1'h1; // @[DCache.scala:1066:27] wire _clock_en_reg_T_11 = 1'h1; // @[DCache.scala:1067:22] wire _clock_en_reg_T_12 = 1'h1; // @[DCache.scala:1067:42] wire _clock_en_reg_T_13 = 1'h1; // @[DCache.scala:1068:18] wire _clock_en_reg_T_15 = 1'h1; // @[DCache.scala:1068:35] wire _clock_en_reg_T_16 = 1'h1; // @[DCache.scala:1069:31] wire _clock_en_reg_T_18 = 1'h1; // @[DCache.scala:1070:22] wire _clock_en_reg_T_20 = 1'h1; // @[DCache.scala:1070:46] wire _clock_en_reg_T_21 = 1'h1; // @[DCache.scala:1071:23] wire _clock_en_reg_T_23 = 1'h1; // @[DCache.scala:1072:23] wire _clock_en_reg_T_25 = 1'h1; // @[DCache.scala:1072:54] wire _clock_en_reg_T_27 = 1'h1; // @[DCache.scala:1073:21] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_2 = 1'h1; // @[DCache.scala:1082:31] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_5 = 1'h1; // @[DCache.scala:1087:31] wire _io_cpu_perf_canAcceptStoreThenLoad_T_3 = 1'h1; // @[DCache.scala:1089:72] wire _io_cpu_perf_canAcceptLoadThenLoad_T_56 = 1'h1; // @[DCache.scala:1092:115] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] pma_checker_io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_satp_asid = 16'h0; // @[TLB.scala:373:17] wire [15:0] _atomics_WIRE_mask = 16'h0; // @[DCache.scala:587:51] wire [15:0] _atomics_WIRE_1_mask = 16'h0; // @[DCache.scala:587:38] wire [15:0] probe_bits_res_mask = 16'h0; // @[DCache.scala:1202:19] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:101:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:101:7] wire [3:0] pma_checker_io_ptw_ptbr_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_satp_mode = 4'h0; // @[TLB.scala:373:17] wire [3:0] pma_checker_real_hits_hi_hi = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_lo = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_hi = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_hi_1 = 4'h0; // @[OneHot.scala:30:18] wire [3:0] pma_checker_lo_1 = 4'h0; // @[OneHot.scala:31:18] wire [3:0] pma_checker__multipleHits_T_31 = 4'h0; // @[Misc.scala:182:39] wire [3:0] pma_checker_r_superpage_repl_addr_valids = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_r_sectored_repl_addr_valids_lo = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_r_sectored_repl_addr_valids_hi = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_r_sectored_hit_bits_lo = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_r_sectored_hit_bits_hi = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_r_sectored_hit_bits_hi_1 = 4'h0; // @[OneHot.scala:30:18] wire [3:0] pma_checker_r_sectored_hit_bits_lo_1 = 4'h0; // @[OneHot.scala:31:18] wire [3:0] pma_checker__r_sectored_hit_bits_T_2 = 4'h0; // @[OneHot.scala:32:28] wire [3:0] pma_checker__r_superpage_hit_bits_T = 4'h0; // @[OneHot.scala:21:45] wire [3:0] s2_meta_correctable_errors_lo = 4'h0; // @[package.scala:45:27] wire [3:0] s2_meta_correctable_errors_hi = 4'h0; // @[package.scala:45:27] wire [3:0] s2_meta_uncorrectable_errors_lo = 4'h0; // @[package.scala:45:27] wire [3:0] s2_meta_uncorrectable_errors_hi = 4'h0; // @[package.scala:45:27] wire [3:0] _r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_63 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_127 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _atomics_WIRE_size = 4'h0; // @[DCache.scala:587:51] wire [3:0] _atomics_WIRE_1_size = 4'h0; // @[DCache.scala:587:38] wire [3:0] _metaArb_io_in_3_bits_data_T_5 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] probe_bits_res_size = 4'h0; // @[DCache.scala:1202:19] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:101:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:101:7] wire [43:0] pma_checker_io_ptw_resp_bits_pte_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_ptbr_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_satp_ppn = 44'h0; // @[TLB.scala:373:17] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[DCache.scala:101:7] wire [22:0] pma_checker_io_ptw_status_zero2 = 23'h0; // @[DCache.scala:120:32] wire [22:0] pma_checker_io_ptw_gstatus_zero2 = 23'h0; // @[DCache.scala:120:32] wire [7:0] io_cpu_req_bits_mask = 8'h0; // @[DCache.scala:101:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[DCache.scala:101:7] wire [7:0] pma_checker_io_ptw_status_zero1 = 8'h0; // @[DCache.scala:120:32] wire [7:0] pma_checker_io_ptw_gstatus_zero1 = 8'h0; // @[DCache.scala:120:32] wire [7:0] pma_checker_r_sectored_repl_addr_valids = 8'h0; // @[package.scala:45:27] wire [7:0] pma_checker__r_sectored_hit_bits_T = 8'h0; // @[OneHot.scala:21:45] wire [7:0] metaArb_io_in_1_bits_way_en = 8'h0; // @[DCache.scala:135:28] wire [7:0] s0_req_mask = 8'h0; // @[DCache.scala:192:24] wire [7:0] s2_meta_correctable_errors = 8'h0; // @[package.scala:45:27] wire [7:0] s2_meta_uncorrectable_errors = 8'h0; // @[package.scala:45:27] wire [7:0] _s2_meta_error_T = 8'h0; // @[DCache.scala:362:53] wire [7:0] _metaArb_io_in_1_bits_way_en_T_8 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_9 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_10 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_11 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_12 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_13 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_14 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_15 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_16 = 8'h0; // @[DCache.scala:452:69] wire [7:0] _metaArb_io_in_1_bits_way_en_T_17 = 8'h0; // @[DCache.scala:452:64] wire [7:0] _pstore2_storegen_mask_mergedMask_T = 8'h0; // @[DCache.scala:533:42] wire [1:0] io_ptw_status_xs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_req_bits_size = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_req_bits_prv = 2'h0; // @[DCache.scala:101:7] wire [1:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_software = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_resp_bits_level = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_dprv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_prv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_sxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_uxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_xs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_fs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_mpp = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_vs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_vsxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_dprv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_prv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_sxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_uxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_fs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_mpp = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_vs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_0_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_1_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_2_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_3_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_4_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_5_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_6_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_7_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_real_hits_lo_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_lo_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker__special_entry_level_T = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_special_entry_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_waddr = 2'h0; // @[TLB.scala:477:22] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_1 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_2 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_3 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_4 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_5 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_6 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_7 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker__pr_array_T = 2'h0; // @[TLB.scala:529:26] wire [1:0] pma_checker__pw_array_T = 2'h0; // @[TLB.scala:531:26] wire [1:0] pma_checker__px_array_T = 2'h0; // @[TLB.scala:533:26] wire [1:0] pma_checker_lo_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_lo_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_2 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_lo_2 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker__state_vec_0_T = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker__state_vec_0_T_11 = 2'h0; // @[Replacement.scala:207:62] wire [1:0] pma_checker_lo_3 = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_3 = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_4 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_lo_4 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker_state_reg_touch_way_sized = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker__multipleHits_T_3 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_12 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_24 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_32 = 2'h0; // @[Misc.scala:181:37] wire [1:0] pma_checker__multipleHits_T_37 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__r_superpage_repl_addr_T_3 = 2'h0; // @[Replacement.scala:249:12] wire [1:0] pma_checker_r_superpage_repl_addr_valids_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_superpage_repl_addr_valids_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker__r_superpage_repl_addr_T_12 = 2'h0; // @[Mux.scala:50:70] wire [1:0] pma_checker__r_superpage_repl_addr_T_13 = 2'h0; // @[TLB.scala:757:8] wire [1:0] pma_checker__r_sectored_repl_addr_T_3 = 2'h0; // @[Replacement.scala:249:12] wire [1:0] pma_checker__r_sectored_repl_addr_T_7 = 2'h0; // @[Replacement.scala:249:12] wire [1:0] pma_checker__r_sectored_repl_addr_T_8 = 2'h0; // @[Replacement.scala:250:16] wire [1:0] pma_checker_r_sectored_repl_addr_valids_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_repl_addr_valids_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_repl_addr_valids_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_repl_addr_valids_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_hit_bits_lo_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_lo_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_hi_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_hi_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_hi_2 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_r_sectored_hit_bits_lo_2 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker__r_sectored_hit_bits_T_4 = 2'h0; // @[OneHot.scala:32:28] wire [1:0] pma_checker__r_sectored_hit_bits_T_6 = 2'h0; // @[OneHot.scala:32:10] wire [1:0] pma_checker_r_superpage_hit_bits_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_superpage_hit_bits_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_superpage_hit_bits_hi_1 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_r_superpage_hit_bits_lo_1 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker__r_superpage_hit_bits_T_2 = 2'h0; // @[OneHot.scala:32:28] wire [1:0] pma_checker__r_superpage_hit_bits_T_4 = 2'h0; // @[OneHot.scala:32:10] wire [1:0] s1_meta_hit_state_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _s2_valid_no_xcpt_T_1 = 2'h0; // @[DCache.scala:332:54] wire [1:0] s2_meta_correctable_errors_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_correctable_errors_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_correctable_errors_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_correctable_errors_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] _r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_75 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_79 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_83 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_87 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_91 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_139 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_143 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_147 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_151 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_155 = 2'h0; // @[Misc.scala:38:63] wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _metaArb_io_in_3_bits_data_T_2 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _metaArb_io_in_3_bits_data_T_4 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] probe_bits_res_param = 2'h0; // @[DCache.scala:1202:19] wire [1:0] _nodeOut_c_bits_legal_T_2 = 2'h0; // @[Parameters.scala:137:41] wire [1:0] _nodeOut_c_bits_legal_T_36 = 2'h0; // @[Parameters.scala:137:41] wire [1:0] _io_cpu_s2_xcpt_WIRE_size = 2'h0; // @[DCache.scala:933:74] wire [1:0] metaArb_io_in_0_bits_data_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] metaArb_io_in_0_bits_data_meta_1_coh_state = 2'h0; // @[HellaCache.scala:305:20] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:101:7] wire [29:0] pma_checker_io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_0_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_1_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_2_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_3_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_4_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_5_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_6_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_7_addr = 30'h0; // @[DCache.scala:120:32] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:101:7] wire [8:0] pma_checker_io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:120:32] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:101:7] wire [5:0] pma_checker_io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:120:32] wire [5:0] pma_checker_real_hits_lo = 6'h0; // @[package.scala:45:27] wire [5:0] pma_checker_special_entry_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_0_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_1_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_2_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_3_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_0_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_1_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_2_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_3_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_4_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_5_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_6_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_7_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker__multipleHits_T = 6'h0; // @[Misc.scala:181:37] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:101:7] wire [4:0] io_tlb_port_req_bits_cmd = 5'h0; // @[DCache.scala:101:7] wire [4:0] pma_checker_io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:120:32] wire [4:0] _io_cpu_s2_xcpt_WIRE_cmd = 5'h0; // @[DCache.scala:933:74] wire [7:0] pma_checker__r_sectored_repl_addr_T_11 = 8'hFF; // @[TLB.scala:757:43] wire [7:0] metaArb_io_in_0_bits_way_en = 8'hFF; // @[DCache.scala:135:28] wire [7:0] dataArb_io_in_1_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_2_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_2_bits_way_en = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_3_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_3_bits_way_en = 8'hFF; // @[DCache.scala:152:28] wire [7:0] _dataArb_io_in_3_bits_eccMask_T = 8'hFF; // @[DCache.scala:256:36] wire [7:0] _dataArb_io_in_3_bits_way_en_T = 8'hFF; // @[DCache.scala:257:35] wire [7:0] tl_out_a_bits_a_mask_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] tl_out_a_bits_a_mask_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] _dataArb_io_in_1_bits_eccMask_T = 8'hFF; // @[DCache.scala:732:38] wire [7:0] _dataArb_io_in_2_bits_eccMask_T = 8'hFF; // @[DCache.scala:905:36] wire [7:0] _dataArb_io_in_2_bits_way_en_T = 8'hFF; // @[DCache.scala:906:35] wire [7:0] _metaArb_io_in_0_bits_way_en_T = 8'hFF; // @[DCache.scala:1049:35] wire [2:0] pma_checker__r_sectored_repl_addr_T_20 = 3'h6; // @[Mux.scala:50:70] wire [2:0] tl_out_a_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] nodeOut_c_bits_c_opcode = 3'h6; // @[Edges.scala:380:17] wire [2:0] pma_checker_real_hits_lo_lo = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_real_hits_lo_hi = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_real_hits_hi_lo = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_special_entry_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_waddr_1 = 3'h0; // @[TLB.scala:485:22] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_state_vec_0_touch_way_sized = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_state_vec_0_left_subtree_state = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_state_vec_0_right_subtree_state = 3'h0; // @[Replacement.scala:198:38] wire [2:0] pma_checker__state_vec_0_T_10 = 3'h0; // @[Replacement.scala:203:16] wire [2:0] pma_checker__multipleHits_T_1 = 3'h0; // @[Misc.scala:181:37] wire [2:0] pma_checker__multipleHits_T_10 = 3'h0; // @[Misc.scala:182:39] wire [2:0] pma_checker__multipleHits_T_22 = 3'h0; // @[Misc.scala:181:37] wire [2:0] pma_checker_r_sectored_repl_addr_left_subtree_state = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_r_sectored_repl_addr_right_subtree_state = 3'h0; // @[Replacement.scala:245:38] wire [2:0] pma_checker__r_sectored_repl_addr_T_9 = 3'h0; // @[Replacement.scala:249:12] wire [2:0] pma_checker__r_sectored_repl_addr_T_26 = 3'h0; // @[Mux.scala:50:70] wire [2:0] pma_checker__r_sectored_repl_addr_T_27 = 3'h0; // @[TLB.scala:757:8] wire [2:0] pma_checker__r_sectored_hit_bits_T_7 = 3'h0; // @[OneHot.scala:32:10] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] putpartial_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[DCache.scala:587:51] wire [2:0] _atomics_WIRE_param = 3'h0; // @[DCache.scala:587:51] wire [2:0] _atomics_WIRE_1_opcode = 3'h0; // @[DCache.scala:587:38] wire [2:0] _atomics_WIRE_1_param = 3'h0; // @[DCache.scala:587:38] wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17] wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17] wire [2:0] probe_bits_res_opcode = 3'h0; // @[DCache.scala:1202:19] wire [2:0] pma_checker__state_vec_0_T_9 = 3'h5; // @[Replacement.scala:202:12] wire [2:0] pma_checker__state_vec_0_T_20 = 3'h5; // @[Replacement.scala:202:12] wire [2:0] pma_checker__state_vec_0_T_21 = 3'h5; // @[Replacement.scala:206:16] wire [2:0] pma_checker__state_reg_T_8 = 3'h5; // @[Replacement.scala:202:12] wire [2:0] pma_checker__r_sectored_repl_addr_T_21 = 3'h5; // @[Mux.scala:50:70] wire [2:0] nackResponseMessage_param = 3'h5; // @[Edges.scala:416:17] wire [2:0] dirtyReleaseMessage_opcode = 3'h5; // @[Edges.scala:433:17] wire [2:0] pma_checker__r_sectored_repl_addr_T_22 = 3'h4; // @[Mux.scala:50:70] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17] wire [2:0] nackResponseMessage_opcode = 3'h4; // @[Edges.scala:416:17] wire [2:0] cleanReleaseMessage_opcode = 3'h4; // @[Edges.scala:416:17] wire [1:0] pma_checker__r_superpage_repl_addr_T_11 = 2'h1; // @[Mux.scala:50:70] wire [1:0] _r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _metaArb_io_in_3_bits_data_T_6 = 2'h1; // @[Metadata.scala:25:15] wire [3:0] pma_checker__r_superpage_repl_addr_T_5 = 4'hF; // @[TLB.scala:757:43] wire [3:0] _r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] tl_out_a_bits_a_mask_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] tl_out_a_bits_a_mask_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] tl_out_a_bits_a_mask_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] tl_out_a_bits_a_mask_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [1:0] io_ptw_status_sxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] pma_checker_state_vec_0_hi = 2'h2; // @[Replacement.scala:202:12] wire [1:0] pma_checker_state_vec_0_hi_1 = 2'h2; // @[Replacement.scala:202:12] wire [1:0] pma_checker_state_reg_hi = 2'h2; // @[Replacement.scala:202:12] wire [1:0] pma_checker__r_superpage_repl_addr_T_10 = 2'h2; // @[Mux.scala:50:70] wire [1:0] pma_checker__state_T = 2'h2; // @[TLB.scala:704:45] wire [1:0] _r_T_118 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_120 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_122 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] tl_out_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [2:0] pma_checker__r_sectored_repl_addr_T_23 = 3'h3; // @[Mux.scala:50:70] wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17] wire [2:0] pma_checker__r_sectored_repl_addr_T_24 = 3'h2; // @[Mux.scala:50:70] wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] pma_checker_mpu_priv = 3'h1; // @[TLB.scala:415:27] wire [2:0] pma_checker__r_sectored_repl_addr_T_25 = 3'h1; // @[Mux.scala:50:70] wire [2:0] putpartial_opcode = 3'h1; // @[Edges.scala:500:17] wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17] wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17] wire [3:0] pma_checker_state_vec_0_hi_2 = 4'h8; // @[Replacement.scala:202:12] wire [3:0] _r_T_71 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_135 = 4'h8; // @[Metadata.scala:133:10] wire [11:0] pma_checker__gpa_hits_hit_mask_T_2 = 12'h0; // @[TLB.scala:606:24] wire [11:0] pma_checker__io_resp_gpa_offset_T = 12'h0; // @[TLB.scala:658:47] wire [26:0] pma_checker_io_ptw_req_bits_bits_addr = 27'h0; // @[DCache.scala:120:32] wire [26:0] pma_checker__io_resp_gpa_page_T_2 = 27'h0; // @[TLB.scala:657:58] wire [6:0] pma_checker__state_vec_0_T_22 = 7'h45; // @[Replacement.scala:202:12] wire [63:0] io_cpu_req_bits_data = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] s0_req_data = 64'h0; // @[DCache.scala:192:24] wire [63:0] _s2_data_word_possibly_uncached_T_1 = 64'h0; // @[DCache.scala:972:43] wire [38:0] pma_checker_io_sfence_bits_addr = 39'h0; // @[DCache.scala:120:32] wire [38:0] pma_checker_io_ptw_resp_bits_gpa_bits = 39'h0; // @[DCache.scala:120:32] wire [39:0] io_tlb_port_req_bits_vaddr = 40'h0; // @[DCache.scala:101:7] wire [39:0] _io_cpu_s2_xcpt_WIRE_gpa = 40'h0; // @[DCache.scala:933:74] wire [21:0] pma_checker_special_entry_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] metaArb_io_in_0_bits_data = 22'h0; // @[DCache.scala:135:28] wire [21:0] _metaArb_io_in_0_bits_data_T = 22'h0; // @[DCache.scala:1050:85] wire [19:0] pma_checker_refill_ppn = 20'h0; // @[TLB.scala:406:44] wire [19:0] pma_checker_newEntry_ppn = 20'h0; // @[TLB.scala:449:24] wire [19:0] pma_checker__ppn_T_42 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_43 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_44 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_45 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_46 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_47 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_48 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_49 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_50 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_51 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_52 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_53 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_54 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_56 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_57 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_58 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_59 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_60 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_61 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_62 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_63 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_64 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_65 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_66 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_67 = 20'h0; // @[Mux.scala:30:73] wire [19:0] metaArb_io_in_0_bits_data_meta_1_tag = 20'h0; // @[HellaCache.scala:305:20] wire [31:0] pma_checker_io_ptw_status_isa = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_gstatus_isa = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_0_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_1_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_2_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_3_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_4_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_5_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_6_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_7_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] _atomics_WIRE_address = 32'h0; // @[DCache.scala:587:51] wire [31:0] _atomics_WIRE_1_address = 32'h0; // @[DCache.scala:587:38] wire [31:0] nodeOut_c_bits_c_address = 32'h0; // @[Edges.scala:380:17] wire [31:0] nodeOut_c_bits_c_1_address = 32'h0; // @[Edges.scala:396:17] wire [31:0] _io_cpu_s2_xcpt_WIRE_paddr = 32'h0; // @[DCache.scala:933:74] wire [1:0] dataArb_io_in_1_bits_wordMask = 2'h3; // @[DCache.scala:152:28] wire [1:0] dataArb_io_in_2_bits_wordMask = 2'h3; // @[DCache.scala:152:28] wire [1:0] _s2_data_word_en_T = 2'h3; // @[DCache.scala:367:40] wire [1:0] _r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] tl_out_a_bits_a_mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _dataArb_io_in_1_bits_wordMask_T = 2'h3; // @[DCache.scala:731:39] wire [1:0] _metaArb_io_in_3_bits_data_T_8 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dataArb_io_in_2_bits_wordMask_T = 2'h3; // @[DCache.scala:904:37] wire [3:0] _r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_65 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_129 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] tl_out_a_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _tl_out_a_bits_a_mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [3:0] _release_state_T_13 = 4'h6; // @[DCache.scala:820:27] wire [3:0] nodeOut_c_bits_c_size = 4'h6; // @[Edges.scala:380:17] wire [3:0] nodeOut_c_bits_c_1_size = 4'h6; // @[Edges.scala:396:17] wire [127:0] get_data = 128'h0; // @[Edges.scala:460:17] wire [127:0] _atomics_WIRE_data = 128'h0; // @[DCache.scala:587:51] wire [127:0] _atomics_WIRE_1_data = 128'h0; // @[DCache.scala:587:38] wire [127:0] tl_out_a_bits_a_data = 128'h0; // @[Edges.scala:346:17] wire [127:0] nackResponseMessage_data = 128'h0; // @[Edges.scala:416:17] wire [127:0] cleanReleaseMessage_data = 128'h0; // @[Edges.scala:416:17] wire [127:0] dirtyReleaseMessage_data = 128'h0; // @[Edges.scala:433:17] wire [127:0] probe_bits_res_data = 128'h0; // @[DCache.scala:1202:19] wire [127:0] nodeOut_c_bits_c_data = 128'h0; // @[Edges.scala:380:17] wire [127:0] nodeOut_c_bits_c_1_data = 128'h0; // @[Edges.scala:396:17] wire [2:0] nodeOut_c_bits_c_1_opcode = 3'h7; // @[Edges.scala:396:17] wire [32:0] _nodeOut_c_bits_legal_T_27 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_28 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_29 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_61 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_62 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_63 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_23 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_24 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_57 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_58 = 33'h8000000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_c_bits_legal_T_22 = 29'h8000000; // @[Parameters.scala:137:41] wire [28:0] _nodeOut_c_bits_legal_T_56 = 29'h8000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_13 = 33'hC000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_14 = 33'hC000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_47 = 33'hC000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_48 = 33'hC000000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_c_bits_legal_T_12 = 29'hC000000; // @[Parameters.scala:137:41] wire [28:0] _nodeOut_c_bits_legal_T_46 = 29'hC000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_8 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_9 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_42 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_43 = 33'h10000; // @[Parameters.scala:137:46] wire [17:0] _nodeOut_c_bits_legal_T_7 = 18'h10000; // @[Parameters.scala:137:41] wire [17:0] _nodeOut_c_bits_legal_T_41 = 18'h10000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_4 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_37 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_38 = 33'h0; // @[Parameters.scala:137:46] wire [3:0] _r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _metaArb_io_in_3_bits_data_T_9 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_67 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_131 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _tl_out_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _tl_out_a_bits_a_mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _metaArb_io_in_3_bits_data_T_7 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_62 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_126 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _metaArb_io_in_3_bits_data_T_3 = 4'h1; // @[Metadata.scala:86:10] wire [8:0] _s1_data_way_T_1 = 9'h100; // @[DCache.scala:694:32] wire [15:0] tl_out_a_bits_a_mask = 16'hFFFF; // @[Edges.scala:346:17] wire [15:0] _tl_out_a_bits_a_mask_T = 16'hFFFF; // @[Misc.scala:222:10] wire [3:0] _r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_66 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_130 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] tl_out_a_bits_a_mask_sizeOH = 4'h5; // @[Misc.scala:202:81] wire [3:0] _r_T_70 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_134 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_69 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_133 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_68 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_132 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_64 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_128 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_61 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_125 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_60 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_124 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [13:0] pma_checker__gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] pma_checker_gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] pma_checker__gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] pma_checker_gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] pma_checker__gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] pma_checker_gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] pma_checker_gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73] wire [13:0] pma_checker__io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] pma_checker__io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] pma_checker__io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [6:0] pma_checker_real_hits_hi = 7'h0; // @[package.scala:45:27] wire [6:0] pma_checker__state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [6:0] pma_checker__multipleHits_T_21 = 7'h0; // @[Misc.scala:182:39] wire [12:0] pma_checker_real_hits = 13'h0; // @[package.scala:45:27] wire [12:0] pma_checker__stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] pma_checker_stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] pma_checker__r_array_T_2 = 13'h0; // @[TLB.scala:520:74] wire [12:0] pma_checker__hr_array_T_2 = 13'h0; // @[TLB.scala:524:60] wire [12:0] pma_checker__gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [12:0] pma_checker__tlb_hit_T = 13'h0; // @[TLB.scala:611:28] wire [12:0] pma_checker__stage1_bypass_T_2 = 13'h1FFF; // @[TLB.scala:517:68] wire [12:0] pma_checker__stage1_bypass_T_4 = 13'h1FFF; // @[TLB.scala:517:95] wire [12:0] pma_checker_stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] pma_checker__hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] pma_checker__hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] pma_checker__hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] pma_checker__gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] pma_checker_gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] pma_checker__gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] pma_checker_gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [13:0] pma_checker_hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] pma_checker_hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] pma_checker_hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] pma_checker__must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] pma_checker__gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire [30:0] pma_checker_special_entry_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_0_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_1_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_2_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_3_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_0_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_1_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_2_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_3_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_4_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_5_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_6_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_7_data_hi = 31'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_special_entry_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_0_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_1_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_2_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_3_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_0_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_1_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_2_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_3_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_4_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_5_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_6_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_7_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_special_entry_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [13:0] pma_checker_hits = 14'h2000; // @[TLB.scala:442:17] wire [9:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_future = 10'h0; // @[DCache.scala:120:32] wire [31:0] _nodeOut_c_bits_legal_T_26 = 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _nodeOut_c_bits_legal_T_60 = 32'h80000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_11 = 28'hC000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_45 = 28'hC000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_21 = 28'h8000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_55 = 28'h8000000; // @[Parameters.scala:137:31] wire [16:0] _nodeOut_c_bits_legal_T_6 = 17'h10000; // @[Parameters.scala:137:31] wire [16:0] _nodeOut_c_bits_legal_T_40 = 17'h10000; // @[Parameters.scala:137:31] wire [41:0] pma_checker__mpu_ppn_WIRE_1 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_1 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_3 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_5 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_7 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_9 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_11 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_13 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_15 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_17 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_19 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_21 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_23 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_25 = 42'h0; // @[TLB.scala:170:77] wire nodeOut_a_ready = auto_out_a_ready_0; // @[DCache.scala:101:7] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[DCache.scala:101:7] wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[DCache.scala:101:7] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[DCache.scala:101:7] wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[DCache.scala:101:7] wire nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[DCache.scala:101:7] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[DCache.scala:101:7] wire [15:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[DCache.scala:101:7] wire [127:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[DCache.scala:101:7] wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[DCache.scala:101:7] wire nodeOut_c_ready = auto_out_c_ready_0; // @[DCache.scala:101:7] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[DCache.scala:101:7] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[DCache.scala:101:7] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[DCache.scala:101:7] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[DCache.scala:101:7] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[DCache.scala:101:7] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[DCache.scala:101:7] wire nodeOut_e_ready = auto_out_e_ready_0; // @[DCache.scala:101:7] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire metaArb_io_in_7_valid = io_cpu_req_valid_0; // @[DCache.scala:101:7, :135:28] wire [39:0] metaArb_io_in_7_bits_addr = io_cpu_req_bits_addr_0; // @[DCache.scala:101:7, :135:28] wire [6:0] s0_req_tag = io_cpu_req_bits_tag_0; // @[DCache.scala:101:7, :192:24] wire [4:0] s0_req_cmd = io_cpu_req_bits_cmd_0; // @[DCache.scala:101:7, :192:24] wire [1:0] s0_req_size = io_cpu_req_bits_size_0; // @[DCache.scala:101:7, :192:24] wire s0_req_signed = io_cpu_req_bits_signed_0; // @[DCache.scala:101:7, :192:24] wire [1:0] s0_req_dprv = io_cpu_req_bits_dprv_0; // @[DCache.scala:101:7, :192:24] wire s0_req_dv = io_cpu_req_bits_dv_0; // @[DCache.scala:101:7, :192:24] wire s0_req_no_resp = io_cpu_req_bits_no_resp_0; // @[DCache.scala:101:7, :192:24] wire _io_cpu_s2_nack_T_5; // @[DCache.scala:445:86] wire _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:574:54] wire _io_cpu_s2_uncached_T_1; // @[DCache.scala:920:37] wire _io_cpu_resp_valid_T_2; // @[DCache.scala:949:70] wire [63:0] _io_cpu_resp_bits_data_T_24; // @[DCache.scala:974:41] wire s2_read; // @[Consts.scala:89:68] wire [63:0] _io_cpu_resp_bits_data_word_bypass_T_7; // @[AMOALU.scala:45:16] wire [63:0] s2_data_word; // @[DCache.scala:970:106] wire _io_cpu_replay_next_T_3; // @[DCache.scala:950:62] wire _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:933:24] wire _io_cpu_ordered_T_8; // @[DCache.scala:929:21] wire _io_cpu_store_pending_T_25; // @[DCache.scala:930:70] wire io_cpu_perf_acquire_done; // @[Edges.scala:233:22] wire io_cpu_perf_release_done; // @[Edges.scala:233:22] wire _io_cpu_perf_grant_T; // @[DCache.scala:1078:39] wire _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire _io_cpu_perf_blocked_T_1; // @[DCache.scala:1106:23] wire _io_cpu_perf_canAcceptStoreThenLoad_T_10; // @[DCache.scala:1088:41] wire _io_cpu_perf_canAcceptStoreThenRMW_T_1; // @[DCache.scala:1091:75] wire _io_cpu_perf_canAcceptLoadThenLoad_T_61; // @[DCache.scala:1092:40] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_7; // @[DCache.scala:1080:44] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_10; // @[DCache.scala:1084:45] wire _io_errors_bus_valid_T_2; // @[DCache.scala:1129:42] wire [2:0] auto_out_a_bits_opcode_0; // @[DCache.scala:101:7] wire [2:0] auto_out_a_bits_param_0; // @[DCache.scala:101:7] wire [3:0] auto_out_a_bits_size_0; // @[DCache.scala:101:7] wire auto_out_a_bits_source_0; // @[DCache.scala:101:7] wire [31:0] auto_out_a_bits_address_0; // @[DCache.scala:101:7] wire [15:0] auto_out_a_bits_mask_0; // @[DCache.scala:101:7] wire [127:0] auto_out_a_bits_data_0; // @[DCache.scala:101:7] wire auto_out_a_valid_0; // @[DCache.scala:101:7] wire auto_out_b_ready_0; // @[DCache.scala:101:7] wire [2:0] auto_out_c_bits_opcode_0; // @[DCache.scala:101:7] wire [2:0] auto_out_c_bits_param_0; // @[DCache.scala:101:7] wire [3:0] auto_out_c_bits_size_0; // @[DCache.scala:101:7] wire auto_out_c_bits_source_0; // @[DCache.scala:101:7] wire [31:0] auto_out_c_bits_address_0; // @[DCache.scala:101:7] wire [127:0] auto_out_c_bits_data_0; // @[DCache.scala:101:7] wire auto_out_c_valid_0; // @[DCache.scala:101:7] wire auto_out_d_ready_0; // @[DCache.scala:101:7] wire [3:0] auto_out_e_bits_sink_0; // @[DCache.scala:101:7] wire auto_out_e_valid_0; // @[DCache.scala:101:7] wire io_cpu_req_ready_0; // @[DCache.scala:101:7] wire [39:0] io_cpu_resp_bits_addr_0; // @[DCache.scala:101:7] wire [6:0] io_cpu_resp_bits_tag_0; // @[DCache.scala:101:7] wire [4:0] io_cpu_resp_bits_cmd_0; // @[DCache.scala:101:7] wire [1:0] io_cpu_resp_bits_size_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_signed_0; // @[DCache.scala:101:7] wire [1:0] io_cpu_resp_bits_dprv_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_dv_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_0; // @[DCache.scala:101:7] wire [7:0] io_cpu_resp_bits_mask_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_replay_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_has_data_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_word_bypass_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_raw_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_store_data_0; // @[DCache.scala:101:7] wire io_cpu_resp_valid_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ma_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ma_st_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_pf_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_pf_st_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ae_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ae_st_0; // @[DCache.scala:101:7] wire io_cpu_perf_acquire_0; // @[DCache.scala:101:7] wire io_cpu_perf_release_0; // @[DCache.scala:101:7] wire io_cpu_perf_grant_0; // @[DCache.scala:101:7] wire io_cpu_perf_tlbMiss_0; // @[DCache.scala:101:7] wire io_cpu_perf_blocked_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptStoreThenLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptStoreThenRMW_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptLoadThenLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_storeBufferEmptyAfterLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_storeBufferEmptyAfterStore_0; // @[DCache.scala:101:7] wire io_cpu_s2_nack_0; // @[DCache.scala:101:7] wire io_cpu_s2_nack_cause_raw_0; // @[DCache.scala:101:7] wire io_cpu_s2_uncached_0; // @[DCache.scala:101:7] wire [31:0] io_cpu_s2_paddr_0; // @[DCache.scala:101:7] wire io_cpu_replay_next_0; // @[DCache.scala:101:7] wire [39:0] io_cpu_s2_gpa_0; // @[DCache.scala:101:7] wire io_cpu_ordered_0; // @[DCache.scala:101:7] wire io_cpu_store_pending_0; // @[DCache.scala:101:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[DCache.scala:101:7] wire io_ptw_req_valid_0; // @[DCache.scala:101:7] wire io_errors_bus_valid; // @[DCache.scala:101:7] wire [31:0] io_errors_bus_bits; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_inst; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_inst; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_miss; // @[DCache.scala:101:7] wire [31:0] io_tlb_port_s1_resp_paddr; // @[DCache.scala:101:7] wire [39:0] io_tlb_port_s1_resp_gpa; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_cacheable; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_must_alloc; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_prefetchable; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_s1_resp_size; // @[DCache.scala:101:7] wire [4:0] io_tlb_port_s1_resp_cmd; // @[DCache.scala:101:7] wire nodeOut_a_deq_ready = nodeOut_a_ready; // @[Decoupled.scala:356:21] wire nodeOut_a_deq_valid; // @[Decoupled.scala:356:21] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[DCache.scala:101:7] wire [2:0] nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[DCache.scala:101:7] wire [2:0] nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[DCache.scala:101:7] wire [3:0] nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[DCache.scala:101:7] wire nodeOut_a_deq_bits_source; // @[Decoupled.scala:356:21] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[DCache.scala:101:7] wire [31:0] nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[DCache.scala:101:7] wire [15:0] nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[DCache.scala:101:7] wire [127:0] nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[DCache.scala:101:7] wire _nodeOut_b_ready_T_4; // @[DCache.scala:770:44] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[DCache.scala:101:7] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[DCache.scala:101:7] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[DCache.scala:101:7] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[DCache.scala:101:7] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[DCache.scala:101:7] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[DCache.scala:101:7] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[DCache.scala:101:7] wire [127:0] s2_data_corrected; // @[package.scala:45:27] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[DCache.scala:101:7] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[DCache.scala:101:7] wire uncachedRespIdxOH_shiftAmount = nodeOut_d_bits_source; // @[OneHot.scala:64:49] wire [3:0] nodeOut_e_bits_e_sink = nodeOut_d_bits_sink; // @[Edges.scala:451:17] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[DCache.scala:101:7] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[DCache.scala:101:7] wire [1:0] pma_checker_io_resp_size = pma_checker_io_req_bits_size; // @[DCache.scala:120:32] wire [4:0] pma_checker_io_resp_cmd = pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32] wire [31:0] pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8] wire pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31] wire pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31] wire pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire [39:0] pma_checker_io_req_bits_vaddr; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_req_bits_prv; // @[DCache.scala:120:32] wire pma_checker_io_req_bits_v; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_st; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_inst; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_st; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_inst; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_st; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_resp_paddr; // @[DCache.scala:120:32] wire [39:0] pma_checker_io_resp_gpa; // @[DCache.scala:120:32] wire pma_checker_io_resp_cacheable; // @[DCache.scala:120:32] wire pma_checker_io_resp_must_alloc; // @[DCache.scala:120:32] wire pma_checker_io_resp_prefetchable; // @[DCache.scala:120:32] wire [26:0] pma_checker_vpn = pma_checker_io_req_bits_vaddr[38:12]; // @[TLB.scala:335:30] wire [26:0] pma_checker__mpu_ppn_T_24 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__mpu_ppn_T_28 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__sector_hits_T_3 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_11 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_19 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_27 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_35 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_43 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_51 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_59 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__superpage_hits_T = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_5 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_10 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_14 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_19 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_24 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_28 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_33 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_38 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_42 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_47 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_52 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_6 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_12 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_18 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_24 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_30 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_36 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_42 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_48 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_53 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_58 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_63 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_68 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_73 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_78 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_83 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_88 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_93 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_98 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_103 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_108 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_113 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_118 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__ppn_T_5 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_13 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_21 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_29 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_33 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_37 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire pma_checker_priv_s = pma_checker_io_req_bits_prv[0]; // @[TLB.scala:370:20] wire pma_checker_priv_uses_vm = ~(pma_checker_io_req_bits_prv[1]); // @[TLB.scala:372:27] wire [19:0] pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_1 = pma_checker__mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_fragmented_superpage = pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_2 = pma_checker__mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_c = pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_3 = pma_checker__mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_eff = pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_4 = pma_checker__mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_paa = pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_5 = pma_checker__mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pal = pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_6 = pma_checker__mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ppp = pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_7 = pma_checker__mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pr = pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_8 = pma_checker__mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_px = pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_9 = pma_checker__mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pw = pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_10 = pma_checker__mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hr = pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_11 = pma_checker__mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hx = pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_12 = pma_checker__mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hw = pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_13 = pma_checker__mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sr = pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_14 = pma_checker__mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sx = pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_15 = pma_checker__mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sw = pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_16 = pma_checker__mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_gf = pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_17 = pma_checker__mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pf = pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_18 = pma_checker__mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_stage2 = pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_19 = pma_checker__mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_final = pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_20 = pma_checker__mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_ptw = pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_21 = pma_checker__mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_g = pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_22 = pma_checker__mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_u = pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_23 = pma_checker__mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__mpu_ppn_WIRE_ppn = pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] pma_checker_mpu_ppn_res = _pma_checker_mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire [26:0] pma_checker__mpu_ppn_T_25 = {pma_checker__mpu_ppn_T_24[26:20], pma_checker__mpu_ppn_T_24[19:0] | _pma_checker_mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__mpu_ppn_T_26 = pma_checker__mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__mpu_ppn_T_27 = {pma_checker_mpu_ppn_res, pma_checker__mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__mpu_ppn_T_29 = {pma_checker__mpu_ppn_T_28[26:20], pma_checker__mpu_ppn_T_28[19:0] | _pma_checker_mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__mpu_ppn_T_30 = pma_checker__mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__mpu_ppn_T_31 = {pma_checker__mpu_ppn_T_27, pma_checker__mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] pma_checker__mpu_ppn_T_32 = pma_checker_io_req_bits_vaddr[39:12]; // @[TLB.scala:413:146] wire [27:0] pma_checker__mpu_ppn_T_33 = pma_checker__mpu_ppn_T_32; // @[TLB.scala:413:{20,146}] wire [27:0] pma_checker_mpu_ppn = pma_checker__mpu_ppn_T_33; // @[TLB.scala:412:20, :413:20] wire [11:0] pma_checker__mpu_physaddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52] wire [11:0] pma_checker__io_resp_paddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :652:46] wire [11:0] pma_checker__io_resp_gpa_offset_T_1 = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :658:82] wire [39:0] pma_checker_mpu_physaddr = {pma_checker_mpu_ppn, pma_checker__mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] pma_checker__homogeneous_T = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_67 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] pma_checker__deny_access_to_debug_T_1 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [2:0] pma_checker__mpu_priv_T_2 = {1'h0, pma_checker_io_req_bits_prv}; // @[TLB.scala:415:103] wire pma_checker_cacheable; // @[TLB.scala:425:41] wire pma_checker_newEntry_c = pma_checker_cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] pma_checker__homogeneous_T_1 = {1'h0, pma_checker__homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_2 = pma_checker__homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_3 = pma_checker__homogeneous_T_2; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_4 = pma_checker__homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_50 = pma_checker__homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN = {pma_checker_mpu_physaddr[39:14], pma_checker_mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_5; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_5 = _GEN; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_72; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_72 = _GEN; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_6 = {1'h0, pma_checker__homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_7 = pma_checker__homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_8 = pma_checker__homogeneous_T_7; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_9 = pma_checker__homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_0 = {pma_checker_mpu_physaddr[39:17], pma_checker_mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_10; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_60; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_60 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_77; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_77 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_109; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_109 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_116; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_116 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_11 = {1'h0, pma_checker__homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_12 = pma_checker__homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_13 = pma_checker__homogeneous_T_12; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_14 = pma_checker__homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_15 = {pma_checker_mpu_physaddr[39:21], pma_checker_mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_16 = {1'h0, pma_checker__homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_17 = pma_checker__homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_18 = pma_checker__homogeneous_T_17; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_19 = pma_checker__homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_20 = {pma_checker_mpu_physaddr[39:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_21 = {1'h0, pma_checker__homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_22 = pma_checker__homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_23 = pma_checker__homogeneous_T_22; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_24 = pma_checker__homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_25 = {pma_checker_mpu_physaddr[39:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_26 = {1'h0, pma_checker__homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_27 = pma_checker__homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_28 = pma_checker__homogeneous_T_27; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_29 = pma_checker__homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {pma_checker_mpu_physaddr[39:28], pma_checker_mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_30; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_30 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_82; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_82 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_97; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_97 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_31 = {1'h0, pma_checker__homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_32 = pma_checker__homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_33 = pma_checker__homogeneous_T_32; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_34 = pma_checker__homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_35 = {pma_checker_mpu_physaddr[39:28], pma_checker_mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_36 = {1'h0, pma_checker__homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_37 = pma_checker__homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_38 = pma_checker__homogeneous_T_37; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_39 = pma_checker__homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_40 = {pma_checker_mpu_physaddr[39:29], pma_checker_mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_41 = {1'h0, pma_checker__homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_42 = pma_checker__homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_43 = pma_checker__homogeneous_T_42; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_44 = pma_checker__homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {pma_checker_mpu_physaddr[39:32], pma_checker_mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] pma_checker__homogeneous_T_45; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_45 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_87; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_87 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_102; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_102 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_46 = {1'h0, pma_checker__homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_47 = pma_checker__homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_48 = pma_checker__homogeneous_T_47; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_49 = pma_checker__homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_51 = pma_checker__homogeneous_T_50 | pma_checker__homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_52 = pma_checker__homogeneous_T_51 | pma_checker__homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_53 = pma_checker__homogeneous_T_52 | pma_checker__homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_54 = pma_checker__homogeneous_T_53 | pma_checker__homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_55 = pma_checker__homogeneous_T_54 | pma_checker__homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_56 = pma_checker__homogeneous_T_55 | pma_checker__homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_57 = pma_checker__homogeneous_T_56 | pma_checker__homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_58 = pma_checker__homogeneous_T_57 | pma_checker__homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire pma_checker_homogeneous = pma_checker__homogeneous_T_58 | pma_checker__homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] pma_checker__homogeneous_T_61 = {1'h0, pma_checker__homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_62 = pma_checker__homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_63 = pma_checker__homogeneous_T_62; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_64 = pma_checker__homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_65 = pma_checker__homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_66 = ~pma_checker__homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] pma_checker__homogeneous_T_68 = {1'h0, pma_checker__homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_69 = pma_checker__homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_70 = pma_checker__homogeneous_T_69; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_71 = pma_checker__homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_92 = pma_checker__homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_73 = {1'h0, pma_checker__homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_74 = pma_checker__homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_75 = pma_checker__homogeneous_T_74; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_76 = pma_checker__homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] pma_checker__homogeneous_T_78 = {1'h0, pma_checker__homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_79 = pma_checker__homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_80 = pma_checker__homogeneous_T_79; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_81 = pma_checker__homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] pma_checker__homogeneous_T_83 = {1'h0, pma_checker__homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_84 = pma_checker__homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_85 = pma_checker__homogeneous_T_84; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_86 = pma_checker__homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] pma_checker__homogeneous_T_88 = {1'h0, pma_checker__homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_89 = pma_checker__homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_90 = pma_checker__homogeneous_T_89; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_91 = pma_checker__homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_93 = pma_checker__homogeneous_T_92 | pma_checker__homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_94 = pma_checker__homogeneous_T_93 | pma_checker__homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_95 = pma_checker__homogeneous_T_94 | pma_checker__homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_96 = pma_checker__homogeneous_T_95 | pma_checker__homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_98 = {1'h0, pma_checker__homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_99 = pma_checker__homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_100 = pma_checker__homogeneous_T_99; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_101 = pma_checker__homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_107 = pma_checker__homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_103 = {1'h0, pma_checker__homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_104 = pma_checker__homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_105 = pma_checker__homogeneous_T_104; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_106 = pma_checker__homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_108 = pma_checker__homogeneous_T_107 | pma_checker__homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_110 = {1'h0, pma_checker__homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_111 = pma_checker__homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_112 = pma_checker__homogeneous_T_111; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_113 = pma_checker__homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_114 = pma_checker__homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_115 = ~pma_checker__homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] pma_checker__homogeneous_T_117 = {1'h0, pma_checker__homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_118 = pma_checker__homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_119 = pma_checker__homogeneous_T_118; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_120 = pma_checker__homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_121 = pma_checker__homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_122 = ~pma_checker__homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] pma_checker__deny_access_to_debug_T_2 = {1'h0, pma_checker__deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__deny_access_to_debug_T_3 = pma_checker__deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__deny_access_to_debug_T_4 = pma_checker__deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire pma_checker__deny_access_to_debug_T_5 = pma_checker__deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker_deny_access_to_debug = pma_checker__deny_access_to_debug_T_5; // @[TLB.scala:428:50] wire pma_checker__prot_r_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire pma_checker__prot_r_T_1 = _pma_checker_pma_io_resp_r & pma_checker__prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire pma_checker__prot_w_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire pma_checker__prot_w_T_1 = _pma_checker_pma_io_resp_w & pma_checker__prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire pma_checker__prot_x_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire pma_checker__prot_x_T_1 = _pma_checker_pma_io_resp_x & pma_checker__prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire [24:0] pma_checker__sector_hits_T_4 = pma_checker__sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_5 = pma_checker__sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_7 = pma_checker__sector_hits_T_5 & pma_checker__sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_12 = pma_checker__sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_13 = pma_checker__sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_15 = pma_checker__sector_hits_T_13 & pma_checker__sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_20 = pma_checker__sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_21 = pma_checker__sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_23 = pma_checker__sector_hits_T_21 & pma_checker__sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_28 = pma_checker__sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_29 = pma_checker__sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_31 = pma_checker__sector_hits_T_29 & pma_checker__sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_36 = pma_checker__sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_37 = pma_checker__sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_39 = pma_checker__sector_hits_T_37 & pma_checker__sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_44 = pma_checker__sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_45 = pma_checker__sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_47 = pma_checker__sector_hits_T_45 & pma_checker__sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_52 = pma_checker__sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_53 = pma_checker__sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_55 = pma_checker__sector_hits_T_53 & pma_checker__sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_60 = pma_checker__sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_61 = pma_checker__sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_63 = pma_checker__sector_hits_T_61 & pma_checker__sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire [8:0] pma_checker__superpage_hits_T_1 = pma_checker__superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_2 = pma_checker__superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_3 = pma_checker__superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_1 = pma_checker__superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_6 = pma_checker__superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_7 = pma_checker__superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_8 = pma_checker_superpage_hits_ignore_1 | pma_checker__superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_11 = pma_checker__superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_12 = pma_checker__superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__superpage_hits_T_15 = pma_checker__superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_16 = pma_checker__superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_17 = pma_checker__superpage_hits_T_16; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_4 = pma_checker__superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_20 = pma_checker__superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_21 = pma_checker__superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_22 = pma_checker_superpage_hits_ignore_4 | pma_checker__superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_25 = pma_checker__superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_26 = pma_checker__superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__superpage_hits_T_29 = pma_checker__superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_30 = pma_checker__superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_31 = pma_checker__superpage_hits_T_30; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_7 = pma_checker__superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_34 = pma_checker__superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_35 = pma_checker__superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_36 = pma_checker_superpage_hits_ignore_7 | pma_checker__superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_39 = pma_checker__superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_40 = pma_checker__superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__superpage_hits_T_43 = pma_checker__superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_44 = pma_checker__superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_45 = pma_checker__superpage_hits_T_44; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_10 = pma_checker__superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_48 = pma_checker__superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_49 = pma_checker__superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_50 = pma_checker_superpage_hits_ignore_10 | pma_checker__superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_53 = pma_checker__superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_54 = pma_checker__superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}] wire [1:0] pma_checker_hitsVec_idx = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_1 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_2 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_3 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_4 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_5 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_6 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_7 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_24 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_48 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_72 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_96 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_120 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_144 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_168 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [24:0] pma_checker__hitsVec_T_1 = pma_checker__hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_2 = pma_checker__hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_4 = pma_checker__hitsVec_T_2 & pma_checker__hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_7 = pma_checker__hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_8 = pma_checker__hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_10 = pma_checker__hitsVec_T_8 & pma_checker__hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_13 = pma_checker__hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_14 = pma_checker__hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_16 = pma_checker__hitsVec_T_14 & pma_checker__hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_19 = pma_checker__hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_20 = pma_checker__hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_22 = pma_checker__hitsVec_T_20 & pma_checker__hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_25 = pma_checker__hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_26 = pma_checker__hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_28 = pma_checker__hitsVec_T_26 & pma_checker__hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_31 = pma_checker__hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_32 = pma_checker__hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_34 = pma_checker__hitsVec_T_32 & pma_checker__hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_37 = pma_checker__hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_38 = pma_checker__hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_40 = pma_checker__hitsVec_T_38 & pma_checker__hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_43 = pma_checker__hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_44 = pma_checker__hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_46 = pma_checker__hitsVec_T_44 & pma_checker__hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [8:0] pma_checker__hitsVec_T_49 = pma_checker__hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_50 = pma_checker__hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_51 = pma_checker__hitsVec_T_50; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_1 = pma_checker__hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_54 = pma_checker__hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_55 = pma_checker__hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_56 = pma_checker_hitsVec_ignore_1 | pma_checker__hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_59 = pma_checker__hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_60 = pma_checker__hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_64 = pma_checker__hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_65 = pma_checker__hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_66 = pma_checker__hitsVec_T_65; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_4 = pma_checker__hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_69 = pma_checker__hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_70 = pma_checker__hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_71 = pma_checker_hitsVec_ignore_4 | pma_checker__hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_74 = pma_checker__hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_75 = pma_checker__hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_79 = pma_checker__hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_80 = pma_checker__hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_81 = pma_checker__hitsVec_T_80; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_7 = pma_checker__hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_84 = pma_checker__hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_85 = pma_checker__hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_86 = pma_checker_hitsVec_ignore_7 | pma_checker__hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_89 = pma_checker__hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_90 = pma_checker__hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_94 = pma_checker__hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_95 = pma_checker__hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_96 = pma_checker__hitsVec_T_95; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_10 = pma_checker__hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_99 = pma_checker__hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_100 = pma_checker__hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_101 = pma_checker_hitsVec_ignore_10 | pma_checker__hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_104 = pma_checker__hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_105 = pma_checker__hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_109 = pma_checker__hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_110 = pma_checker__hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_111 = pma_checker__hitsVec_T_110; // @[TLB.scala:183:{40,79}] wire [8:0] pma_checker__hitsVec_T_114 = pma_checker__hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_115 = pma_checker__hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_119 = pma_checker__hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_120 = pma_checker__hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker_newEntry_ppp; // @[TLB.scala:449:24] wire pma_checker_newEntry_pal; // @[TLB.scala:449:24] wire pma_checker_newEntry_paa; // @[TLB.scala:449:24] wire pma_checker_newEntry_eff; // @[TLB.scala:449:24] wire [1:0] _GEN_3 = {pma_checker_newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] pma_checker_special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] _GEN_4 = {pma_checker_newEntry_pal, pma_checker_newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] pma_checker_special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_lo_lo_hi = {pma_checker_special_entry_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_special_entry_data_0_lo_lo = {pma_checker_special_entry_data_0_lo_lo_hi, pma_checker_special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] _GEN_5 = {2'h0, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] pma_checker_special_entry_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [5:0] pma_checker_special_entry_data_0_lo_hi = {3'h0, pma_checker_special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_special_entry_data_0_lo = {pma_checker_special_entry_data_0_lo_hi, pma_checker_special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__special_entry_data_0_T = {31'h0, pma_checker_special_entry_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi = {pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_0_data_0_lo_lo = {pma_checker_superpage_entries_0_data_0_lo_lo_hi, pma_checker_superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_0_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_0_data_0_lo = {pma_checker_superpage_entries_0_data_0_lo_hi, pma_checker_superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_0_data_0_T = {31'h0, pma_checker_superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi = {pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_1_data_0_lo_lo = {pma_checker_superpage_entries_1_data_0_lo_lo_hi, pma_checker_superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_1_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_1_data_0_lo = {pma_checker_superpage_entries_1_data_0_lo_hi, pma_checker_superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_1_data_0_T = {31'h0, pma_checker_superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi = {pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_2_data_0_lo_lo = {pma_checker_superpage_entries_2_data_0_lo_lo_hi, pma_checker_superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_2_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_2_data_0_lo = {pma_checker_superpage_entries_2_data_0_lo_hi, pma_checker_superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_2_data_0_T = {31'h0, pma_checker_superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi = {pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_3_data_0_lo_lo = {pma_checker_superpage_entries_3_data_0_lo_lo_hi, pma_checker_superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_3_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_3_data_0_lo = {pma_checker_superpage_entries_3_data_0_lo_hi, pma_checker_superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_3_data_0_T = {31'h0, pma_checker_superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi = {pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_0_data_lo_lo = {pma_checker_sectored_entries_0_0_data_lo_lo_hi, pma_checker_sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_0_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_0_data_lo = {pma_checker_sectored_entries_0_0_data_lo_hi, pma_checker_sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_0_data_T = {31'h0, pma_checker_sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi = {pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_1_data_lo_lo = {pma_checker_sectored_entries_0_1_data_lo_lo_hi, pma_checker_sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_1_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_1_data_lo = {pma_checker_sectored_entries_0_1_data_lo_hi, pma_checker_sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_1_data_T = {31'h0, pma_checker_sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi = {pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_2_data_lo_lo = {pma_checker_sectored_entries_0_2_data_lo_lo_hi, pma_checker_sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_2_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_2_data_lo = {pma_checker_sectored_entries_0_2_data_lo_hi, pma_checker_sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_2_data_T = {31'h0, pma_checker_sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi = {pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_3_data_lo_lo = {pma_checker_sectored_entries_0_3_data_lo_lo_hi, pma_checker_sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_3_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_3_data_lo = {pma_checker_sectored_entries_0_3_data_lo_hi, pma_checker_sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_3_data_T = {31'h0, pma_checker_sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi = {pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_4_data_lo_lo = {pma_checker_sectored_entries_0_4_data_lo_lo_hi, pma_checker_sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_4_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_4_data_lo = {pma_checker_sectored_entries_0_4_data_lo_hi, pma_checker_sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_4_data_T = {31'h0, pma_checker_sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi = {pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_5_data_lo_lo = {pma_checker_sectored_entries_0_5_data_lo_lo_hi, pma_checker_sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_5_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_5_data_lo = {pma_checker_sectored_entries_0_5_data_lo_hi, pma_checker_sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_5_data_T = {31'h0, pma_checker_sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi = {pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_6_data_lo_lo = {pma_checker_sectored_entries_0_6_data_lo_lo_hi, pma_checker_sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_6_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_6_data_lo = {pma_checker_sectored_entries_0_6_data_lo_hi, pma_checker_sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_6_data_T = {31'h0, pma_checker_sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi = {pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_7_data_lo_lo = {pma_checker_sectored_entries_0_7_data_lo_lo_hi, pma_checker_sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_7_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_7_data_lo = {pma_checker_sectored_entries_0_7_data_lo_hi, pma_checker_sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_7_data_T = {31'h0, pma_checker_sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] pma_checker__entries_T_23; // @[TLB.scala:170:77] wire pma_checker__entries_T_22; // @[TLB.scala:170:77] wire pma_checker__entries_T_21; // @[TLB.scala:170:77] wire pma_checker__entries_T_20; // @[TLB.scala:170:77] wire pma_checker__entries_T_19; // @[TLB.scala:170:77] wire pma_checker__entries_T_18; // @[TLB.scala:170:77] wire pma_checker__entries_T_17; // @[TLB.scala:170:77] wire pma_checker__entries_T_16; // @[TLB.scala:170:77] wire pma_checker__entries_T_15; // @[TLB.scala:170:77] wire pma_checker__entries_T_14; // @[TLB.scala:170:77] wire pma_checker__entries_T_13; // @[TLB.scala:170:77] wire pma_checker__entries_T_12; // @[TLB.scala:170:77] wire pma_checker__entries_T_11; // @[TLB.scala:170:77] wire pma_checker__entries_T_10; // @[TLB.scala:170:77] wire pma_checker__entries_T_9; // @[TLB.scala:170:77] wire pma_checker__entries_T_8; // @[TLB.scala:170:77] wire pma_checker__entries_T_7; // @[TLB.scala:170:77] wire pma_checker__entries_T_6; // @[TLB.scala:170:77] wire pma_checker__entries_T_5; // @[TLB.scala:170:77] wire pma_checker__entries_T_4; // @[TLB.scala:170:77] wire pma_checker__entries_T_3; // @[TLB.scala:170:77] wire pma_checker__entries_T_2; // @[TLB.scala:170:77] wire pma_checker__entries_T_1; // @[TLB.scala:170:77] assign pma_checker__entries_T_1 = pma_checker__entries_WIRE_1[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_fragmented_superpage = pma_checker__entries_T_1; // @[TLB.scala:170:77] assign pma_checker__entries_T_2 = pma_checker__entries_WIRE_1[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_c = pma_checker__entries_T_2; // @[TLB.scala:170:77] assign pma_checker__entries_T_3 = pma_checker__entries_WIRE_1[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_eff = pma_checker__entries_T_3; // @[TLB.scala:170:77] assign pma_checker__entries_T_4 = pma_checker__entries_WIRE_1[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_paa = pma_checker__entries_T_4; // @[TLB.scala:170:77] assign pma_checker__entries_T_5 = pma_checker__entries_WIRE_1[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pal = pma_checker__entries_T_5; // @[TLB.scala:170:77] assign pma_checker__entries_T_6 = pma_checker__entries_WIRE_1[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ppp = pma_checker__entries_T_6; // @[TLB.scala:170:77] assign pma_checker__entries_T_7 = pma_checker__entries_WIRE_1[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pr = pma_checker__entries_T_7; // @[TLB.scala:170:77] assign pma_checker__entries_T_8 = pma_checker__entries_WIRE_1[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_px = pma_checker__entries_T_8; // @[TLB.scala:170:77] assign pma_checker__entries_T_9 = pma_checker__entries_WIRE_1[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pw = pma_checker__entries_T_9; // @[TLB.scala:170:77] assign pma_checker__entries_T_10 = pma_checker__entries_WIRE_1[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hr = pma_checker__entries_T_10; // @[TLB.scala:170:77] assign pma_checker__entries_T_11 = pma_checker__entries_WIRE_1[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hx = pma_checker__entries_T_11; // @[TLB.scala:170:77] assign pma_checker__entries_T_12 = pma_checker__entries_WIRE_1[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hw = pma_checker__entries_T_12; // @[TLB.scala:170:77] assign pma_checker__entries_T_13 = pma_checker__entries_WIRE_1[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sr = pma_checker__entries_T_13; // @[TLB.scala:170:77] assign pma_checker__entries_T_14 = pma_checker__entries_WIRE_1[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sx = pma_checker__entries_T_14; // @[TLB.scala:170:77] assign pma_checker__entries_T_15 = pma_checker__entries_WIRE_1[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sw = pma_checker__entries_T_15; // @[TLB.scala:170:77] assign pma_checker__entries_T_16 = pma_checker__entries_WIRE_1[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_gf = pma_checker__entries_T_16; // @[TLB.scala:170:77] assign pma_checker__entries_T_17 = pma_checker__entries_WIRE_1[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pf = pma_checker__entries_T_17; // @[TLB.scala:170:77] assign pma_checker__entries_T_18 = pma_checker__entries_WIRE_1[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_stage2 = pma_checker__entries_T_18; // @[TLB.scala:170:77] assign pma_checker__entries_T_19 = pma_checker__entries_WIRE_1[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_final = pma_checker__entries_T_19; // @[TLB.scala:170:77] assign pma_checker__entries_T_20 = pma_checker__entries_WIRE_1[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_ptw = pma_checker__entries_T_20; // @[TLB.scala:170:77] assign pma_checker__entries_T_21 = pma_checker__entries_WIRE_1[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_g = pma_checker__entries_T_21; // @[TLB.scala:170:77] assign pma_checker__entries_T_22 = pma_checker__entries_WIRE_1[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_u = pma_checker__entries_T_22; // @[TLB.scala:170:77] assign pma_checker__entries_T_23 = pma_checker__entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_ppn = pma_checker__entries_T_23; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_47; // @[TLB.scala:170:77] wire pma_checker__entries_T_46; // @[TLB.scala:170:77] wire pma_checker__entries_T_45; // @[TLB.scala:170:77] wire pma_checker__entries_T_44; // @[TLB.scala:170:77] wire pma_checker__entries_T_43; // @[TLB.scala:170:77] wire pma_checker__entries_T_42; // @[TLB.scala:170:77] wire pma_checker__entries_T_41; // @[TLB.scala:170:77] wire pma_checker__entries_T_40; // @[TLB.scala:170:77] wire pma_checker__entries_T_39; // @[TLB.scala:170:77] wire pma_checker__entries_T_38; // @[TLB.scala:170:77] wire pma_checker__entries_T_37; // @[TLB.scala:170:77] wire pma_checker__entries_T_36; // @[TLB.scala:170:77] wire pma_checker__entries_T_35; // @[TLB.scala:170:77] wire pma_checker__entries_T_34; // @[TLB.scala:170:77] wire pma_checker__entries_T_33; // @[TLB.scala:170:77] wire pma_checker__entries_T_32; // @[TLB.scala:170:77] wire pma_checker__entries_T_31; // @[TLB.scala:170:77] wire pma_checker__entries_T_30; // @[TLB.scala:170:77] wire pma_checker__entries_T_29; // @[TLB.scala:170:77] wire pma_checker__entries_T_28; // @[TLB.scala:170:77] wire pma_checker__entries_T_27; // @[TLB.scala:170:77] wire pma_checker__entries_T_26; // @[TLB.scala:170:77] wire pma_checker__entries_T_25; // @[TLB.scala:170:77] assign pma_checker__entries_T_25 = pma_checker__entries_WIRE_3[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_fragmented_superpage = pma_checker__entries_T_25; // @[TLB.scala:170:77] assign pma_checker__entries_T_26 = pma_checker__entries_WIRE_3[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_c = pma_checker__entries_T_26; // @[TLB.scala:170:77] assign pma_checker__entries_T_27 = pma_checker__entries_WIRE_3[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_eff = pma_checker__entries_T_27; // @[TLB.scala:170:77] assign pma_checker__entries_T_28 = pma_checker__entries_WIRE_3[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_paa = pma_checker__entries_T_28; // @[TLB.scala:170:77] assign pma_checker__entries_T_29 = pma_checker__entries_WIRE_3[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pal = pma_checker__entries_T_29; // @[TLB.scala:170:77] assign pma_checker__entries_T_30 = pma_checker__entries_WIRE_3[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ppp = pma_checker__entries_T_30; // @[TLB.scala:170:77] assign pma_checker__entries_T_31 = pma_checker__entries_WIRE_3[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pr = pma_checker__entries_T_31; // @[TLB.scala:170:77] assign pma_checker__entries_T_32 = pma_checker__entries_WIRE_3[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_px = pma_checker__entries_T_32; // @[TLB.scala:170:77] assign pma_checker__entries_T_33 = pma_checker__entries_WIRE_3[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pw = pma_checker__entries_T_33; // @[TLB.scala:170:77] assign pma_checker__entries_T_34 = pma_checker__entries_WIRE_3[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hr = pma_checker__entries_T_34; // @[TLB.scala:170:77] assign pma_checker__entries_T_35 = pma_checker__entries_WIRE_3[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hx = pma_checker__entries_T_35; // @[TLB.scala:170:77] assign pma_checker__entries_T_36 = pma_checker__entries_WIRE_3[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hw = pma_checker__entries_T_36; // @[TLB.scala:170:77] assign pma_checker__entries_T_37 = pma_checker__entries_WIRE_3[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sr = pma_checker__entries_T_37; // @[TLB.scala:170:77] assign pma_checker__entries_T_38 = pma_checker__entries_WIRE_3[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sx = pma_checker__entries_T_38; // @[TLB.scala:170:77] assign pma_checker__entries_T_39 = pma_checker__entries_WIRE_3[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sw = pma_checker__entries_T_39; // @[TLB.scala:170:77] assign pma_checker__entries_T_40 = pma_checker__entries_WIRE_3[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_gf = pma_checker__entries_T_40; // @[TLB.scala:170:77] assign pma_checker__entries_T_41 = pma_checker__entries_WIRE_3[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pf = pma_checker__entries_T_41; // @[TLB.scala:170:77] assign pma_checker__entries_T_42 = pma_checker__entries_WIRE_3[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_stage2 = pma_checker__entries_T_42; // @[TLB.scala:170:77] assign pma_checker__entries_T_43 = pma_checker__entries_WIRE_3[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_final = pma_checker__entries_T_43; // @[TLB.scala:170:77] assign pma_checker__entries_T_44 = pma_checker__entries_WIRE_3[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_ptw = pma_checker__entries_T_44; // @[TLB.scala:170:77] assign pma_checker__entries_T_45 = pma_checker__entries_WIRE_3[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_g = pma_checker__entries_T_45; // @[TLB.scala:170:77] assign pma_checker__entries_T_46 = pma_checker__entries_WIRE_3[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_u = pma_checker__entries_T_46; // @[TLB.scala:170:77] assign pma_checker__entries_T_47 = pma_checker__entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_2_ppn = pma_checker__entries_T_47; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_71; // @[TLB.scala:170:77] wire pma_checker__entries_T_70; // @[TLB.scala:170:77] wire pma_checker__entries_T_69; // @[TLB.scala:170:77] wire pma_checker__entries_T_68; // @[TLB.scala:170:77] wire pma_checker__entries_T_67; // @[TLB.scala:170:77] wire pma_checker__entries_T_66; // @[TLB.scala:170:77] wire pma_checker__entries_T_65; // @[TLB.scala:170:77] wire pma_checker__entries_T_64; // @[TLB.scala:170:77] wire pma_checker__entries_T_63; // @[TLB.scala:170:77] wire pma_checker__entries_T_62; // @[TLB.scala:170:77] wire pma_checker__entries_T_61; // @[TLB.scala:170:77] wire pma_checker__entries_T_60; // @[TLB.scala:170:77] wire pma_checker__entries_T_59; // @[TLB.scala:170:77] wire pma_checker__entries_T_58; // @[TLB.scala:170:77] wire pma_checker__entries_T_57; // @[TLB.scala:170:77] wire pma_checker__entries_T_56; // @[TLB.scala:170:77] wire pma_checker__entries_T_55; // @[TLB.scala:170:77] wire pma_checker__entries_T_54; // @[TLB.scala:170:77] wire pma_checker__entries_T_53; // @[TLB.scala:170:77] wire pma_checker__entries_T_52; // @[TLB.scala:170:77] wire pma_checker__entries_T_51; // @[TLB.scala:170:77] wire pma_checker__entries_T_50; // @[TLB.scala:170:77] wire pma_checker__entries_T_49; // @[TLB.scala:170:77] assign pma_checker__entries_T_49 = pma_checker__entries_WIRE_5[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_fragmented_superpage = pma_checker__entries_T_49; // @[TLB.scala:170:77] assign pma_checker__entries_T_50 = pma_checker__entries_WIRE_5[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_c = pma_checker__entries_T_50; // @[TLB.scala:170:77] assign pma_checker__entries_T_51 = pma_checker__entries_WIRE_5[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_eff = pma_checker__entries_T_51; // @[TLB.scala:170:77] assign pma_checker__entries_T_52 = pma_checker__entries_WIRE_5[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_paa = pma_checker__entries_T_52; // @[TLB.scala:170:77] assign pma_checker__entries_T_53 = pma_checker__entries_WIRE_5[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pal = pma_checker__entries_T_53; // @[TLB.scala:170:77] assign pma_checker__entries_T_54 = pma_checker__entries_WIRE_5[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ppp = pma_checker__entries_T_54; // @[TLB.scala:170:77] assign pma_checker__entries_T_55 = pma_checker__entries_WIRE_5[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pr = pma_checker__entries_T_55; // @[TLB.scala:170:77] assign pma_checker__entries_T_56 = pma_checker__entries_WIRE_5[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_px = pma_checker__entries_T_56; // @[TLB.scala:170:77] assign pma_checker__entries_T_57 = pma_checker__entries_WIRE_5[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pw = pma_checker__entries_T_57; // @[TLB.scala:170:77] assign pma_checker__entries_T_58 = pma_checker__entries_WIRE_5[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hr = pma_checker__entries_T_58; // @[TLB.scala:170:77] assign pma_checker__entries_T_59 = pma_checker__entries_WIRE_5[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hx = pma_checker__entries_T_59; // @[TLB.scala:170:77] assign pma_checker__entries_T_60 = pma_checker__entries_WIRE_5[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hw = pma_checker__entries_T_60; // @[TLB.scala:170:77] assign pma_checker__entries_T_61 = pma_checker__entries_WIRE_5[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sr = pma_checker__entries_T_61; // @[TLB.scala:170:77] assign pma_checker__entries_T_62 = pma_checker__entries_WIRE_5[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sx = pma_checker__entries_T_62; // @[TLB.scala:170:77] assign pma_checker__entries_T_63 = pma_checker__entries_WIRE_5[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sw = pma_checker__entries_T_63; // @[TLB.scala:170:77] assign pma_checker__entries_T_64 = pma_checker__entries_WIRE_5[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_gf = pma_checker__entries_T_64; // @[TLB.scala:170:77] assign pma_checker__entries_T_65 = pma_checker__entries_WIRE_5[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pf = pma_checker__entries_T_65; // @[TLB.scala:170:77] assign pma_checker__entries_T_66 = pma_checker__entries_WIRE_5[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_stage2 = pma_checker__entries_T_66; // @[TLB.scala:170:77] assign pma_checker__entries_T_67 = pma_checker__entries_WIRE_5[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_final = pma_checker__entries_T_67; // @[TLB.scala:170:77] assign pma_checker__entries_T_68 = pma_checker__entries_WIRE_5[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_ptw = pma_checker__entries_T_68; // @[TLB.scala:170:77] assign pma_checker__entries_T_69 = pma_checker__entries_WIRE_5[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_g = pma_checker__entries_T_69; // @[TLB.scala:170:77] assign pma_checker__entries_T_70 = pma_checker__entries_WIRE_5[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_u = pma_checker__entries_T_70; // @[TLB.scala:170:77] assign pma_checker__entries_T_71 = pma_checker__entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_4_ppn = pma_checker__entries_T_71; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_95; // @[TLB.scala:170:77] wire pma_checker__entries_T_94; // @[TLB.scala:170:77] wire pma_checker__entries_T_93; // @[TLB.scala:170:77] wire pma_checker__entries_T_92; // @[TLB.scala:170:77] wire pma_checker__entries_T_91; // @[TLB.scala:170:77] wire pma_checker__entries_T_90; // @[TLB.scala:170:77] wire pma_checker__entries_T_89; // @[TLB.scala:170:77] wire pma_checker__entries_T_88; // @[TLB.scala:170:77] wire pma_checker__entries_T_87; // @[TLB.scala:170:77] wire pma_checker__entries_T_86; // @[TLB.scala:170:77] wire pma_checker__entries_T_85; // @[TLB.scala:170:77] wire pma_checker__entries_T_84; // @[TLB.scala:170:77] wire pma_checker__entries_T_83; // @[TLB.scala:170:77] wire pma_checker__entries_T_82; // @[TLB.scala:170:77] wire pma_checker__entries_T_81; // @[TLB.scala:170:77] wire pma_checker__entries_T_80; // @[TLB.scala:170:77] wire pma_checker__entries_T_79; // @[TLB.scala:170:77] wire pma_checker__entries_T_78; // @[TLB.scala:170:77] wire pma_checker__entries_T_77; // @[TLB.scala:170:77] wire pma_checker__entries_T_76; // @[TLB.scala:170:77] wire pma_checker__entries_T_75; // @[TLB.scala:170:77] wire pma_checker__entries_T_74; // @[TLB.scala:170:77] wire pma_checker__entries_T_73; // @[TLB.scala:170:77] assign pma_checker__entries_T_73 = pma_checker__entries_WIRE_7[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_fragmented_superpage = pma_checker__entries_T_73; // @[TLB.scala:170:77] assign pma_checker__entries_T_74 = pma_checker__entries_WIRE_7[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_c = pma_checker__entries_T_74; // @[TLB.scala:170:77] assign pma_checker__entries_T_75 = pma_checker__entries_WIRE_7[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_eff = pma_checker__entries_T_75; // @[TLB.scala:170:77] assign pma_checker__entries_T_76 = pma_checker__entries_WIRE_7[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_paa = pma_checker__entries_T_76; // @[TLB.scala:170:77] assign pma_checker__entries_T_77 = pma_checker__entries_WIRE_7[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pal = pma_checker__entries_T_77; // @[TLB.scala:170:77] assign pma_checker__entries_T_78 = pma_checker__entries_WIRE_7[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ppp = pma_checker__entries_T_78; // @[TLB.scala:170:77] assign pma_checker__entries_T_79 = pma_checker__entries_WIRE_7[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pr = pma_checker__entries_T_79; // @[TLB.scala:170:77] assign pma_checker__entries_T_80 = pma_checker__entries_WIRE_7[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_px = pma_checker__entries_T_80; // @[TLB.scala:170:77] assign pma_checker__entries_T_81 = pma_checker__entries_WIRE_7[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pw = pma_checker__entries_T_81; // @[TLB.scala:170:77] assign pma_checker__entries_T_82 = pma_checker__entries_WIRE_7[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hr = pma_checker__entries_T_82; // @[TLB.scala:170:77] assign pma_checker__entries_T_83 = pma_checker__entries_WIRE_7[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hx = pma_checker__entries_T_83; // @[TLB.scala:170:77] assign pma_checker__entries_T_84 = pma_checker__entries_WIRE_7[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hw = pma_checker__entries_T_84; // @[TLB.scala:170:77] assign pma_checker__entries_T_85 = pma_checker__entries_WIRE_7[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sr = pma_checker__entries_T_85; // @[TLB.scala:170:77] assign pma_checker__entries_T_86 = pma_checker__entries_WIRE_7[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sx = pma_checker__entries_T_86; // @[TLB.scala:170:77] assign pma_checker__entries_T_87 = pma_checker__entries_WIRE_7[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sw = pma_checker__entries_T_87; // @[TLB.scala:170:77] assign pma_checker__entries_T_88 = pma_checker__entries_WIRE_7[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_gf = pma_checker__entries_T_88; // @[TLB.scala:170:77] assign pma_checker__entries_T_89 = pma_checker__entries_WIRE_7[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pf = pma_checker__entries_T_89; // @[TLB.scala:170:77] assign pma_checker__entries_T_90 = pma_checker__entries_WIRE_7[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_stage2 = pma_checker__entries_T_90; // @[TLB.scala:170:77] assign pma_checker__entries_T_91 = pma_checker__entries_WIRE_7[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_final = pma_checker__entries_T_91; // @[TLB.scala:170:77] assign pma_checker__entries_T_92 = pma_checker__entries_WIRE_7[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_ptw = pma_checker__entries_T_92; // @[TLB.scala:170:77] assign pma_checker__entries_T_93 = pma_checker__entries_WIRE_7[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_g = pma_checker__entries_T_93; // @[TLB.scala:170:77] assign pma_checker__entries_T_94 = pma_checker__entries_WIRE_7[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_u = pma_checker__entries_T_94; // @[TLB.scala:170:77] assign pma_checker__entries_T_95 = pma_checker__entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_6_ppn = pma_checker__entries_T_95; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_119; // @[TLB.scala:170:77] wire pma_checker__entries_T_118; // @[TLB.scala:170:77] wire pma_checker__entries_T_117; // @[TLB.scala:170:77] wire pma_checker__entries_T_116; // @[TLB.scala:170:77] wire pma_checker__entries_T_115; // @[TLB.scala:170:77] wire pma_checker__entries_T_114; // @[TLB.scala:170:77] wire pma_checker__entries_T_113; // @[TLB.scala:170:77] wire pma_checker__entries_T_112; // @[TLB.scala:170:77] wire pma_checker__entries_T_111; // @[TLB.scala:170:77] wire pma_checker__entries_T_110; // @[TLB.scala:170:77] wire pma_checker__entries_T_109; // @[TLB.scala:170:77] wire pma_checker__entries_T_108; // @[TLB.scala:170:77] wire pma_checker__entries_T_107; // @[TLB.scala:170:77] wire pma_checker__entries_T_106; // @[TLB.scala:170:77] wire pma_checker__entries_T_105; // @[TLB.scala:170:77] wire pma_checker__entries_T_104; // @[TLB.scala:170:77] wire pma_checker__entries_T_103; // @[TLB.scala:170:77] wire pma_checker__entries_T_102; // @[TLB.scala:170:77] wire pma_checker__entries_T_101; // @[TLB.scala:170:77] wire pma_checker__entries_T_100; // @[TLB.scala:170:77] wire pma_checker__entries_T_99; // @[TLB.scala:170:77] wire pma_checker__entries_T_98; // @[TLB.scala:170:77] wire pma_checker__entries_T_97; // @[TLB.scala:170:77] assign pma_checker__entries_T_97 = pma_checker__entries_WIRE_9[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_fragmented_superpage = pma_checker__entries_T_97; // @[TLB.scala:170:77] assign pma_checker__entries_T_98 = pma_checker__entries_WIRE_9[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_c = pma_checker__entries_T_98; // @[TLB.scala:170:77] assign pma_checker__entries_T_99 = pma_checker__entries_WIRE_9[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_eff = pma_checker__entries_T_99; // @[TLB.scala:170:77] assign pma_checker__entries_T_100 = pma_checker__entries_WIRE_9[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_paa = pma_checker__entries_T_100; // @[TLB.scala:170:77] assign pma_checker__entries_T_101 = pma_checker__entries_WIRE_9[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pal = pma_checker__entries_T_101; // @[TLB.scala:170:77] assign pma_checker__entries_T_102 = pma_checker__entries_WIRE_9[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ppp = pma_checker__entries_T_102; // @[TLB.scala:170:77] assign pma_checker__entries_T_103 = pma_checker__entries_WIRE_9[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pr = pma_checker__entries_T_103; // @[TLB.scala:170:77] assign pma_checker__entries_T_104 = pma_checker__entries_WIRE_9[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_px = pma_checker__entries_T_104; // @[TLB.scala:170:77] assign pma_checker__entries_T_105 = pma_checker__entries_WIRE_9[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pw = pma_checker__entries_T_105; // @[TLB.scala:170:77] assign pma_checker__entries_T_106 = pma_checker__entries_WIRE_9[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hr = pma_checker__entries_T_106; // @[TLB.scala:170:77] assign pma_checker__entries_T_107 = pma_checker__entries_WIRE_9[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hx = pma_checker__entries_T_107; // @[TLB.scala:170:77] assign pma_checker__entries_T_108 = pma_checker__entries_WIRE_9[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hw = pma_checker__entries_T_108; // @[TLB.scala:170:77] assign pma_checker__entries_T_109 = pma_checker__entries_WIRE_9[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sr = pma_checker__entries_T_109; // @[TLB.scala:170:77] assign pma_checker__entries_T_110 = pma_checker__entries_WIRE_9[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sx = pma_checker__entries_T_110; // @[TLB.scala:170:77] assign pma_checker__entries_T_111 = pma_checker__entries_WIRE_9[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sw = pma_checker__entries_T_111; // @[TLB.scala:170:77] assign pma_checker__entries_T_112 = pma_checker__entries_WIRE_9[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_gf = pma_checker__entries_T_112; // @[TLB.scala:170:77] assign pma_checker__entries_T_113 = pma_checker__entries_WIRE_9[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pf = pma_checker__entries_T_113; // @[TLB.scala:170:77] assign pma_checker__entries_T_114 = pma_checker__entries_WIRE_9[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_stage2 = pma_checker__entries_T_114; // @[TLB.scala:170:77] assign pma_checker__entries_T_115 = pma_checker__entries_WIRE_9[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_final = pma_checker__entries_T_115; // @[TLB.scala:170:77] assign pma_checker__entries_T_116 = pma_checker__entries_WIRE_9[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_ptw = pma_checker__entries_T_116; // @[TLB.scala:170:77] assign pma_checker__entries_T_117 = pma_checker__entries_WIRE_9[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_g = pma_checker__entries_T_117; // @[TLB.scala:170:77] assign pma_checker__entries_T_118 = pma_checker__entries_WIRE_9[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_u = pma_checker__entries_T_118; // @[TLB.scala:170:77] assign pma_checker__entries_T_119 = pma_checker__entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_8_ppn = pma_checker__entries_T_119; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_143; // @[TLB.scala:170:77] wire pma_checker__entries_T_142; // @[TLB.scala:170:77] wire pma_checker__entries_T_141; // @[TLB.scala:170:77] wire pma_checker__entries_T_140; // @[TLB.scala:170:77] wire pma_checker__entries_T_139; // @[TLB.scala:170:77] wire pma_checker__entries_T_138; // @[TLB.scala:170:77] wire pma_checker__entries_T_137; // @[TLB.scala:170:77] wire pma_checker__entries_T_136; // @[TLB.scala:170:77] wire pma_checker__entries_T_135; // @[TLB.scala:170:77] wire pma_checker__entries_T_134; // @[TLB.scala:170:77] wire pma_checker__entries_T_133; // @[TLB.scala:170:77] wire pma_checker__entries_T_132; // @[TLB.scala:170:77] wire pma_checker__entries_T_131; // @[TLB.scala:170:77] wire pma_checker__entries_T_130; // @[TLB.scala:170:77] wire pma_checker__entries_T_129; // @[TLB.scala:170:77] wire pma_checker__entries_T_128; // @[TLB.scala:170:77] wire pma_checker__entries_T_127; // @[TLB.scala:170:77] wire pma_checker__entries_T_126; // @[TLB.scala:170:77] wire pma_checker__entries_T_125; // @[TLB.scala:170:77] wire pma_checker__entries_T_124; // @[TLB.scala:170:77] wire pma_checker__entries_T_123; // @[TLB.scala:170:77] wire pma_checker__entries_T_122; // @[TLB.scala:170:77] wire pma_checker__entries_T_121; // @[TLB.scala:170:77] assign pma_checker__entries_T_121 = pma_checker__entries_WIRE_11[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_fragmented_superpage = pma_checker__entries_T_121; // @[TLB.scala:170:77] assign pma_checker__entries_T_122 = pma_checker__entries_WIRE_11[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_c = pma_checker__entries_T_122; // @[TLB.scala:170:77] assign pma_checker__entries_T_123 = pma_checker__entries_WIRE_11[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_eff = pma_checker__entries_T_123; // @[TLB.scala:170:77] assign pma_checker__entries_T_124 = pma_checker__entries_WIRE_11[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_paa = pma_checker__entries_T_124; // @[TLB.scala:170:77] assign pma_checker__entries_T_125 = pma_checker__entries_WIRE_11[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pal = pma_checker__entries_T_125; // @[TLB.scala:170:77] assign pma_checker__entries_T_126 = pma_checker__entries_WIRE_11[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ppp = pma_checker__entries_T_126; // @[TLB.scala:170:77] assign pma_checker__entries_T_127 = pma_checker__entries_WIRE_11[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pr = pma_checker__entries_T_127; // @[TLB.scala:170:77] assign pma_checker__entries_T_128 = pma_checker__entries_WIRE_11[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_px = pma_checker__entries_T_128; // @[TLB.scala:170:77] assign pma_checker__entries_T_129 = pma_checker__entries_WIRE_11[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pw = pma_checker__entries_T_129; // @[TLB.scala:170:77] assign pma_checker__entries_T_130 = pma_checker__entries_WIRE_11[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hr = pma_checker__entries_T_130; // @[TLB.scala:170:77] assign pma_checker__entries_T_131 = pma_checker__entries_WIRE_11[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hx = pma_checker__entries_T_131; // @[TLB.scala:170:77] assign pma_checker__entries_T_132 = pma_checker__entries_WIRE_11[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hw = pma_checker__entries_T_132; // @[TLB.scala:170:77] assign pma_checker__entries_T_133 = pma_checker__entries_WIRE_11[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sr = pma_checker__entries_T_133; // @[TLB.scala:170:77] assign pma_checker__entries_T_134 = pma_checker__entries_WIRE_11[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sx = pma_checker__entries_T_134; // @[TLB.scala:170:77] assign pma_checker__entries_T_135 = pma_checker__entries_WIRE_11[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sw = pma_checker__entries_T_135; // @[TLB.scala:170:77] assign pma_checker__entries_T_136 = pma_checker__entries_WIRE_11[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_gf = pma_checker__entries_T_136; // @[TLB.scala:170:77] assign pma_checker__entries_T_137 = pma_checker__entries_WIRE_11[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pf = pma_checker__entries_T_137; // @[TLB.scala:170:77] assign pma_checker__entries_T_138 = pma_checker__entries_WIRE_11[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_stage2 = pma_checker__entries_T_138; // @[TLB.scala:170:77] assign pma_checker__entries_T_139 = pma_checker__entries_WIRE_11[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_final = pma_checker__entries_T_139; // @[TLB.scala:170:77] assign pma_checker__entries_T_140 = pma_checker__entries_WIRE_11[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_ptw = pma_checker__entries_T_140; // @[TLB.scala:170:77] assign pma_checker__entries_T_141 = pma_checker__entries_WIRE_11[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_g = pma_checker__entries_T_141; // @[TLB.scala:170:77] assign pma_checker__entries_T_142 = pma_checker__entries_WIRE_11[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_u = pma_checker__entries_T_142; // @[TLB.scala:170:77] assign pma_checker__entries_T_143 = pma_checker__entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_10_ppn = pma_checker__entries_T_143; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_167; // @[TLB.scala:170:77] wire pma_checker__entries_T_166; // @[TLB.scala:170:77] wire pma_checker__entries_T_165; // @[TLB.scala:170:77] wire pma_checker__entries_T_164; // @[TLB.scala:170:77] wire pma_checker__entries_T_163; // @[TLB.scala:170:77] wire pma_checker__entries_T_162; // @[TLB.scala:170:77] wire pma_checker__entries_T_161; // @[TLB.scala:170:77] wire pma_checker__entries_T_160; // @[TLB.scala:170:77] wire pma_checker__entries_T_159; // @[TLB.scala:170:77] wire pma_checker__entries_T_158; // @[TLB.scala:170:77] wire pma_checker__entries_T_157; // @[TLB.scala:170:77] wire pma_checker__entries_T_156; // @[TLB.scala:170:77] wire pma_checker__entries_T_155; // @[TLB.scala:170:77] wire pma_checker__entries_T_154; // @[TLB.scala:170:77] wire pma_checker__entries_T_153; // @[TLB.scala:170:77] wire pma_checker__entries_T_152; // @[TLB.scala:170:77] wire pma_checker__entries_T_151; // @[TLB.scala:170:77] wire pma_checker__entries_T_150; // @[TLB.scala:170:77] wire pma_checker__entries_T_149; // @[TLB.scala:170:77] wire pma_checker__entries_T_148; // @[TLB.scala:170:77] wire pma_checker__entries_T_147; // @[TLB.scala:170:77] wire pma_checker__entries_T_146; // @[TLB.scala:170:77] wire pma_checker__entries_T_145; // @[TLB.scala:170:77] assign pma_checker__entries_T_145 = pma_checker__entries_WIRE_13[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_fragmented_superpage = pma_checker__entries_T_145; // @[TLB.scala:170:77] assign pma_checker__entries_T_146 = pma_checker__entries_WIRE_13[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_c = pma_checker__entries_T_146; // @[TLB.scala:170:77] assign pma_checker__entries_T_147 = pma_checker__entries_WIRE_13[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_eff = pma_checker__entries_T_147; // @[TLB.scala:170:77] assign pma_checker__entries_T_148 = pma_checker__entries_WIRE_13[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_paa = pma_checker__entries_T_148; // @[TLB.scala:170:77] assign pma_checker__entries_T_149 = pma_checker__entries_WIRE_13[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pal = pma_checker__entries_T_149; // @[TLB.scala:170:77] assign pma_checker__entries_T_150 = pma_checker__entries_WIRE_13[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ppp = pma_checker__entries_T_150; // @[TLB.scala:170:77] assign pma_checker__entries_T_151 = pma_checker__entries_WIRE_13[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pr = pma_checker__entries_T_151; // @[TLB.scala:170:77] assign pma_checker__entries_T_152 = pma_checker__entries_WIRE_13[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_px = pma_checker__entries_T_152; // @[TLB.scala:170:77] assign pma_checker__entries_T_153 = pma_checker__entries_WIRE_13[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pw = pma_checker__entries_T_153; // @[TLB.scala:170:77] assign pma_checker__entries_T_154 = pma_checker__entries_WIRE_13[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hr = pma_checker__entries_T_154; // @[TLB.scala:170:77] assign pma_checker__entries_T_155 = pma_checker__entries_WIRE_13[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hx = pma_checker__entries_T_155; // @[TLB.scala:170:77] assign pma_checker__entries_T_156 = pma_checker__entries_WIRE_13[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hw = pma_checker__entries_T_156; // @[TLB.scala:170:77] assign pma_checker__entries_T_157 = pma_checker__entries_WIRE_13[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sr = pma_checker__entries_T_157; // @[TLB.scala:170:77] assign pma_checker__entries_T_158 = pma_checker__entries_WIRE_13[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sx = pma_checker__entries_T_158; // @[TLB.scala:170:77] assign pma_checker__entries_T_159 = pma_checker__entries_WIRE_13[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sw = pma_checker__entries_T_159; // @[TLB.scala:170:77] assign pma_checker__entries_T_160 = pma_checker__entries_WIRE_13[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_gf = pma_checker__entries_T_160; // @[TLB.scala:170:77] assign pma_checker__entries_T_161 = pma_checker__entries_WIRE_13[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pf = pma_checker__entries_T_161; // @[TLB.scala:170:77] assign pma_checker__entries_T_162 = pma_checker__entries_WIRE_13[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_stage2 = pma_checker__entries_T_162; // @[TLB.scala:170:77] assign pma_checker__entries_T_163 = pma_checker__entries_WIRE_13[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_final = pma_checker__entries_T_163; // @[TLB.scala:170:77] assign pma_checker__entries_T_164 = pma_checker__entries_WIRE_13[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_ptw = pma_checker__entries_T_164; // @[TLB.scala:170:77] assign pma_checker__entries_T_165 = pma_checker__entries_WIRE_13[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_g = pma_checker__entries_T_165; // @[TLB.scala:170:77] assign pma_checker__entries_T_166 = pma_checker__entries_WIRE_13[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_u = pma_checker__entries_T_166; // @[TLB.scala:170:77] assign pma_checker__entries_T_167 = pma_checker__entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_12_ppn = pma_checker__entries_T_167; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_191; // @[TLB.scala:170:77] wire pma_checker__entries_T_190; // @[TLB.scala:170:77] wire pma_checker__entries_T_189; // @[TLB.scala:170:77] wire pma_checker__entries_T_188; // @[TLB.scala:170:77] wire pma_checker__entries_T_187; // @[TLB.scala:170:77] wire pma_checker__entries_T_186; // @[TLB.scala:170:77] wire pma_checker__entries_T_185; // @[TLB.scala:170:77] wire pma_checker__entries_T_184; // @[TLB.scala:170:77] wire pma_checker__entries_T_183; // @[TLB.scala:170:77] wire pma_checker__entries_T_182; // @[TLB.scala:170:77] wire pma_checker__entries_T_181; // @[TLB.scala:170:77] wire pma_checker__entries_T_180; // @[TLB.scala:170:77] wire pma_checker__entries_T_179; // @[TLB.scala:170:77] wire pma_checker__entries_T_178; // @[TLB.scala:170:77] wire pma_checker__entries_T_177; // @[TLB.scala:170:77] wire pma_checker__entries_T_176; // @[TLB.scala:170:77] wire pma_checker__entries_T_175; // @[TLB.scala:170:77] wire pma_checker__entries_T_174; // @[TLB.scala:170:77] wire pma_checker__entries_T_173; // @[TLB.scala:170:77] wire pma_checker__entries_T_172; // @[TLB.scala:170:77] wire pma_checker__entries_T_171; // @[TLB.scala:170:77] wire pma_checker__entries_T_170; // @[TLB.scala:170:77] wire pma_checker__entries_T_169; // @[TLB.scala:170:77] assign pma_checker__entries_T_169 = pma_checker__entries_WIRE_15[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_fragmented_superpage = pma_checker__entries_T_169; // @[TLB.scala:170:77] assign pma_checker__entries_T_170 = pma_checker__entries_WIRE_15[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_c = pma_checker__entries_T_170; // @[TLB.scala:170:77] assign pma_checker__entries_T_171 = pma_checker__entries_WIRE_15[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_eff = pma_checker__entries_T_171; // @[TLB.scala:170:77] assign pma_checker__entries_T_172 = pma_checker__entries_WIRE_15[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_paa = pma_checker__entries_T_172; // @[TLB.scala:170:77] assign pma_checker__entries_T_173 = pma_checker__entries_WIRE_15[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pal = pma_checker__entries_T_173; // @[TLB.scala:170:77] assign pma_checker__entries_T_174 = pma_checker__entries_WIRE_15[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ppp = pma_checker__entries_T_174; // @[TLB.scala:170:77] assign pma_checker__entries_T_175 = pma_checker__entries_WIRE_15[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pr = pma_checker__entries_T_175; // @[TLB.scala:170:77] assign pma_checker__entries_T_176 = pma_checker__entries_WIRE_15[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_px = pma_checker__entries_T_176; // @[TLB.scala:170:77] assign pma_checker__entries_T_177 = pma_checker__entries_WIRE_15[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pw = pma_checker__entries_T_177; // @[TLB.scala:170:77] assign pma_checker__entries_T_178 = pma_checker__entries_WIRE_15[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hr = pma_checker__entries_T_178; // @[TLB.scala:170:77] assign pma_checker__entries_T_179 = pma_checker__entries_WIRE_15[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hx = pma_checker__entries_T_179; // @[TLB.scala:170:77] assign pma_checker__entries_T_180 = pma_checker__entries_WIRE_15[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hw = pma_checker__entries_T_180; // @[TLB.scala:170:77] assign pma_checker__entries_T_181 = pma_checker__entries_WIRE_15[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sr = pma_checker__entries_T_181; // @[TLB.scala:170:77] assign pma_checker__entries_T_182 = pma_checker__entries_WIRE_15[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sx = pma_checker__entries_T_182; // @[TLB.scala:170:77] assign pma_checker__entries_T_183 = pma_checker__entries_WIRE_15[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sw = pma_checker__entries_T_183; // @[TLB.scala:170:77] assign pma_checker__entries_T_184 = pma_checker__entries_WIRE_15[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_gf = pma_checker__entries_T_184; // @[TLB.scala:170:77] assign pma_checker__entries_T_185 = pma_checker__entries_WIRE_15[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pf = pma_checker__entries_T_185; // @[TLB.scala:170:77] assign pma_checker__entries_T_186 = pma_checker__entries_WIRE_15[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_stage2 = pma_checker__entries_T_186; // @[TLB.scala:170:77] assign pma_checker__entries_T_187 = pma_checker__entries_WIRE_15[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_final = pma_checker__entries_T_187; // @[TLB.scala:170:77] assign pma_checker__entries_T_188 = pma_checker__entries_WIRE_15[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_ptw = pma_checker__entries_T_188; // @[TLB.scala:170:77] assign pma_checker__entries_T_189 = pma_checker__entries_WIRE_15[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_g = pma_checker__entries_T_189; // @[TLB.scala:170:77] assign pma_checker__entries_T_190 = pma_checker__entries_WIRE_15[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_u = pma_checker__entries_T_190; // @[TLB.scala:170:77] assign pma_checker__entries_T_191 = pma_checker__entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_14_ppn = pma_checker__entries_T_191; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_214; // @[TLB.scala:170:77] wire pma_checker__entries_T_213; // @[TLB.scala:170:77] wire pma_checker__entries_T_212; // @[TLB.scala:170:77] wire pma_checker__entries_T_211; // @[TLB.scala:170:77] wire pma_checker__entries_T_210; // @[TLB.scala:170:77] wire pma_checker__entries_T_209; // @[TLB.scala:170:77] wire pma_checker__entries_T_208; // @[TLB.scala:170:77] wire pma_checker__entries_T_207; // @[TLB.scala:170:77] wire pma_checker__entries_T_206; // @[TLB.scala:170:77] wire pma_checker__entries_T_205; // @[TLB.scala:170:77] wire pma_checker__entries_T_204; // @[TLB.scala:170:77] wire pma_checker__entries_T_203; // @[TLB.scala:170:77] wire pma_checker__entries_T_202; // @[TLB.scala:170:77] wire pma_checker__entries_T_201; // @[TLB.scala:170:77] wire pma_checker__entries_T_200; // @[TLB.scala:170:77] wire pma_checker__entries_T_199; // @[TLB.scala:170:77] wire pma_checker__entries_T_198; // @[TLB.scala:170:77] wire pma_checker__entries_T_197; // @[TLB.scala:170:77] wire pma_checker__entries_T_196; // @[TLB.scala:170:77] wire pma_checker__entries_T_195; // @[TLB.scala:170:77] wire pma_checker__entries_T_194; // @[TLB.scala:170:77] wire pma_checker__entries_T_193; // @[TLB.scala:170:77] wire pma_checker__entries_T_192; // @[TLB.scala:170:77] assign pma_checker__entries_T_192 = pma_checker__entries_WIRE_17[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_fragmented_superpage = pma_checker__entries_T_192; // @[TLB.scala:170:77] assign pma_checker__entries_T_193 = pma_checker__entries_WIRE_17[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_c = pma_checker__entries_T_193; // @[TLB.scala:170:77] assign pma_checker__entries_T_194 = pma_checker__entries_WIRE_17[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_eff = pma_checker__entries_T_194; // @[TLB.scala:170:77] assign pma_checker__entries_T_195 = pma_checker__entries_WIRE_17[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_paa = pma_checker__entries_T_195; // @[TLB.scala:170:77] assign pma_checker__entries_T_196 = pma_checker__entries_WIRE_17[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pal = pma_checker__entries_T_196; // @[TLB.scala:170:77] assign pma_checker__entries_T_197 = pma_checker__entries_WIRE_17[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ppp = pma_checker__entries_T_197; // @[TLB.scala:170:77] assign pma_checker__entries_T_198 = pma_checker__entries_WIRE_17[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pr = pma_checker__entries_T_198; // @[TLB.scala:170:77] assign pma_checker__entries_T_199 = pma_checker__entries_WIRE_17[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_px = pma_checker__entries_T_199; // @[TLB.scala:170:77] assign pma_checker__entries_T_200 = pma_checker__entries_WIRE_17[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pw = pma_checker__entries_T_200; // @[TLB.scala:170:77] assign pma_checker__entries_T_201 = pma_checker__entries_WIRE_17[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hr = pma_checker__entries_T_201; // @[TLB.scala:170:77] assign pma_checker__entries_T_202 = pma_checker__entries_WIRE_17[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hx = pma_checker__entries_T_202; // @[TLB.scala:170:77] assign pma_checker__entries_T_203 = pma_checker__entries_WIRE_17[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hw = pma_checker__entries_T_203; // @[TLB.scala:170:77] assign pma_checker__entries_T_204 = pma_checker__entries_WIRE_17[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sr = pma_checker__entries_T_204; // @[TLB.scala:170:77] assign pma_checker__entries_T_205 = pma_checker__entries_WIRE_17[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sx = pma_checker__entries_T_205; // @[TLB.scala:170:77] assign pma_checker__entries_T_206 = pma_checker__entries_WIRE_17[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sw = pma_checker__entries_T_206; // @[TLB.scala:170:77] assign pma_checker__entries_T_207 = pma_checker__entries_WIRE_17[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_gf = pma_checker__entries_T_207; // @[TLB.scala:170:77] assign pma_checker__entries_T_208 = pma_checker__entries_WIRE_17[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pf = pma_checker__entries_T_208; // @[TLB.scala:170:77] assign pma_checker__entries_T_209 = pma_checker__entries_WIRE_17[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_stage2 = pma_checker__entries_T_209; // @[TLB.scala:170:77] assign pma_checker__entries_T_210 = pma_checker__entries_WIRE_17[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_final = pma_checker__entries_T_210; // @[TLB.scala:170:77] assign pma_checker__entries_T_211 = pma_checker__entries_WIRE_17[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_ptw = pma_checker__entries_T_211; // @[TLB.scala:170:77] assign pma_checker__entries_T_212 = pma_checker__entries_WIRE_17[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_g = pma_checker__entries_T_212; // @[TLB.scala:170:77] assign pma_checker__entries_T_213 = pma_checker__entries_WIRE_17[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_u = pma_checker__entries_T_213; // @[TLB.scala:170:77] assign pma_checker__entries_T_214 = pma_checker__entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_16_ppn = pma_checker__entries_T_214; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_237; // @[TLB.scala:170:77] wire pma_checker__entries_T_236; // @[TLB.scala:170:77] wire pma_checker__entries_T_235; // @[TLB.scala:170:77] wire pma_checker__entries_T_234; // @[TLB.scala:170:77] wire pma_checker__entries_T_233; // @[TLB.scala:170:77] wire pma_checker__entries_T_232; // @[TLB.scala:170:77] wire pma_checker__entries_T_231; // @[TLB.scala:170:77] wire pma_checker__entries_T_230; // @[TLB.scala:170:77] wire pma_checker__entries_T_229; // @[TLB.scala:170:77] wire pma_checker__entries_T_228; // @[TLB.scala:170:77] wire pma_checker__entries_T_227; // @[TLB.scala:170:77] wire pma_checker__entries_T_226; // @[TLB.scala:170:77] wire pma_checker__entries_T_225; // @[TLB.scala:170:77] wire pma_checker__entries_T_224; // @[TLB.scala:170:77] wire pma_checker__entries_T_223; // @[TLB.scala:170:77] wire pma_checker__entries_T_222; // @[TLB.scala:170:77] wire pma_checker__entries_T_221; // @[TLB.scala:170:77] wire pma_checker__entries_T_220; // @[TLB.scala:170:77] wire pma_checker__entries_T_219; // @[TLB.scala:170:77] wire pma_checker__entries_T_218; // @[TLB.scala:170:77] wire pma_checker__entries_T_217; // @[TLB.scala:170:77] wire pma_checker__entries_T_216; // @[TLB.scala:170:77] wire pma_checker__entries_T_215; // @[TLB.scala:170:77] assign pma_checker__entries_T_215 = pma_checker__entries_WIRE_19[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_fragmented_superpage = pma_checker__entries_T_215; // @[TLB.scala:170:77] assign pma_checker__entries_T_216 = pma_checker__entries_WIRE_19[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_c = pma_checker__entries_T_216; // @[TLB.scala:170:77] assign pma_checker__entries_T_217 = pma_checker__entries_WIRE_19[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_eff = pma_checker__entries_T_217; // @[TLB.scala:170:77] assign pma_checker__entries_T_218 = pma_checker__entries_WIRE_19[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_paa = pma_checker__entries_T_218; // @[TLB.scala:170:77] assign pma_checker__entries_T_219 = pma_checker__entries_WIRE_19[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pal = pma_checker__entries_T_219; // @[TLB.scala:170:77] assign pma_checker__entries_T_220 = pma_checker__entries_WIRE_19[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ppp = pma_checker__entries_T_220; // @[TLB.scala:170:77] assign pma_checker__entries_T_221 = pma_checker__entries_WIRE_19[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pr = pma_checker__entries_T_221; // @[TLB.scala:170:77] assign pma_checker__entries_T_222 = pma_checker__entries_WIRE_19[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_px = pma_checker__entries_T_222; // @[TLB.scala:170:77] assign pma_checker__entries_T_223 = pma_checker__entries_WIRE_19[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pw = pma_checker__entries_T_223; // @[TLB.scala:170:77] assign pma_checker__entries_T_224 = pma_checker__entries_WIRE_19[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hr = pma_checker__entries_T_224; // @[TLB.scala:170:77] assign pma_checker__entries_T_225 = pma_checker__entries_WIRE_19[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hx = pma_checker__entries_T_225; // @[TLB.scala:170:77] assign pma_checker__entries_T_226 = pma_checker__entries_WIRE_19[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hw = pma_checker__entries_T_226; // @[TLB.scala:170:77] assign pma_checker__entries_T_227 = pma_checker__entries_WIRE_19[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sr = pma_checker__entries_T_227; // @[TLB.scala:170:77] assign pma_checker__entries_T_228 = pma_checker__entries_WIRE_19[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sx = pma_checker__entries_T_228; // @[TLB.scala:170:77] assign pma_checker__entries_T_229 = pma_checker__entries_WIRE_19[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sw = pma_checker__entries_T_229; // @[TLB.scala:170:77] assign pma_checker__entries_T_230 = pma_checker__entries_WIRE_19[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_gf = pma_checker__entries_T_230; // @[TLB.scala:170:77] assign pma_checker__entries_T_231 = pma_checker__entries_WIRE_19[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pf = pma_checker__entries_T_231; // @[TLB.scala:170:77] assign pma_checker__entries_T_232 = pma_checker__entries_WIRE_19[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_stage2 = pma_checker__entries_T_232; // @[TLB.scala:170:77] assign pma_checker__entries_T_233 = pma_checker__entries_WIRE_19[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_final = pma_checker__entries_T_233; // @[TLB.scala:170:77] assign pma_checker__entries_T_234 = pma_checker__entries_WIRE_19[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_ptw = pma_checker__entries_T_234; // @[TLB.scala:170:77] assign pma_checker__entries_T_235 = pma_checker__entries_WIRE_19[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_g = pma_checker__entries_T_235; // @[TLB.scala:170:77] assign pma_checker__entries_T_236 = pma_checker__entries_WIRE_19[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_u = pma_checker__entries_T_236; // @[TLB.scala:170:77] assign pma_checker__entries_T_237 = pma_checker__entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_18_ppn = pma_checker__entries_T_237; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_260; // @[TLB.scala:170:77] wire pma_checker__entries_T_259; // @[TLB.scala:170:77] wire pma_checker__entries_T_258; // @[TLB.scala:170:77] wire pma_checker__entries_T_257; // @[TLB.scala:170:77] wire pma_checker__entries_T_256; // @[TLB.scala:170:77] wire pma_checker__entries_T_255; // @[TLB.scala:170:77] wire pma_checker__entries_T_254; // @[TLB.scala:170:77] wire pma_checker__entries_T_253; // @[TLB.scala:170:77] wire pma_checker__entries_T_252; // @[TLB.scala:170:77] wire pma_checker__entries_T_251; // @[TLB.scala:170:77] wire pma_checker__entries_T_250; // @[TLB.scala:170:77] wire pma_checker__entries_T_249; // @[TLB.scala:170:77] wire pma_checker__entries_T_248; // @[TLB.scala:170:77] wire pma_checker__entries_T_247; // @[TLB.scala:170:77] wire pma_checker__entries_T_246; // @[TLB.scala:170:77] wire pma_checker__entries_T_245; // @[TLB.scala:170:77] wire pma_checker__entries_T_244; // @[TLB.scala:170:77] wire pma_checker__entries_T_243; // @[TLB.scala:170:77] wire pma_checker__entries_T_242; // @[TLB.scala:170:77] wire pma_checker__entries_T_241; // @[TLB.scala:170:77] wire pma_checker__entries_T_240; // @[TLB.scala:170:77] wire pma_checker__entries_T_239; // @[TLB.scala:170:77] wire pma_checker__entries_T_238; // @[TLB.scala:170:77] assign pma_checker__entries_T_238 = pma_checker__entries_WIRE_21[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_fragmented_superpage = pma_checker__entries_T_238; // @[TLB.scala:170:77] assign pma_checker__entries_T_239 = pma_checker__entries_WIRE_21[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_c = pma_checker__entries_T_239; // @[TLB.scala:170:77] assign pma_checker__entries_T_240 = pma_checker__entries_WIRE_21[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_eff = pma_checker__entries_T_240; // @[TLB.scala:170:77] assign pma_checker__entries_T_241 = pma_checker__entries_WIRE_21[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_paa = pma_checker__entries_T_241; // @[TLB.scala:170:77] assign pma_checker__entries_T_242 = pma_checker__entries_WIRE_21[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pal = pma_checker__entries_T_242; // @[TLB.scala:170:77] assign pma_checker__entries_T_243 = pma_checker__entries_WIRE_21[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ppp = pma_checker__entries_T_243; // @[TLB.scala:170:77] assign pma_checker__entries_T_244 = pma_checker__entries_WIRE_21[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pr = pma_checker__entries_T_244; // @[TLB.scala:170:77] assign pma_checker__entries_T_245 = pma_checker__entries_WIRE_21[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_px = pma_checker__entries_T_245; // @[TLB.scala:170:77] assign pma_checker__entries_T_246 = pma_checker__entries_WIRE_21[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pw = pma_checker__entries_T_246; // @[TLB.scala:170:77] assign pma_checker__entries_T_247 = pma_checker__entries_WIRE_21[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hr = pma_checker__entries_T_247; // @[TLB.scala:170:77] assign pma_checker__entries_T_248 = pma_checker__entries_WIRE_21[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hx = pma_checker__entries_T_248; // @[TLB.scala:170:77] assign pma_checker__entries_T_249 = pma_checker__entries_WIRE_21[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hw = pma_checker__entries_T_249; // @[TLB.scala:170:77] assign pma_checker__entries_T_250 = pma_checker__entries_WIRE_21[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sr = pma_checker__entries_T_250; // @[TLB.scala:170:77] assign pma_checker__entries_T_251 = pma_checker__entries_WIRE_21[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sx = pma_checker__entries_T_251; // @[TLB.scala:170:77] assign pma_checker__entries_T_252 = pma_checker__entries_WIRE_21[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sw = pma_checker__entries_T_252; // @[TLB.scala:170:77] assign pma_checker__entries_T_253 = pma_checker__entries_WIRE_21[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_gf = pma_checker__entries_T_253; // @[TLB.scala:170:77] assign pma_checker__entries_T_254 = pma_checker__entries_WIRE_21[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pf = pma_checker__entries_T_254; // @[TLB.scala:170:77] assign pma_checker__entries_T_255 = pma_checker__entries_WIRE_21[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_stage2 = pma_checker__entries_T_255; // @[TLB.scala:170:77] assign pma_checker__entries_T_256 = pma_checker__entries_WIRE_21[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_final = pma_checker__entries_T_256; // @[TLB.scala:170:77] assign pma_checker__entries_T_257 = pma_checker__entries_WIRE_21[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_ptw = pma_checker__entries_T_257; // @[TLB.scala:170:77] assign pma_checker__entries_T_258 = pma_checker__entries_WIRE_21[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_g = pma_checker__entries_T_258; // @[TLB.scala:170:77] assign pma_checker__entries_T_259 = pma_checker__entries_WIRE_21[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_u = pma_checker__entries_T_259; // @[TLB.scala:170:77] assign pma_checker__entries_T_260 = pma_checker__entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_20_ppn = pma_checker__entries_T_260; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_283; // @[TLB.scala:170:77] wire pma_checker__entries_T_282; // @[TLB.scala:170:77] wire pma_checker__entries_T_281; // @[TLB.scala:170:77] wire pma_checker__entries_T_280; // @[TLB.scala:170:77] wire pma_checker__entries_T_279; // @[TLB.scala:170:77] wire pma_checker__entries_T_278; // @[TLB.scala:170:77] wire pma_checker__entries_T_277; // @[TLB.scala:170:77] wire pma_checker__entries_T_276; // @[TLB.scala:170:77] wire pma_checker__entries_T_275; // @[TLB.scala:170:77] wire pma_checker__entries_T_274; // @[TLB.scala:170:77] wire pma_checker__entries_T_273; // @[TLB.scala:170:77] wire pma_checker__entries_T_272; // @[TLB.scala:170:77] wire pma_checker__entries_T_271; // @[TLB.scala:170:77] wire pma_checker__entries_T_270; // @[TLB.scala:170:77] wire pma_checker__entries_T_269; // @[TLB.scala:170:77] wire pma_checker__entries_T_268; // @[TLB.scala:170:77] wire pma_checker__entries_T_267; // @[TLB.scala:170:77] wire pma_checker__entries_T_266; // @[TLB.scala:170:77] wire pma_checker__entries_T_265; // @[TLB.scala:170:77] wire pma_checker__entries_T_264; // @[TLB.scala:170:77] wire pma_checker__entries_T_263; // @[TLB.scala:170:77] wire pma_checker__entries_T_262; // @[TLB.scala:170:77] wire pma_checker__entries_T_261; // @[TLB.scala:170:77] assign pma_checker__entries_T_261 = pma_checker__entries_WIRE_23[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_fragmented_superpage = pma_checker__entries_T_261; // @[TLB.scala:170:77] assign pma_checker__entries_T_262 = pma_checker__entries_WIRE_23[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_c = pma_checker__entries_T_262; // @[TLB.scala:170:77] assign pma_checker__entries_T_263 = pma_checker__entries_WIRE_23[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_eff = pma_checker__entries_T_263; // @[TLB.scala:170:77] assign pma_checker__entries_T_264 = pma_checker__entries_WIRE_23[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_paa = pma_checker__entries_T_264; // @[TLB.scala:170:77] assign pma_checker__entries_T_265 = pma_checker__entries_WIRE_23[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pal = pma_checker__entries_T_265; // @[TLB.scala:170:77] assign pma_checker__entries_T_266 = pma_checker__entries_WIRE_23[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ppp = pma_checker__entries_T_266; // @[TLB.scala:170:77] assign pma_checker__entries_T_267 = pma_checker__entries_WIRE_23[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pr = pma_checker__entries_T_267; // @[TLB.scala:170:77] assign pma_checker__entries_T_268 = pma_checker__entries_WIRE_23[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_px = pma_checker__entries_T_268; // @[TLB.scala:170:77] assign pma_checker__entries_T_269 = pma_checker__entries_WIRE_23[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pw = pma_checker__entries_T_269; // @[TLB.scala:170:77] assign pma_checker__entries_T_270 = pma_checker__entries_WIRE_23[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hr = pma_checker__entries_T_270; // @[TLB.scala:170:77] assign pma_checker__entries_T_271 = pma_checker__entries_WIRE_23[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hx = pma_checker__entries_T_271; // @[TLB.scala:170:77] assign pma_checker__entries_T_272 = pma_checker__entries_WIRE_23[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hw = pma_checker__entries_T_272; // @[TLB.scala:170:77] assign pma_checker__entries_T_273 = pma_checker__entries_WIRE_23[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sr = pma_checker__entries_T_273; // @[TLB.scala:170:77] assign pma_checker__entries_T_274 = pma_checker__entries_WIRE_23[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sx = pma_checker__entries_T_274; // @[TLB.scala:170:77] assign pma_checker__entries_T_275 = pma_checker__entries_WIRE_23[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sw = pma_checker__entries_T_275; // @[TLB.scala:170:77] assign pma_checker__entries_T_276 = pma_checker__entries_WIRE_23[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_gf = pma_checker__entries_T_276; // @[TLB.scala:170:77] assign pma_checker__entries_T_277 = pma_checker__entries_WIRE_23[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pf = pma_checker__entries_T_277; // @[TLB.scala:170:77] assign pma_checker__entries_T_278 = pma_checker__entries_WIRE_23[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_stage2 = pma_checker__entries_T_278; // @[TLB.scala:170:77] assign pma_checker__entries_T_279 = pma_checker__entries_WIRE_23[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_final = pma_checker__entries_T_279; // @[TLB.scala:170:77] assign pma_checker__entries_T_280 = pma_checker__entries_WIRE_23[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_ptw = pma_checker__entries_T_280; // @[TLB.scala:170:77] assign pma_checker__entries_T_281 = pma_checker__entries_WIRE_23[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_g = pma_checker__entries_T_281; // @[TLB.scala:170:77] assign pma_checker__entries_T_282 = pma_checker__entries_WIRE_23[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_u = pma_checker__entries_T_282; // @[TLB.scala:170:77] assign pma_checker__entries_T_283 = pma_checker__entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_22_ppn = pma_checker__entries_T_283; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_306; // @[TLB.scala:170:77] wire pma_checker__entries_T_305; // @[TLB.scala:170:77] wire pma_checker__entries_T_304; // @[TLB.scala:170:77] wire pma_checker__entries_T_303; // @[TLB.scala:170:77] wire pma_checker__entries_T_302; // @[TLB.scala:170:77] wire pma_checker__entries_T_301; // @[TLB.scala:170:77] wire pma_checker__entries_T_300; // @[TLB.scala:170:77] wire pma_checker__entries_T_299; // @[TLB.scala:170:77] wire pma_checker__entries_T_298; // @[TLB.scala:170:77] wire pma_checker__entries_T_297; // @[TLB.scala:170:77] wire pma_checker__entries_T_296; // @[TLB.scala:170:77] wire pma_checker__entries_T_295; // @[TLB.scala:170:77] wire pma_checker__entries_T_294; // @[TLB.scala:170:77] wire pma_checker__entries_T_293; // @[TLB.scala:170:77] wire pma_checker__entries_T_292; // @[TLB.scala:170:77] wire pma_checker__entries_T_291; // @[TLB.scala:170:77] wire pma_checker__entries_T_290; // @[TLB.scala:170:77] wire pma_checker__entries_T_289; // @[TLB.scala:170:77] wire pma_checker__entries_T_288; // @[TLB.scala:170:77] wire pma_checker__entries_T_287; // @[TLB.scala:170:77] wire pma_checker__entries_T_286; // @[TLB.scala:170:77] wire pma_checker__entries_T_285; // @[TLB.scala:170:77] wire pma_checker__entries_T_284; // @[TLB.scala:170:77] assign pma_checker__entries_T_284 = pma_checker__entries_WIRE_25[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_fragmented_superpage = pma_checker__entries_T_284; // @[TLB.scala:170:77] assign pma_checker__entries_T_285 = pma_checker__entries_WIRE_25[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_c = pma_checker__entries_T_285; // @[TLB.scala:170:77] assign pma_checker__entries_T_286 = pma_checker__entries_WIRE_25[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_eff = pma_checker__entries_T_286; // @[TLB.scala:170:77] assign pma_checker__entries_T_287 = pma_checker__entries_WIRE_25[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_paa = pma_checker__entries_T_287; // @[TLB.scala:170:77] assign pma_checker__entries_T_288 = pma_checker__entries_WIRE_25[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pal = pma_checker__entries_T_288; // @[TLB.scala:170:77] assign pma_checker__entries_T_289 = pma_checker__entries_WIRE_25[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ppp = pma_checker__entries_T_289; // @[TLB.scala:170:77] assign pma_checker__entries_T_290 = pma_checker__entries_WIRE_25[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pr = pma_checker__entries_T_290; // @[TLB.scala:170:77] assign pma_checker__entries_T_291 = pma_checker__entries_WIRE_25[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_px = pma_checker__entries_T_291; // @[TLB.scala:170:77] assign pma_checker__entries_T_292 = pma_checker__entries_WIRE_25[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pw = pma_checker__entries_T_292; // @[TLB.scala:170:77] assign pma_checker__entries_T_293 = pma_checker__entries_WIRE_25[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hr = pma_checker__entries_T_293; // @[TLB.scala:170:77] assign pma_checker__entries_T_294 = pma_checker__entries_WIRE_25[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hx = pma_checker__entries_T_294; // @[TLB.scala:170:77] assign pma_checker__entries_T_295 = pma_checker__entries_WIRE_25[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hw = pma_checker__entries_T_295; // @[TLB.scala:170:77] assign pma_checker__entries_T_296 = pma_checker__entries_WIRE_25[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sr = pma_checker__entries_T_296; // @[TLB.scala:170:77] assign pma_checker__entries_T_297 = pma_checker__entries_WIRE_25[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sx = pma_checker__entries_T_297; // @[TLB.scala:170:77] assign pma_checker__entries_T_298 = pma_checker__entries_WIRE_25[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sw = pma_checker__entries_T_298; // @[TLB.scala:170:77] assign pma_checker__entries_T_299 = pma_checker__entries_WIRE_25[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_gf = pma_checker__entries_T_299; // @[TLB.scala:170:77] assign pma_checker__entries_T_300 = pma_checker__entries_WIRE_25[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pf = pma_checker__entries_T_300; // @[TLB.scala:170:77] assign pma_checker__entries_T_301 = pma_checker__entries_WIRE_25[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_stage2 = pma_checker__entries_T_301; // @[TLB.scala:170:77] assign pma_checker__entries_T_302 = pma_checker__entries_WIRE_25[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_final = pma_checker__entries_T_302; // @[TLB.scala:170:77] assign pma_checker__entries_T_303 = pma_checker__entries_WIRE_25[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_ptw = pma_checker__entries_T_303; // @[TLB.scala:170:77] assign pma_checker__entries_T_304 = pma_checker__entries_WIRE_25[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_g = pma_checker__entries_T_304; // @[TLB.scala:170:77] assign pma_checker__entries_T_305 = pma_checker__entries_WIRE_25[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_u = pma_checker__entries_T_305; // @[TLB.scala:170:77] assign pma_checker__entries_T_306 = pma_checker__entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_24_ppn = pma_checker__entries_T_306; // @[TLB.scala:170:77] wire [1:0] pma_checker_ppn_res = _pma_checker_entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore = pma_checker__ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_1 = pma_checker_ppn_ignore ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_2 = {pma_checker__ppn_T_1[26:20], pma_checker__ppn_T_1[19:0] | _pma_checker_entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_3 = pma_checker__ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_4 = {pma_checker_ppn_res, pma_checker__ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_6 = {pma_checker__ppn_T_5[26:20], pma_checker__ppn_T_5[19:0] | _pma_checker_entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_7 = pma_checker__ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_8 = {pma_checker__ppn_T_4, pma_checker__ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_1 = _pma_checker_entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore_2 = pma_checker__ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_9 = pma_checker_ppn_ignore_2 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_10 = {pma_checker__ppn_T_9[26:20], pma_checker__ppn_T_9[19:0] | _pma_checker_entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_11 = pma_checker__ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_12 = {pma_checker_ppn_res_1, pma_checker__ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_14 = {pma_checker__ppn_T_13[26:20], pma_checker__ppn_T_13[19:0] | _pma_checker_entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_15 = pma_checker__ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_16 = {pma_checker__ppn_T_12, pma_checker__ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_2 = _pma_checker_entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore_4 = pma_checker__ppn_ignore_T_4; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_17 = pma_checker_ppn_ignore_4 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_18 = {pma_checker__ppn_T_17[26:20], pma_checker__ppn_T_17[19:0] | _pma_checker_entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_19 = pma_checker__ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_20 = {pma_checker_ppn_res_2, pma_checker__ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_22 = {pma_checker__ppn_T_21[26:20], pma_checker__ppn_T_21[19:0] | _pma_checker_entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_23 = pma_checker__ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_24 = {pma_checker__ppn_T_20, pma_checker__ppn_T_23}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_3 = _pma_checker_entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore_6 = pma_checker__ppn_ignore_T_6; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_25 = pma_checker_ppn_ignore_6 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_26 = {pma_checker__ppn_T_25[26:20], pma_checker__ppn_T_25[19:0] | _pma_checker_entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_27 = pma_checker__ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_28 = {pma_checker_ppn_res_3, pma_checker__ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_30 = {pma_checker__ppn_T_29[26:20], pma_checker__ppn_T_29[19:0] | _pma_checker_entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_31 = pma_checker__ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_32 = {pma_checker__ppn_T_28, pma_checker__ppn_T_31}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_4 = _pma_checker_entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25] wire [26:0] pma_checker__ppn_T_34 = {pma_checker__ppn_T_33[26:20], pma_checker__ppn_T_33[19:0] | _pma_checker_entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_35 = pma_checker__ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_36 = {pma_checker_ppn_res_4, pma_checker__ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_38 = {pma_checker__ppn_T_37[26:20], pma_checker__ppn_T_37[19:0] | _pma_checker_entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_39 = pma_checker__ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_40 = {pma_checker__ppn_T_36, pma_checker__ppn_T_39}; // @[TLB.scala:198:{18,58}] wire [19:0] pma_checker__ppn_T_41 = pma_checker_vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] pma_checker__ppn_T_55 = pma_checker__ppn_T_41; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_68 = pma_checker__ppn_T_55; // @[Mux.scala:30:73] wire [19:0] pma_checker_ppn = pma_checker__ppn_T_68; // @[Mux.scala:30:73] wire [1:0] pma_checker_ptw_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_ptw, _pma_checker_entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_lo_lo = {pma_checker_ptw_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_ptw, _pma_checker_entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_lo_hi = {pma_checker_ptw_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_ae_array_lo = {pma_checker_ptw_ae_array_lo_hi, pma_checker_ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_ptw, _pma_checker_entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_hi_lo = {pma_checker_ptw_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_ptw, _pma_checker_entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_ptw, _pma_checker_entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_ae_array_hi_hi = {pma_checker_ptw_ae_array_hi_hi_hi, pma_checker_ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_ae_array_hi = {pma_checker_ptw_ae_array_hi_hi, pma_checker_ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_ae_array_T = {pma_checker_ptw_ae_array_hi, pma_checker_ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_ae_array = {1'h0, pma_checker__ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_final_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_final, _pma_checker_entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_lo_lo = {pma_checker_final_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_final, _pma_checker_entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_lo_hi = {pma_checker_final_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_final_ae_array_lo = {pma_checker_final_ae_array_lo_hi, pma_checker_final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_final_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_final, _pma_checker_entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_hi_lo = {pma_checker_final_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_final, _pma_checker_entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_final, _pma_checker_entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_final_ae_array_hi_hi = {pma_checker_final_ae_array_hi_hi_hi, pma_checker_final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_final_ae_array_hi = {pma_checker_final_ae_array_hi_hi, pma_checker_final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__final_ae_array_T = {pma_checker_final_ae_array_hi, pma_checker_final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_final_ae_array = {1'h0, pma_checker__final_ae_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_pf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pf, _pma_checker_entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_lo_lo = {pma_checker_ptw_pf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pf, _pma_checker_entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_lo_hi = {pma_checker_ptw_pf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_pf_array_lo = {pma_checker_ptw_pf_array_lo_hi, pma_checker_ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_pf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pf, _pma_checker_entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_hi_lo = {pma_checker_ptw_pf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_pf, _pma_checker_entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_pf, _pma_checker_entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_pf_array_hi_hi = {pma_checker_ptw_pf_array_hi_hi_hi, pma_checker_ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_pf_array_hi = {pma_checker_ptw_pf_array_hi_hi, pma_checker_ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_pf_array_T = {pma_checker_ptw_pf_array_hi, pma_checker_ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_pf_array = {1'h0, pma_checker__ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_gf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_gf, _pma_checker_entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_lo_lo = {pma_checker_ptw_gf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_gf, _pma_checker_entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_lo_hi = {pma_checker_ptw_gf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_gf_array_lo = {pma_checker_ptw_gf_array_lo_hi, pma_checker_ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_gf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_gf, _pma_checker_entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_hi_lo = {pma_checker_ptw_gf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_gf, _pma_checker_entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_gf, _pma_checker_entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_gf_array_hi_hi = {pma_checker_ptw_gf_array_hi_hi_hi, pma_checker_ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_gf_array_hi = {pma_checker_ptw_gf_array_hi_hi, pma_checker_ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_gf_array_T = {pma_checker_ptw_gf_array_hi, pma_checker_ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_gf_array = {1'h0, pma_checker__ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] pma_checker__gf_ld_array_T_3 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] pma_checker__gf_st_array_T_2 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] pma_checker__gf_inst_array_T_1 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire pma_checker__priv_rw_ok_T = ~pma_checker_priv_s; // @[TLB.scala:370:20, :513:24] wire pma_checker__priv_rw_ok_T_1 = pma_checker__priv_rw_ok_T; // @[TLB.scala:513:{24,32}] wire [1:0] _GEN_6 = {_pma_checker_entries_barrier_2_io_y_u, _pma_checker_entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_lo_hi = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_lo_hi_1 = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_lo_hi = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_lo_hi_1 = _GEN_6; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_lo = {pma_checker_priv_rw_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_7 = {_pma_checker_entries_barrier_5_io_y_u, _pma_checker_entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_hi_hi = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_hi_hi_1 = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_hi_hi = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_hi_hi_1 = _GEN_7; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_hi = {pma_checker_priv_rw_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_rw_ok_lo = {pma_checker_priv_rw_ok_lo_hi, pma_checker_priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_8 = {_pma_checker_entries_barrier_8_io_y_u, _pma_checker_entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_lo_hi = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_lo_hi_1 = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_lo_hi = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_lo_hi_1 = _GEN_8; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_hi_lo = {pma_checker_priv_rw_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_9 = {_pma_checker_entries_barrier_10_io_y_u, _pma_checker_entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_lo = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_lo_1 = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_lo = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_lo_1 = _GEN_9; // @[package.scala:45:27] wire [1:0] _GEN_10 = {_pma_checker_entries_barrier_12_io_y_u, _pma_checker_entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_hi = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_hi_1 = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_hi = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_hi_1 = _GEN_10; // @[package.scala:45:27] wire [3:0] pma_checker_priv_rw_ok_hi_hi = {pma_checker_priv_rw_ok_hi_hi_hi, pma_checker_priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_rw_ok_hi = {pma_checker_priv_rw_ok_hi_hi, pma_checker_priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_2 = {pma_checker_priv_rw_ok_hi, pma_checker_priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_3 = pma_checker__priv_rw_ok_T_1 ? pma_checker__priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_lo_1 = {pma_checker_priv_rw_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_rw_ok_lo_hi_1 = {pma_checker_priv_rw_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_rw_ok_lo_1 = {pma_checker_priv_rw_ok_lo_hi_1, pma_checker_priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_hi_lo_1 = {pma_checker_priv_rw_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_rw_ok_hi_hi_1 = {pma_checker_priv_rw_ok_hi_hi_hi_1, pma_checker_priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_rw_ok_hi_1 = {pma_checker_priv_rw_ok_hi_hi_1, pma_checker_priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_4 = {pma_checker_priv_rw_ok_hi_1, pma_checker_priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_5 = ~pma_checker__priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_6 = pma_checker_priv_s ? pma_checker__priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] pma_checker_priv_rw_ok = pma_checker__priv_rw_ok_T_3 | pma_checker__priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] pma_checker_priv_x_ok_lo_lo = {pma_checker_priv_x_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_x_ok_lo_hi = {pma_checker_priv_x_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_x_ok_lo = {pma_checker_priv_x_ok_lo_hi, pma_checker_priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_hi_lo = {pma_checker_priv_x_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_x_ok_hi_hi = {pma_checker_priv_x_ok_hi_hi_hi, pma_checker_priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_x_ok_hi = {pma_checker_priv_x_ok_hi_hi, pma_checker_priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T = {pma_checker_priv_x_ok_hi, pma_checker_priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T_1 = ~pma_checker__priv_x_ok_T; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_lo_lo_1 = {pma_checker_priv_x_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_x_ok_lo_hi_1 = {pma_checker_priv_x_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_x_ok_lo_1 = {pma_checker_priv_x_ok_lo_hi_1, pma_checker_priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_hi_lo_1 = {pma_checker_priv_x_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_x_ok_hi_hi_1 = {pma_checker_priv_x_ok_hi_hi_hi_1, pma_checker_priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_x_ok_hi_1 = {pma_checker_priv_x_ok_hi_hi_1, pma_checker_priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T_2 = {pma_checker_priv_x_ok_hi_1, pma_checker_priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker_priv_x_ok = pma_checker_priv_s ? pma_checker__priv_x_ok_T_1 : pma_checker__priv_x_ok_T_2; // @[package.scala:45:27] wire [1:0] pma_checker_stage1_bypass_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_stage2, _pma_checker_entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_lo_lo = {pma_checker_stage1_bypass_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_stage2, _pma_checker_entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_lo_hi = {pma_checker_stage1_bypass_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_stage1_bypass_lo = {pma_checker_stage1_bypass_lo_hi, pma_checker_stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_stage1_bypass_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_stage2, _pma_checker_entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_hi_lo = {pma_checker_stage1_bypass_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_stage2, _pma_checker_entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_stage2, _pma_checker_entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_stage1_bypass_hi_hi = {pma_checker_stage1_bypass_hi_hi_hi, pma_checker_stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_stage1_bypass_hi = {pma_checker_stage1_bypass_hi_hi, pma_checker_stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__stage1_bypass_T_3 = {pma_checker_stage1_bypass_hi, pma_checker_stage1_bypass_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_r_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sr, _pma_checker_entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_lo_lo = {pma_checker_r_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sr, _pma_checker_entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_lo_hi = {pma_checker_r_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_r_array_lo = {pma_checker_r_array_lo_hi, pma_checker_r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_r_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sr, _pma_checker_entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_hi_lo = {pma_checker_r_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sr, _pma_checker_entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sr, _pma_checker_entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_r_array_hi_hi = {pma_checker_r_array_hi_hi_hi, pma_checker_r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_r_array_hi = {pma_checker_r_array_hi_hi, pma_checker_r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T = {pma_checker_r_array_hi, pma_checker_r_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_3 = pma_checker__r_array_T; // @[package.scala:45:27] wire [1:0] _GEN_11 = {_pma_checker_entries_barrier_2_io_y_sx, _pma_checker_entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_lo_lo_hi_1 = _GEN_11; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_x_array_lo_lo_hi = _GEN_11; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_lo_lo_1 = {pma_checker_r_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_12 = {_pma_checker_entries_barrier_5_io_y_sx, _pma_checker_entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_lo_hi_hi_1 = _GEN_12; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_x_array_lo_hi_hi = _GEN_12; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_lo_hi_1 = {pma_checker_r_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_r_array_lo_1 = {pma_checker_r_array_lo_hi_1, pma_checker_r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_13 = {_pma_checker_entries_barrier_8_io_y_sx, _pma_checker_entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_lo_hi_1 = _GEN_13; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_x_array_hi_lo_hi = _GEN_13; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_hi_lo_1 = {pma_checker_r_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_14 = {_pma_checker_entries_barrier_10_io_y_sx, _pma_checker_entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_hi_lo_1 = _GEN_14; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_x_array_hi_hi_lo = _GEN_14; // @[package.scala:45:27] wire [1:0] _GEN_15 = {_pma_checker_entries_barrier_12_io_y_sx, _pma_checker_entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_hi_hi_1 = _GEN_15; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_x_array_hi_hi_hi = _GEN_15; // @[package.scala:45:27] wire [3:0] pma_checker_r_array_hi_hi_1 = {pma_checker_r_array_hi_hi_hi_1, pma_checker_r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_r_array_hi_1 = {pma_checker_r_array_hi_hi_1, pma_checker_r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_1 = {pma_checker_r_array_hi_1, pma_checker_r_array_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_4 = pma_checker_priv_rw_ok & pma_checker__r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] pma_checker__r_array_T_5 = pma_checker__r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] pma_checker_r_array = {1'h1, pma_checker__r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] pma_checker__pf_ld_array_T = pma_checker_r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] pma_checker_w_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sw, _pma_checker_entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_lo_lo = {pma_checker_w_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sw, _pma_checker_entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_lo_hi = {pma_checker_w_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_w_array_lo = {pma_checker_w_array_lo_hi, pma_checker_w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_w_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sw, _pma_checker_entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_hi_lo = {pma_checker_w_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sw, _pma_checker_entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sw, _pma_checker_entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_w_array_hi_hi = {pma_checker_w_array_hi_hi_hi, pma_checker_w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_w_array_hi = {pma_checker_w_array_hi_hi, pma_checker_w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T = {pma_checker_w_array_hi, pma_checker_w_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T_1 = pma_checker_priv_rw_ok & pma_checker__w_array_T; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T_2 = pma_checker__w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] pma_checker_w_array = {1'h1, pma_checker__w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] pma_checker_x_array_lo_lo = {pma_checker_x_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_x_array_lo_hi = {pma_checker_x_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_x_array_lo = {pma_checker_x_array_lo_hi, pma_checker_x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_x_array_hi_lo = {pma_checker_x_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_x_array_hi_hi = {pma_checker_x_array_hi_hi_hi, pma_checker_x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_x_array_hi = {pma_checker_x_array_hi_hi, pma_checker_x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T = {pma_checker_x_array_hi, pma_checker_x_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T_1 = pma_checker_priv_x_ok & pma_checker__x_array_T; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T_2 = pma_checker__x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] pma_checker_x_array = {1'h1, pma_checker__x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] pma_checker_hr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hr, _pma_checker_entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_lo_lo = {pma_checker_hr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hr, _pma_checker_entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_lo_hi = {pma_checker_hr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hr_array_lo = {pma_checker_hr_array_lo_hi, pma_checker_hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_hr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hr, _pma_checker_entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_hi_lo = {pma_checker_hr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hr, _pma_checker_entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hr, _pma_checker_entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hr_array_hi_hi = {pma_checker_hr_array_hi_hi_hi, pma_checker_hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hr_array_hi = {pma_checker_hr_array_hi_hi, pma_checker_hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T = {pma_checker_hr_array_hi, pma_checker_hr_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T_3 = pma_checker__hr_array_T; // @[package.scala:45:27] wire [1:0] _GEN_16 = {_pma_checker_entries_barrier_2_io_y_hx, _pma_checker_entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_lo_lo_hi_1 = _GEN_16; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_hx_array_lo_lo_hi = _GEN_16; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_lo_lo_1 = {pma_checker_hr_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_17 = {_pma_checker_entries_barrier_5_io_y_hx, _pma_checker_entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_lo_hi_hi_1 = _GEN_17; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_hx_array_lo_hi_hi = _GEN_17; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_lo_hi_1 = {pma_checker_hr_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hr_array_lo_1 = {pma_checker_hr_array_lo_hi_1, pma_checker_hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_18 = {_pma_checker_entries_barrier_8_io_y_hx, _pma_checker_entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_lo_hi_1 = _GEN_18; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_hx_array_hi_lo_hi = _GEN_18; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_hi_lo_1 = {pma_checker_hr_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_19 = {_pma_checker_entries_barrier_10_io_y_hx, _pma_checker_entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_hi_lo_1 = _GEN_19; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_hx_array_hi_hi_lo = _GEN_19; // @[package.scala:45:27] wire [1:0] _GEN_20 = {_pma_checker_entries_barrier_12_io_y_hx, _pma_checker_entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_hi_hi_1 = _GEN_20; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_hx_array_hi_hi_hi = _GEN_20; // @[package.scala:45:27] wire [3:0] pma_checker_hr_array_hi_hi_1 = {pma_checker_hr_array_hi_hi_hi_1, pma_checker_hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_hr_array_hi_1 = {pma_checker_hr_array_hi_hi_1, pma_checker_hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T_1 = {pma_checker_hr_array_hi_1, pma_checker_hr_array_lo_1}; // @[package.scala:45:27] wire [1:0] pma_checker_hw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hw, _pma_checker_entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_lo_lo = {pma_checker_hw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hw, _pma_checker_entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_lo_hi = {pma_checker_hw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hw_array_lo = {pma_checker_hw_array_lo_hi, pma_checker_hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_hw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hw, _pma_checker_entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_hi_lo = {pma_checker_hw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hw, _pma_checker_entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hw, _pma_checker_entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hw_array_hi_hi = {pma_checker_hw_array_hi_hi_hi, pma_checker_hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hw_array_hi = {pma_checker_hw_array_hi_hi, pma_checker_hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hw_array_T = {pma_checker_hw_array_hi, pma_checker_hw_array_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_hx_array_lo_lo = {pma_checker_hx_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hx_array_lo_hi = {pma_checker_hx_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hx_array_lo = {pma_checker_hx_array_lo_hi, pma_checker_hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_hx_array_hi_lo = {pma_checker_hx_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hx_array_hi_hi = {pma_checker_hx_array_hi_hi_hi, pma_checker_hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hx_array_hi = {pma_checker_hx_array_hi_hi, pma_checker_hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hx_array_T = {pma_checker_hx_array_hi, pma_checker_hx_array_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pr, _pma_checker_entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_lo_lo = {pma_checker_pr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pr, _pma_checker_entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_lo_hi = {pma_checker_pr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pr_array_lo = {pma_checker_pr_array_lo_hi, pma_checker_pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pr, _pma_checker_entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_hi_lo = {pma_checker_pr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pr_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pr, _pma_checker_entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_hi_hi = {pma_checker_pr_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pr_array_hi = {pma_checker_pr_array_hi_hi, pma_checker_pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pr_array_T_1 = {pma_checker_pr_array_hi, pma_checker_pr_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__pr_array_T_2 = {2'h0, pma_checker__pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_21 = pma_checker_ptw_ae_array | pma_checker_final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] pma_checker__pr_array_T_3; // @[TLB.scala:529:104] assign pma_checker__pr_array_T_3 = _GEN_21; // @[TLB.scala:529:104] wire [13:0] pma_checker__pw_array_T_3; // @[TLB.scala:531:104] assign pma_checker__pw_array_T_3 = _GEN_21; // @[TLB.scala:529:104, :531:104] wire [13:0] pma_checker__px_array_T_3; // @[TLB.scala:533:104] assign pma_checker__px_array_T_3 = _GEN_21; // @[TLB.scala:529:104, :533:104] wire [13:0] pma_checker__pr_array_T_4 = ~pma_checker__pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pma_checker_pr_array = pma_checker__pr_array_T_2 & pma_checker__pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] pma_checker_pw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pw, _pma_checker_entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_lo_lo = {pma_checker_pw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pw, _pma_checker_entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_lo_hi = {pma_checker_pw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pw_array_lo = {pma_checker_pw_array_lo_hi, pma_checker_pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pw, _pma_checker_entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_hi_lo = {pma_checker_pw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pw_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pw, _pma_checker_entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_hi_hi = {pma_checker_pw_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pw_array_hi = {pma_checker_pw_array_hi_hi, pma_checker_pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pw_array_T_1 = {pma_checker_pw_array_hi, pma_checker_pw_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__pw_array_T_2 = {2'h0, pma_checker__pw_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker__pw_array_T_4 = ~pma_checker__pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pma_checker_pw_array = pma_checker__pw_array_T_2 & pma_checker__pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] pma_checker_px_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_px, _pma_checker_entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_lo_lo = {pma_checker_px_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_px_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_px, _pma_checker_entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_lo_hi = {pma_checker_px_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_px_array_lo = {pma_checker_px_array_lo_hi, pma_checker_px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_px_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_px, _pma_checker_entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_hi_lo = {pma_checker_px_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_px_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_px, _pma_checker_entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_hi_hi = {pma_checker_px_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_px_array_hi = {pma_checker_px_array_hi_hi, pma_checker_px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__px_array_T_1 = {pma_checker_px_array_hi, pma_checker_px_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__px_array_T_2 = {2'h0, pma_checker__px_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker__px_array_T_4 = ~pma_checker__px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] pma_checker_px_array = pma_checker__px_array_T_2 & pma_checker__px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] pma_checker__eff_array_T = {2{_pma_checker_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] pma_checker_eff_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_eff, _pma_checker_entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_lo_lo = {pma_checker_eff_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_eff_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_eff, _pma_checker_entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_lo_hi = {pma_checker_eff_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_eff_array_lo = {pma_checker_eff_array_lo_hi, pma_checker_eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_eff_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_eff, _pma_checker_entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_hi_lo = {pma_checker_eff_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_eff_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_eff, _pma_checker_entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_hi_hi = {pma_checker_eff_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_eff_array_hi = {pma_checker_eff_array_hi_hi, pma_checker_eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__eff_array_T_1 = {pma_checker_eff_array_hi, pma_checker_eff_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_eff_array = {pma_checker__eff_array_T, pma_checker__eff_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__c_array_T = {2{pma_checker_cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_22 = {_pma_checker_entries_barrier_2_io_y_c, _pma_checker_entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_c_array_lo_lo_hi = _GEN_22; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_lo_lo_hi = _GEN_22; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_lo_lo = {pma_checker_c_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_23 = {_pma_checker_entries_barrier_5_io_y_c, _pma_checker_entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_c_array_lo_hi_hi = _GEN_23; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_lo_hi_hi = _GEN_23; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_lo_hi = {pma_checker_c_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_c_array_lo = {pma_checker_c_array_lo_hi, pma_checker_c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_24 = {_pma_checker_entries_barrier_8_io_y_c, _pma_checker_entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_c_array_hi_lo_hi = _GEN_24; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_hi_lo_hi = _GEN_24; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_hi_lo = {pma_checker_c_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_25 = {_pma_checker_entries_barrier_11_io_y_c, _pma_checker_entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_c_array_hi_hi_hi = _GEN_25; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_hi_hi_hi = _GEN_25; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_hi_hi = {pma_checker_c_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_c_array_hi = {pma_checker_c_array_hi_hi, pma_checker_c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__c_array_T_1 = {pma_checker_c_array_hi, pma_checker_c_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_c_array = {pma_checker__c_array_T, pma_checker__c_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker_lrscAllowed = pma_checker_c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] pma_checker__ppp_array_T = {2{_pma_checker_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] pma_checker_ppp_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ppp, _pma_checker_entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_lo_lo = {pma_checker_ppp_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ppp_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ppp, _pma_checker_entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_lo_hi = {pma_checker_ppp_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ppp_array_lo = {pma_checker_ppp_array_lo_hi, pma_checker_ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ppp_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ppp, _pma_checker_entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_hi_lo = {pma_checker_ppp_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ppp_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_ppp, _pma_checker_entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_hi_hi = {pma_checker_ppp_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ppp_array_hi = {pma_checker_ppp_array_hi_hi, pma_checker_ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__ppp_array_T_1 = {pma_checker_ppp_array_hi, pma_checker_ppp_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ppp_array = {pma_checker__ppp_array_T, pma_checker__ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__paa_array_T = {2{_pma_checker_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] pma_checker_paa_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_paa, _pma_checker_entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_lo_lo = {pma_checker_paa_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_paa_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_paa, _pma_checker_entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_lo_hi = {pma_checker_paa_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_paa_array_lo = {pma_checker_paa_array_lo_hi, pma_checker_paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_paa_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_paa, _pma_checker_entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_hi_lo = {pma_checker_paa_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_paa_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_paa, _pma_checker_entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_hi_hi = {pma_checker_paa_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_paa_array_hi = {pma_checker_paa_array_hi_hi, pma_checker_paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__paa_array_T_1 = {pma_checker_paa_array_hi, pma_checker_paa_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_paa_array = {pma_checker__paa_array_T, pma_checker__paa_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__pal_array_T = {2{_pma_checker_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pma_checker_pal_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pal, _pma_checker_entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_lo_lo = {pma_checker_pal_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pal_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pal, _pma_checker_entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_lo_hi = {pma_checker_pal_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pal_array_lo = {pma_checker_pal_array_lo_hi, pma_checker_pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pal_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pal, _pma_checker_entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_hi_lo = {pma_checker_pal_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pal_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pal, _pma_checker_entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_hi_hi = {pma_checker_pal_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pal_array_hi = {pma_checker_pal_array_hi_hi, pma_checker_pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pal_array_T_1 = {pma_checker_pal_array_hi, pma_checker_pal_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_pal_array = {pma_checker__pal_array_T, pma_checker__pal_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker_ppp_array_if_cached = pma_checker_ppp_array | pma_checker_c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [13:0] pma_checker_paa_array_if_cached = pma_checker_paa_array | pma_checker_c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [13:0] pma_checker_pal_array_if_cached = pma_checker_pal_array | pma_checker_c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire pma_checker__prefetchable_array_T = pma_checker_cacheable & pma_checker_homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] pma_checker__prefetchable_array_T_1 = {pma_checker__prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] pma_checker_prefetchable_array_lo_lo = {pma_checker_prefetchable_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_prefetchable_array_lo_hi = {pma_checker_prefetchable_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_prefetchable_array_lo = {pma_checker_prefetchable_array_lo_hi, pma_checker_prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_prefetchable_array_hi_lo = {pma_checker_prefetchable_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_prefetchable_array_hi_hi = {pma_checker_prefetchable_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_prefetchable_array_hi = {pma_checker_prefetchable_array_hi_hi, pma_checker_prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__prefetchable_array_T_2 = {pma_checker_prefetchable_array_hi, pma_checker_prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_prefetchable_array = {pma_checker__prefetchable_array_T_1, pma_checker__prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] pma_checker__misaligned_T = 4'h1 << pma_checker_io_req_bits_size; // @[OneHot.scala:58:35] wire [4:0] pma_checker__misaligned_T_1 = {1'h0, pma_checker__misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] pma_checker__misaligned_T_2 = pma_checker__misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] pma_checker__misaligned_T_3 = {36'h0, pma_checker_io_req_bits_vaddr[3:0] & pma_checker__misaligned_T_2}; // @[TLB.scala:550:{39,69}] wire pma_checker_misaligned = |pma_checker__misaligned_T_3; // @[TLB.scala:550:{39,77}] wire [39:0] pma_checker_bad_va_maskedVAddr = pma_checker_io_req_bits_vaddr & 40'hC000000000; // @[TLB.scala:559:43] wire pma_checker__bad_va_T_2 = pma_checker_bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51] wire pma_checker__bad_va_T_3 = pma_checker_bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire pma_checker__bad_va_T_4 = pma_checker__bad_va_T_3; // @[TLB.scala:560:{71,86}] wire pma_checker__bad_va_T_5 = pma_checker__bad_va_T_2 | pma_checker__bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire pma_checker__bad_va_T_6 = ~pma_checker__bad_va_T_5; // @[TLB.scala:560:{37,59}] wire pma_checker__bad_va_T_7 = pma_checker__bad_va_T_6; // @[TLB.scala:560:{34,37}] wire _GEN_26 = pma_checker_io_req_bits_cmd == 5'h6; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T; // @[package.scala:16:47] assign pma_checker__cmd_lrsc_T = _GEN_26; // @[package.scala:16:47] wire pma_checker__cmd_read_T_2; // @[package.scala:16:47] assign pma_checker__cmd_read_T_2 = _GEN_26; // @[package.scala:16:47] wire _GEN_27 = pma_checker_io_req_bits_cmd == 5'h7; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47] assign pma_checker__cmd_lrsc_T_1 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_read_T_3; // @[package.scala:16:47] assign pma_checker__cmd_read_T_3 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_write_T_3; // @[Consts.scala:90:66] assign pma_checker__cmd_write_T_3 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T_2 = pma_checker__cmd_lrsc_T | pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_lrsc = pma_checker__cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_28 = pma_checker_io_req_bits_cmd == 5'h4; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T = _GEN_28; // @[package.scala:16:47] wire pma_checker__cmd_read_T_7; // @[package.scala:16:47] assign pma_checker__cmd_read_T_7 = _GEN_28; // @[package.scala:16:47] wire pma_checker__cmd_write_T_5; // @[package.scala:16:47] assign pma_checker__cmd_write_T_5 = _GEN_28; // @[package.scala:16:47] wire _GEN_29 = pma_checker_io_req_bits_cmd == 5'h9; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_1 = _GEN_29; // @[package.scala:16:47] wire pma_checker__cmd_read_T_8; // @[package.scala:16:47] assign pma_checker__cmd_read_T_8 = _GEN_29; // @[package.scala:16:47] wire pma_checker__cmd_write_T_6; // @[package.scala:16:47] assign pma_checker__cmd_write_T_6 = _GEN_29; // @[package.scala:16:47] wire _GEN_30 = pma_checker_io_req_bits_cmd == 5'hA; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_2 = _GEN_30; // @[package.scala:16:47] wire pma_checker__cmd_read_T_9; // @[package.scala:16:47] assign pma_checker__cmd_read_T_9 = _GEN_30; // @[package.scala:16:47] wire pma_checker__cmd_write_T_7; // @[package.scala:16:47] assign pma_checker__cmd_write_T_7 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = pma_checker_io_req_bits_cmd == 5'hB; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_3 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_read_T_10; // @[package.scala:16:47] assign pma_checker__cmd_read_T_10 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_write_T_8; // @[package.scala:16:47] assign pma_checker__cmd_write_T_8 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_4 = pma_checker__cmd_amo_logical_T | pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_logical_T_5 = pma_checker__cmd_amo_logical_T_4 | pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_logical_T_6 = pma_checker__cmd_amo_logical_T_5 | pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_amo_logical = pma_checker__cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_32 = pma_checker_io_req_bits_cmd == 5'h8; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T = _GEN_32; // @[package.scala:16:47] wire pma_checker__cmd_read_T_14; // @[package.scala:16:47] assign pma_checker__cmd_read_T_14 = _GEN_32; // @[package.scala:16:47] wire pma_checker__cmd_write_T_12; // @[package.scala:16:47] assign pma_checker__cmd_write_T_12 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = pma_checker_io_req_bits_cmd == 5'hC; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_1 = _GEN_33; // @[package.scala:16:47] wire pma_checker__cmd_read_T_15; // @[package.scala:16:47] assign pma_checker__cmd_read_T_15 = _GEN_33; // @[package.scala:16:47] wire pma_checker__cmd_write_T_13; // @[package.scala:16:47] assign pma_checker__cmd_write_T_13 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = pma_checker_io_req_bits_cmd == 5'hD; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_2 = _GEN_34; // @[package.scala:16:47] wire pma_checker__cmd_read_T_16; // @[package.scala:16:47] assign pma_checker__cmd_read_T_16 = _GEN_34; // @[package.scala:16:47] wire pma_checker__cmd_write_T_14; // @[package.scala:16:47] assign pma_checker__cmd_write_T_14 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = pma_checker_io_req_bits_cmd == 5'hE; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_3 = _GEN_35; // @[package.scala:16:47] wire pma_checker__cmd_read_T_17; // @[package.scala:16:47] assign pma_checker__cmd_read_T_17 = _GEN_35; // @[package.scala:16:47] wire pma_checker__cmd_write_T_15; // @[package.scala:16:47] assign pma_checker__cmd_write_T_15 = _GEN_35; // @[package.scala:16:47] wire _GEN_36 = pma_checker_io_req_bits_cmd == 5'hF; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_4 = _GEN_36; // @[package.scala:16:47] wire pma_checker__cmd_read_T_18; // @[package.scala:16:47] assign pma_checker__cmd_read_T_18 = _GEN_36; // @[package.scala:16:47] wire pma_checker__cmd_write_T_16; // @[package.scala:16:47] assign pma_checker__cmd_write_T_16 = _GEN_36; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_5 = pma_checker__cmd_amo_arithmetic_T | pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_6 = pma_checker__cmd_amo_arithmetic_T_5 | pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_7 = pma_checker__cmd_amo_arithmetic_T_6 | pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_8 = pma_checker__cmd_amo_arithmetic_T_7 | pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_amo_arithmetic = pma_checker__cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_37 = pma_checker_io_req_bits_cmd == 5'h11; // @[TLB.scala:573:41] wire pma_checker_cmd_put_partial; // @[TLB.scala:573:41] assign pma_checker_cmd_put_partial = _GEN_37; // @[TLB.scala:573:41] wire pma_checker__cmd_write_T_1; // @[Consts.scala:90:49] assign pma_checker__cmd_write_T_1 = _GEN_37; // @[TLB.scala:573:41] wire pma_checker__cmd_read_T = pma_checker_io_req_bits_cmd == 5'h0; // @[package.scala:16:47] wire _GEN_38 = pma_checker_io_req_bits_cmd == 5'h10; // @[package.scala:16:47] wire pma_checker__cmd_read_T_1; // @[package.scala:16:47] assign pma_checker__cmd_read_T_1 = _GEN_38; // @[package.scala:16:47] wire pma_checker__cmd_readx_T; // @[TLB.scala:575:56] assign pma_checker__cmd_readx_T = _GEN_38; // @[package.scala:16:47] wire pma_checker__cmd_read_T_4 = pma_checker__cmd_read_T | pma_checker__cmd_read_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_5 = pma_checker__cmd_read_T_4 | pma_checker__cmd_read_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_6 = pma_checker__cmd_read_T_5 | pma_checker__cmd_read_T_3; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_11 = pma_checker__cmd_read_T_7 | pma_checker__cmd_read_T_8; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_12 = pma_checker__cmd_read_T_11 | pma_checker__cmd_read_T_9; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_13 = pma_checker__cmd_read_T_12 | pma_checker__cmd_read_T_10; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_19 = pma_checker__cmd_read_T_14 | pma_checker__cmd_read_T_15; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_20 = pma_checker__cmd_read_T_19 | pma_checker__cmd_read_T_16; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_21 = pma_checker__cmd_read_T_20 | pma_checker__cmd_read_T_17; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_22 = pma_checker__cmd_read_T_21 | pma_checker__cmd_read_T_18; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_23 = pma_checker__cmd_read_T_13 | pma_checker__cmd_read_T_22; // @[package.scala:81:59] wire pma_checker_cmd_read = pma_checker__cmd_read_T_6 | pma_checker__cmd_read_T_23; // @[package.scala:81:59] wire pma_checker__cmd_write_T = pma_checker_io_req_bits_cmd == 5'h1; // @[DCache.scala:120:32] wire pma_checker__cmd_write_T_2 = pma_checker__cmd_write_T | pma_checker__cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire pma_checker__cmd_write_T_4 = pma_checker__cmd_write_T_2 | pma_checker__cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire pma_checker__cmd_write_T_9 = pma_checker__cmd_write_T_5 | pma_checker__cmd_write_T_6; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_10 = pma_checker__cmd_write_T_9 | pma_checker__cmd_write_T_7; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_11 = pma_checker__cmd_write_T_10 | pma_checker__cmd_write_T_8; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_17 = pma_checker__cmd_write_T_12 | pma_checker__cmd_write_T_13; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_18 = pma_checker__cmd_write_T_17 | pma_checker__cmd_write_T_14; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_19 = pma_checker__cmd_write_T_18 | pma_checker__cmd_write_T_15; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_20 = pma_checker__cmd_write_T_19 | pma_checker__cmd_write_T_16; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_21 = pma_checker__cmd_write_T_11 | pma_checker__cmd_write_T_20; // @[package.scala:81:59] wire pma_checker_cmd_write = pma_checker__cmd_write_T_4 | pma_checker__cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire pma_checker__cmd_write_perms_T = pma_checker_io_req_bits_cmd == 5'h5; // @[package.scala:16:47] wire pma_checker__cmd_write_perms_T_1 = pma_checker_io_req_bits_cmd == 5'h17; // @[package.scala:16:47] wire pma_checker__cmd_write_perms_T_2 = pma_checker__cmd_write_perms_T | pma_checker__cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_write_perms = pma_checker_cmd_write | pma_checker__cmd_write_perms_T_2; // @[package.scala:81:59] wire [13:0] pma_checker__ae_array_T = pma_checker_misaligned ? pma_checker_eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] pma_checker__ae_array_T_1 = ~pma_checker_lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [13:0] pma_checker__ae_array_T_2 = pma_checker_cmd_lrsc ? pma_checker__ae_array_T_1 : 14'h0; // @[TLB.scala:570:33, :583:{8,19}] wire [13:0] pma_checker_ae_array = pma_checker__ae_array_T | pma_checker__ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8] wire [13:0] pma_checker__ae_ld_array_T = ~pma_checker_pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] pma_checker__ae_ld_array_T_1 = pma_checker_ae_array | pma_checker__ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] pma_checker_ae_ld_array = pma_checker_cmd_read ? pma_checker__ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}] wire [13:0] pma_checker__ae_st_array_T = ~pma_checker_pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] pma_checker__ae_st_array_T_1 = pma_checker_ae_array | pma_checker__ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] pma_checker__ae_st_array_T_2 = pma_checker_cmd_write_perms ? pma_checker__ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [13:0] pma_checker__ae_st_array_T_3 = ~pma_checker_ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] pma_checker__ae_st_array_T_4 = pma_checker_cmd_put_partial ? pma_checker__ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [13:0] pma_checker__ae_st_array_T_5 = pma_checker__ae_st_array_T_2 | pma_checker__ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [13:0] pma_checker__ae_st_array_T_6 = ~pma_checker_pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] pma_checker__ae_st_array_T_7 = pma_checker_cmd_amo_logical ? pma_checker__ae_st_array_T_6 : 14'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [13:0] pma_checker__ae_st_array_T_8 = pma_checker__ae_st_array_T_5 | pma_checker__ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [13:0] pma_checker__ae_st_array_T_9 = ~pma_checker_paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] pma_checker__ae_st_array_T_10 = pma_checker_cmd_amo_arithmetic ? pma_checker__ae_st_array_T_9 : 14'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [13:0] pma_checker_ae_st_array = pma_checker__ae_st_array_T_8 | pma_checker__ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [13:0] pma_checker__must_alloc_array_T = ~pma_checker_ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] pma_checker__must_alloc_array_T_1 = pma_checker_cmd_put_partial ? pma_checker__must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [13:0] pma_checker__must_alloc_array_T_2 = ~pma_checker_pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] pma_checker__must_alloc_array_T_3 = pma_checker_cmd_amo_logical ? pma_checker__must_alloc_array_T_2 : 14'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [13:0] pma_checker__must_alloc_array_T_4 = pma_checker__must_alloc_array_T_1 | pma_checker__must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [13:0] pma_checker__must_alloc_array_T_5 = ~pma_checker_paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] pma_checker__must_alloc_array_T_6 = pma_checker_cmd_amo_arithmetic ? pma_checker__must_alloc_array_T_5 : 14'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [13:0] pma_checker__must_alloc_array_T_7 = pma_checker__must_alloc_array_T_4 | pma_checker__must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [13:0] pma_checker__must_alloc_array_T_9 = {14{pma_checker_cmd_lrsc}}; // @[TLB.scala:570:33, :596:8] wire [13:0] pma_checker_must_alloc_array = pma_checker__must_alloc_array_T_7 | pma_checker__must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [13:0] pma_checker__pf_ld_array_T_1 = ~pma_checker__pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] pma_checker__pf_ld_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] pma_checker__pf_ld_array_T_3 = pma_checker__pf_ld_array_T_1 & pma_checker__pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] pma_checker__pf_ld_array_T_4 = pma_checker__pf_ld_array_T_3 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] pma_checker__pf_ld_array_T_5 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] pma_checker__pf_ld_array_T_6 = pma_checker__pf_ld_array_T_4 & pma_checker__pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pma_checker_pf_ld_array = pma_checker_cmd_read ? pma_checker__pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}] wire [13:0] pma_checker__pf_st_array_T = ~pma_checker_w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] pma_checker__pf_st_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] pma_checker__pf_st_array_T_2 = pma_checker__pf_st_array_T & pma_checker__pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] pma_checker__pf_st_array_T_3 = pma_checker__pf_st_array_T_2 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] pma_checker__pf_st_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] pma_checker__pf_st_array_T_5 = pma_checker__pf_st_array_T_3 & pma_checker__pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] pma_checker_pf_st_array = pma_checker_cmd_write_perms ? pma_checker__pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [13:0] pma_checker__pf_inst_array_T = ~pma_checker_x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] pma_checker__pf_inst_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] pma_checker__pf_inst_array_T_2 = pma_checker__pf_inst_array_T & pma_checker__pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] pma_checker__pf_inst_array_T_3 = pma_checker__pf_inst_array_T_2 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] pma_checker__pf_inst_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pma_checker_pf_inst_array = pma_checker__pf_inst_array_T_3 & pma_checker__pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] pma_checker__gf_ld_array_T_4 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] pma_checker__gf_ld_array_T_5 = pma_checker__gf_ld_array_T_3 & pma_checker__gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] pma_checker__gf_st_array_T_3 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] pma_checker__gf_st_array_T_4 = pma_checker__gf_st_array_T_2 & pma_checker__gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] pma_checker__gf_inst_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] pma_checker__gf_inst_array_T_3 = pma_checker__gf_inst_array_T_1 & pma_checker__gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire pma_checker__gpa_hits_hit_mask_T = pma_checker_vpn == 27'h0; // @[TLB.scala:335:30, :606:73] wire [13:0] pma_checker__io_resp_pf_ld_T_1 = pma_checker_pf_ld_array & 14'h2000; // @[TLB.scala:597:24, :633:57] wire pma_checker__io_resp_pf_ld_T_2 = |pma_checker__io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign pma_checker__io_resp_pf_ld_T_3 = pma_checker__io_resp_pf_ld_T_2; // @[TLB.scala:633:{41,65}] assign pma_checker_io_resp_pf_ld = pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire [13:0] pma_checker__io_resp_pf_st_T_1 = pma_checker_pf_st_array & 14'h2000; // @[TLB.scala:598:24, :634:64] wire pma_checker__io_resp_pf_st_T_2 = |pma_checker__io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign pma_checker__io_resp_pf_st_T_3 = pma_checker__io_resp_pf_st_T_2; // @[TLB.scala:634:{48,72}] assign pma_checker_io_resp_pf_st = pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire [13:0] pma_checker__io_resp_pf_inst_T = pma_checker_pf_inst_array & 14'h2000; // @[TLB.scala:599:67, :635:47] wire pma_checker__io_resp_pf_inst_T_1 = |pma_checker__io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign pma_checker__io_resp_pf_inst_T_2 = pma_checker__io_resp_pf_inst_T_1; // @[TLB.scala:635:{29,55}] assign pma_checker_io_resp_pf_inst = pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire [13:0] pma_checker__io_resp_ae_ld_T = pma_checker_ae_ld_array & 14'h2000; // @[TLB.scala:586:24, :641:33] assign pma_checker__io_resp_ae_ld_T_1 = |pma_checker__io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign pma_checker_io_resp_ae_ld = pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire [13:0] pma_checker__io_resp_ae_st_T = pma_checker_ae_st_array & 14'h2000; // @[TLB.scala:590:53, :642:33] assign pma_checker__io_resp_ae_st_T_1 = |pma_checker__io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign pma_checker_io_resp_ae_st = pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire [13:0] pma_checker__io_resp_ae_inst_T = ~pma_checker_px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] pma_checker__io_resp_ae_inst_T_1 = pma_checker__io_resp_ae_inst_T & 14'h2000; // @[TLB.scala:643:{23,33}] assign pma_checker__io_resp_ae_inst_T_2 = |pma_checker__io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign pma_checker_io_resp_ae_inst = pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41] assign pma_checker__io_resp_ma_ld_T = pma_checker_misaligned & pma_checker_cmd_read; // @[TLB.scala:550:77, :645:31] assign pma_checker_io_resp_ma_ld = pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31] assign pma_checker__io_resp_ma_st_T = pma_checker_misaligned & pma_checker_cmd_write; // @[TLB.scala:550:77, :646:31] assign pma_checker_io_resp_ma_st = pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31] wire [13:0] pma_checker__io_resp_cacheable_T = pma_checker_c_array & 14'h2000; // @[TLB.scala:537:20, :648:33] assign pma_checker__io_resp_cacheable_T_1 = |pma_checker__io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign pma_checker_io_resp_cacheable = pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire [13:0] pma_checker__io_resp_must_alloc_T = pma_checker_must_alloc_array & 14'h2000; // @[TLB.scala:595:46, :649:43] assign pma_checker__io_resp_must_alloc_T_1 = |pma_checker__io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign pma_checker_io_resp_must_alloc = pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire [13:0] pma_checker__io_resp_prefetchable_T = pma_checker_prefetchable_array & 14'h2000; // @[TLB.scala:547:31, :650:47] wire pma_checker__io_resp_prefetchable_T_1 = |pma_checker__io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign pma_checker__io_resp_prefetchable_T_2 = pma_checker__io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign pma_checker_io_resp_prefetchable = pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59] assign pma_checker__io_resp_paddr_T_1 = {pma_checker_ppn, pma_checker__io_resp_paddr_T}; // @[Mux.scala:30:73] assign pma_checker_io_resp_paddr = pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [27:0] pma_checker__io_resp_gpa_page_T_1 = {1'h0, pma_checker_vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] pma_checker_io_resp_gpa_page = pma_checker__io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [11:0] pma_checker_io_resp_gpa_offset = pma_checker__io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign pma_checker__io_resp_gpa_T = {pma_checker_io_resp_gpa_page, pma_checker_io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign pma_checker_io_resp_gpa = pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8] wire pma_checker_ignore_1 = pma_checker__ignore_T_1; // @[TLB.scala:182:{28,34}] wire pma_checker_ignore_4 = pma_checker__ignore_T_4; // @[TLB.scala:182:{28,34}] wire pma_checker_ignore_7 = pma_checker__ignore_T_7; // @[TLB.scala:182:{28,34}] wire pma_checker_ignore_10 = pma_checker__ignore_T_10; // @[TLB.scala:182:{28,34}] wire replace; // @[Replacement.scala:37:29] wire [1:0] lfsr_lo_lo_lo = {_lfsr_prng_io_out_1, _lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_lo_lo_hi = {_lfsr_prng_io_out_3, _lfsr_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_lo_lo = {lfsr_lo_lo_hi, lfsr_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_lo_hi_lo = {_lfsr_prng_io_out_5, _lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_lo_hi_hi = {_lfsr_prng_io_out_7, _lfsr_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_lo_hi = {lfsr_lo_hi_hi, lfsr_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] lfsr_lo = {lfsr_lo_hi, lfsr_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_hi_lo_lo = {_lfsr_prng_io_out_9, _lfsr_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_hi_lo_hi = {_lfsr_prng_io_out_11, _lfsr_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_hi_lo = {lfsr_hi_lo_hi, lfsr_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_hi_hi_lo = {_lfsr_prng_io_out_13, _lfsr_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_hi_hi_hi = {_lfsr_prng_io_out_15, _lfsr_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_hi_hi = {lfsr_hi_hi_hi, lfsr_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] lfsr_hi = {lfsr_hi_hi, lfsr_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] lfsr = {lfsr_hi, lfsr_lo}; // @[PRNG.scala:95:17] wire metaArb__grant_T = metaArb_io_in_0_valid; // @[Arbiter.scala:45:68] wire [39:0] _metaArb_io_in_5_bits_addr_T_2; // @[DCache.scala:1018:36] wire [5:0] _metaArb_io_in_5_bits_idx_T; // @[DCache.scala:1017:44] wire metaArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] wire [39:0] _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:454:36] wire [5:0] _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:453:35] wire [21:0] _metaArb_io_in_1_bits_data_T; // @[DCache.scala:458:14] wire metaArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_2_valid_T; // @[DCache.scala:462:63] wire [39:0] _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:466:36] wire [5:0] _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:465:40] wire [7:0] s2_victim_or_hit_way; // @[DCache.scala:432:33] wire [21:0] _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:467:97] wire metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_3_valid_T_2; // @[DCache.scala:741:53] wire [39:0] _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:745:36] wire [5:0] _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:744:40] wire [21:0] _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:746:134] wire metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_4_valid_T_2; // @[package.scala:81:59] wire [39:0] _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:912:36] wire [5:0] _metaArb_io_in_4_bits_idx_T; // @[DCache.scala:1200:47] wire [7:0] releaseWay; // @[DCache.scala:232:24] wire [21:0] _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:913:97] wire metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19] wire [5:0] _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:263:58] wire metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire [5:0] _s1_meta_WIRE = metaArb_io_out_bits_idx; // @[DCache.scala:135:28, :314:35] wire [39:0] metaArb_io_in_0_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_0_bits_idx; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_1_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_1_bits_idx; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_1_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_1_ready; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_2_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_2_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_2_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_2_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_2_ready; // @[DCache.scala:135:28] wire metaArb_io_in_2_valid; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_3_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_3_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_3_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_3_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_3_ready; // @[DCache.scala:135:28] wire metaArb_io_in_3_valid; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_4_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_4_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_4_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_4_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_4_ready; // @[DCache.scala:135:28] wire metaArb_io_in_4_valid; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_5_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_5_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_5_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_5_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_5_ready; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_6_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_6_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_6_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_6_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_6_ready; // @[DCache.scala:135:28] wire metaArb_io_in_6_valid; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_7_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_7_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_7_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_7_ready; // @[DCache.scala:135:28] wire metaArb_io_out_bits_write; // @[DCache.scala:135:28] wire [39:0] metaArb_io_out_bits_addr; // @[DCache.scala:135:28] wire [7:0] metaArb_io_out_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_out_bits_data; // @[DCache.scala:135:28] wire metaArb_io_out_valid; // @[DCache.scala:135:28] wire [2:0] metaArb_io_chosen; // @[DCache.scala:135:28] assign metaArb_io_chosen = metaArb_io_in_0_valid ? 3'h0 : metaArb_io_in_2_valid ? 3'h2 : metaArb_io_in_3_valid ? 3'h3 : metaArb_io_in_4_valid ? 3'h4 : {2'h3, ~metaArb_io_in_6_valid}; // @[Arbiter.scala:142:13, :145:26, :146:17] assign metaArb_io_out_bits_write = metaArb_io_in_0_valid | metaArb_io_in_2_valid | metaArb_io_in_3_valid | metaArb_io_in_4_valid; // @[Arbiter.scala:145:26, :147:19] assign metaArb_io_out_bits_addr = metaArb_io_in_0_valid ? metaArb_io_in_0_bits_addr : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_addr : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_addr : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_addr : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_addr : metaArb_io_in_7_bits_addr; // @[Arbiter.scala:143:15, :145:26, :147:19] assign metaArb_io_out_bits_idx = metaArb_io_in_0_valid ? metaArb_io_in_0_bits_idx : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_idx : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_idx : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_idx : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_idx : metaArb_io_in_7_bits_idx; // @[Arbiter.scala:143:15, :145:26, :147:19] assign metaArb_io_out_bits_way_en = metaArb_io_in_0_valid ? 8'hFF : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_way_en : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_way_en : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_way_en : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_way_en : metaArb_io_in_7_bits_way_en; // @[Arbiter.scala:143:15, :145:26, :147:19] assign metaArb_io_out_bits_data = metaArb_io_in_0_valid ? 22'h0 : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_data : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_data : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_data : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_data : metaArb_io_in_7_bits_data; // @[Arbiter.scala:143:15, :145:26, :147:19] wire metaArb__grant_T_1 = metaArb__grant_T | metaArb_io_in_2_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_2 = metaArb__grant_T_1 | metaArb_io_in_3_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_3 = metaArb__grant_T_2 | metaArb_io_in_4_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_4 = metaArb__grant_T_3; // @[Arbiter.scala:45:68] wire metaArb__grant_T_5 = metaArb__grant_T_4 | metaArb_io_in_6_valid; // @[Arbiter.scala:45:68] wire metaArb_grant_1 = ~metaArb_io_in_0_valid; // @[Arbiter.scala:45:78] assign metaArb__io_in_1_ready_T = metaArb_grant_1; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_2 = ~metaArb__grant_T; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_2_ready_T = metaArb_grant_2; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_3 = ~metaArb__grant_T_1; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_3_ready_T = metaArb_grant_3; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_4 = ~metaArb__grant_T_2; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_4_ready_T = metaArb_grant_4; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_5 = ~metaArb__grant_T_3; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_5_ready_T = metaArb_grant_5; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_6 = ~metaArb__grant_T_4; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_6_ready_T = metaArb_grant_6; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_7 = ~metaArb__grant_T_5; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_7_ready_T = metaArb_grant_7; // @[Arbiter.scala:45:78, :153:19] assign metaArb_io_in_1_ready = metaArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_2_ready = metaArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_3_ready = metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_4_ready = metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_5_ready = metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_6_ready = metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_7_ready = metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_out_valid_T = ~metaArb_grant_7; // @[Arbiter.scala:45:78, :154:19] assign metaArb__io_out_valid_T_1 = metaArb__io_out_valid_T | metaArb_io_in_7_valid; // @[Arbiter.scala:154:{19,31}] assign metaArb_io_out_valid = metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire _s1_meta_T_1; // @[DCache.scala:314:59] wire wmask_0; // @[DCache.scala:311:74] wire wmask_1; // @[DCache.scala:311:74] wire wmask_2; // @[DCache.scala:311:74] wire wmask_3; // @[DCache.scala:311:74] wire wmask_4; // @[DCache.scala:311:74] wire wmask_5; // @[DCache.scala:311:74] wire wmask_6; // @[DCache.scala:311:74] wire wmask_7; // @[DCache.scala:311:74] wire [21:0] _s1_meta_uncorrected_WIRE = _rockettile_dcache_tag_array_RW0_rdata[21:0]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_1 = _rockettile_dcache_tag_array_RW0_rdata[43:22]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_2 = _rockettile_dcache_tag_array_RW0_rdata[65:44]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_3 = _rockettile_dcache_tag_array_RW0_rdata[87:66]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_4 = _rockettile_dcache_tag_array_RW0_rdata[109:88]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_5 = _rockettile_dcache_tag_array_RW0_rdata[131:110]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_6 = _rockettile_dcache_tag_array_RW0_rdata[153:132]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_7 = _rockettile_dcache_tag_array_RW0_rdata[175:154]; // @[DescribedSRAM.scala:17:26] wire _dataArb_io_in_0_valid_T_12; // @[DCache.scala:516:27] wire pstore_drain; // @[DCache.scala:516:27] wire [127:0] _dataArb_io_in_0_bits_wdata_T_18; // @[package.scala:45:27] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_4; // @[DCache.scala:555:55] wire [7:0] _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27] wire [7:0] _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:550:38] wire dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] wire [127:0] tl_d_data_encoded; // @[DCache.scala:324:31] wire dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] wire _dataArb_io_in_2_valid_T_1; // @[DCache.scala:900:41] wire [11:0] _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:903:72] wire dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire _dataArb_io_in_3_valid_T_58; // @[DCache.scala:242:46] wire dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire [11:0] dataArb_io_in_0_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_in_0_bits_write; // @[DCache.scala:152:28] wire [127:0] dataArb_io_in_0_bits_wdata; // @[DCache.scala:152:28] wire [1:0] dataArb_io_in_0_bits_wordMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_0_bits_eccMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_0_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_in_0_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_in_1_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_in_1_bits_write; // @[DCache.scala:152:28] wire [127:0] dataArb_io_in_1_bits_wdata; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_1_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_in_1_ready; // @[DCache.scala:152:28] wire dataArb_io_in_1_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_in_2_bits_addr; // @[DCache.scala:152:28] wire [127:0] dataArb_io_in_2_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_2_ready; // @[DCache.scala:152:28] wire dataArb_io_in_2_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_in_3_bits_addr; // @[DCache.scala:152:28] wire [127:0] dataArb_io_in_3_bits_wdata; // @[DCache.scala:152:28] wire [1:0] dataArb_io_in_3_bits_wordMask; // @[DCache.scala:152:28] wire dataArb_io_in_3_ready; // @[DCache.scala:152:28] wire dataArb_io_in_3_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_out_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_out_bits_write; // @[DCache.scala:152:28] wire [127:0] dataArb_io_out_bits_wdata; // @[DCache.scala:152:28] wire [1:0] dataArb_io_out_bits_wordMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_out_bits_eccMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_out_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_out_valid; // @[DCache.scala:152:28] wire [1:0] dataArb_io_chosen; // @[DCache.scala:152:28] assign dataArb_io_chosen = dataArb_io_in_0_valid ? 2'h0 : dataArb_io_in_1_valid ? 2'h1 : {1'h1, ~dataArb_io_in_2_valid}; // @[Arbiter.scala:142:13, :145:26, :146:17] assign dataArb_io_out_bits_addr = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_addr : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_addr : dataArb_io_in_2_valid ? dataArb_io_in_2_bits_addr : dataArb_io_in_3_bits_addr; // @[Arbiter.scala:143:15, :145:26, :147:19] assign dataArb_io_out_bits_write = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_write : dataArb_io_in_1_valid & dataArb_io_in_1_bits_write; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_wdata = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wdata : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_wdata : dataArb_io_in_2_valid ? dataArb_io_in_2_bits_wdata : dataArb_io_in_3_bits_wdata; // @[Arbiter.scala:143:15, :145:26, :147:19] assign dataArb_io_out_bits_wordMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wordMask : dataArb_io_in_1_valid | dataArb_io_in_2_valid ? 2'h3 : dataArb_io_in_3_bits_wordMask; // @[Arbiter.scala:143:15, :145:26, :147:19] assign dataArb_io_out_bits_eccMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_eccMask : 8'hFF; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_way_en = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_way_en : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_way_en : 8'hFF; // @[Arbiter.scala:145:26, :147:19] wire dataArb__grant_T = dataArb_io_in_0_valid | dataArb_io_in_1_valid; // @[Arbiter.scala:45:68] wire dataArb__grant_T_1 = dataArb__grant_T | dataArb_io_in_2_valid; // @[Arbiter.scala:45:68] wire dataArb_grant_1 = ~dataArb_io_in_0_valid; // @[Arbiter.scala:45:78] assign dataArb__io_in_1_ready_T = dataArb_grant_1; // @[Arbiter.scala:45:78, :153:19] wire dataArb_grant_2 = ~dataArb__grant_T; // @[Arbiter.scala:45:{68,78}] assign dataArb__io_in_2_ready_T = dataArb_grant_2; // @[Arbiter.scala:45:78, :153:19] wire dataArb_grant_3 = ~dataArb__grant_T_1; // @[Arbiter.scala:45:{68,78}] assign dataArb__io_in_3_ready_T = dataArb_grant_3; // @[Arbiter.scala:45:78, :153:19] assign dataArb_io_in_1_ready = dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] assign dataArb_io_in_2_ready = dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] assign dataArb_io_in_3_ready = dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire dataArb__io_out_valid_T = ~dataArb_grant_3; // @[Arbiter.scala:45:78, :154:19] assign dataArb__io_out_valid_T_1 = dataArb__io_out_valid_T | dataArb_io_in_3_valid; // @[Arbiter.scala:154:{19,31}] assign dataArb_io_out_valid = dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire _tl_out_a_valid_T_14; // @[DCache.scala:603:37] assign nodeOut_a_deq_valid = tl_out_a_valid; // @[Decoupled.scala:356:21] wire [2:0] _tl_out_a_bits_T_9_opcode; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_opcode = tl_out_a_bits_opcode; // @[Decoupled.scala:356:21] wire [2:0] _tl_out_a_bits_T_9_param; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_param = tl_out_a_bits_param; // @[Decoupled.scala:356:21] wire [3:0] _tl_out_a_bits_T_9_size; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_size = tl_out_a_bits_size; // @[Decoupled.scala:356:21] wire _tl_out_a_bits_T_9_source; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_source = tl_out_a_bits_source; // @[Decoupled.scala:356:21] wire [31:0] _tl_out_a_bits_T_9_address; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_address = tl_out_a_bits_address; // @[Decoupled.scala:356:21] wire [15:0] _tl_out_a_bits_T_9_mask; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_mask = tl_out_a_bits_mask; // @[Decoupled.scala:356:21] wire [127:0] _tl_out_a_bits_T_9_data; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_data = tl_out_a_bits_data; // @[Decoupled.scala:356:21] wire tl_out_a_ready; // @[DCache.scala:159:22] assign tl_out_a_ready = nodeOut_a_deq_ready; // @[Decoupled.scala:356:21] assign nodeOut_a_valid = nodeOut_a_deq_valid; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_opcode = nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_param = nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_size = nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_source = nodeOut_a_deq_bits_source; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_address = nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_mask = nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_data = nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21] wire _s1_valid_T = io_cpu_req_ready_0 & io_cpu_req_valid_0; // @[Decoupled.scala:51:35] reg s1_valid; // @[DCache.scala:182:25] wire _io_cpu_ordered_T_1 = s1_valid; // @[DCache.scala:182:25, :929:32] wire _GEN_39 = nodeOut_b_ready & nodeOut_b_valid; // @[Decoupled.scala:51:35] wire _s1_probe_T; // @[Decoupled.scala:51:35] assign _s1_probe_T = _GEN_39; // @[Decoupled.scala:51:35] wire _probe_bits_T; // @[Decoupled.scala:51:35] assign _probe_bits_T = _GEN_39; // @[Decoupled.scala:51:35] reg s1_probe; // @[DCache.scala:183:25] reg [2:0] probe_bits_opcode; // @[DCache.scala:184:29] reg [1:0] probe_bits_param; // @[DCache.scala:184:29] reg [3:0] probe_bits_size; // @[DCache.scala:184:29] wire [3:0] nackResponseMessage_size = probe_bits_size; // @[Edges.scala:416:17] wire [3:0] cleanReleaseMessage_size = probe_bits_size; // @[Edges.scala:416:17] wire [3:0] dirtyReleaseMessage_size = probe_bits_size; // @[Edges.scala:433:17] reg probe_bits_source; // @[DCache.scala:184:29] assign nodeOut_c_bits_source = probe_bits_source; // @[DCache.scala:184:29] wire nackResponseMessage_source = probe_bits_source; // @[Edges.scala:416:17] wire cleanReleaseMessage_source = probe_bits_source; // @[Edges.scala:416:17] wire dirtyReleaseMessage_source = probe_bits_source; // @[Edges.scala:433:17] reg [31:0] probe_bits_address; // @[DCache.scala:184:29] assign nodeOut_c_bits_address = probe_bits_address; // @[DCache.scala:184:29] wire [31:0] nackResponseMessage_address = probe_bits_address; // @[Edges.scala:416:17] wire [31:0] cleanReleaseMessage_address = probe_bits_address; // @[Edges.scala:416:17] wire [31:0] dirtyReleaseMessage_address = probe_bits_address; // @[Edges.scala:433:17] reg [15:0] probe_bits_mask; // @[DCache.scala:184:29] reg [127:0] probe_bits_data; // @[DCache.scala:184:29] reg probe_bits_corrupt; // @[DCache.scala:184:29] wire s1_nack; // @[DCache.scala:185:28] wire _s1_valid_masked_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37] wire s1_valid_masked = s1_valid & _s1_valid_masked_T; // @[DCache.scala:182:25, :186:{34,37}] wire _s1_valid_not_nacked_T = ~s1_nack; // @[DCache.scala:185:28, :187:41] wire s1_valid_not_nacked = s1_valid & _s1_valid_not_nacked_T; // @[DCache.scala:182:25, :187:{38,41}] wire _s0_clk_en_T = ~metaArb_io_out_bits_write; // @[DCache.scala:135:28, :190:43] wire s0_clk_en = metaArb_io_out_valid & _s0_clk_en_T; // @[DCache.scala:135:28, :190:{40,43}] wire _s1_tlb_req_T = s0_clk_en; // @[DCache.scala:190:40, :208:52] wire [39:0] _s0_req_addr_T_2; // @[DCache.scala:193:21] wire [39:0] s0_tlb_req_vaddr = s0_req_addr; // @[DCache.scala:192:24, :199:28] wire [4:0] s0_tlb_req_cmd = s0_req_cmd; // @[DCache.scala:192:24, :199:28] wire [1:0] s0_tlb_req_size = s0_req_size; // @[DCache.scala:192:24, :199:28] wire [1:0] s0_tlb_req_prv = s0_req_dprv; // @[DCache.scala:192:24, :199:28] wire s0_tlb_req_v = s0_req_dv; // @[DCache.scala:192:24, :199:28] wire s0_tlb_req_passthrough = s0_req_phys; // @[DCache.scala:192:24, :199:28] wire [33:0] _s0_req_addr_T = metaArb_io_out_bits_addr[39:6]; // @[DCache.scala:135:28, :193:47] wire [5:0] _s0_req_addr_T_1 = io_cpu_req_bits_addr_0[5:0]; // @[DCache.scala:101:7, :193:84] assign _s0_req_addr_T_2 = {_s0_req_addr_T, _s0_req_addr_T_1}; // @[DCache.scala:193:{21,47,84}] assign s0_req_addr = _s0_req_addr_T_2; // @[DCache.scala:192:24, :193:21] assign s0_req_phys = ~metaArb_io_in_7_ready | io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :135:28, :192:24, :195:{9,34,48}] reg [39:0] s1_req_addr; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_vaddr = s1_req_addr; // @[DCache.scala:120:32, :196:25] reg [6:0] s1_req_tag; // @[DCache.scala:196:25] reg [4:0] s1_req_cmd; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_cmd = s1_req_cmd; // @[DCache.scala:120:32, :196:25] reg [1:0] s1_req_size; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_size = s1_req_size; // @[DCache.scala:120:32, :196:25] wire [1:0] s1_mask_xwr_size = s1_req_size; // @[DCache.scala:196:25] reg s1_req_signed; // @[DCache.scala:196:25] reg [1:0] s1_req_dprv; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_prv = s1_req_dprv; // @[DCache.scala:120:32, :196:25] reg s1_req_dv; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_v = s1_req_dv; // @[DCache.scala:120:32, :196:25] reg s1_req_phys; // @[DCache.scala:196:25] reg s1_req_no_resp; // @[DCache.scala:196:25] wire [27:0] _s1_vaddr_T = s1_req_addr[39:12]; // @[DCache.scala:196:25, :197:56] wire [11:0] _s1_vaddr_T_1 = s1_req_addr[11:0]; // @[DCache.scala:196:25, :197:78] wire [11:0] _s1_paddr_T_3 = s1_req_addr[11:0]; // @[DCache.scala:196:25, :197:78, :298:125] wire [39:0] s1_vaddr = {_s1_vaddr_T, _s1_vaddr_T_1}; // @[DCache.scala:197:{21,56,78}] reg [39:0] s1_tlb_req_vaddr; // @[DCache.scala:208:29] reg s1_tlb_req_passthrough; // @[DCache.scala:208:29] reg [1:0] s1_tlb_req_size; // @[DCache.scala:208:29] reg [4:0] s1_tlb_req_cmd; // @[DCache.scala:208:29] reg [1:0] s1_tlb_req_prv; // @[DCache.scala:208:29] reg s1_tlb_req_v; // @[DCache.scala:208:29] wire _GEN_40 = s1_req_cmd == 5'h0; // @[package.scala:16:47] wire _s1_read_T; // @[package.scala:16:47] assign _s1_read_T = _GEN_40; // @[package.scala:16:47] wire _pstore1_rmw_T; // @[package.scala:16:47] assign _pstore1_rmw_T = _GEN_40; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_1; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_1 = _GEN_40; // @[package.scala:16:47] wire _GEN_41 = s1_req_cmd == 5'h10; // @[package.scala:16:47] wire _s1_read_T_1; // @[package.scala:16:47] assign _s1_read_T_1 = _GEN_41; // @[package.scala:16:47] wire _pstore1_rmw_T_1; // @[package.scala:16:47] assign _pstore1_rmw_T_1 = _GEN_41; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_2; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_2 = _GEN_41; // @[package.scala:16:47] wire _GEN_42 = s1_req_cmd == 5'h6; // @[package.scala:16:47] wire _s1_read_T_2; // @[package.scala:16:47] assign _s1_read_T_2 = _GEN_42; // @[package.scala:16:47] wire _pstore1_rmw_T_2; // @[package.scala:16:47] assign _pstore1_rmw_T_2 = _GEN_42; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_3; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_3 = _GEN_42; // @[package.scala:16:47] wire _GEN_43 = s1_req_cmd == 5'h7; // @[package.scala:16:47] wire _s1_read_T_3; // @[package.scala:16:47] assign _s1_read_T_3 = _GEN_43; // @[package.scala:16:47] wire _s1_write_T_3; // @[Consts.scala:90:66] assign _s1_write_T_3 = _GEN_43; // @[package.scala:16:47] wire _pstore1_rmw_T_3; // @[package.scala:16:47] assign _pstore1_rmw_T_3 = _GEN_43; // @[package.scala:16:47] wire _pstore1_rmw_T_28; // @[Consts.scala:90:66] assign _pstore1_rmw_T_28 = _GEN_43; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_4; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_4 = _GEN_43; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_29; // @[Consts.scala:90:66] assign _io_cpu_perf_canAcceptLoadThenLoad_T_29 = _GEN_43; // @[package.scala:16:47] wire _s1_read_T_4 = _s1_read_T | _s1_read_T_1; // @[package.scala:16:47, :81:59] wire _s1_read_T_5 = _s1_read_T_4 | _s1_read_T_2; // @[package.scala:16:47, :81:59] wire _s1_read_T_6 = _s1_read_T_5 | _s1_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_44 = s1_req_cmd == 5'h4; // @[package.scala:16:47] wire _s1_read_T_7; // @[package.scala:16:47] assign _s1_read_T_7 = _GEN_44; // @[package.scala:16:47] wire _s1_write_T_5; // @[package.scala:16:47] assign _s1_write_T_5 = _GEN_44; // @[package.scala:16:47] wire _pstore1_rmw_T_7; // @[package.scala:16:47] assign _pstore1_rmw_T_7 = _GEN_44; // @[package.scala:16:47] wire _pstore1_rmw_T_30; // @[package.scala:16:47] assign _pstore1_rmw_T_30 = _GEN_44; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_8; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_8 = _GEN_44; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_31; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_31 = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = s1_req_cmd == 5'h9; // @[package.scala:16:47] wire _s1_read_T_8; // @[package.scala:16:47] assign _s1_read_T_8 = _GEN_45; // @[package.scala:16:47] wire _s1_write_T_6; // @[package.scala:16:47] assign _s1_write_T_6 = _GEN_45; // @[package.scala:16:47] wire _pstore1_rmw_T_8; // @[package.scala:16:47] assign _pstore1_rmw_T_8 = _GEN_45; // @[package.scala:16:47] wire _pstore1_rmw_T_31; // @[package.scala:16:47] assign _pstore1_rmw_T_31 = _GEN_45; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_9; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_9 = _GEN_45; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_32; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_32 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = s1_req_cmd == 5'hA; // @[package.scala:16:47] wire _s1_read_T_9; // @[package.scala:16:47] assign _s1_read_T_9 = _GEN_46; // @[package.scala:16:47] wire _s1_write_T_7; // @[package.scala:16:47] assign _s1_write_T_7 = _GEN_46; // @[package.scala:16:47] wire _pstore1_rmw_T_9; // @[package.scala:16:47] assign _pstore1_rmw_T_9 = _GEN_46; // @[package.scala:16:47] wire _pstore1_rmw_T_32; // @[package.scala:16:47] assign _pstore1_rmw_T_32 = _GEN_46; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_10; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_10 = _GEN_46; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_33; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_33 = _GEN_46; // @[package.scala:16:47] wire _GEN_47 = s1_req_cmd == 5'hB; // @[package.scala:16:47] wire _s1_read_T_10; // @[package.scala:16:47] assign _s1_read_T_10 = _GEN_47; // @[package.scala:16:47] wire _s1_write_T_8; // @[package.scala:16:47] assign _s1_write_T_8 = _GEN_47; // @[package.scala:16:47] wire _pstore1_rmw_T_10; // @[package.scala:16:47] assign _pstore1_rmw_T_10 = _GEN_47; // @[package.scala:16:47] wire _pstore1_rmw_T_33; // @[package.scala:16:47] assign _pstore1_rmw_T_33 = _GEN_47; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_11; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_11 = _GEN_47; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_34; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_34 = _GEN_47; // @[package.scala:16:47] wire _s1_read_T_11 = _s1_read_T_7 | _s1_read_T_8; // @[package.scala:16:47, :81:59] wire _s1_read_T_12 = _s1_read_T_11 | _s1_read_T_9; // @[package.scala:16:47, :81:59] wire _s1_read_T_13 = _s1_read_T_12 | _s1_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_48 = s1_req_cmd == 5'h8; // @[package.scala:16:47] wire _s1_read_T_14; // @[package.scala:16:47] assign _s1_read_T_14 = _GEN_48; // @[package.scala:16:47] wire _s1_write_T_12; // @[package.scala:16:47] assign _s1_write_T_12 = _GEN_48; // @[package.scala:16:47] wire _pstore1_rmw_T_14; // @[package.scala:16:47] assign _pstore1_rmw_T_14 = _GEN_48; // @[package.scala:16:47] wire _pstore1_rmw_T_37; // @[package.scala:16:47] assign _pstore1_rmw_T_37 = _GEN_48; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_15; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_15 = _GEN_48; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_38; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_38 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = s1_req_cmd == 5'hC; // @[package.scala:16:47] wire _s1_read_T_15; // @[package.scala:16:47] assign _s1_read_T_15 = _GEN_49; // @[package.scala:16:47] wire _s1_write_T_13; // @[package.scala:16:47] assign _s1_write_T_13 = _GEN_49; // @[package.scala:16:47] wire _pstore1_rmw_T_15; // @[package.scala:16:47] assign _pstore1_rmw_T_15 = _GEN_49; // @[package.scala:16:47] wire _pstore1_rmw_T_38; // @[package.scala:16:47] assign _pstore1_rmw_T_38 = _GEN_49; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_16; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_16 = _GEN_49; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_39; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_39 = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = s1_req_cmd == 5'hD; // @[package.scala:16:47] wire _s1_read_T_16; // @[package.scala:16:47] assign _s1_read_T_16 = _GEN_50; // @[package.scala:16:47] wire _s1_write_T_14; // @[package.scala:16:47] assign _s1_write_T_14 = _GEN_50; // @[package.scala:16:47] wire _pstore1_rmw_T_16; // @[package.scala:16:47] assign _pstore1_rmw_T_16 = _GEN_50; // @[package.scala:16:47] wire _pstore1_rmw_T_39; // @[package.scala:16:47] assign _pstore1_rmw_T_39 = _GEN_50; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_17; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_17 = _GEN_50; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_40; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_40 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = s1_req_cmd == 5'hE; // @[package.scala:16:47] wire _s1_read_T_17; // @[package.scala:16:47] assign _s1_read_T_17 = _GEN_51; // @[package.scala:16:47] wire _s1_write_T_15; // @[package.scala:16:47] assign _s1_write_T_15 = _GEN_51; // @[package.scala:16:47] wire _pstore1_rmw_T_17; // @[package.scala:16:47] assign _pstore1_rmw_T_17 = _GEN_51; // @[package.scala:16:47] wire _pstore1_rmw_T_40; // @[package.scala:16:47] assign _pstore1_rmw_T_40 = _GEN_51; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_18; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_18 = _GEN_51; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_41; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_41 = _GEN_51; // @[package.scala:16:47] wire _GEN_52 = s1_req_cmd == 5'hF; // @[package.scala:16:47] wire _s1_read_T_18; // @[package.scala:16:47] assign _s1_read_T_18 = _GEN_52; // @[package.scala:16:47] wire _s1_write_T_16; // @[package.scala:16:47] assign _s1_write_T_16 = _GEN_52; // @[package.scala:16:47] wire _pstore1_rmw_T_18; // @[package.scala:16:47] assign _pstore1_rmw_T_18 = _GEN_52; // @[package.scala:16:47] wire _pstore1_rmw_T_41; // @[package.scala:16:47] assign _pstore1_rmw_T_41 = _GEN_52; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_19; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_19 = _GEN_52; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_42; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_42 = _GEN_52; // @[package.scala:16:47] wire _s1_read_T_19 = _s1_read_T_14 | _s1_read_T_15; // @[package.scala:16:47, :81:59] wire _s1_read_T_20 = _s1_read_T_19 | _s1_read_T_16; // @[package.scala:16:47, :81:59] wire _s1_read_T_21 = _s1_read_T_20 | _s1_read_T_17; // @[package.scala:16:47, :81:59] wire _s1_read_T_22 = _s1_read_T_21 | _s1_read_T_18; // @[package.scala:16:47, :81:59] wire _s1_read_T_23 = _s1_read_T_13 | _s1_read_T_22; // @[package.scala:81:59] wire s1_read = _s1_read_T_6 | _s1_read_T_23; // @[package.scala:81:59] wire _GEN_53 = s1_req_cmd == 5'h1; // @[DCache.scala:196:25] wire _s1_write_T; // @[Consts.scala:90:32] assign _s1_write_T = _GEN_53; // @[Consts.scala:90:32] wire _pstore1_rmw_T_25; // @[Consts.scala:90:32] assign _pstore1_rmw_T_25 = _GEN_53; // @[Consts.scala:90:32] wire _io_cpu_perf_canAcceptLoadThenLoad_T_26; // @[Consts.scala:90:32] assign _io_cpu_perf_canAcceptLoadThenLoad_T_26 = _GEN_53; // @[Consts.scala:90:32] wire _T_20 = s1_req_cmd == 5'h11; // @[DCache.scala:196:25] wire _s1_write_T_1; // @[Consts.scala:90:49] assign _s1_write_T_1 = _T_20; // @[Consts.scala:90:49] wire _s1_mask_T; // @[DCache.scala:327:32] assign _s1_mask_T = _T_20; // @[DCache.scala:327:32] wire _pstore1_rmw_T_26; // @[Consts.scala:90:49] assign _pstore1_rmw_T_26 = _T_20; // @[Consts.scala:90:49] wire _pstore1_rmw_T_48; // @[DCache.scala:1191:35] assign _pstore1_rmw_T_48 = _T_20; // @[DCache.scala:1191:35] wire _io_cpu_perf_canAcceptLoadThenLoad_T_27; // @[Consts.scala:90:49] assign _io_cpu_perf_canAcceptLoadThenLoad_T_27 = _T_20; // @[Consts.scala:90:49] wire _io_cpu_perf_canAcceptLoadThenLoad_T_49; // @[DCache.scala:1191:35] assign _io_cpu_perf_canAcceptLoadThenLoad_T_49 = _T_20; // @[DCache.scala:1191:35] wire _s1_write_T_2 = _s1_write_T | _s1_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _s1_write_T_4 = _s1_write_T_2 | _s1_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _s1_write_T_9 = _s1_write_T_5 | _s1_write_T_6; // @[package.scala:16:47, :81:59] wire _s1_write_T_10 = _s1_write_T_9 | _s1_write_T_7; // @[package.scala:16:47, :81:59] wire _s1_write_T_11 = _s1_write_T_10 | _s1_write_T_8; // @[package.scala:16:47, :81:59] wire _s1_write_T_17 = _s1_write_T_12 | _s1_write_T_13; // @[package.scala:16:47, :81:59] wire _s1_write_T_18 = _s1_write_T_17 | _s1_write_T_14; // @[package.scala:16:47, :81:59] wire _s1_write_T_19 = _s1_write_T_18 | _s1_write_T_15; // @[package.scala:16:47, :81:59] wire _s1_write_T_20 = _s1_write_T_19 | _s1_write_T_16; // @[package.scala:16:47, :81:59] wire _s1_write_T_21 = _s1_write_T_11 | _s1_write_T_20; // @[package.scala:81:59] wire s1_write = _s1_write_T_4 | _s1_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire s1_readwrite = s1_read | s1_write; // @[DCache.scala:212:30] wire _s1_sfence_T = s1_req_cmd == 5'h14; // @[DCache.scala:196:25, :213:30] wire _GEN_54 = s1_req_cmd == 5'h15; // @[DCache.scala:196:25, :213:57] wire _s1_sfence_T_1; // @[DCache.scala:213:57] assign _s1_sfence_T_1 = _GEN_54; // @[DCache.scala:213:57] wire _tlb_io_sfence_bits_hv_T; // @[DCache.scala:283:39] assign _tlb_io_sfence_bits_hv_T = _GEN_54; // @[DCache.scala:213:57, :283:39] wire _s1_sfence_T_2 = _s1_sfence_T | _s1_sfence_T_1; // @[DCache.scala:213:{30,43,57}] wire _GEN_55 = s1_req_cmd == 5'h16; // @[DCache.scala:196:25, :213:85] wire _s1_sfence_T_3; // @[DCache.scala:213:85] assign _s1_sfence_T_3 = _GEN_55; // @[DCache.scala:213:85] wire _tlb_io_sfence_bits_hg_T; // @[DCache.scala:284:39] assign _tlb_io_sfence_bits_hg_T = _GEN_55; // @[DCache.scala:213:85, :284:39] wire s1_sfence = _s1_sfence_T_2 | _s1_sfence_T_3; // @[DCache.scala:213:{43,71,85}] wire _s1_flush_line_T = s1_req_cmd == 5'h5; // @[DCache.scala:196:25, :214:34] wire _s1_flush_line_T_1 = s1_req_size[0]; // @[DCache.scala:196:25, :214:64] wire _tlb_io_sfence_bits_rs1_T = s1_req_size[0]; // @[DCache.scala:196:25, :214:64, :279:40] wire s1_flush_line = _s1_flush_line_T & _s1_flush_line_T_1; // @[DCache.scala:214:{34,50,64}] reg s1_flush_valid; // @[DCache.scala:215:27] reg cached_grant_wait; // @[DCache.scala:223:34] reg resetting; // @[DCache.scala:224:26] assign metaArb_io_in_0_valid = resetting; // @[DCache.scala:135:28, :224:26] reg [8:0] flushCounter; // @[DCache.scala:225:29] reg release_ack_wait; // @[DCache.scala:226:33] reg [31:0] release_ack_addr; // @[DCache.scala:227:29] reg [3:0] release_state; // @[DCache.scala:228:30] reg [7:0] refill_way; // @[DCache.scala:229:23] assign metaArb_io_in_3_bits_way_en = refill_way; // @[DCache.scala:135:28, :229:23] assign dataArb_io_in_1_bits_way_en = refill_way; // @[DCache.scala:152:28, :229:23] wire _any_pstore_valid_T; // @[DCache.scala:508:36] wire any_pstore_valid; // @[DCache.scala:230:30] wire _T_114 = release_state == 4'h1; // @[package.scala:16:47] wire _inWriteback_T; // @[package.scala:16:47] assign _inWriteback_T = _T_114; // @[package.scala:16:47] wire _canAcceptCachedGrant_T; // @[package.scala:16:47] assign _canAcceptCachedGrant_T = _T_114; // @[package.scala:16:47] wire _inWriteback_T_1 = release_state == 4'h2; // @[package.scala:16:47] wire inWriteback = _inWriteback_T | _inWriteback_T_1; // @[package.scala:16:47, :81:59] assign metaArb_io_in_4_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_5_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_6_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_7_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] wire _io_cpu_req_ready_T = ~(|release_state); // @[DCache.scala:228:30, :233:38] wire _io_cpu_req_ready_T_1 = ~cached_grant_wait; // @[DCache.scala:223:34, :233:54] wire _io_cpu_req_ready_T_2 = _io_cpu_req_ready_T & _io_cpu_req_ready_T_1; // @[DCache.scala:233:{38,51,54}] wire _io_cpu_req_ready_T_3 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :233:76] wire _io_cpu_req_ready_T_4 = _io_cpu_req_ready_T_2 & _io_cpu_req_ready_T_3; // @[DCache.scala:233:{51,73,76}] reg uncachedInFlight_0; // @[DCache.scala:236:33] wire _s2_valid_cached_miss_T_2 = uncachedInFlight_0; // @[DCache.scala:236:33, :425:88] wire _s2_valid_uncached_pending_T_1 = uncachedInFlight_0; // @[DCache.scala:236:33, :430:92] wire _io_cpu_ordered_T_6 = uncachedInFlight_0; // @[DCache.scala:236:33, :929:142] wire _io_cpu_store_pending_T_24 = uncachedInFlight_0; // @[DCache.scala:236:33, :930:97] wire _clock_en_reg_T_22 = uncachedInFlight_0; // @[DCache.scala:236:33, :1072:50] reg [39:0] uncachedReqs_0_addr; // @[DCache.scala:237:25] wire [39:0] uncachedResp_addr = uncachedReqs_0_addr; // @[DCache.scala:237:25, :238:30] reg [6:0] uncachedReqs_0_tag; // @[DCache.scala:237:25] wire [6:0] uncachedResp_tag = uncachedReqs_0_tag; // @[DCache.scala:237:25, :238:30] reg [4:0] uncachedReqs_0_cmd; // @[DCache.scala:237:25] wire [4:0] uncachedResp_cmd = uncachedReqs_0_cmd; // @[DCache.scala:237:25, :238:30] reg [1:0] uncachedReqs_0_size; // @[DCache.scala:237:25] wire [1:0] uncachedResp_size = uncachedReqs_0_size; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_signed; // @[DCache.scala:237:25] wire uncachedResp_signed = uncachedReqs_0_signed; // @[DCache.scala:237:25, :238:30] reg [1:0] uncachedReqs_0_dprv; // @[DCache.scala:237:25] wire [1:0] uncachedResp_dprv = uncachedReqs_0_dprv; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_dv; // @[DCache.scala:237:25] wire uncachedResp_dv = uncachedReqs_0_dv; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_phys; // @[DCache.scala:237:25] wire uncachedResp_phys = uncachedReqs_0_phys; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_resp; // @[DCache.scala:237:25] wire uncachedResp_no_resp = uncachedReqs_0_no_resp; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_alloc; // @[DCache.scala:237:25] wire uncachedResp_no_alloc = uncachedReqs_0_no_alloc; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25] wire uncachedResp_no_xcpt = uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25, :238:30] reg [63:0] uncachedReqs_0_data; // @[DCache.scala:237:25] wire [63:0] uncachedResp_data = uncachedReqs_0_data; // @[DCache.scala:237:25, :238:30] reg [7:0] uncachedReqs_0_mask; // @[DCache.scala:237:25] wire [7:0] uncachedResp_mask = uncachedReqs_0_mask; // @[DCache.scala:237:25, :238:30] wire _GEN_56 = io_cpu_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _s0_read_T; // @[package.scala:16:47] assign _s0_read_T = _GEN_56; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T = _GEN_56; // @[package.scala:16:47] wire _s1_did_read_T; // @[package.scala:16:47] assign _s1_did_read_T = _GEN_56; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T = _GEN_56; // @[package.scala:16:47] wire _GEN_57 = io_cpu_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _s0_read_T_1; // @[package.scala:16:47] assign _s0_read_T_1 = _GEN_57; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_1 = _GEN_57; // @[package.scala:16:47] wire _s1_did_read_T_1; // @[package.scala:16:47] assign _s1_did_read_T_1 = _GEN_57; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_1; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_1 = _GEN_57; // @[package.scala:16:47] wire _GEN_58 = io_cpu_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _s0_read_T_2; // @[package.scala:16:47] assign _s0_read_T_2 = _GEN_58; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_2 = _GEN_58; // @[package.scala:16:47] wire _s1_did_read_T_2; // @[package.scala:16:47] assign _s1_did_read_T_2 = _GEN_58; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_2; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_2 = _GEN_58; // @[package.scala:16:47] wire _GEN_59 = io_cpu_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _s0_read_T_3; // @[package.scala:16:47] assign _s0_read_T_3 = _GEN_59; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_3 = _GEN_59; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:66] assign _dataArb_io_in_3_valid_T_28 = _GEN_59; // @[package.scala:16:47] wire _s1_did_read_T_3; // @[package.scala:16:47] assign _s1_did_read_T_3 = _GEN_59; // @[package.scala:16:47] wire _s1_did_read_T_28; // @[Consts.scala:90:66] assign _s1_did_read_T_28 = _GEN_59; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_3; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_3 = _GEN_59; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:66] assign _pstore_drain_opportunistic_T_28 = _GEN_59; // @[package.scala:16:47] wire _s0_read_T_4 = _s0_read_T | _s0_read_T_1; // @[package.scala:16:47, :81:59] wire _s0_read_T_5 = _s0_read_T_4 | _s0_read_T_2; // @[package.scala:16:47, :81:59] wire _s0_read_T_6 = _s0_read_T_5 | _s0_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_60 = io_cpu_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _s0_read_T_7; // @[package.scala:16:47] assign _s0_read_T_7 = _GEN_60; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_7; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_7 = _GEN_60; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_30; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_30 = _GEN_60; // @[package.scala:16:47] wire _s1_did_read_T_7; // @[package.scala:16:47] assign _s1_did_read_T_7 = _GEN_60; // @[package.scala:16:47] wire _s1_did_read_T_30; // @[package.scala:16:47] assign _s1_did_read_T_30 = _GEN_60; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_7; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_7 = _GEN_60; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_30; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_30 = _GEN_60; // @[package.scala:16:47] wire _GEN_61 = io_cpu_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _s0_read_T_8; // @[package.scala:16:47] assign _s0_read_T_8 = _GEN_61; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_8 = _GEN_61; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_31 = _GEN_61; // @[package.scala:16:47] wire _s1_did_read_T_8; // @[package.scala:16:47] assign _s1_did_read_T_8 = _GEN_61; // @[package.scala:16:47] wire _s1_did_read_T_31; // @[package.scala:16:47] assign _s1_did_read_T_31 = _GEN_61; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_8; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_8 = _GEN_61; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_31; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_31 = _GEN_61; // @[package.scala:16:47] wire _GEN_62 = io_cpu_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _s0_read_T_9; // @[package.scala:16:47] assign _s0_read_T_9 = _GEN_62; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_9 = _GEN_62; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_32 = _GEN_62; // @[package.scala:16:47] wire _s1_did_read_T_9; // @[package.scala:16:47] assign _s1_did_read_T_9 = _GEN_62; // @[package.scala:16:47] wire _s1_did_read_T_32; // @[package.scala:16:47] assign _s1_did_read_T_32 = _GEN_62; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_9; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_9 = _GEN_62; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_32; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_32 = _GEN_62; // @[package.scala:16:47] wire _GEN_63 = io_cpu_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _s0_read_T_10; // @[package.scala:16:47] assign _s0_read_T_10 = _GEN_63; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_10 = _GEN_63; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_33 = _GEN_63; // @[package.scala:16:47] wire _s1_did_read_T_10; // @[package.scala:16:47] assign _s1_did_read_T_10 = _GEN_63; // @[package.scala:16:47] wire _s1_did_read_T_33; // @[package.scala:16:47] assign _s1_did_read_T_33 = _GEN_63; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_10; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_10 = _GEN_63; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_33; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_33 = _GEN_63; // @[package.scala:16:47] wire _s0_read_T_11 = _s0_read_T_7 | _s0_read_T_8; // @[package.scala:16:47, :81:59] wire _s0_read_T_12 = _s0_read_T_11 | _s0_read_T_9; // @[package.scala:16:47, :81:59] wire _s0_read_T_13 = _s0_read_T_12 | _s0_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_64 = io_cpu_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _s0_read_T_14; // @[package.scala:16:47] assign _s0_read_T_14 = _GEN_64; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_14; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_14 = _GEN_64; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_37; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_37 = _GEN_64; // @[package.scala:16:47] wire _s1_did_read_T_14; // @[package.scala:16:47] assign _s1_did_read_T_14 = _GEN_64; // @[package.scala:16:47] wire _s1_did_read_T_37; // @[package.scala:16:47] assign _s1_did_read_T_37 = _GEN_64; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_14; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_14 = _GEN_64; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_37; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_37 = _GEN_64; // @[package.scala:16:47] wire _GEN_65 = io_cpu_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _s0_read_T_15; // @[package.scala:16:47] assign _s0_read_T_15 = _GEN_65; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_15 = _GEN_65; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_38 = _GEN_65; // @[package.scala:16:47] wire _s1_did_read_T_15; // @[package.scala:16:47] assign _s1_did_read_T_15 = _GEN_65; // @[package.scala:16:47] wire _s1_did_read_T_38; // @[package.scala:16:47] assign _s1_did_read_T_38 = _GEN_65; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_15; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_15 = _GEN_65; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_38; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_38 = _GEN_65; // @[package.scala:16:47] wire _GEN_66 = io_cpu_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _s0_read_T_16; // @[package.scala:16:47] assign _s0_read_T_16 = _GEN_66; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_16 = _GEN_66; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_39 = _GEN_66; // @[package.scala:16:47] wire _s1_did_read_T_16; // @[package.scala:16:47] assign _s1_did_read_T_16 = _GEN_66; // @[package.scala:16:47] wire _s1_did_read_T_39; // @[package.scala:16:47] assign _s1_did_read_T_39 = _GEN_66; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_16; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_16 = _GEN_66; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_39; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_39 = _GEN_66; // @[package.scala:16:47] wire _GEN_67 = io_cpu_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _s0_read_T_17; // @[package.scala:16:47] assign _s0_read_T_17 = _GEN_67; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_17 = _GEN_67; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_40 = _GEN_67; // @[package.scala:16:47] wire _s1_did_read_T_17; // @[package.scala:16:47] assign _s1_did_read_T_17 = _GEN_67; // @[package.scala:16:47] wire _s1_did_read_T_40; // @[package.scala:16:47] assign _s1_did_read_T_40 = _GEN_67; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_17; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_17 = _GEN_67; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_40; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_40 = _GEN_67; // @[package.scala:16:47] wire _GEN_68 = io_cpu_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _s0_read_T_18; // @[package.scala:16:47] assign _s0_read_T_18 = _GEN_68; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_18 = _GEN_68; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_41 = _GEN_68; // @[package.scala:16:47] wire _s1_did_read_T_18; // @[package.scala:16:47] assign _s1_did_read_T_18 = _GEN_68; // @[package.scala:16:47] wire _s1_did_read_T_41; // @[package.scala:16:47] assign _s1_did_read_T_41 = _GEN_68; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_18; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_18 = _GEN_68; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_41; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_41 = _GEN_68; // @[package.scala:16:47] wire _s0_read_T_19 = _s0_read_T_14 | _s0_read_T_15; // @[package.scala:16:47, :81:59] wire _s0_read_T_20 = _s0_read_T_19 | _s0_read_T_16; // @[package.scala:16:47, :81:59] wire _s0_read_T_21 = _s0_read_T_20 | _s0_read_T_17; // @[package.scala:16:47, :81:59] wire _s0_read_T_22 = _s0_read_T_21 | _s0_read_T_18; // @[package.scala:16:47, :81:59] wire _s0_read_T_23 = _s0_read_T_13 | _s0_read_T_22; // @[package.scala:81:59] wire s0_read = _s0_read_T_6 | _s0_read_T_23; // @[package.scala:81:59] wire _GEN_69 = io_cpu_req_bits_cmd_0 == 5'h1; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_res_T = _GEN_69; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_25; // @[Consts.scala:90:32] assign _dataArb_io_in_3_valid_T_25 = _GEN_69; // @[package.scala:16:47] wire _s1_did_read_T_25; // @[Consts.scala:90:32] assign _s1_did_read_T_25 = _GEN_69; // @[package.scala:16:47] wire _pstore_drain_opportunistic_res_T; // @[package.scala:16:47] assign _pstore_drain_opportunistic_res_T = _GEN_69; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_25; // @[Consts.scala:90:32] assign _pstore_drain_opportunistic_T_25 = _GEN_69; // @[package.scala:16:47] wire _GEN_70 = io_cpu_req_bits_cmd_0 == 5'h3; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_res_T_1 = _GEN_70; // @[package.scala:16:47] wire _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47] assign _pstore_drain_opportunistic_res_T_1 = _GEN_70; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T_2 = _dataArb_io_in_3_valid_res_T | _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_res_T_3 = ~_dataArb_io_in_3_valid_res_T_2; // @[package.scala:81:59] wire dataArb_io_in_3_valid_res = _dataArb_io_in_3_valid_res_T_3; // @[DCache.scala:1185:{15,46}] wire _dataArb_io_in_3_valid_T_4 = _dataArb_io_in_3_valid_T | _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_5 = _dataArb_io_in_3_valid_T_4 | _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_6 = _dataArb_io_in_3_valid_T_5 | _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_11 = _dataArb_io_in_3_valid_T_7 | _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_12 = _dataArb_io_in_3_valid_T_11 | _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_13 = _dataArb_io_in_3_valid_T_12 | _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_19 = _dataArb_io_in_3_valid_T_14 | _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_20 = _dataArb_io_in_3_valid_T_19 | _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_21 = _dataArb_io_in_3_valid_T_20 | _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_22 = _dataArb_io_in_3_valid_T_21 | _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_23 = _dataArb_io_in_3_valid_T_13 | _dataArb_io_in_3_valid_T_22; // @[package.scala:81:59] wire _dataArb_io_in_3_valid_T_24 = _dataArb_io_in_3_valid_T_6 | _dataArb_io_in_3_valid_T_23; // @[package.scala:81:59] wire _GEN_71 = io_cpu_req_bits_cmd_0 == 5'h11; // @[DCache.scala:101:7] wire _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:49] assign _dataArb_io_in_3_valid_T_26 = _GEN_71; // @[Consts.scala:90:49] wire _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:35] assign _dataArb_io_in_3_valid_T_48 = _GEN_71; // @[DCache.scala:1191:35] wire _s1_did_read_T_26; // @[Consts.scala:90:49] assign _s1_did_read_T_26 = _GEN_71; // @[Consts.scala:90:49] wire _s1_did_read_T_48; // @[DCache.scala:1191:35] assign _s1_did_read_T_48 = _GEN_71; // @[DCache.scala:1191:35] wire _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:49] assign _pstore_drain_opportunistic_T_26 = _GEN_71; // @[Consts.scala:90:49] wire _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:35] assign _pstore_drain_opportunistic_T_48 = _GEN_71; // @[DCache.scala:1191:35] wire _dataArb_io_in_3_valid_T_27 = _dataArb_io_in_3_valid_T_25 | _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:{32,42,49}] wire _dataArb_io_in_3_valid_T_29 = _dataArb_io_in_3_valid_T_27 | _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:{42,59,66}] wire _dataArb_io_in_3_valid_T_34 = _dataArb_io_in_3_valid_T_30 | _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_35 = _dataArb_io_in_3_valid_T_34 | _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_36 = _dataArb_io_in_3_valid_T_35 | _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_42 = _dataArb_io_in_3_valid_T_37 | _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_43 = _dataArb_io_in_3_valid_T_42 | _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_44 = _dataArb_io_in_3_valid_T_43 | _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_45 = _dataArb_io_in_3_valid_T_44 | _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_46 = _dataArb_io_in_3_valid_T_36 | _dataArb_io_in_3_valid_T_45; // @[package.scala:81:59] wire _dataArb_io_in_3_valid_T_47 = _dataArb_io_in_3_valid_T_29 | _dataArb_io_in_3_valid_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _dataArb_io_in_3_valid_T_50 = _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:{35,45}] wire _dataArb_io_in_3_valid_T_51 = _dataArb_io_in_3_valid_T_47 & _dataArb_io_in_3_valid_T_50; // @[DCache.scala:1191:{23,45}] wire _dataArb_io_in_3_valid_T_52 = _dataArb_io_in_3_valid_T_24 | _dataArb_io_in_3_valid_T_51; // @[DCache.scala:1190:21, :1191:23] wire _dataArb_io_in_3_valid_T_53 = ~_dataArb_io_in_3_valid_T_52; // @[DCache.scala:1186:12, :1190:21] wire _dataArb_io_in_3_valid_T_54 = _dataArb_io_in_3_valid_T_53 | dataArb_io_in_3_valid_res; // @[DCache.scala:1185:46, :1186:{12,28}] wire _dataArb_io_in_3_valid_T_56 = ~_dataArb_io_in_3_valid_T_55; // @[DCache.scala:1186:11] wire _dataArb_io_in_3_valid_T_57 = ~_dataArb_io_in_3_valid_T_54; // @[DCache.scala:1186:{11,28}] assign _dataArb_io_in_3_valid_T_58 = io_cpu_req_valid_0 & dataArb_io_in_3_valid_res; // @[DCache.scala:101:7, :242:46, :1185:46] assign dataArb_io_in_3_valid = _dataArb_io_in_3_valid_T_58; // @[DCache.scala:152:28, :242:46] wire [27:0] _dataArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89] wire [27:0] _metaArb_io_in_1_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :454:58] wire [27:0] _metaArb_io_in_2_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :466:58] wire [27:0] _metaArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :745:58] wire [27:0] _metaArb_io_in_4_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :912:58] wire [27:0] _metaArb_io_in_5_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :1018:58] wire [11:0] _dataArb_io_in_3_bits_addr_T_1 = io_cpu_req_bits_addr_0[11:0]; // @[DCache.scala:101:7, :245:120] wire [39:0] _dataArb_io_in_3_bits_addr_T_2 = {_dataArb_io_in_3_bits_addr_T, _dataArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:245:{36,89,120}] assign dataArb_io_in_3_bits_addr = _dataArb_io_in_3_bits_addr_T_2[11:0]; // @[DCache.scala:152:28, :245:{30,36}] wire _dataArb_io_in_3_bits_wordMask_mask_upper_T = io_cpu_req_bits_addr_0[3]; // @[DCache.scala:101:7, :250:43] wire _dataArb_io_in_3_bits_wordMask_mask_lower_T = io_cpu_req_bits_addr_0[3]; // @[DCache.scala:101:7, :250:43, :251:43] wire _dataArb_io_in_3_bits_wordMask_mask_upper_T_1 = _dataArb_io_in_3_bits_wordMask_mask_upper_T; // @[DCache.scala:250:{22,43}] wire dataArb_io_in_3_bits_wordMask_mask_upper = _dataArb_io_in_3_bits_wordMask_mask_upper_T_1; // @[DCache.scala:250:{22,57}] wire dataArb_io_in_3_bits_wordMask_mask_lower = ~_dataArb_io_in_3_bits_wordMask_mask_lower_T; // @[DCache.scala:251:{22,43}] wire [1:0] dataArb_io_in_3_bits_wordMask_mask = {dataArb_io_in_3_bits_wordMask_mask_upper, dataArb_io_in_3_bits_wordMask_mask_lower}; // @[DCache.scala:250:57, :251:22, :252:13] wire [3:0] _dataArb_io_in_3_bits_wordMask_T = {2{dataArb_io_in_3_bits_wordMask_mask}}; // @[DCache.scala:252:13, :254:9] wire [7:0] _dataArb_io_in_3_bits_wordMask_T_1 = {2{_dataArb_io_in_3_bits_wordMask_T}}; // @[DCache.scala:254:9] wire [15:0] _dataArb_io_in_3_bits_wordMask_T_2 = {2{_dataArb_io_in_3_bits_wordMask_T_1}}; // @[DCache.scala:254:9] assign dataArb_io_in_3_bits_wordMask = _dataArb_io_in_3_bits_wordMask_T_2[1:0]; // @[DCache.scala:152:28, :246:34, :254:9] wire _T_4 = ~dataArb_io_in_3_ready & s0_read; // @[DCache.scala:152:28, :258:{9,33}] wire _s1_did_read_T_4 = _s1_did_read_T | _s1_did_read_T_1; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_5 = _s1_did_read_T_4 | _s1_did_read_T_2; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_6 = _s1_did_read_T_5 | _s1_did_read_T_3; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_11 = _s1_did_read_T_7 | _s1_did_read_T_8; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_12 = _s1_did_read_T_11 | _s1_did_read_T_9; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_13 = _s1_did_read_T_12 | _s1_did_read_T_10; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_19 = _s1_did_read_T_14 | _s1_did_read_T_15; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_20 = _s1_did_read_T_19 | _s1_did_read_T_16; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_21 = _s1_did_read_T_20 | _s1_did_read_T_17; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_22 = _s1_did_read_T_21 | _s1_did_read_T_18; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_23 = _s1_did_read_T_13 | _s1_did_read_T_22; // @[package.scala:81:59] wire _s1_did_read_T_24 = _s1_did_read_T_6 | _s1_did_read_T_23; // @[package.scala:81:59] wire _s1_did_read_T_27 = _s1_did_read_T_25 | _s1_did_read_T_26; // @[Consts.scala:90:{32,42,49}] wire _s1_did_read_T_29 = _s1_did_read_T_27 | _s1_did_read_T_28; // @[Consts.scala:90:{42,59,66}] wire _s1_did_read_T_34 = _s1_did_read_T_30 | _s1_did_read_T_31; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_35 = _s1_did_read_T_34 | _s1_did_read_T_32; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_36 = _s1_did_read_T_35 | _s1_did_read_T_33; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_42 = _s1_did_read_T_37 | _s1_did_read_T_38; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_43 = _s1_did_read_T_42 | _s1_did_read_T_39; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_44 = _s1_did_read_T_43 | _s1_did_read_T_40; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_45 = _s1_did_read_T_44 | _s1_did_read_T_41; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_46 = _s1_did_read_T_36 | _s1_did_read_T_45; // @[package.scala:81:59] wire _s1_did_read_T_47 = _s1_did_read_T_29 | _s1_did_read_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _s1_did_read_T_50 = _s1_did_read_T_48; // @[DCache.scala:1191:{35,45}] wire _s1_did_read_T_51 = _s1_did_read_T_47 & _s1_did_read_T_50; // @[DCache.scala:1191:{23,45}] wire _s1_did_read_T_52 = _s1_did_read_T_24 | _s1_did_read_T_51; // @[DCache.scala:1190:21, :1191:23] wire _s1_did_read_T_53 = io_cpu_req_valid_0 & _s1_did_read_T_52; // @[DCache.scala:101:7, :259:75, :1190:21] wire _s1_did_read_T_54 = dataArb_io_in_3_ready & _s1_did_read_T_53; // @[DCache.scala:152:28, :259:{54,75}] reg s1_did_read; // @[DCache.scala:259:30] reg [1:0] s1_read_mask; // @[DCache.scala:260:31] assign _metaArb_io_in_7_bits_idx_T = _dataArb_io_in_3_bits_addr_T_2[11:6]; // @[DCache.scala:245:36, :263:58] assign metaArb_io_in_7_bits_idx = _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:135:28, :263:58] wire _s1_cmd_uses_tlb_T = s1_readwrite | s1_flush_line; // @[DCache.scala:212:30, :214:50, :270:38] wire _s1_cmd_uses_tlb_T_1 = s1_req_cmd == 5'h17; // @[DCache.scala:196:25, :270:69] wire s1_cmd_uses_tlb = _s1_cmd_uses_tlb_T | _s1_cmd_uses_tlb_T_1; // @[DCache.scala:270:{38,55,69}] wire _tlb_io_req_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :273:55] wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[DCache.scala:182:25, :273:{52,55}] wire _tlb_io_req_valid_T_2 = _tlb_io_req_valid_T_1 & s1_cmd_uses_tlb; // @[DCache.scala:270:55, :273:{52,71}] wire _tlb_io_req_valid_T_3 = _tlb_io_req_valid_T_2; // @[DCache.scala:273:{40,71}] wire _s1_xcpt_valid_T_1 = _tlb_io_req_valid_T_3; // @[DCache.scala:273:40, :932:40] wire _T_10 = ~_tlb_io_req_ready & ~io_ptw_resp_valid_0 & ~io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :119:19, :275:{9,27,30,53,56}] wire _T_14 = s1_valid & s1_cmd_uses_tlb & _tlb_io_resp_miss; // @[DCache.scala:119:19, :182:25, :270:55, :276:{39,58}] wire _tlb_io_sfence_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :278:38] wire _tlb_io_sfence_valid_T_1 = s1_valid & _tlb_io_sfence_valid_T; // @[DCache.scala:182:25, :278:{35,38}] wire _tlb_io_sfence_valid_T_2 = _tlb_io_sfence_valid_T_1 & s1_sfence; // @[DCache.scala:213:71, :278:{35,54}] wire _tlb_io_sfence_bits_rs2_T = s1_req_size[1]; // @[DCache.scala:196:25, :280:40] wire [19:0] _s1_paddr_T = s1_req_addr[31:12]; // @[DCache.scala:196:25, :298:55] wire [19:0] _s1_paddr_T_1 = _tlb_io_resp_paddr[31:12]; // @[DCache.scala:119:19, :298:99] wire [19:0] _s1_paddr_T_2 = _s1_paddr_T_1; // @[DCache.scala:298:{25,99}] wire [31:0] s1_paddr = {_s1_paddr_T_2, _s1_paddr_T_3}; // @[DCache.scala:298:{21,25,125}] wire [2:0] _s1_victim_way_T; // @[package.scala:163:13] wire [2:0] s1_victim_way; // @[DCache.scala:299:27] assign rockettile_dcache_tag_array_MPORT_en = metaArb_io_out_valid & metaArb_io_out_bits_write; // @[DCache.scala:135:28, :310:27] assign wmask_0 = metaArb_io_out_bits_way_en[0]; // @[DCache.scala:135:28, :311:74] assign wmask_1 = metaArb_io_out_bits_way_en[1]; // @[DCache.scala:135:28, :311:74] assign wmask_2 = metaArb_io_out_bits_way_en[2]; // @[DCache.scala:135:28, :311:74] assign wmask_3 = metaArb_io_out_bits_way_en[3]; // @[DCache.scala:135:28, :311:74] assign wmask_4 = metaArb_io_out_bits_way_en[4]; // @[DCache.scala:135:28, :311:74] assign wmask_5 = metaArb_io_out_bits_way_en[5]; // @[DCache.scala:135:28, :311:74] assign wmask_6 = metaArb_io_out_bits_way_en[6]; // @[DCache.scala:135:28, :311:74] assign wmask_7 = metaArb_io_out_bits_way_en[7]; // @[DCache.scala:135:28, :311:74] wire _s1_meta_T = ~metaArb_io_out_bits_write; // @[DCache.scala:135:28, :190:43, :314:62] assign _s1_meta_T_1 = metaArb_io_out_valid & _s1_meta_T; // @[DCache.scala:135:28, :314:{59,62}] wire [1:0] _s1_meta_uncorrected_T_1; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_0_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_0_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T = _s1_meta_uncorrected_WIRE[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_0_tag = _s1_meta_uncorrected_T; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_1 = _s1_meta_uncorrected_WIRE[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_0_coh_state = _s1_meta_uncorrected_T_1; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_3; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_2; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_1_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_1_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_2 = _s1_meta_uncorrected_WIRE_1[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_1_tag = _s1_meta_uncorrected_T_2; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_3 = _s1_meta_uncorrected_WIRE_1[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_1_coh_state = _s1_meta_uncorrected_T_3; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_5; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_4; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_2_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_2_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_4 = _s1_meta_uncorrected_WIRE_2[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_2_tag = _s1_meta_uncorrected_T_4; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_5 = _s1_meta_uncorrected_WIRE_2[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_2_coh_state = _s1_meta_uncorrected_T_5; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_7; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_6; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_3_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_3_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_6 = _s1_meta_uncorrected_WIRE_3[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_3_tag = _s1_meta_uncorrected_T_6; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_7 = _s1_meta_uncorrected_WIRE_3[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_3_coh_state = _s1_meta_uncorrected_T_7; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_9; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_8; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_4_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_4_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_8 = _s1_meta_uncorrected_WIRE_4[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_4_tag = _s1_meta_uncorrected_T_8; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_9 = _s1_meta_uncorrected_WIRE_4[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_4_coh_state = _s1_meta_uncorrected_T_9; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_11; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_10; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_5_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_5_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_10 = _s1_meta_uncorrected_WIRE_5[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_5_tag = _s1_meta_uncorrected_T_10; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_11 = _s1_meta_uncorrected_WIRE_5[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_5_coh_state = _s1_meta_uncorrected_T_11; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_13; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_12; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_6_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_6_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_12 = _s1_meta_uncorrected_WIRE_6[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_6_tag = _s1_meta_uncorrected_T_12; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_13 = _s1_meta_uncorrected_WIRE_6[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_6_coh_state = _s1_meta_uncorrected_T_13; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_15; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_14; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_7_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_7_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_14 = _s1_meta_uncorrected_WIRE_7[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_7_tag = _s1_meta_uncorrected_T_14; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_15 = _s1_meta_uncorrected_WIRE_7[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_7_coh_state = _s1_meta_uncorrected_T_15; // @[DCache.scala:315:80] wire [19:0] s1_tag = s1_paddr[31:12]; // @[DCache.scala:298:21, :316:29] wire _s1_meta_hit_way_T = |s1_meta_uncorrected_0_coh_state; // @[Metadata.scala:50:45] wire _GEN_72 = s1_meta_uncorrected_0_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_1; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_1 = _GEN_72; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T = _GEN_72; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_2 = _s1_meta_hit_way_T & _s1_meta_hit_way_T_1; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_3 = |s1_meta_uncorrected_1_coh_state; // @[Metadata.scala:50:45] wire _GEN_73 = s1_meta_uncorrected_1_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_4; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_4 = _GEN_73; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_4; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_4 = _GEN_73; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_5 = _s1_meta_hit_way_T_3 & _s1_meta_hit_way_T_4; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_6 = |s1_meta_uncorrected_2_coh_state; // @[Metadata.scala:50:45] wire _GEN_74 = s1_meta_uncorrected_2_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_7; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_7 = _GEN_74; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_8; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_8 = _GEN_74; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_8 = _s1_meta_hit_way_T_6 & _s1_meta_hit_way_T_7; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_9 = |s1_meta_uncorrected_3_coh_state; // @[Metadata.scala:50:45] wire _GEN_75 = s1_meta_uncorrected_3_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_10; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_10 = _GEN_75; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_12; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_12 = _GEN_75; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_11 = _s1_meta_hit_way_T_9 & _s1_meta_hit_way_T_10; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_12 = |s1_meta_uncorrected_4_coh_state; // @[Metadata.scala:50:45] wire _GEN_76 = s1_meta_uncorrected_4_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_13; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_13 = _GEN_76; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_16; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_16 = _GEN_76; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_14 = _s1_meta_hit_way_T_12 & _s1_meta_hit_way_T_13; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_15 = |s1_meta_uncorrected_5_coh_state; // @[Metadata.scala:50:45] wire _GEN_77 = s1_meta_uncorrected_5_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_16; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_16 = _GEN_77; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_20; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_20 = _GEN_77; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_17 = _s1_meta_hit_way_T_15 & _s1_meta_hit_way_T_16; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_18 = |s1_meta_uncorrected_6_coh_state; // @[Metadata.scala:50:45] wire _GEN_78 = s1_meta_uncorrected_6_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_19; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_19 = _GEN_78; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_24; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_24 = _GEN_78; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_20 = _s1_meta_hit_way_T_18 & _s1_meta_hit_way_T_19; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_21 = |s1_meta_uncorrected_7_coh_state; // @[Metadata.scala:50:45] wire _GEN_79 = s1_meta_uncorrected_7_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_22; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_22 = _GEN_79; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_28; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_28 = _GEN_79; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_23 = _s1_meta_hit_way_T_21 & _s1_meta_hit_way_T_22; // @[Metadata.scala:50:45] wire [1:0] s1_meta_hit_way_lo_lo = {_s1_meta_hit_way_T_5, _s1_meta_hit_way_T_2}; // @[package.scala:45:27] wire [1:0] s1_meta_hit_way_lo_hi = {_s1_meta_hit_way_T_11, _s1_meta_hit_way_T_8}; // @[package.scala:45:27] wire [3:0] s1_meta_hit_way_lo = {s1_meta_hit_way_lo_hi, s1_meta_hit_way_lo_lo}; // @[package.scala:45:27] wire [1:0] s1_meta_hit_way_hi_lo = {_s1_meta_hit_way_T_17, _s1_meta_hit_way_T_14}; // @[package.scala:45:27] wire [1:0] s1_meta_hit_way_hi_hi = {_s1_meta_hit_way_T_23, _s1_meta_hit_way_T_20}; // @[package.scala:45:27] wire [3:0] s1_meta_hit_way_hi = {s1_meta_hit_way_hi_hi, s1_meta_hit_way_hi_lo}; // @[package.scala:45:27] wire [7:0] s1_hit_way = {s1_meta_hit_way_hi, s1_meta_hit_way_lo}; // @[package.scala:45:27] wire _s1_meta_hit_state_T_1 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_2 = _s1_meta_hit_state_T & _s1_meta_hit_state_T_1; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_3 = _s1_meta_hit_state_T_2 ? s1_meta_uncorrected_0_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_5 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_6 = _s1_meta_hit_state_T_4 & _s1_meta_hit_state_T_5; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_7 = _s1_meta_hit_state_T_6 ? s1_meta_uncorrected_1_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_9 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_10 = _s1_meta_hit_state_T_8 & _s1_meta_hit_state_T_9; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_11 = _s1_meta_hit_state_T_10 ? s1_meta_uncorrected_2_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_13 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_14 = _s1_meta_hit_state_T_12 & _s1_meta_hit_state_T_13; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_15 = _s1_meta_hit_state_T_14 ? s1_meta_uncorrected_3_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_17 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_18 = _s1_meta_hit_state_T_16 & _s1_meta_hit_state_T_17; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_19 = _s1_meta_hit_state_T_18 ? s1_meta_uncorrected_4_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_21 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_22 = _s1_meta_hit_state_T_20 & _s1_meta_hit_state_T_21; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_23 = _s1_meta_hit_state_T_22 ? s1_meta_uncorrected_5_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_25 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_26 = _s1_meta_hit_state_T_24 & _s1_meta_hit_state_T_25; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_27 = _s1_meta_hit_state_T_26 ? s1_meta_uncorrected_6_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_29 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_30 = _s1_meta_hit_state_T_28 & _s1_meta_hit_state_T_29; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_31 = _s1_meta_hit_state_T_30 ? s1_meta_uncorrected_7_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire [1:0] _s1_meta_hit_state_T_32 = _s1_meta_hit_state_T_3 | _s1_meta_hit_state_T_7; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_33 = _s1_meta_hit_state_T_32 | _s1_meta_hit_state_T_11; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_34 = _s1_meta_hit_state_T_33 | _s1_meta_hit_state_T_15; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_35 = _s1_meta_hit_state_T_34 | _s1_meta_hit_state_T_19; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_36 = _s1_meta_hit_state_T_35 | _s1_meta_hit_state_T_23; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_37 = _s1_meta_hit_state_T_36 | _s1_meta_hit_state_T_27; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_38 = _s1_meta_hit_state_T_37 | _s1_meta_hit_state_T_31; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_WIRE = _s1_meta_hit_state_T_38; // @[DCache.scala:320:{19,32}] wire [1:0] _s1_meta_hit_state_T_39; // @[DCache.scala:320:32] wire [1:0] s1_hit_state_state; // @[DCache.scala:320:32] assign _s1_meta_hit_state_T_39 = _s1_meta_hit_state_WIRE; // @[DCache.scala:320:32] assign s1_hit_state_state = _s1_meta_hit_state_T_39; // @[DCache.scala:320:32] wire [7:0] _s1_data_way_T = inWriteback ? releaseWay : s1_hit_way; // @[package.scala:45:27, :81:59] wire [8:0] s1_data_way; // @[DCache.scala:323:32] wire [7:0] _tl_d_data_encoded_T = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_22 = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_1 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_23 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_2 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_24 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_3 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_25 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_4 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_26 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_5 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_27 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_6 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_28 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_7 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_29 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_8 = nodeOut_d_bits_data[71:64]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_30 = nodeOut_d_bits_data[71:64]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_9 = nodeOut_d_bits_data[79:72]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_31 = nodeOut_d_bits_data[79:72]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_10 = nodeOut_d_bits_data[87:80]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_32 = nodeOut_d_bits_data[87:80]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_11 = nodeOut_d_bits_data[95:88]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_33 = nodeOut_d_bits_data[95:88]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_12 = nodeOut_d_bits_data[103:96]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_34 = nodeOut_d_bits_data[103:96]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_13 = nodeOut_d_bits_data[111:104]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_35 = nodeOut_d_bits_data[111:104]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_14 = nodeOut_d_bits_data[119:112]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_36 = nodeOut_d_bits_data[119:112]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_15 = nodeOut_d_bits_data[127:120]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_37 = nodeOut_d_bits_data[127:120]; // @[package.scala:211:50] wire [15:0] tl_d_data_encoded_lo_lo_lo = {_tl_d_data_encoded_T_1, _tl_d_data_encoded_T}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_lo_hi = {_tl_d_data_encoded_T_3, _tl_d_data_encoded_T_2}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo_lo = {tl_d_data_encoded_lo_lo_hi, tl_d_data_encoded_lo_lo_lo}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_lo_hi_lo = {_tl_d_data_encoded_T_5, _tl_d_data_encoded_T_4}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_hi_hi = {_tl_d_data_encoded_T_7, _tl_d_data_encoded_T_6}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo_hi = {tl_d_data_encoded_lo_hi_hi, tl_d_data_encoded_lo_hi_lo}; // @[package.scala:45:27] wire [63:0] tl_d_data_encoded_lo = {tl_d_data_encoded_lo_hi, tl_d_data_encoded_lo_lo}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_lo_lo = {_tl_d_data_encoded_T_9, _tl_d_data_encoded_T_8}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_lo_hi = {_tl_d_data_encoded_T_11, _tl_d_data_encoded_T_10}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi_lo = {tl_d_data_encoded_hi_lo_hi, tl_d_data_encoded_hi_lo_lo}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_hi_lo = {_tl_d_data_encoded_T_13, _tl_d_data_encoded_T_12}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_hi_hi = {_tl_d_data_encoded_T_15, _tl_d_data_encoded_T_14}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi_hi = {tl_d_data_encoded_hi_hi_hi, tl_d_data_encoded_hi_hi_lo}; // @[package.scala:45:27] wire [63:0] tl_d_data_encoded_hi = {tl_d_data_encoded_hi_hi, tl_d_data_encoded_hi_lo}; // @[package.scala:45:27] wire [127:0] _tl_d_data_encoded_T_16 = {tl_d_data_encoded_hi, tl_d_data_encoded_lo}; // @[package.scala:45:27] wire [127:0] _tl_d_data_encoded_T_38; // @[package.scala:45:27] assign dataArb_io_in_1_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31] assign dataArb_io_in_2_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31] assign dataArb_io_in_3_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31] wire [127:0] s1_all_data_ways_8 = tl_d_data_encoded; // @[DCache.scala:324:31, :325:33] wire [127:0] s1_all_data_ways_0; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_1; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_2; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_3; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_4; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_5; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_6; // @[DCache.scala:325:33] wire [127:0] s1_all_data_ways_7; // @[DCache.scala:325:33] wire _s1_mask_xwr_upper_T = s1_req_addr[0]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T = s1_req_addr[0]; // @[DCache.scala:196:25] wire _s1_mask_xwr_upper_T_1 = _s1_mask_xwr_upper_T; // @[AMOALU.scala:20:{22,27}] wire _s1_mask_xwr_upper_T_2 = |s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53] wire _s1_mask_xwr_upper_T_3 = _s1_mask_xwr_upper_T_2; // @[AMOALU.scala:20:{47,53}] wire s1_mask_xwr_upper = _s1_mask_xwr_upper_T_1 | _s1_mask_xwr_upper_T_3; // @[AMOALU.scala:20:{22,42,47}] wire s1_mask_xwr_lower = ~_s1_mask_xwr_lower_T; // @[AMOALU.scala:21:{22,27}] wire [1:0] _s1_mask_xwr_T = {s1_mask_xwr_upper, s1_mask_xwr_lower}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire _s1_mask_xwr_upper_T_4 = s1_req_addr[1]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T_1 = s1_req_addr[1]; // @[DCache.scala:196:25] wire [1:0] _s1_mask_xwr_upper_T_5 = _s1_mask_xwr_upper_T_4 ? _s1_mask_xwr_T : 2'h0; // @[AMOALU.scala:20:{22,27}, :22:16] wire _s1_mask_xwr_upper_T_6 = s1_mask_xwr_size[1]; // @[AMOALU.scala:11:18, :20:53] wire [1:0] _s1_mask_xwr_upper_T_7 = {2{_s1_mask_xwr_upper_T_6}}; // @[AMOALU.scala:20:{47,53}] wire [1:0] s1_mask_xwr_upper_1 = _s1_mask_xwr_upper_T_5 | _s1_mask_xwr_upper_T_7; // @[AMOALU.scala:20:{22,42,47}] wire [1:0] s1_mask_xwr_lower_1 = _s1_mask_xwr_lower_T_1 ? 2'h0 : _s1_mask_xwr_T; // @[AMOALU.scala:21:{22,27}, :22:16] wire [3:0] _s1_mask_xwr_T_1 = {s1_mask_xwr_upper_1, s1_mask_xwr_lower_1}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire _s1_mask_xwr_upper_T_8 = s1_req_addr[2]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T_2 = s1_req_addr[2]; // @[DCache.scala:196:25] wire [3:0] _s1_mask_xwr_upper_T_9 = _s1_mask_xwr_upper_T_8 ? _s1_mask_xwr_T_1 : 4'h0; // @[AMOALU.scala:20:{22,27}, :22:16] wire _s1_mask_xwr_upper_T_10 = &s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53] wire [3:0] _s1_mask_xwr_upper_T_11 = {4{_s1_mask_xwr_upper_T_10}}; // @[AMOALU.scala:20:{47,53}] wire [3:0] s1_mask_xwr_upper_2 = _s1_mask_xwr_upper_T_9 | _s1_mask_xwr_upper_T_11; // @[AMOALU.scala:20:{22,42,47}] wire [3:0] s1_mask_xwr_lower_2 = _s1_mask_xwr_lower_T_2 ? 4'h0 : _s1_mask_xwr_T_1; // @[AMOALU.scala:21:{22,27}, :22:16] wire [7:0] s1_mask_xwr = {s1_mask_xwr_upper_2, s1_mask_xwr_lower_2}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire [7:0] s1_mask = _s1_mask_T ? io_cpu_s1_data_mask_0 : s1_mask_xwr; // @[DCache.scala:101:7, :327:{20,32}] wire _s2_valid_T = ~s1_sfence; // @[DCache.scala:213:71, :331:45] wire _s2_valid_T_1 = s1_valid_masked & _s2_valid_T; // @[DCache.scala:186:34, :331:{42,45}] reg s2_valid; // @[DCache.scala:331:25] wire [1:0] _s2_valid_no_xcpt_T = {io_cpu_s2_xcpt_ae_ld_0, io_cpu_s2_xcpt_ae_st_0}; // @[DCache.scala:101:7, :332:54] wire [1:0] _s2_valid_no_xcpt_T_2 = {io_cpu_s2_xcpt_pf_ld_0, io_cpu_s2_xcpt_pf_st_0}; // @[DCache.scala:101:7, :332:54] wire [1:0] _s2_valid_no_xcpt_T_3 = {io_cpu_s2_xcpt_ma_ld_0, io_cpu_s2_xcpt_ma_st_0}; // @[DCache.scala:101:7, :332:54] wire [3:0] s2_valid_no_xcpt_lo = {2'h0, _s2_valid_no_xcpt_T}; // @[DCache.scala:332:54] wire [3:0] s2_valid_no_xcpt_hi = {_s2_valid_no_xcpt_T_3, _s2_valid_no_xcpt_T_2}; // @[DCache.scala:332:54] wire [7:0] _s2_valid_no_xcpt_T_4 = {s2_valid_no_xcpt_hi, s2_valid_no_xcpt_lo}; // @[DCache.scala:332:54] wire _s2_valid_no_xcpt_T_5 = |_s2_valid_no_xcpt_T_4; // @[DCache.scala:332:{54,61}] wire _s2_valid_no_xcpt_T_6 = ~_s2_valid_no_xcpt_T_5; // @[DCache.scala:332:{38,61}] wire s2_valid_no_xcpt = s2_valid & _s2_valid_no_xcpt_T_6; // @[DCache.scala:331:25, :332:{35,38}] reg s2_probe; // @[DCache.scala:333:25] wire _releaseInFlight_T = s1_probe | s2_probe; // @[DCache.scala:183:25, :333:25, :334:34] wire _releaseInFlight_T_1 = |release_state; // @[DCache.scala:228:30, :233:38, :334:63] wire releaseInFlight = _releaseInFlight_T | _releaseInFlight_T_1; // @[DCache.scala:334:{34,46,63}] wire _s2_not_nacked_in_s1_T = ~s1_nack; // @[DCache.scala:185:28, :187:41, :335:37] reg s2_not_nacked_in_s1; // @[DCache.scala:335:36] wire s2_valid_not_nacked_in_s1 = s2_valid & s2_not_nacked_in_s1; // @[DCache.scala:331:25, :335:36, :336:44] wire s2_valid_masked = s2_valid_no_xcpt & s2_not_nacked_in_s1; // @[DCache.scala:332:35, :335:36, :337:42] wire s2_valid_not_killed = s2_valid_masked; // @[DCache.scala:337:42, :338:45] wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :397:71] wire _s2_dont_nack_misc_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :441:43] reg [39:0] s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _put_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _putpartial_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_4 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_63 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_122 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_181 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_240 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_299 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_358 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_417 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_476 = s2_req_addr; // @[DCache.scala:339:19] reg [6:0] s2_req_tag; // @[DCache.scala:339:19] assign io_cpu_resp_bits_tag_0 = s2_req_tag; // @[DCache.scala:101:7, :339:19] reg [4:0] s2_req_cmd; // @[DCache.scala:339:19] assign io_cpu_resp_bits_cmd_0 = s2_req_cmd; // @[DCache.scala:101:7, :339:19] reg [1:0] s2_req_size; // @[DCache.scala:339:19] assign io_cpu_resp_bits_size_0 = s2_req_size; // @[DCache.scala:101:7, :339:19] wire [1:0] size = s2_req_size; // @[DCache.scala:339:19] reg s2_req_signed; // @[DCache.scala:339:19] assign io_cpu_resp_bits_signed_0 = s2_req_signed; // @[DCache.scala:101:7, :339:19] reg [1:0] s2_req_dprv; // @[DCache.scala:339:19] assign io_cpu_resp_bits_dprv_0 = s2_req_dprv; // @[DCache.scala:101:7, :339:19] reg s2_req_dv; // @[DCache.scala:339:19] assign io_cpu_resp_bits_dv_0 = s2_req_dv; // @[DCache.scala:101:7, :339:19] reg s2_req_phys; // @[DCache.scala:339:19] reg s2_req_no_resp; // @[DCache.scala:339:19] reg s2_req_no_alloc; // @[DCache.scala:339:19] reg s2_req_no_xcpt; // @[DCache.scala:339:19] reg [63:0] s2_req_data; // @[DCache.scala:339:19] reg [7:0] s2_req_mask; // @[DCache.scala:339:19] assign io_cpu_resp_bits_mask_0 = s2_req_mask; // @[DCache.scala:101:7, :339:19] wire _GEN_80 = s2_req_cmd == 5'h5; // @[DCache.scala:339:19, :340:37] wire _s2_cmd_flush_all_T; // @[DCache.scala:340:37] assign _s2_cmd_flush_all_T = _GEN_80; // @[DCache.scala:340:37] wire _s2_cmd_flush_line_T; // @[DCache.scala:341:38] assign _s2_cmd_flush_line_T = _GEN_80; // @[DCache.scala:340:37, :341:38] wire _s2_cmd_flush_all_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68] wire _s2_cmd_flush_line_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68, :341:68] wire _s2_cmd_flush_all_T_2 = ~_s2_cmd_flush_all_T_1; // @[DCache.scala:340:{56,68}] wire s2_cmd_flush_all = _s2_cmd_flush_all_T & _s2_cmd_flush_all_T_2; // @[DCache.scala:340:{37,53,56}] wire s2_cmd_flush_line = _s2_cmd_flush_line_T & _s2_cmd_flush_line_T_1; // @[DCache.scala:341:{38,54,68}] reg s2_tlb_xcpt_miss; // @[DCache.scala:342:24] reg [31:0] s2_tlb_xcpt_paddr; // @[DCache.scala:342:24] reg [39:0] s2_tlb_xcpt_gpa; // @[DCache.scala:342:24] assign io_cpu_s2_gpa_0 = s2_tlb_xcpt_gpa; // @[DCache.scala:101:7, :342:24] reg s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24] reg s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24] reg s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24] reg [1:0] s2_tlb_xcpt_size; // @[DCache.scala:342:24] reg [4:0] s2_tlb_xcpt_cmd; // @[DCache.scala:342:24] reg s2_pma_miss; // @[DCache.scala:343:19] reg [31:0] s2_pma_paddr; // @[DCache.scala:343:19] reg [39:0] s2_pma_gpa; // @[DCache.scala:343:19] reg s2_pma_pf_ld; // @[DCache.scala:343:19] reg s2_pma_pf_st; // @[DCache.scala:343:19] reg s2_pma_pf_inst; // @[DCache.scala:343:19] reg s2_pma_ae_ld; // @[DCache.scala:343:19] reg s2_pma_ae_st; // @[DCache.scala:343:19] reg s2_pma_ae_inst; // @[DCache.scala:343:19] reg s2_pma_ma_ld; // @[DCache.scala:343:19] reg s2_pma_ma_st; // @[DCache.scala:343:19] reg s2_pma_cacheable; // @[DCache.scala:343:19] reg s2_pma_must_alloc; // @[DCache.scala:343:19] reg s2_pma_prefetchable; // @[DCache.scala:343:19] reg [1:0] s2_pma_size; // @[DCache.scala:343:19] reg [4:0] s2_pma_cmd; // @[DCache.scala:343:19] reg [39:0] s2_uncached_resp_addr; // @[DCache.scala:344:34] wire _T_30 = s1_valid_not_nacked | s1_flush_valid; // @[DCache.scala:187:38, :215:27, :345:29] wire _s2_vaddr_T; // @[DCache.scala:351:62] assign _s2_vaddr_T = _T_30; // @[DCache.scala:345:29, :351:62] wire _s1_meta_clk_en_T; // @[DCache.scala:357:44] assign _s1_meta_clk_en_T = _T_30; // @[DCache.scala:345:29, :357:44] wire _s2_hit_state_T; // @[DCache.scala:386:66] assign _s2_hit_state_T = _T_30; // @[DCache.scala:345:29, :386:66] wire _s2_victim_way_T; // @[DCache.scala:431:77] assign _s2_victim_way_T = _T_30; // @[DCache.scala:345:29, :431:77] reg [39:0] s2_vaddr_r; // @[DCache.scala:351:31] wire [27:0] _s2_vaddr_T_1 = s2_vaddr_r[39:12]; // @[DCache.scala:351:{31,81}] wire [11:0] _s2_vaddr_T_2 = s2_req_addr[11:0]; // @[DCache.scala:339:19, :351:103] wire [39:0] s2_vaddr = {_s2_vaddr_T_1, _s2_vaddr_T_2}; // @[DCache.scala:351:{21,81,103}] wire _s2_read_T = s2_req_cmd == 5'h0; // @[package.scala:16:47] wire _s2_read_T_1 = s2_req_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_81 = s2_req_cmd == 5'h6; // @[package.scala:16:47] wire _s2_read_T_2; // @[package.scala:16:47] assign _s2_read_T_2 = _GEN_81; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_81; // @[package.scala:16:47] wire _s2_lr_T; // @[DCache.scala:470:70] assign _s2_lr_T = _GEN_81; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:71] assign _metaArb_io_in_3_bits_data_c_cat_T_48 = _GEN_81; // @[package.scala:16:47] wire _GEN_82 = s2_req_cmd == 5'h7; // @[package.scala:16:47] wire _s2_read_T_3; // @[package.scala:16:47] assign _s2_read_T_3 = _GEN_82; // @[package.scala:16:47] wire _s2_write_T_3; // @[Consts.scala:90:66] assign _s2_write_T_3 = _GEN_82; // @[package.scala:16:47] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _GEN_82; // @[package.scala:16:47] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _GEN_82; // @[package.scala:16:47] wire _s2_sc_T; // @[DCache.scala:471:70] assign _s2_sc_T = _GEN_82; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:66] assign _metaArb_io_in_3_bits_data_c_cat_T_3 = _GEN_82; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:66] assign _metaArb_io_in_3_bits_data_c_cat_T_26 = _GEN_82; // @[package.scala:16:47] wire _io_cpu_store_pending_T_3; // @[Consts.scala:90:66] assign _io_cpu_store_pending_T_3 = _GEN_82; // @[package.scala:16:47] wire _s2_read_T_4 = _s2_read_T | _s2_read_T_1; // @[package.scala:16:47, :81:59] wire _s2_read_T_5 = _s2_read_T_4 | _s2_read_T_2; // @[package.scala:16:47, :81:59] wire _s2_read_T_6 = _s2_read_T_5 | _s2_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_83 = s2_req_cmd == 5'h4; // @[package.scala:16:47] wire _s2_read_T_7; // @[package.scala:16:47] assign _s2_read_T_7 = _GEN_83; // @[package.scala:16:47] wire _s2_write_T_5; // @[package.scala:16:47] assign _s2_write_T_5 = _GEN_83; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _GEN_83; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _GEN_83; // @[package.scala:16:47] wire _atomics_T; // @[DCache.scala:587:81] assign _atomics_T = _GEN_83; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_5; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_5 = _GEN_83; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_28; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_28 = _GEN_83; // @[package.scala:16:47] wire _io_cpu_store_pending_T_5; // @[package.scala:16:47] assign _io_cpu_store_pending_T_5 = _GEN_83; // @[package.scala:16:47] wire _GEN_84 = s2_req_cmd == 5'h9; // @[package.scala:16:47] wire _s2_read_T_8; // @[package.scala:16:47] assign _s2_read_T_8 = _GEN_84; // @[package.scala:16:47] wire _s2_write_T_6; // @[package.scala:16:47] assign _s2_write_T_6 = _GEN_84; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _GEN_84; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _GEN_84; // @[package.scala:16:47] wire _atomics_T_2; // @[DCache.scala:587:81] assign _atomics_T_2 = _GEN_84; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_6 = _GEN_84; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_29 = _GEN_84; // @[package.scala:16:47] wire _io_cpu_store_pending_T_6; // @[package.scala:16:47] assign _io_cpu_store_pending_T_6 = _GEN_84; // @[package.scala:16:47] wire _GEN_85 = s2_req_cmd == 5'hA; // @[package.scala:16:47] wire _s2_read_T_9; // @[package.scala:16:47] assign _s2_read_T_9 = _GEN_85; // @[package.scala:16:47] wire _s2_write_T_7; // @[package.scala:16:47] assign _s2_write_T_7 = _GEN_85; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _GEN_85; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _GEN_85; // @[package.scala:16:47] wire _atomics_T_4; // @[DCache.scala:587:81] assign _atomics_T_4 = _GEN_85; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_7 = _GEN_85; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_30 = _GEN_85; // @[package.scala:16:47] wire _io_cpu_store_pending_T_7; // @[package.scala:16:47] assign _io_cpu_store_pending_T_7 = _GEN_85; // @[package.scala:16:47] wire _GEN_86 = s2_req_cmd == 5'hB; // @[package.scala:16:47] wire _s2_read_T_10; // @[package.scala:16:47] assign _s2_read_T_10 = _GEN_86; // @[package.scala:16:47] wire _s2_write_T_8; // @[package.scala:16:47] assign _s2_write_T_8 = _GEN_86; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _GEN_86; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _GEN_86; // @[package.scala:16:47] wire _atomics_T_6; // @[DCache.scala:587:81] assign _atomics_T_6 = _GEN_86; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_8 = _GEN_86; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_31 = _GEN_86; // @[package.scala:16:47] wire _io_cpu_store_pending_T_8; // @[package.scala:16:47] assign _io_cpu_store_pending_T_8 = _GEN_86; // @[package.scala:16:47] wire _s2_read_T_11 = _s2_read_T_7 | _s2_read_T_8; // @[package.scala:16:47, :81:59] wire _s2_read_T_12 = _s2_read_T_11 | _s2_read_T_9; // @[package.scala:16:47, :81:59] wire _s2_read_T_13 = _s2_read_T_12 | _s2_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_87 = s2_req_cmd == 5'h8; // @[package.scala:16:47] wire _s2_read_T_14; // @[package.scala:16:47] assign _s2_read_T_14 = _GEN_87; // @[package.scala:16:47] wire _s2_write_T_12; // @[package.scala:16:47] assign _s2_write_T_12 = _GEN_87; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _GEN_87; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _GEN_87; // @[package.scala:16:47] wire _atomics_T_8; // @[DCache.scala:587:81] assign _atomics_T_8 = _GEN_87; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_12; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_12 = _GEN_87; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_35; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_35 = _GEN_87; // @[package.scala:16:47] wire _io_cpu_store_pending_T_12; // @[package.scala:16:47] assign _io_cpu_store_pending_T_12 = _GEN_87; // @[package.scala:16:47] wire _GEN_88 = s2_req_cmd == 5'hC; // @[package.scala:16:47] wire _s2_read_T_15; // @[package.scala:16:47] assign _s2_read_T_15 = _GEN_88; // @[package.scala:16:47] wire _s2_write_T_13; // @[package.scala:16:47] assign _s2_write_T_13 = _GEN_88; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _GEN_88; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _GEN_88; // @[package.scala:16:47] wire _atomics_T_10; // @[DCache.scala:587:81] assign _atomics_T_10 = _GEN_88; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_13 = _GEN_88; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_36 = _GEN_88; // @[package.scala:16:47] wire _io_cpu_store_pending_T_13; // @[package.scala:16:47] assign _io_cpu_store_pending_T_13 = _GEN_88; // @[package.scala:16:47] wire _GEN_89 = s2_req_cmd == 5'hD; // @[package.scala:16:47] wire _s2_read_T_16; // @[package.scala:16:47] assign _s2_read_T_16 = _GEN_89; // @[package.scala:16:47] wire _s2_write_T_14; // @[package.scala:16:47] assign _s2_write_T_14 = _GEN_89; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _GEN_89; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _GEN_89; // @[package.scala:16:47] wire _atomics_T_12; // @[DCache.scala:587:81] assign _atomics_T_12 = _GEN_89; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_14 = _GEN_89; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_37 = _GEN_89; // @[package.scala:16:47] wire _io_cpu_store_pending_T_14; // @[package.scala:16:47] assign _io_cpu_store_pending_T_14 = _GEN_89; // @[package.scala:16:47] wire _GEN_90 = s2_req_cmd == 5'hE; // @[package.scala:16:47] wire _s2_read_T_17; // @[package.scala:16:47] assign _s2_read_T_17 = _GEN_90; // @[package.scala:16:47] wire _s2_write_T_15; // @[package.scala:16:47] assign _s2_write_T_15 = _GEN_90; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _GEN_90; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _GEN_90; // @[package.scala:16:47] wire _atomics_T_14; // @[DCache.scala:587:81] assign _atomics_T_14 = _GEN_90; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_15 = _GEN_90; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_38 = _GEN_90; // @[package.scala:16:47] wire _io_cpu_store_pending_T_15; // @[package.scala:16:47] assign _io_cpu_store_pending_T_15 = _GEN_90; // @[package.scala:16:47] wire _GEN_91 = s2_req_cmd == 5'hF; // @[package.scala:16:47] wire _s2_read_T_18; // @[package.scala:16:47] assign _s2_read_T_18 = _GEN_91; // @[package.scala:16:47] wire _s2_write_T_16; // @[package.scala:16:47] assign _s2_write_T_16 = _GEN_91; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _GEN_91; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _GEN_91; // @[package.scala:16:47] wire _atomics_T_16; // @[DCache.scala:587:81] assign _atomics_T_16 = _GEN_91; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_16 = _GEN_91; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_39 = _GEN_91; // @[package.scala:16:47] wire _io_cpu_store_pending_T_16; // @[package.scala:16:47] assign _io_cpu_store_pending_T_16 = _GEN_91; // @[package.scala:16:47] wire _s2_read_T_19 = _s2_read_T_14 | _s2_read_T_15; // @[package.scala:16:47, :81:59] wire _s2_read_T_20 = _s2_read_T_19 | _s2_read_T_16; // @[package.scala:16:47, :81:59] wire _s2_read_T_21 = _s2_read_T_20 | _s2_read_T_17; // @[package.scala:16:47, :81:59] wire _s2_read_T_22 = _s2_read_T_21 | _s2_read_T_18; // @[package.scala:16:47, :81:59] wire _s2_read_T_23 = _s2_read_T_13 | _s2_read_T_22; // @[package.scala:81:59] assign s2_read = _s2_read_T_6 | _s2_read_T_23; // @[package.scala:81:59] assign io_cpu_resp_bits_has_data_0 = s2_read; // @[DCache.scala:101:7] wire _GEN_92 = s2_req_cmd == 5'h1; // @[DCache.scala:339:19] wire _s2_write_T; // @[Consts.scala:90:32] assign _s2_write_T = _GEN_92; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _GEN_92; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _GEN_92; // @[Consts.scala:90:32] wire _metaArb_io_in_3_bits_data_c_cat_T; // @[Consts.scala:90:32] assign _metaArb_io_in_3_bits_data_c_cat_T = _GEN_92; // @[Consts.scala:90:32] wire _metaArb_io_in_3_bits_data_c_cat_T_23; // @[Consts.scala:90:32] assign _metaArb_io_in_3_bits_data_c_cat_T_23 = _GEN_92; // @[Consts.scala:90:32] wire _io_cpu_store_pending_T; // @[Consts.scala:90:32] assign _io_cpu_store_pending_T = _GEN_92; // @[Consts.scala:90:32] wire _GEN_93 = s2_req_cmd == 5'h11; // @[DCache.scala:339:19] wire _s2_write_T_1; // @[Consts.scala:90:49] assign _s2_write_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _GEN_93; // @[Consts.scala:90:49] wire _tl_out_a_bits_T_4; // @[DCache.scala:610:20] assign _tl_out_a_bits_T_4 = _GEN_93; // @[DCache.scala:610:20] wire _uncachedReqs_0_cmd_T; // @[DCache.scala:637:49] assign _uncachedReqs_0_cmd_T = _GEN_93; // @[DCache.scala:637:49] wire _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:49] assign _metaArb_io_in_3_bits_data_c_cat_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:49] assign _metaArb_io_in_3_bits_data_c_cat_T_24 = _GEN_93; // @[Consts.scala:90:49] wire _io_cpu_store_pending_T_1; // @[Consts.scala:90:49] assign _io_cpu_store_pending_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _s2_write_T_2 = _s2_write_T | _s2_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _s2_write_T_4 = _s2_write_T_2 | _s2_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _s2_write_T_9 = _s2_write_T_5 | _s2_write_T_6; // @[package.scala:16:47, :81:59] wire _s2_write_T_10 = _s2_write_T_9 | _s2_write_T_7; // @[package.scala:16:47, :81:59] wire _s2_write_T_11 = _s2_write_T_10 | _s2_write_T_8; // @[package.scala:16:47, :81:59] wire _s2_write_T_17 = _s2_write_T_12 | _s2_write_T_13; // @[package.scala:16:47, :81:59] wire _s2_write_T_18 = _s2_write_T_17 | _s2_write_T_14; // @[package.scala:16:47, :81:59] wire _s2_write_T_19 = _s2_write_T_18 | _s2_write_T_15; // @[package.scala:16:47, :81:59] wire _s2_write_T_20 = _s2_write_T_19 | _s2_write_T_16; // @[package.scala:16:47, :81:59] wire _s2_write_T_21 = _s2_write_T_11 | _s2_write_T_20; // @[package.scala:81:59] wire s2_write = _s2_write_T_4 | _s2_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire s2_readwrite = s2_read | s2_write; // @[DCache.scala:354:30] reg s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43] wire s2_flush_valid = s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43, :363:51] wire s1_meta_clk_en = _s1_meta_clk_en_T | s1_probe; // @[DCache.scala:183:25, :357:{44,62}] reg [21:0] s2_meta_corrected_r; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE = s2_meta_corrected_r; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_1; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_0_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_0_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T = _s2_meta_corrected_WIRE[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_0_tag = _s2_meta_corrected_T; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_1 = _s2_meta_corrected_WIRE[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_0_coh_state = _s2_meta_corrected_T_1; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_1; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_1 = s2_meta_corrected_r_1; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_3; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_2; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_1_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_1_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_2 = _s2_meta_corrected_WIRE_1[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_1_tag = _s2_meta_corrected_T_2; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_3 = _s2_meta_corrected_WIRE_1[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_1_coh_state = _s2_meta_corrected_T_3; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_2; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_2 = s2_meta_corrected_r_2; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_5; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_4; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_2_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_2_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_4 = _s2_meta_corrected_WIRE_2[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_2_tag = _s2_meta_corrected_T_4; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_5 = _s2_meta_corrected_WIRE_2[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_2_coh_state = _s2_meta_corrected_T_5; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_3; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_3 = s2_meta_corrected_r_3; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_7; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_6; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_3_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_3_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_6 = _s2_meta_corrected_WIRE_3[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_3_tag = _s2_meta_corrected_T_6; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_7 = _s2_meta_corrected_WIRE_3[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_3_coh_state = _s2_meta_corrected_T_7; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_4; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_4 = s2_meta_corrected_r_4; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_9; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_8; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_4_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_4_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_8 = _s2_meta_corrected_WIRE_4[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_4_tag = _s2_meta_corrected_T_8; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_9 = _s2_meta_corrected_WIRE_4[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_4_coh_state = _s2_meta_corrected_T_9; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_5; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_5 = s2_meta_corrected_r_5; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_11; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_10; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_5_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_5_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_10 = _s2_meta_corrected_WIRE_5[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_5_tag = _s2_meta_corrected_T_10; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_11 = _s2_meta_corrected_WIRE_5[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_5_coh_state = _s2_meta_corrected_T_11; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_6; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_6 = s2_meta_corrected_r_6; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_13; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_12; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_6_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_6_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_12 = _s2_meta_corrected_WIRE_6[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_6_tag = _s2_meta_corrected_T_12; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_13 = _s2_meta_corrected_WIRE_6[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_6_coh_state = _s2_meta_corrected_T_13; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_7; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_7 = s2_meta_corrected_r_7; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_15; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_14; // @[DCache.scala:361:99] wire [1:0] _s2_first_meta_corrected_T_8_coh_state = s2_meta_corrected_7_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_8_tag = s2_meta_corrected_7_tag; // @[Mux.scala:50:70] assign _s2_meta_corrected_T_14 = _s2_meta_corrected_WIRE_7[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_7_tag = _s2_meta_corrected_T_14; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_15 = _s2_meta_corrected_WIRE_7[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_7_coh_state = _s2_meta_corrected_T_15; // @[DCache.scala:361:99] wire _s2_data_en_T = s1_valid | inWriteback; // @[package.scala:81:59] wire s2_data_en = _s2_data_en_T | io_cpu_replay_next_0; // @[DCache.scala:101:7, :366:{23,38}] wire [1:0] _s2_data_word_en_T_1 = s1_did_read ? s1_read_mask : 2'h0; // @[DCache.scala:259:30, :260:31, :367:63] wire [1:0] s2_data_word_en = inWriteback ? 2'h3 : _s2_data_word_en_T_1; // @[package.scala:81:59] wire [63:0] s2_data_s1_way_words_0_0 = s1_all_data_ways_0[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_0_1 = s1_all_data_ways_0[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_1_0 = s1_all_data_ways_1[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_1_1 = s1_all_data_ways_1[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_2_0 = s1_all_data_ways_2[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_2_1 = s1_all_data_ways_2[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_3_0 = s1_all_data_ways_3[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_3_1 = s1_all_data_ways_3[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_4_0 = s1_all_data_ways_4[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_4_1 = s1_all_data_ways_4[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_5_0 = s1_all_data_ways_5[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_5_1 = s1_all_data_ways_5[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_6_0 = s1_all_data_ways_6[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_6_1 = s1_all_data_ways_6[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_7_0 = s1_all_data_ways_7[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_7_1 = s1_all_data_ways_7[127:64]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_8_0 = s1_all_data_ways_8[63:0]; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_8_1 = s1_all_data_ways_8[127:64]; // @[package.scala:211:50] wire _s2_data_s1_word_en_T = ~io_cpu_replay_next_0; // @[DCache.scala:101:7, :377:28] wire _s2_data_s1_word_en_T_1 = uncachedResp_addr[3]; // @[package.scala:163:13] wire s1_uncached_data_word_word_idx = uncachedResp_addr[3]; // @[package.scala:163:13] wire s2_data_s1_word_en_shiftAmount = _s2_data_s1_word_en_T_1; // @[OneHot.scala:64:49] wire [1:0] _s2_data_s1_word_en_T_2 = 2'h1 << s2_data_s1_word_en_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _s2_data_s1_word_en_T_3 = _s2_data_s1_word_en_T_2; // @[OneHot.scala:65:{12,27}] wire [1:0] s2_data_s1_word_en = _s2_data_s1_word_en_T ? s2_data_word_en : _s2_data_s1_word_en_T_3; // @[OneHot.scala:65:27] wire _s2_data_T = s2_data_s1_word_en[0]; // @[DCache.scala:377:27, :379:39] wire [8:0] _s2_data_T_1 = _s2_data_T ? s1_data_way : 9'h0; // @[DCache.scala:323:32, :379:{28,39}] wire _s2_data_T_2 = _s2_data_T_1[0]; // @[Mux.scala:32:36] wire _s2_data_T_3 = _s2_data_T_1[1]; // @[Mux.scala:32:36] wire _s2_data_T_4 = _s2_data_T_1[2]; // @[Mux.scala:32:36] wire _s2_data_T_5 = _s2_data_T_1[3]; // @[Mux.scala:32:36] wire _s2_data_T_6 = _s2_data_T_1[4]; // @[Mux.scala:32:36] wire _s2_data_T_7 = _s2_data_T_1[5]; // @[Mux.scala:32:36] wire _s2_data_T_8 = _s2_data_T_1[6]; // @[Mux.scala:32:36] wire _s2_data_T_9 = _s2_data_T_1[7]; // @[Mux.scala:32:36] wire _s2_data_T_10 = _s2_data_T_1[8]; // @[Mux.scala:32:36] wire [63:0] _s2_data_T_11 = _s2_data_T_2 ? s2_data_s1_way_words_0_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_12 = _s2_data_T_3 ? s2_data_s1_way_words_1_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_13 = _s2_data_T_4 ? s2_data_s1_way_words_2_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_14 = _s2_data_T_5 ? s2_data_s1_way_words_3_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_15 = _s2_data_T_6 ? s2_data_s1_way_words_4_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_16 = _s2_data_T_7 ? s2_data_s1_way_words_5_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_17 = _s2_data_T_8 ? s2_data_s1_way_words_6_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_18 = _s2_data_T_9 ? s2_data_s1_way_words_7_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_19 = _s2_data_T_10 ? s2_data_s1_way_words_8_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_20 = _s2_data_T_11 | _s2_data_T_12; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_21 = _s2_data_T_20 | _s2_data_T_13; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_22 = _s2_data_T_21 | _s2_data_T_14; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_23 = _s2_data_T_22 | _s2_data_T_15; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_24 = _s2_data_T_23 | _s2_data_T_16; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_25 = _s2_data_T_24 | _s2_data_T_17; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_26 = _s2_data_T_25 | _s2_data_T_18; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_27 = _s2_data_T_26 | _s2_data_T_19; // @[Mux.scala:30:73] wire [63:0] _s2_data_WIRE = _s2_data_T_27; // @[Mux.scala:30:73] reg [63:0] s2_data_r; // @[DCache.scala:379:18] wire _s2_data_T_28 = s2_data_s1_word_en[1]; // @[DCache.scala:377:27, :379:39] wire [8:0] _s2_data_T_29 = _s2_data_T_28 ? s1_data_way : 9'h0; // @[DCache.scala:323:32, :379:{28,39}] wire _s2_data_T_30 = _s2_data_T_29[0]; // @[Mux.scala:32:36] wire _s2_data_T_31 = _s2_data_T_29[1]; // @[Mux.scala:32:36] wire _s2_data_T_32 = _s2_data_T_29[2]; // @[Mux.scala:32:36] wire _s2_data_T_33 = _s2_data_T_29[3]; // @[Mux.scala:32:36] wire _s2_data_T_34 = _s2_data_T_29[4]; // @[Mux.scala:32:36] wire _s2_data_T_35 = _s2_data_T_29[5]; // @[Mux.scala:32:36] wire _s2_data_T_36 = _s2_data_T_29[6]; // @[Mux.scala:32:36] wire _s2_data_T_37 = _s2_data_T_29[7]; // @[Mux.scala:32:36] wire _s2_data_T_38 = _s2_data_T_29[8]; // @[Mux.scala:32:36] wire [63:0] _s2_data_T_39 = _s2_data_T_30 ? s2_data_s1_way_words_0_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_40 = _s2_data_T_31 ? s2_data_s1_way_words_1_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_41 = _s2_data_T_32 ? s2_data_s1_way_words_2_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_42 = _s2_data_T_33 ? s2_data_s1_way_words_3_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_43 = _s2_data_T_34 ? s2_data_s1_way_words_4_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_44 = _s2_data_T_35 ? s2_data_s1_way_words_5_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_45 = _s2_data_T_36 ? s2_data_s1_way_words_6_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_46 = _s2_data_T_37 ? s2_data_s1_way_words_7_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_47 = _s2_data_T_38 ? s2_data_s1_way_words_8_1 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_48 = _s2_data_T_39 | _s2_data_T_40; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_49 = _s2_data_T_48 | _s2_data_T_41; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_50 = _s2_data_T_49 | _s2_data_T_42; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_51 = _s2_data_T_50 | _s2_data_T_43; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_52 = _s2_data_T_51 | _s2_data_T_44; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_53 = _s2_data_T_52 | _s2_data_T_45; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_54 = _s2_data_T_53 | _s2_data_T_46; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_55 = _s2_data_T_54 | _s2_data_T_47; // @[Mux.scala:30:73] wire [63:0] _s2_data_WIRE_1 = _s2_data_T_55; // @[Mux.scala:30:73] reg [63:0] s2_data_r_1; // @[DCache.scala:379:18] wire [127:0] s2_data = {s2_data_r_1, s2_data_r}; // @[package.scala:45:27] reg [7:0] s2_probe_way; // @[DCache.scala:383:31] reg [1:0] s2_probe_state_state; // @[DCache.scala:384:33] reg [7:0] s2_hit_way; // @[DCache.scala:385:29] reg [1:0] s2_hit_state_state; // @[DCache.scala:386:31] wire s2_hit_valid = |s2_hit_state_state; // @[Metadata.scala:50:45] wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_94 = s2_req_cmd == 5'h3; // @[DCache.scala:339:19] wire _r_c_cat_T_46; // @[Consts.scala:91:54] assign _r_c_cat_T_46 = _GEN_94; // @[Consts.scala:91:54] wire _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:91:54] assign _metaArb_io_in_3_bits_data_c_cat_T_46 = _GEN_94; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T = {r_c, s2_hit_state_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_25 = _r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_27 = {1'h0, _r_T_25}; // @[Misc.scala:35:36, :49:20] wire _r_T_28 = _r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_30 = _r_T_28 ? 2'h2 : _r_T_27; // @[Misc.scala:35:36, :49:20] wire _r_T_31 = _r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_33 = _r_T_31 ? 2'h1 : _r_T_30; // @[Misc.scala:35:36, :49:20] wire _r_T_34 = _r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_36 = _r_T_34 ? 2'h2 : _r_T_33; // @[Misc.scala:35:36, :49:20] wire _r_T_37 = _r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_39 = _r_T_37 ? 2'h0 : _r_T_36; // @[Misc.scala:35:36, :49:20] wire _r_T_40 = _r_T == 4'hE; // @[Misc.scala:49:20] wire _r_T_41 = _r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_42 = _r_T_40 ? 2'h3 : _r_T_39; // @[Misc.scala:35:36, :49:20] wire _r_T_43 = &_r_T; // @[Misc.scala:49:20] wire _r_T_44 = _r_T_43 | _r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_45 = _r_T_43 ? 2'h3 : _r_T_42; // @[Misc.scala:35:36, :49:20] wire _r_T_46 = _r_T == 4'h6; // @[Misc.scala:49:20] wire _r_T_47 = _r_T_46 | _r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_48 = _r_T_46 ? 2'h2 : _r_T_45; // @[Misc.scala:35:36, :49:20] wire _r_T_49 = _r_T == 4'h7; // @[Misc.scala:49:20] wire _r_T_50 = _r_T_49 | _r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_51 = _r_T_49 ? 2'h3 : _r_T_48; // @[Misc.scala:35:36, :49:20] wire _r_T_52 = _r_T == 4'h1; // @[Misc.scala:49:20] wire _r_T_53 = _r_T_52 | _r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_54 = _r_T_52 ? 2'h1 : _r_T_51; // @[Misc.scala:35:36, :49:20] wire _r_T_55 = _r_T == 4'h2; // @[Misc.scala:49:20] wire _r_T_56 = _r_T_55 | _r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_57 = _r_T_55 ? 2'h2 : _r_T_54; // @[Misc.scala:35:36, :49:20] wire _r_T_58 = _r_T == 4'h3; // @[Misc.scala:49:20] wire s2_hit = _r_T_58 | _r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] s2_grow_param = _r_T_58 ? 2'h3 : _r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] s2_new_hit_state_state = s2_grow_param; // @[Misc.scala:35:36] wire [1:0] metaArb_io_in_2_bits_data_meta_coh_state = s2_new_hit_state_state; // @[Metadata.scala:160:20] wire s2_word_idx = s2_req_addr[3]; // @[package.scala:163:13] wire _a_mask_T = s2_req_addr[3]; // @[package.scala:163:13] wire get_a_mask_sub_sub_sub_bit = s2_req_addr[3]; // @[package.scala:163:13] wire put_a_mask_sub_sub_sub_bit = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_1 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_2 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_3 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_4 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_5 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_6 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_7 = s2_req_addr[3]; // @[package.scala:163:13] wire atomics_a_mask_sub_sub_sub_bit_8 = s2_req_addr[3]; // @[package.scala:163:13] wire [15:0] s2_data_corrected_lo_lo_lo = s2_data[15:0]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_lo_lo = s2_data[15:0]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_lo_lo_hi = s2_data[31:16]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_lo_hi = s2_data[31:16]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_lo_lo = {s2_data_corrected_lo_lo_hi, s2_data_corrected_lo_lo_lo}; // @[package.scala:45:27] wire [15:0] s2_data_corrected_lo_hi_lo = s2_data[47:32]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_hi_lo = s2_data[47:32]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_lo_hi_hi = s2_data[63:48]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_hi_hi = s2_data[63:48]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_lo_hi = {s2_data_corrected_lo_hi_hi, s2_data_corrected_lo_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_corrected_lo = {s2_data_corrected_lo_hi, s2_data_corrected_lo_lo}; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_lo_lo = s2_data[79:64]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_lo_lo = s2_data[79:64]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_lo_hi = s2_data[95:80]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_lo_hi = s2_data[95:80]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_hi_lo = {s2_data_corrected_hi_lo_hi, s2_data_corrected_hi_lo_lo}; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_hi_lo = s2_data[111:96]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_hi_lo = s2_data[111:96]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_hi_hi = s2_data[127:112]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_hi_hi = s2_data[127:112]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_hi_hi = {s2_data_corrected_hi_hi_hi, s2_data_corrected_hi_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_corrected_hi = {s2_data_corrected_hi_hi, s2_data_corrected_hi_lo}; // @[package.scala:45:27] assign s2_data_corrected = {s2_data_corrected_hi, s2_data_corrected_lo}; // @[package.scala:45:27] assign nodeOut_c_bits_data = s2_data_corrected; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_lo_lo = {s2_data_uncorrected_lo_lo_hi, s2_data_uncorrected_lo_lo_lo}; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_lo_hi = {s2_data_uncorrected_lo_hi_hi, s2_data_uncorrected_lo_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_uncorrected_lo = {s2_data_uncorrected_lo_hi, s2_data_uncorrected_lo_lo}; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_hi_lo = {s2_data_uncorrected_hi_lo_hi, s2_data_uncorrected_hi_lo_lo}; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_hi_hi = {s2_data_uncorrected_hi_hi_hi, s2_data_uncorrected_hi_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_uncorrected_hi = {s2_data_uncorrected_hi_hi, s2_data_uncorrected_hi_lo}; // @[package.scala:45:27] wire [127:0] s2_data_uncorrected = {s2_data_uncorrected_hi, s2_data_uncorrected_lo}; // @[package.scala:45:27] wire s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 & s2_hit; // @[Misc.scala:35:9] wire _s2_valid_hit_pre_data_ecc_and_waw_T = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_readwrite; // @[DCache.scala:354:30, :397:89, :418:89] wire s2_valid_hit_pre_data_ecc_and_waw = _s2_valid_hit_pre_data_ecc_and_waw_T; // @[DCache.scala:418:{89,105}] wire s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw; // @[DCache.scala:418:105, :420:69] wire s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_cmd_flush_line; // @[DCache.scala:341:54, :397:89, :419:75] wire _s2_victim_tag_T = s2_valid_flush_line; // @[DCache.scala:419:75, :433:47] wire s2_valid_hit = s2_valid_hit_pre_data_ecc; // @[DCache.scala:420:69, :422:48] wire _s2_valid_miss_T = s2_valid_masked & s2_readwrite; // @[DCache.scala:337:42, :354:30, :423:39] wire _s2_valid_miss_T_2 = _s2_valid_miss_T; // @[DCache.scala:423:{39,55}] wire _s2_valid_miss_T_3 = ~s2_hit; // @[Misc.scala:35:9] wire s2_valid_miss = _s2_valid_miss_T_2 & _s2_valid_miss_T_3; // @[DCache.scala:423:{55,73,76}] wire _s2_uncached_T = ~s2_pma_cacheable; // @[DCache.scala:343:19, :424:21] wire _s2_uncached_T_1 = ~s2_pma_must_alloc; // @[DCache.scala:343:19, :424:61] wire _s2_uncached_T_2 = s2_req_no_alloc & _s2_uncached_T_1; // @[DCache.scala:339:19, :424:{58,61}] wire _s2_uncached_T_3 = ~s2_hit_valid; // @[Metadata.scala:50:45] wire _s2_uncached_T_4 = _s2_uncached_T_2 & _s2_uncached_T_3; // @[DCache.scala:424:{58,80,83}] wire s2_uncached = _s2_uncached_T | _s2_uncached_T_4; // @[DCache.scala:424:{21,39,80}] wire _s2_valid_cached_miss_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47] wire _s2_valid_cached_miss_T_1 = s2_valid_miss & _s2_valid_cached_miss_T; // @[DCache.scala:423:73, :425:{44,47}] wire _s2_valid_cached_miss_T_3 = ~_s2_valid_cached_miss_T_2; // @[DCache.scala:425:{63,88}] wire s2_valid_cached_miss = _s2_valid_cached_miss_T_1 & _s2_valid_cached_miss_T_3; // @[DCache.scala:425:{44,60,63}] wire _s2_want_victimize_T = s2_valid_cached_miss | s2_valid_flush_line; // @[DCache.scala:419:75, :425:60, :427:77] wire _s2_want_victimize_T_1 = _s2_want_victimize_T; // @[DCache.scala:427:{77,100}] wire _s2_want_victimize_T_2 = _s2_want_victimize_T_1 | s2_flush_valid; // @[DCache.scala:363:51, :427:{100,123}] wire s2_want_victimize = _s2_want_victimize_T_2; // @[DCache.scala:427:{52,123}] wire s2_victimize = s2_want_victimize; // @[DCache.scala:427:52, :429:40] wire _s2_cannot_victimize_T = ~s2_flush_valid; // @[DCache.scala:363:51, :428:29] wire _s2_valid_uncached_pending_T = s2_valid_miss & s2_uncached; // @[DCache.scala:423:73, :424:39, :430:49] wire _s2_valid_uncached_pending_T_2 = ~_s2_valid_uncached_pending_T_1; // @[DCache.scala:430:{67,92}] wire s2_valid_uncached_pending = _s2_valid_uncached_pending_T & _s2_valid_uncached_pending_T_2; // @[DCache.scala:430:{49,64,67}] reg [2:0] s2_victim_way_r; // @[DCache.scala:431:41] wire [7:0] s2_victim_way = 8'h1 << s2_victim_way_r; // @[OneHot.scala:58:35] assign s2_victim_or_hit_way = s2_hit_valid ? s2_hit_way : s2_victim_way; // @[OneHot.scala:58:35] assign metaArb_io_in_2_bits_way_en = s2_victim_or_hit_way; // @[DCache.scala:135:28, :432:33] wire [19:0] _s2_victim_tag_T_1 = s2_req_addr[31:12]; // @[DCache.scala:339:19, :433:82] wire _s2_victim_tag_T_2 = s2_victim_way[0]; // @[OneHot.scala:58:35] wire _s2_victim_state_T = s2_victim_way[0]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_3 = s2_victim_way[1]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_1 = s2_victim_way[1]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_4 = s2_victim_way[2]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_2 = s2_victim_way[2]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_5 = s2_victim_way[3]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_3 = s2_victim_way[3]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_6 = s2_victim_way[4]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_4 = s2_victim_way[4]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_7 = s2_victim_way[5]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_5 = s2_victim_way[5]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_8 = s2_victim_way[6]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_6 = s2_victim_way[6]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_9 = s2_victim_way[7]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_7 = s2_victim_way[7]; // @[OneHot.scala:58:35] wire [1:0] _s2_victim_tag_WIRE_2_state; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_WIRE_1; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_10 = _s2_victim_tag_T_2 ? s2_meta_corrected_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_11 = _s2_victim_tag_T_3 ? s2_meta_corrected_1_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_12 = _s2_victim_tag_T_4 ? s2_meta_corrected_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_13 = _s2_victim_tag_T_5 ? s2_meta_corrected_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_14 = _s2_victim_tag_T_6 ? s2_meta_corrected_4_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_15 = _s2_victim_tag_T_7 ? s2_meta_corrected_5_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_16 = _s2_victim_tag_T_8 ? s2_meta_corrected_6_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_17 = _s2_victim_tag_T_9 ? s2_meta_corrected_7_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_18 = _s2_victim_tag_T_10 | _s2_victim_tag_T_11; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_19 = _s2_victim_tag_T_18 | _s2_victim_tag_T_12; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_20 = _s2_victim_tag_T_19 | _s2_victim_tag_T_13; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_21 = _s2_victim_tag_T_20 | _s2_victim_tag_T_14; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_22 = _s2_victim_tag_T_21 | _s2_victim_tag_T_15; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_23 = _s2_victim_tag_T_22 | _s2_victim_tag_T_16; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_24 = _s2_victim_tag_T_23 | _s2_victim_tag_T_17; // @[Mux.scala:30:73] assign _s2_victim_tag_WIRE_1 = _s2_victim_tag_T_24; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_WIRE_tag = _s2_victim_tag_WIRE_1; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_WIRE_coh_state = _s2_victim_tag_WIRE_2_state; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_25 = _s2_victim_tag_T_2 ? s2_meta_corrected_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_26 = _s2_victim_tag_T_3 ? s2_meta_corrected_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_27 = _s2_victim_tag_T_4 ? s2_meta_corrected_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_28 = _s2_victim_tag_T_5 ? s2_meta_corrected_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_29 = _s2_victim_tag_T_6 ? s2_meta_corrected_4_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_30 = _s2_victim_tag_T_7 ? s2_meta_corrected_5_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_31 = _s2_victim_tag_T_8 ? s2_meta_corrected_6_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_32 = _s2_victim_tag_T_9 ? s2_meta_corrected_7_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_33 = _s2_victim_tag_T_25 | _s2_victim_tag_T_26; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_34 = _s2_victim_tag_T_33 | _s2_victim_tag_T_27; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_35 = _s2_victim_tag_T_34 | _s2_victim_tag_T_28; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_36 = _s2_victim_tag_T_35 | _s2_victim_tag_T_29; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_37 = _s2_victim_tag_T_36 | _s2_victim_tag_T_30; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_38 = _s2_victim_tag_T_37 | _s2_victim_tag_T_31; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_39 = _s2_victim_tag_T_38 | _s2_victim_tag_T_32; // @[Mux.scala:30:73] assign _s2_victim_tag_WIRE_3 = _s2_victim_tag_T_39; // @[Mux.scala:30:73] assign _s2_victim_tag_WIRE_2_state = _s2_victim_tag_WIRE_3; // @[Mux.scala:30:73] wire [19:0] s2_victim_tag = _s2_victim_tag_T ? _s2_victim_tag_T_1 : _s2_victim_tag_WIRE_tag; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_WIRE_2_state; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_WIRE_1; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_8 = _s2_victim_state_T ? s2_meta_corrected_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_9 = _s2_victim_state_T_1 ? s2_meta_corrected_1_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_10 = _s2_victim_state_T_2 ? s2_meta_corrected_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_11 = _s2_victim_state_T_3 ? s2_meta_corrected_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_12 = _s2_victim_state_T_4 ? s2_meta_corrected_4_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_13 = _s2_victim_state_T_5 ? s2_meta_corrected_5_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_14 = _s2_victim_state_T_6 ? s2_meta_corrected_6_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_15 = _s2_victim_state_T_7 ? s2_meta_corrected_7_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_16 = _s2_victim_state_T_8 | _s2_victim_state_T_9; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_17 = _s2_victim_state_T_16 | _s2_victim_state_T_10; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_18 = _s2_victim_state_T_17 | _s2_victim_state_T_11; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_19 = _s2_victim_state_T_18 | _s2_victim_state_T_12; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_20 = _s2_victim_state_T_19 | _s2_victim_state_T_13; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_21 = _s2_victim_state_T_20 | _s2_victim_state_T_14; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_22 = _s2_victim_state_T_21 | _s2_victim_state_T_15; // @[Mux.scala:30:73] assign _s2_victim_state_WIRE_1 = _s2_victim_state_T_22; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_WIRE_tag = _s2_victim_state_WIRE_1; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_WIRE_coh_state = _s2_victim_state_WIRE_2_state; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_23 = _s2_victim_state_T ? s2_meta_corrected_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_24 = _s2_victim_state_T_1 ? s2_meta_corrected_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_25 = _s2_victim_state_T_2 ? s2_meta_corrected_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_26 = _s2_victim_state_T_3 ? s2_meta_corrected_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_27 = _s2_victim_state_T_4 ? s2_meta_corrected_4_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_28 = _s2_victim_state_T_5 ? s2_meta_corrected_5_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_29 = _s2_victim_state_T_6 ? s2_meta_corrected_6_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_30 = _s2_victim_state_T_7 ? s2_meta_corrected_7_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_31 = _s2_victim_state_T_23 | _s2_victim_state_T_24; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_32 = _s2_victim_state_T_31 | _s2_victim_state_T_25; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_33 = _s2_victim_state_T_32 | _s2_victim_state_T_26; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_34 = _s2_victim_state_T_33 | _s2_victim_state_T_27; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_35 = _s2_victim_state_T_34 | _s2_victim_state_T_28; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_36 = _s2_victim_state_T_35 | _s2_victim_state_T_29; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_37 = _s2_victim_state_T_36 | _s2_victim_state_T_30; // @[Mux.scala:30:73] assign _s2_victim_state_WIRE_3 = _s2_victim_state_T_37; // @[Mux.scala:30:73] assign _s2_victim_state_WIRE_2_state = _s2_victim_state_WIRE_3; // @[Mux.scala:30:73] wire [1:0] s2_victim_state_state = s2_hit_valid ? s2_hit_state_state : _s2_victim_state_WIRE_coh_state; // @[Mux.scala:30:73] wire [3:0] _r_T_59 = {probe_bits_param, s2_probe_state_state}; // @[Metadata.scala:120:19] wire _r_T_72 = _r_T_59 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_74 = _r_T_72 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_76 = _r_T_59 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_78 = _r_T_76 ? 3'h2 : _r_T_74; // @[Misc.scala:38:36, :56:20] wire _r_T_80 = _r_T_59 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_82 = _r_T_80 ? 3'h1 : _r_T_78; // @[Misc.scala:38:36, :56:20] wire _r_T_84 = _r_T_59 == 4'hB; // @[Misc.scala:56:20] wire _r_T_85 = _r_T_84; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_86 = _r_T_84 ? 3'h1 : _r_T_82; // @[Misc.scala:38:36, :56:20] wire _r_T_88 = _r_T_59 == 4'h4; // @[Misc.scala:56:20] wire _r_T_89 = ~_r_T_88 & _r_T_85; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_90 = _r_T_88 ? 3'h5 : _r_T_86; // @[Misc.scala:38:36, :56:20] wire _r_T_92 = _r_T_59 == 4'h5; // @[Misc.scala:56:20] wire _r_T_93 = ~_r_T_92 & _r_T_89; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_94 = _r_T_92 ? 3'h4 : _r_T_90; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_95 = {1'h0, _r_T_92}; // @[Misc.scala:38:63, :56:20] wire _r_T_96 = _r_T_59 == 4'h6; // @[Misc.scala:56:20] wire _r_T_97 = ~_r_T_96 & _r_T_93; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_98 = _r_T_96 ? 3'h0 : _r_T_94; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_99 = _r_T_96 ? 2'h1 : _r_T_95; // @[Misc.scala:38:63, :56:20] wire _r_T_100 = _r_T_59 == 4'h7; // @[Misc.scala:56:20] wire _r_T_101 = _r_T_100 | _r_T_97; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_102 = _r_T_100 ? 3'h0 : _r_T_98; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_103 = _r_T_100 ? 2'h1 : _r_T_99; // @[Misc.scala:38:63, :56:20] wire _r_T_104 = _r_T_59 == 4'h0; // @[Misc.scala:56:20] wire _r_T_105 = ~_r_T_104 & _r_T_101; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_106 = _r_T_104 ? 3'h5 : _r_T_102; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_107 = _r_T_104 ? 2'h0 : _r_T_103; // @[Misc.scala:38:63, :56:20] wire _r_T_108 = _r_T_59 == 4'h1; // @[Misc.scala:56:20] wire _r_T_109 = ~_r_T_108 & _r_T_105; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_110 = _r_T_108 ? 3'h4 : _r_T_106; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_111 = _r_T_108 ? 2'h1 : _r_T_107; // @[Misc.scala:38:63, :56:20] wire _r_T_112 = _r_T_59 == 4'h2; // @[Misc.scala:56:20] wire _r_T_113 = ~_r_T_112 & _r_T_109; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_114 = _r_T_112 ? 3'h3 : _r_T_110; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_115 = _r_T_112 ? 2'h2 : _r_T_111; // @[Misc.scala:38:63, :56:20] wire _r_T_116 = _r_T_59 == 4'h3; // @[Misc.scala:56:20] wire s2_prb_ack_data = _r_T_116 | _r_T_113; // @[Misc.scala:38:9, :56:20] wire [2:0] s2_report_param = _r_T_116 ? 3'h3 : _r_T_114; // @[Misc.scala:38:36, :56:20] wire [2:0] cleanReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36] wire [2:0] dirtyReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_116 ? 2'h2 : _r_T_115; // @[Misc.scala:38:63, :56:20] wire [1:0] probeNewCoh_state = r_3; // @[Misc.scala:38:63] wire [3:0] _r_T_123 = {2'h2, s2_victim_state_state}; // @[Metadata.scala:120:19] wire _r_T_136 = _r_T_123 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_138 = _r_T_136 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_140 = _r_T_123 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_142 = _r_T_140 ? 3'h2 : _r_T_138; // @[Misc.scala:38:36, :56:20] wire _r_T_144 = _r_T_123 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_146 = _r_T_144 ? 3'h1 : _r_T_142; // @[Misc.scala:38:36, :56:20] wire _r_T_148 = _r_T_123 == 4'hB; // @[Misc.scala:56:20] wire _r_T_149 = _r_T_148; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_150 = _r_T_148 ? 3'h1 : _r_T_146; // @[Misc.scala:38:36, :56:20] wire _r_T_152 = _r_T_123 == 4'h4; // @[Misc.scala:56:20] wire _r_T_153 = ~_r_T_152 & _r_T_149; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_154 = _r_T_152 ? 3'h5 : _r_T_150; // @[Misc.scala:38:36, :56:20] wire _r_T_156 = _r_T_123 == 4'h5; // @[Misc.scala:56:20] wire _r_T_157 = ~_r_T_156 & _r_T_153; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_158 = _r_T_156 ? 3'h4 : _r_T_154; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_159 = {1'h0, _r_T_156}; // @[Misc.scala:38:63, :56:20] wire _r_T_160 = _r_T_123 == 4'h6; // @[Misc.scala:56:20] wire _r_T_161 = ~_r_T_160 & _r_T_157; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_162 = _r_T_160 ? 3'h0 : _r_T_158; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_163 = _r_T_160 ? 2'h1 : _r_T_159; // @[Misc.scala:38:63, :56:20] wire _r_T_164 = _r_T_123 == 4'h7; // @[Misc.scala:56:20] wire _r_T_165 = _r_T_164 | _r_T_161; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_166 = _r_T_164 ? 3'h0 : _r_T_162; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_167 = _r_T_164 ? 2'h1 : _r_T_163; // @[Misc.scala:38:63, :56:20] wire _r_T_168 = _r_T_123 == 4'h0; // @[Misc.scala:56:20] wire _r_T_169 = ~_r_T_168 & _r_T_165; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_170 = _r_T_168 ? 3'h5 : _r_T_166; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_171 = _r_T_168 ? 2'h0 : _r_T_167; // @[Misc.scala:38:63, :56:20] wire _r_T_172 = _r_T_123 == 4'h1; // @[Misc.scala:56:20] wire _r_T_173 = ~_r_T_172 & _r_T_169; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_174 = _r_T_172 ? 3'h4 : _r_T_170; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_175 = _r_T_172 ? 2'h1 : _r_T_171; // @[Misc.scala:38:63, :56:20] wire _r_T_176 = _r_T_123 == 4'h2; // @[Misc.scala:56:20] wire _r_T_177 = ~_r_T_176 & _r_T_173; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_178 = _r_T_176 ? 3'h3 : _r_T_174; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_179 = _r_T_176 ? 2'h2 : _r_T_175; // @[Misc.scala:38:63, :56:20] wire _r_T_180 = _r_T_123 == 4'h3; // @[Misc.scala:56:20] wire s2_victim_dirty = _r_T_180 | _r_T_177; // @[Misc.scala:38:9, :56:20] wire [2:0] s2_shrink_param = _r_T_180 ? 3'h3 : _r_T_178; // @[Misc.scala:38:36, :56:20] wire [2:0] nodeOut_c_bits_c_param = s2_shrink_param; // @[Misc.scala:38:36] wire [2:0] nodeOut_c_bits_c_1_param = s2_shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3_1 = _r_T_180 ? 2'h2 : _r_T_179; // @[Misc.scala:38:63, :56:20] wire [1:0] voluntaryNewCoh_state = r_3_1; // @[Misc.scala:38:63] wire _s2_update_meta_T = s2_hit_state_state == s2_new_hit_state_state; // @[Metadata.scala:46:46, :160:20] wire s2_update_meta = ~_s2_update_meta_T; // @[Metadata.scala:46:46, :47:40] wire s2_dont_nack_uncached = s2_valid_uncached_pending & tl_out_a_ready; // @[DCache.scala:159:22, :430:64, :440:57] wire _s2_dont_nack_misc_T_7 = ~s2_hit; // @[Misc.scala:35:9] wire _s2_dont_nack_misc_T_10 = s2_req_cmd == 5'h17; // @[DCache.scala:339:19, :444:17] wire _s2_dont_nack_misc_T_11 = _s2_dont_nack_misc_T_10; // @[DCache.scala:443:55, :444:17] wire s2_dont_nack_misc = _s2_dont_nack_misc_T_1 & _s2_dont_nack_misc_T_11; // @[DCache.scala:441:{43,61}, :443:55] wire _io_cpu_s2_nack_T = ~s2_dont_nack_uncached; // @[DCache.scala:440:57, :445:41] wire _io_cpu_s2_nack_T_1 = s2_valid_no_xcpt & _io_cpu_s2_nack_T; // @[DCache.scala:332:35, :445:{38,41}] wire _io_cpu_s2_nack_T_2 = ~s2_dont_nack_misc; // @[DCache.scala:441:61, :445:67] wire _io_cpu_s2_nack_T_3 = _io_cpu_s2_nack_T_1 & _io_cpu_s2_nack_T_2; // @[DCache.scala:445:{38,64,67}] wire _io_cpu_s2_nack_T_4 = ~s2_valid_hit; // @[DCache.scala:422:48, :445:89] assign _io_cpu_s2_nack_T_5 = _io_cpu_s2_nack_T_3 & _io_cpu_s2_nack_T_4; // @[DCache.scala:445:{64,86,89}] assign io_cpu_s2_nack_0 = _io_cpu_s2_nack_T_5; // @[DCache.scala:101:7, :445:86] assign _metaArb_io_in_2_valid_T = s2_valid_hit_pre_data_ecc_and_waw & s2_update_meta; // @[Metadata.scala:47:40] wire _T_48 = io_cpu_s2_nack_0 | _metaArb_io_in_2_valid_T; // @[DCache.scala:101:7, :446:24, :462:63] wire [1:0] _s2_first_meta_corrected_T_9_coh_state = _s2_first_meta_corrected_T_8_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_9_tag = _s2_first_meta_corrected_T_8_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_10_coh_state = _s2_first_meta_corrected_T_9_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_10_tag = _s2_first_meta_corrected_T_9_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_11_coh_state = _s2_first_meta_corrected_T_10_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_11_tag = _s2_first_meta_corrected_T_10_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_12_coh_state = _s2_first_meta_corrected_T_11_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_12_tag = _s2_first_meta_corrected_T_11_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_13_coh_state = _s2_first_meta_corrected_T_12_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_13_tag = _s2_first_meta_corrected_T_12_tag; // @[Mux.scala:50:70] wire [1:0] s2_first_meta_corrected_coh_state = _s2_first_meta_corrected_T_13_coh_state; // @[Mux.scala:50:70] wire [19:0] s2_first_meta_corrected_tag = _s2_first_meta_corrected_T_13_tag; // @[Mux.scala:50:70] wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_state = s2_first_meta_corrected_coh_state; // @[Mux.scala:50:70] wire [19:0] metaArb_io_in_1_bits_data_new_meta_tag = s2_first_meta_corrected_tag; // @[Mux.scala:50:70] wire _metaArb_io_in_1_valid_T = s2_valid_masked | s2_flush_valid_pre_tag_ecc; // @[DCache.scala:337:42, :355:43, :450:63] wire _metaArb_io_in_1_valid_T_1 = _metaArb_io_in_1_valid_T | s2_probe; // @[DCache.scala:333:25, :450:{63,93}] wire [5:0] _metaArb_io_in_1_bits_idx_T = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] wire [5:0] _metaArb_io_in_6_bits_idx_T_1 = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] wire [5:0] _dataArb_io_in_2_bits_addr_T = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] assign _metaArb_io_in_4_bits_idx_T = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] wire [5:0] _metaArb_io_in_1_bits_idx_T_1 = s2_vaddr[11:6]; // @[DCache.scala:351:21, :453:76] assign _metaArb_io_in_2_bits_idx_T = s2_vaddr[11:6]; // @[DCache.scala:351:21, :453:76, :465:40] assign _metaArb_io_in_3_bits_idx_T = s2_vaddr[11:6]; // @[DCache.scala:351:21, :453:76, :744:40] assign _metaArb_io_in_1_bits_idx_T_2 = s2_probe ? _metaArb_io_in_1_bits_idx_T : _metaArb_io_in_1_bits_idx_T_1; // @[DCache.scala:333:25, :453:{35,76}, :1200:47] assign metaArb_io_in_1_bits_idx = _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:135:28, :453:35] wire [11:0] _metaArb_io_in_1_bits_addr_T_1 = {_metaArb_io_in_1_bits_idx_T_2, 6'h0}; // @[DCache.scala:453:35, :454:98] assign _metaArb_io_in_1_bits_addr_T_2 = {_metaArb_io_in_1_bits_addr_T, _metaArb_io_in_1_bits_addr_T_1}; // @[DCache.scala:454:{36,58,98}] assign metaArb_io_in_1_bits_addr = _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:135:28, :454:36] assign _metaArb_io_in_1_bits_data_T = {metaArb_io_in_1_bits_data_new_meta_coh_state, metaArb_io_in_1_bits_data_new_meta_tag}; // @[DCache.scala:456:31, :458:14] assign metaArb_io_in_1_bits_data = _metaArb_io_in_1_bits_data_T; // @[DCache.scala:135:28, :458:14] assign metaArb_io_in_2_valid = _metaArb_io_in_2_valid_T; // @[DCache.scala:135:28, :462:63] assign metaArb_io_in_2_bits_idx = _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:135:28, :465:40] wire [11:0] _metaArb_io_in_2_bits_addr_T_1 = s2_vaddr[11:0]; // @[DCache.scala:351:21, :466:80] wire [11:0] _metaArb_io_in_3_bits_addr_T_1 = s2_vaddr[11:0]; // @[DCache.scala:351:21, :466:80, :745:80] assign _metaArb_io_in_2_bits_addr_T_2 = {_metaArb_io_in_2_bits_addr_T, _metaArb_io_in_2_bits_addr_T_1}; // @[DCache.scala:466:{36,58,80}] assign metaArb_io_in_2_bits_addr = _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:135:28, :466:36] wire [27:0] _metaArb_io_in_2_bits_data_T = s2_req_addr[39:12]; // @[DCache.scala:339:19, :467:68] wire [27:0] _metaArb_io_in_3_bits_data_T = s2_req_addr[39:12]; // @[DCache.scala:339:19, :467:68, :746:68] wire [19:0] metaArb_io_in_2_bits_data_meta_tag; // @[HellaCache.scala:305:20] assign metaArb_io_in_2_bits_data_meta_tag = _metaArb_io_in_2_bits_data_T[19:0]; // @[HellaCache.scala:305:20, :306:14] assign _metaArb_io_in_2_bits_data_T_1 = {metaArb_io_in_2_bits_data_meta_coh_state, metaArb_io_in_2_bits_data_meta_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_2_bits_data = _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:135:28, :467:97] wire s2_lr = _s2_lr_T; // @[DCache.scala:470:{56,70}] wire s2_sc = _s2_sc_T; // @[DCache.scala:471:{56,70}] wire io_cpu_resp_bits_data_doZero_2 = s2_sc; // @[DCache.scala:471:56] reg [6:0] lrscCount; // @[DCache.scala:472:26] wire lrscValid = |(lrscCount[6:2]); // @[DCache.scala:472:26, :473:29] wire _lrscBackingOff_T = |lrscCount; // @[DCache.scala:472:26, :474:34] wire _lrscBackingOff_T_1 = ~lrscValid; // @[DCache.scala:473:29, :474:43] wire lrscBackingOff = _lrscBackingOff_T & _lrscBackingOff_T_1; // @[DCache.scala:474:{34,40,43}] reg [33:0] lrscAddr; // @[DCache.scala:475:21] wire [33:0] _lrscAddrMatch_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49] wire [33:0] _lrscAddr_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :480:29] wire [33:0] _acquire_address_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :578:38] wire [33:0] _tl_out_a_bits_T_1 = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :1210:39] wire [33:0] _io_errors_bus_bits_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :1130:58] wire lrscAddrMatch = lrscAddr == _lrscAddrMatch_T; // @[DCache.scala:475:21, :476:{32,49}] wire _s2_sc_fail_T = lrscValid & lrscAddrMatch; // @[DCache.scala:473:29, :476:32, :477:41] wire _s2_sc_fail_T_1 = ~_s2_sc_fail_T; // @[DCache.scala:477:{29,41}] wire s2_sc_fail = s2_sc & _s2_sc_fail_T_1; // @[DCache.scala:471:56, :477:{26,29}] wire [6:0] _lrscCount_T = s2_hit ? 7'h4F : 7'h0; // @[Misc.scala:35:9] wire [7:0] _lrscCount_T_1 = {1'h0, lrscCount} - 8'h1; // @[DCache.scala:472:26, :482:51] wire [6:0] _lrscCount_T_2 = _lrscCount_T_1[6:0]; // @[DCache.scala:482:51] wire _s2_correct_T = ~any_pstore_valid; // @[DCache.scala:230:30, :487:37] wire _s2_correct_T_2 = any_pstore_valid | s2_valid; // @[DCache.scala:230:30, :331:25, :487:84] reg s2_correct_REG; // @[DCache.scala:487:66] wire _s2_correct_T_3 = ~s2_correct_REG; // @[DCache.scala:487:{58,66}] wire _GEN_95 = s1_valid_not_nacked & s1_write; // @[DCache.scala:187:38, :492:63] wire _pstore1_cmd_T; // @[DCache.scala:492:63] assign _pstore1_cmd_T = _GEN_95; // @[DCache.scala:492:63] wire _pstore1_addr_T; // @[DCache.scala:493:62] assign _pstore1_addr_T = _GEN_95; // @[DCache.scala:492:63, :493:62] wire _pstore1_data_T; // @[DCache.scala:494:73] assign _pstore1_data_T = _GEN_95; // @[DCache.scala:492:63, :494:73] wire _pstore1_way_T; // @[DCache.scala:495:63] assign _pstore1_way_T = _GEN_95; // @[DCache.scala:492:63, :495:63] wire _pstore1_mask_T; // @[DCache.scala:496:61] assign _pstore1_mask_T = _GEN_95; // @[DCache.scala:492:63, :496:61] wire _pstore1_rmw_T_53; // @[DCache.scala:498:84] assign _pstore1_rmw_T_53 = _GEN_95; // @[DCache.scala:492:63, :498:84] reg [4:0] pstore1_cmd; // @[DCache.scala:492:30] reg [39:0] pstore1_addr; // @[DCache.scala:493:31] wire [39:0] _pstore2_addr_T = pstore1_addr; // @[DCache.scala:493:31, :524:35] reg [63:0] pstore1_data; // @[DCache.scala:494:31] assign io_cpu_resp_bits_store_data_0 = pstore1_data; // @[DCache.scala:101:7, :494:31] wire [63:0] _amoalu_io_rhs_T = pstore1_data; // @[DCache.scala:494:31, :986:37] reg [7:0] pstore1_way; // @[DCache.scala:495:30] wire [7:0] _pstore2_way_T = pstore1_way; // @[DCache.scala:495:30, :525:34] reg [7:0] pstore1_mask; // @[DCache.scala:496:31] wire [7:0] pstore2_storegen_mask_mergedMask = pstore1_mask; // @[DCache.scala:496:31, :533:37] wire [7:0] _amoalu_io_mask_T = pstore1_mask; // @[DCache.scala:496:31, :983:38] wire [63:0] pstore1_storegen_data; // @[DCache.scala:497:42] wire _pstore1_rmw_T_4 = _pstore1_rmw_T | _pstore1_rmw_T_1; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_5 = _pstore1_rmw_T_4 | _pstore1_rmw_T_2; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_6 = _pstore1_rmw_T_5 | _pstore1_rmw_T_3; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_11 = _pstore1_rmw_T_7 | _pstore1_rmw_T_8; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_12 = _pstore1_rmw_T_11 | _pstore1_rmw_T_9; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_13 = _pstore1_rmw_T_12 | _pstore1_rmw_T_10; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_19 = _pstore1_rmw_T_14 | _pstore1_rmw_T_15; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_20 = _pstore1_rmw_T_19 | _pstore1_rmw_T_16; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_21 = _pstore1_rmw_T_20 | _pstore1_rmw_T_17; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_22 = _pstore1_rmw_T_21 | _pstore1_rmw_T_18; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_23 = _pstore1_rmw_T_13 | _pstore1_rmw_T_22; // @[package.scala:81:59] wire _pstore1_rmw_T_24 = _pstore1_rmw_T_6 | _pstore1_rmw_T_23; // @[package.scala:81:59] wire _pstore1_rmw_T_27 = _pstore1_rmw_T_25 | _pstore1_rmw_T_26; // @[Consts.scala:90:{32,42,49}] wire _pstore1_rmw_T_29 = _pstore1_rmw_T_27 | _pstore1_rmw_T_28; // @[Consts.scala:90:{42,59,66}] wire _pstore1_rmw_T_34 = _pstore1_rmw_T_30 | _pstore1_rmw_T_31; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_35 = _pstore1_rmw_T_34 | _pstore1_rmw_T_32; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_36 = _pstore1_rmw_T_35 | _pstore1_rmw_T_33; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_42 = _pstore1_rmw_T_37 | _pstore1_rmw_T_38; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_43 = _pstore1_rmw_T_42 | _pstore1_rmw_T_39; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_44 = _pstore1_rmw_T_43 | _pstore1_rmw_T_40; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_45 = _pstore1_rmw_T_44 | _pstore1_rmw_T_41; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_46 = _pstore1_rmw_T_36 | _pstore1_rmw_T_45; // @[package.scala:81:59] wire _pstore1_rmw_T_47 = _pstore1_rmw_T_29 | _pstore1_rmw_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _pstore1_rmw_T_50 = _pstore1_rmw_T_48; // @[DCache.scala:1191:{35,45}] wire _pstore1_rmw_T_51 = _pstore1_rmw_T_47 & _pstore1_rmw_T_50; // @[DCache.scala:1191:{23,45}] wire _pstore1_rmw_T_52 = _pstore1_rmw_T_24 | _pstore1_rmw_T_51; // @[DCache.scala:1190:21, :1191:23] reg pstore1_rmw_r; // @[DCache.scala:498:44] wire pstore1_rmw = pstore1_rmw_r; // @[DCache.scala:498:{32,44}] wire _pstore1_merge_likely_T = s2_valid_not_nacked_in_s1 & s2_write; // @[DCache.scala:336:44, :499:56] wire _GEN_96 = s2_valid_hit & s2_write; // @[DCache.scala:422:48, :490:46] wire _pstore1_merge_T; // @[DCache.scala:490:46] assign _pstore1_merge_T = _GEN_96; // @[DCache.scala:490:46] wire _pstore1_valid_T; // @[DCache.scala:490:46] assign _pstore1_valid_T = _GEN_96; // @[DCache.scala:490:46] wire _pstore1_held_T; // @[DCache.scala:490:46] assign _pstore1_held_T = _GEN_96; // @[DCache.scala:490:46] wire _pstore1_merge_T_1 = ~s2_sc_fail; // @[DCache.scala:477:26, :490:61] wire _pstore1_merge_T_2 = _pstore1_merge_T & _pstore1_merge_T_1; // @[DCache.scala:490:{46,58,61}] wire _pstore1_merge_T_4 = _pstore1_merge_T_2; // @[DCache.scala:490:58, :491:48] reg pstore2_valid; // @[DCache.scala:501:30] wire _pstore_drain_opportunistic_res_T_2 = _pstore_drain_opportunistic_res_T | _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_res_T_3 = ~_pstore_drain_opportunistic_res_T_2; // @[package.scala:81:59] wire pstore_drain_opportunistic_res = _pstore_drain_opportunistic_res_T_3; // @[DCache.scala:1185:{15,46}] wire _pstore_drain_opportunistic_T_4 = _pstore_drain_opportunistic_T | _pstore_drain_opportunistic_T_1; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_5 = _pstore_drain_opportunistic_T_4 | _pstore_drain_opportunistic_T_2; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_6 = _pstore_drain_opportunistic_T_5 | _pstore_drain_opportunistic_T_3; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_11 = _pstore_drain_opportunistic_T_7 | _pstore_drain_opportunistic_T_8; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_12 = _pstore_drain_opportunistic_T_11 | _pstore_drain_opportunistic_T_9; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_13 = _pstore_drain_opportunistic_T_12 | _pstore_drain_opportunistic_T_10; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_19 = _pstore_drain_opportunistic_T_14 | _pstore_drain_opportunistic_T_15; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_20 = _pstore_drain_opportunistic_T_19 | _pstore_drain_opportunistic_T_16; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_21 = _pstore_drain_opportunistic_T_20 | _pstore_drain_opportunistic_T_17; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_22 = _pstore_drain_opportunistic_T_21 | _pstore_drain_opportunistic_T_18; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_23 = _pstore_drain_opportunistic_T_13 | _pstore_drain_opportunistic_T_22; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_24 = _pstore_drain_opportunistic_T_6 | _pstore_drain_opportunistic_T_23; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_27 = _pstore_drain_opportunistic_T_25 | _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:{32,42,49}] wire _pstore_drain_opportunistic_T_29 = _pstore_drain_opportunistic_T_27 | _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:{42,59,66}] wire _pstore_drain_opportunistic_T_34 = _pstore_drain_opportunistic_T_30 | _pstore_drain_opportunistic_T_31; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_35 = _pstore_drain_opportunistic_T_34 | _pstore_drain_opportunistic_T_32; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_36 = _pstore_drain_opportunistic_T_35 | _pstore_drain_opportunistic_T_33; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_42 = _pstore_drain_opportunistic_T_37 | _pstore_drain_opportunistic_T_38; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_43 = _pstore_drain_opportunistic_T_42 | _pstore_drain_opportunistic_T_39; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_44 = _pstore_drain_opportunistic_T_43 | _pstore_drain_opportunistic_T_40; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_45 = _pstore_drain_opportunistic_T_44 | _pstore_drain_opportunistic_T_41; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_46 = _pstore_drain_opportunistic_T_36 | _pstore_drain_opportunistic_T_45; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_47 = _pstore_drain_opportunistic_T_29 | _pstore_drain_opportunistic_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _pstore_drain_opportunistic_T_50 = _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:{35,45}] wire _pstore_drain_opportunistic_T_51 = _pstore_drain_opportunistic_T_47 & _pstore_drain_opportunistic_T_50; // @[DCache.scala:1191:{23,45}] wire _pstore_drain_opportunistic_T_52 = _pstore_drain_opportunistic_T_24 | _pstore_drain_opportunistic_T_51; // @[DCache.scala:1190:21, :1191:23] wire _pstore_drain_opportunistic_T_53 = ~_pstore_drain_opportunistic_T_52; // @[DCache.scala:1186:12, :1190:21] wire _pstore_drain_opportunistic_T_54 = _pstore_drain_opportunistic_T_53 | pstore_drain_opportunistic_res; // @[DCache.scala:1185:46, :1186:{12,28}] wire _pstore_drain_opportunistic_T_56 = ~_pstore_drain_opportunistic_T_55; // @[DCache.scala:1186:11] wire _pstore_drain_opportunistic_T_57 = ~_pstore_drain_opportunistic_T_54; // @[DCache.scala:1186:{11,28}] wire _pstore_drain_opportunistic_T_58 = io_cpu_req_valid_0 & pstore_drain_opportunistic_res; // @[DCache.scala:101:7, :502:55, :1185:46] wire _pstore_drain_opportunistic_T_59 = ~_pstore_drain_opportunistic_T_58; // @[DCache.scala:502:{36,55}] wire pstore_drain_opportunistic = _pstore_drain_opportunistic_T_59; // @[DCache.scala:502:{36,92}] reg pstore_drain_on_miss_REG; // @[DCache.scala:503:56] wire pstore_drain_on_miss = releaseInFlight | pstore_drain_on_miss_REG; // @[DCache.scala:334:46, :503:{46,56}] reg pstore1_held; // @[DCache.scala:504:29] wire _GEN_97 = s2_valid & s2_write; // @[DCache.scala:331:25, :505:39] wire _pstore1_valid_likely_T; // @[DCache.scala:505:39] assign _pstore1_valid_likely_T = _GEN_97; // @[DCache.scala:505:39] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_1; // @[DCache.scala:1082:16] assign _io_cpu_perf_storeBufferEmptyAfterLoad_T_1 = _GEN_97; // @[DCache.scala:505:39, :1082:16] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_1; // @[DCache.scala:1086:15] assign _io_cpu_perf_storeBufferEmptyAfterStore_T_1 = _GEN_97; // @[DCache.scala:505:39, :1086:15] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_4; // @[DCache.scala:1087:16] assign _io_cpu_perf_storeBufferEmptyAfterStore_T_4 = _GEN_97; // @[DCache.scala:505:39, :1087:16] wire _io_cpu_perf_canAcceptStoreThenLoad_T; // @[DCache.scala:1089:16] assign _io_cpu_perf_canAcceptStoreThenLoad_T = _GEN_97; // @[DCache.scala:505:39, :1089:16] wire _io_cpu_perf_canAcceptLoadThenLoad_T_55; // @[DCache.scala:1092:100] assign _io_cpu_perf_canAcceptLoadThenLoad_T_55 = _GEN_97; // @[DCache.scala:505:39, :1092:100] wire pstore1_valid_likely = _pstore1_valid_likely_T | pstore1_held; // @[DCache.scala:504:29, :505:{39,51}] wire _pstore1_valid_T_1 = ~s2_sc_fail; // @[DCache.scala:477:26, :490:61] wire _pstore1_valid_T_2 = _pstore1_valid_T & _pstore1_valid_T_1; // @[DCache.scala:490:{46,58,61}] wire _pstore1_valid_T_4 = _pstore1_valid_T_2; // @[DCache.scala:490:58, :491:48] wire pstore1_valid = _pstore1_valid_T_4 | pstore1_held; // @[DCache.scala:491:48, :504:29, :507:38] wire _advance_pstore1_T = pstore1_valid; // @[DCache.scala:507:38, :522:40] assign _any_pstore_valid_T = pstore1_held | pstore2_valid; // @[DCache.scala:501:30, :504:29, :508:36] assign any_pstore_valid = _any_pstore_valid_T; // @[DCache.scala:230:30, :508:36] wire _GEN_98 = pstore1_valid_likely & pstore2_valid; // @[DCache.scala:501:30, :505:51, :509:54] wire _pstore_drain_structural_T; // @[DCache.scala:509:54] assign _pstore_drain_structural_T = _GEN_98; // @[DCache.scala:509:54] wire _io_cpu_perf_canAcceptStoreThenLoad_T_6; // @[DCache.scala:1090:20] assign _io_cpu_perf_canAcceptStoreThenLoad_T_6 = _GEN_98; // @[DCache.scala:509:54, :1090:20] wire _GEN_99 = s1_valid & s1_write; // @[DCache.scala:182:25, :509:85] wire _pstore_drain_structural_T_1; // @[DCache.scala:509:85] assign _pstore_drain_structural_T_1 = _GEN_99; // @[DCache.scala:509:85] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T; // @[DCache.scala:1081:15] assign _io_cpu_perf_storeBufferEmptyAfterLoad_T = _GEN_99; // @[DCache.scala:509:85, :1081:15] wire _io_cpu_perf_storeBufferEmptyAfterStore_T; // @[DCache.scala:1085:15] assign _io_cpu_perf_storeBufferEmptyAfterStore_T = _GEN_99; // @[DCache.scala:509:85, :1085:15] wire _io_cpu_perf_canAcceptStoreThenLoad_T_2; // @[DCache.scala:1089:57] assign _io_cpu_perf_canAcceptStoreThenLoad_T_2 = _GEN_99; // @[DCache.scala:509:85, :1089:57] wire _io_cpu_perf_canAcceptStoreThenLoad_T_7; // @[DCache.scala:1090:57] assign _io_cpu_perf_canAcceptStoreThenLoad_T_7 = _GEN_99; // @[DCache.scala:509:85, :1090:57] wire _io_cpu_perf_canAcceptLoadThenLoad_T; // @[DCache.scala:1092:52] assign _io_cpu_perf_canAcceptLoadThenLoad_T = _GEN_99; // @[DCache.scala:509:85, :1092:52] wire _pstore_drain_structural_T_2 = _pstore_drain_structural_T_1 | pstore1_rmw; // @[DCache.scala:498:32, :509:{85,98}] wire pstore_drain_structural = _pstore_drain_structural_T & _pstore_drain_structural_T_2; // @[DCache.scala:509:{54,71,98}] wire _pstore_drain_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17] wire _dataArb_io_in_0_valid_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17] wire _T_57 = s2_valid_hit_pre_data_ecc & s2_write; // @[DCache.scala:420:69, :506:72] wire _pstore_drain_T_2; // @[DCache.scala:506:72] assign _pstore_drain_T_2 = _T_57; // @[DCache.scala:506:72] wire _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:72] assign _dataArb_io_in_0_valid_T_2 = _T_57; // @[DCache.scala:506:72] wire _pstore_drain_T_4 = _pstore_drain_T_2; // @[DCache.scala:506:{72,84}] wire _pstore_drain_T_5 = _pstore_drain_T_4 | pstore1_held; // @[DCache.scala:504:29, :506:{84,96}] wire _pstore_drain_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44] wire _pstore_drain_T_7 = _pstore_drain_T_5 & _pstore_drain_T_6; // @[DCache.scala:506:96, :518:{41,44}] wire _pstore_drain_T_8 = _pstore_drain_T_7 | pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}] wire _GEN_100 = pstore_drain_opportunistic | pstore_drain_on_miss; // @[DCache.scala:502:92, :503:46, :518:107] wire _pstore_drain_T_9; // @[DCache.scala:518:107] assign _pstore_drain_T_9 = _GEN_100; // @[DCache.scala:518:107] wire _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:107] assign _dataArb_io_in_0_valid_T_9 = _GEN_100; // @[DCache.scala:518:107] wire _pstore_drain_T_10 = _pstore_drain_T_8 & _pstore_drain_T_9; // @[DCache.scala:518:{58,76,107}] wire _pstore_drain_T_11 = _pstore_drain_T_1 | _pstore_drain_T_10; // @[DCache.scala:517:{17,44}, :518:76] assign pstore_drain = _pstore_drain_T_11; // @[DCache.scala:516:27, :517:44] assign dataArb_io_in_0_bits_write = pstore_drain; // @[DCache.scala:152:28, :516:27] wire _pstore1_held_T_1 = ~s2_sc_fail; // @[DCache.scala:477:26, :490:61] wire _pstore1_held_T_2 = _pstore1_held_T & _pstore1_held_T_1; // @[DCache.scala:490:{46,58,61}] wire _pstore1_held_T_4 = _pstore1_held_T_2; // @[DCache.scala:490:58, :491:48] wire _pstore1_held_T_6 = _pstore1_held_T_4; // @[DCache.scala:491:48, :521:35] wire _pstore1_held_T_7 = _pstore1_held_T_6 | pstore1_held; // @[DCache.scala:504:29, :521:{35,54}] wire _pstore1_held_T_8 = _pstore1_held_T_7 & pstore2_valid; // @[DCache.scala:501:30, :521:{54,71}] wire _pstore1_held_T_9 = ~pstore_drain; // @[DCache.scala:516:27, :521:91] wire _pstore1_held_T_10 = _pstore1_held_T_8 & _pstore1_held_T_9; // @[DCache.scala:521:{71,88,91}] wire _advance_pstore1_T_1 = pstore2_valid == pstore_drain; // @[DCache.scala:501:30, :516:27, :522:79] wire advance_pstore1 = _advance_pstore1_T & _advance_pstore1_T_1; // @[DCache.scala:522:{40,61,79}] wire _pstore2_storegen_data_T_3 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_7 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_11 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_15 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_19 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_23 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_27 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_31 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_mask_T = advance_pstore1; // @[DCache.scala:522:61, :532:27] wire _pstore2_valid_T = ~pstore_drain; // @[DCache.scala:516:27, :521:91, :523:37] wire _pstore2_valid_T_1 = pstore2_valid & _pstore2_valid_T; // @[DCache.scala:501:30, :523:{34,37}] wire _pstore2_valid_T_2 = _pstore2_valid_T_1 | advance_pstore1; // @[DCache.scala:522:61, :523:{34,51}] reg [39:0] pstore2_addr; // @[DCache.scala:524:31] reg [7:0] pstore2_way; // @[DCache.scala:525:30] wire [7:0] _pstore2_storegen_data_T = pstore1_storegen_data[7:0]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_1 = pstore1_mask[0]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_3 = pstore1_mask[0]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_4 = pstore1_storegen_data[15:8]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_5 = pstore1_mask[1]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_4 = pstore1_mask[1]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_1; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_8 = pstore1_storegen_data[23:16]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_9 = pstore1_mask[2]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_5 = pstore1_mask[2]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_2; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_12 = pstore1_storegen_data[31:24]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_13 = pstore1_mask[3]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_6 = pstore1_mask[3]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_3; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_16 = pstore1_storegen_data[39:32]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_17 = pstore1_mask[4]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_7 = pstore1_mask[4]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_4; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_20 = pstore1_storegen_data[47:40]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_21 = pstore1_mask[5]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_8 = pstore1_mask[5]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_5; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_24 = pstore1_storegen_data[55:48]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_25 = pstore1_mask[6]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_9 = pstore1_mask[6]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_6; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_28 = pstore1_storegen_data[63:56]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_29 = pstore1_mask[7]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_10 = pstore1_mask[7]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_7; // @[DCache.scala:528:22] wire [15:0] pstore2_storegen_data_lo_lo = {pstore2_storegen_data_r_1, pstore2_storegen_data_r}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_lo_hi = {pstore2_storegen_data_r_3, pstore2_storegen_data_r_2}; // @[package.scala:45:27] wire [31:0] pstore2_storegen_data_lo = {pstore2_storegen_data_lo_hi, pstore2_storegen_data_lo_lo}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_hi_lo = {pstore2_storegen_data_r_5, pstore2_storegen_data_r_4}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_hi_hi = {pstore2_storegen_data_r_7, pstore2_storegen_data_r_6}; // @[package.scala:45:27] wire [31:0] pstore2_storegen_data_hi = {pstore2_storegen_data_hi_hi, pstore2_storegen_data_hi_lo}; // @[package.scala:45:27] wire [63:0] pstore2_storegen_data = {pstore2_storegen_data_hi, pstore2_storegen_data_lo}; // @[package.scala:45:27] reg [7:0] pstore2_storegen_mask; // @[DCache.scala:531:19] wire [7:0] _pstore2_storegen_mask_mask_T = ~pstore2_storegen_mask_mergedMask; // @[DCache.scala:533:37, :534:37] wire [7:0] _pstore2_storegen_mask_mask_T_1 = _pstore2_storegen_mask_mask_T; // @[DCache.scala:534:{19,37}] wire [7:0] _pstore2_storegen_mask_mask_T_2 = ~_pstore2_storegen_mask_mask_T_1; // @[DCache.scala:534:{15,19}] wire _dataArb_io_in_0_valid_T_4 = _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:{72,84}] wire _dataArb_io_in_0_valid_T_5 = _dataArb_io_in_0_valid_T_4 | pstore1_held; // @[DCache.scala:504:29, :506:{84,96}] wire _dataArb_io_in_0_valid_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44] wire _dataArb_io_in_0_valid_T_7 = _dataArb_io_in_0_valid_T_5 & _dataArb_io_in_0_valid_T_6; // @[DCache.scala:506:96, :518:{41,44}] wire _dataArb_io_in_0_valid_T_8 = _dataArb_io_in_0_valid_T_7 | pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}] wire _dataArb_io_in_0_valid_T_10 = _dataArb_io_in_0_valid_T_8 & _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:{58,76,107}] wire _dataArb_io_in_0_valid_T_11 = _dataArb_io_in_0_valid_T_1 | _dataArb_io_in_0_valid_T_10; // @[DCache.scala:517:{17,44}, :518:76] assign _dataArb_io_in_0_valid_T_12 = _dataArb_io_in_0_valid_T_11; // @[DCache.scala:516:27, :517:44] assign dataArb_io_in_0_valid = _dataArb_io_in_0_valid_T_12; // @[DCache.scala:152:28, :516:27] wire [39:0] _GEN_101 = pstore2_valid ? pstore2_addr : pstore1_addr; // @[DCache.scala:493:31, :501:30, :524:31, :549:36] wire [39:0] _dataArb_io_in_0_bits_addr_T; // @[DCache.scala:549:36] assign _dataArb_io_in_0_bits_addr_T = _GEN_101; // @[DCache.scala:549:36] wire [39:0] _dataArb_io_in_0_bits_wordMask_wordMask_T; // @[DCache.scala:554:32] assign _dataArb_io_in_0_bits_wordMask_wordMask_T = _GEN_101; // @[DCache.scala:549:36, :554:32] assign dataArb_io_in_0_bits_addr = _dataArb_io_in_0_bits_addr_T[11:0]; // @[DCache.scala:152:28, :549:{30,36}] assign _dataArb_io_in_0_bits_way_en_T = pstore2_valid ? pstore2_way : pstore1_way; // @[DCache.scala:495:30, :501:30, :525:30, :550:38] assign dataArb_io_in_0_bits_way_en = _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:152:28, :550:38] wire [63:0] _dataArb_io_in_0_bits_wdata_T = pstore2_valid ? pstore2_storegen_data : pstore1_data; // @[package.scala:45:27] wire [127:0] _dataArb_io_in_0_bits_wdata_T_1 = {2{_dataArb_io_in_0_bits_wdata_T}}; // @[DCache.scala:551:{49,63}] wire [7:0] _dataArb_io_in_0_bits_wdata_T_2 = _dataArb_io_in_0_bits_wdata_T_1[7:0]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_3 = _dataArb_io_in_0_bits_wdata_T_1[15:8]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_4 = _dataArb_io_in_0_bits_wdata_T_1[23:16]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_5 = _dataArb_io_in_0_bits_wdata_T_1[31:24]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_6 = _dataArb_io_in_0_bits_wdata_T_1[39:32]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_7 = _dataArb_io_in_0_bits_wdata_T_1[47:40]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_8 = _dataArb_io_in_0_bits_wdata_T_1[55:48]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_9 = _dataArb_io_in_0_bits_wdata_T_1[63:56]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_10 = _dataArb_io_in_0_bits_wdata_T_1[71:64]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_11 = _dataArb_io_in_0_bits_wdata_T_1[79:72]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_12 = _dataArb_io_in_0_bits_wdata_T_1[87:80]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_13 = _dataArb_io_in_0_bits_wdata_T_1[95:88]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_14 = _dataArb_io_in_0_bits_wdata_T_1[103:96]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_15 = _dataArb_io_in_0_bits_wdata_T_1[111:104]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_16 = _dataArb_io_in_0_bits_wdata_T_1[119:112]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_17 = _dataArb_io_in_0_bits_wdata_T_1[127:120]; // @[package.scala:211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_lo_lo = {_dataArb_io_in_0_bits_wdata_T_3, _dataArb_io_in_0_bits_wdata_T_2}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_lo_hi = {_dataArb_io_in_0_bits_wdata_T_5, _dataArb_io_in_0_bits_wdata_T_4}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_lo_lo = {dataArb_io_in_0_bits_wdata_lo_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo_lo}; // @[package.scala:45:27] wire [15:0] dataArb_io_in_0_bits_wdata_lo_hi_lo = {_dataArb_io_in_0_bits_wdata_T_7, _dataArb_io_in_0_bits_wdata_T_6}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_hi_hi = {_dataArb_io_in_0_bits_wdata_T_9, _dataArb_io_in_0_bits_wdata_T_8}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_lo_hi = {dataArb_io_in_0_bits_wdata_lo_hi_hi, dataArb_io_in_0_bits_wdata_lo_hi_lo}; // @[package.scala:45:27] wire [63:0] dataArb_io_in_0_bits_wdata_lo = {dataArb_io_in_0_bits_wdata_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo}; // @[package.scala:45:27] wire [15:0] dataArb_io_in_0_bits_wdata_hi_lo_lo = {_dataArb_io_in_0_bits_wdata_T_11, _dataArb_io_in_0_bits_wdata_T_10}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_hi_lo_hi = {_dataArb_io_in_0_bits_wdata_T_13, _dataArb_io_in_0_bits_wdata_T_12}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_hi_lo = {dataArb_io_in_0_bits_wdata_hi_lo_hi, dataArb_io_in_0_bits_wdata_hi_lo_lo}; // @[package.scala:45:27] wire [15:0] dataArb_io_in_0_bits_wdata_hi_hi_lo = {_dataArb_io_in_0_bits_wdata_T_15, _dataArb_io_in_0_bits_wdata_T_14}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_hi_hi_hi = {_dataArb_io_in_0_bits_wdata_T_17, _dataArb_io_in_0_bits_wdata_T_16}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_hi_hi = {dataArb_io_in_0_bits_wdata_hi_hi_hi, dataArb_io_in_0_bits_wdata_hi_hi_lo}; // @[package.scala:45:27] wire [63:0] dataArb_io_in_0_bits_wdata_hi = {dataArb_io_in_0_bits_wdata_hi_hi, dataArb_io_in_0_bits_wdata_hi_lo}; // @[package.scala:45:27] assign _dataArb_io_in_0_bits_wdata_T_18 = {dataArb_io_in_0_bits_wdata_hi, dataArb_io_in_0_bits_wdata_lo}; // @[package.scala:45:27] assign dataArb_io_in_0_bits_wdata = _dataArb_io_in_0_bits_wdata_T_18; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T = _dataArb_io_in_0_bits_eccMask_T_17[0]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T_17[1]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T_17[2]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T_17[3]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T_17[4]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T_17[5]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T_17[6]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T_17[7]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_8 = _dataArb_io_in_0_bits_wordMask_eccMask_T | _dataArb_io_in_0_bits_wordMask_eccMask_T_1; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_9 = _dataArb_io_in_0_bits_wordMask_eccMask_T_8 | _dataArb_io_in_0_bits_wordMask_eccMask_T_2; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_10 = _dataArb_io_in_0_bits_wordMask_eccMask_T_9 | _dataArb_io_in_0_bits_wordMask_eccMask_T_3; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_11 = _dataArb_io_in_0_bits_wordMask_eccMask_T_10 | _dataArb_io_in_0_bits_wordMask_eccMask_T_4; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_12 = _dataArb_io_in_0_bits_wordMask_eccMask_T_11 | _dataArb_io_in_0_bits_wordMask_eccMask_T_5; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_13 = _dataArb_io_in_0_bits_wordMask_eccMask_T_12 | _dataArb_io_in_0_bits_wordMask_eccMask_T_6; // @[package.scala:81:59] wire dataArb_io_in_0_bits_wordMask_eccMask = _dataArb_io_in_0_bits_wordMask_eccMask_T_13 | _dataArb_io_in_0_bits_wordMask_eccMask_T_7; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_wordMask_T_1 = _dataArb_io_in_0_bits_wordMask_wordMask_T[3]; // @[package.scala:163:13] wire [1:0] dataArb_io_in_0_bits_wordMask_wordMask = 2'h1 << _dataArb_io_in_0_bits_wordMask_wordMask_T_1; // @[OneHot.scala:58:35] wire _dataArb_io_in_0_bits_wordMask_T = dataArb_io_in_0_bits_wordMask_wordMask[0]; // @[OneHot.scala:58:35] wire _dataArb_io_in_0_bits_wordMask_T_1 = dataArb_io_in_0_bits_wordMask_wordMask[1]; // @[OneHot.scala:58:35] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_2 = {_dataArb_io_in_0_bits_wordMask_T_1, _dataArb_io_in_0_bits_wordMask_T}; // @[DCache.scala:555:20] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_3 = {2{dataArb_io_in_0_bits_wordMask_eccMask}}; // @[package.scala:81:59] assign _dataArb_io_in_0_bits_wordMask_T_4 = _dataArb_io_in_0_bits_wordMask_T_2 & _dataArb_io_in_0_bits_wordMask_T_3; // @[DCache.scala:555:{20,55,61}] assign dataArb_io_in_0_bits_wordMask = _dataArb_io_in_0_bits_wordMask_T_4; // @[DCache.scala:152:28, :555:55] wire [7:0] _dataArb_io_in_0_bits_eccMask_T = pstore2_valid ? pstore2_storegen_mask : pstore1_mask; // @[DCache.scala:496:31, :501:30, :531:19, :557:47] wire _dataArb_io_in_0_bits_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T[0]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_9 = _dataArb_io_in_0_bits_eccMask_T_1; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T[1]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_10 = _dataArb_io_in_0_bits_eccMask_T_2; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T[2]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_11 = _dataArb_io_in_0_bits_eccMask_T_3; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T[3]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_12 = _dataArb_io_in_0_bits_eccMask_T_4; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T[4]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_13 = _dataArb_io_in_0_bits_eccMask_T_5; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T[5]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_14 = _dataArb_io_in_0_bits_eccMask_T_6; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T[6]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_15 = _dataArb_io_in_0_bits_eccMask_T_7; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_8 = _dataArb_io_in_0_bits_eccMask_T[7]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_16 = _dataArb_io_in_0_bits_eccMask_T_8; // @[package.scala:211:50] wire [1:0] dataArb_io_in_0_bits_eccMask_lo_lo = {_dataArb_io_in_0_bits_eccMask_T_10, _dataArb_io_in_0_bits_eccMask_T_9}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_lo_hi = {_dataArb_io_in_0_bits_eccMask_T_12, _dataArb_io_in_0_bits_eccMask_T_11}; // @[package.scala:45:27] wire [3:0] dataArb_io_in_0_bits_eccMask_lo = {dataArb_io_in_0_bits_eccMask_lo_hi, dataArb_io_in_0_bits_eccMask_lo_lo}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_hi_lo = {_dataArb_io_in_0_bits_eccMask_T_14, _dataArb_io_in_0_bits_eccMask_T_13}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_hi_hi = {_dataArb_io_in_0_bits_eccMask_T_16, _dataArb_io_in_0_bits_eccMask_T_15}; // @[package.scala:45:27] wire [3:0] dataArb_io_in_0_bits_eccMask_hi = {dataArb_io_in_0_bits_eccMask_hi_hi, dataArb_io_in_0_bits_eccMask_hi_lo}; // @[package.scala:45:27] assign _dataArb_io_in_0_bits_eccMask_T_17 = {dataArb_io_in_0_bits_eccMask_hi, dataArb_io_in_0_bits_eccMask_lo}; // @[package.scala:45:27] assign dataArb_io_in_0_bits_eccMask = _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27] wire [8:0] _s1_hazard_T = pstore1_addr[11:3]; // @[DCache.scala:493:31, :561:9] wire [8:0] _s1_hazard_T_1 = s1_vaddr[11:3]; // @[DCache.scala:197:21, :561:43] wire [8:0] _s1_hazard_T_63 = s1_vaddr[11:3]; // @[DCache.scala:197:21, :561:43] wire _s1_hazard_T_2 = _s1_hazard_T == _s1_hazard_T_1; // @[DCache.scala:561:{9,31,43}] wire _s1_hazard_T_11 = _s1_hazard_T_3; // @[package.scala:211:50] wire _s1_hazard_T_12 = _s1_hazard_T_4; // @[package.scala:211:50] wire _s1_hazard_T_13 = _s1_hazard_T_5; // @[package.scala:211:50] wire _s1_hazard_T_14 = _s1_hazard_T_6; // @[package.scala:211:50] wire _s1_hazard_T_15 = _s1_hazard_T_7; // @[package.scala:211:50] wire _s1_hazard_T_16 = _s1_hazard_T_8; // @[package.scala:211:50] wire _s1_hazard_T_17 = _s1_hazard_T_9; // @[package.scala:211:50] wire _s1_hazard_T_18 = _s1_hazard_T_10; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo = {_s1_hazard_T_12, _s1_hazard_T_11}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi = {_s1_hazard_T_14, _s1_hazard_T_13}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo = {s1_hazard_lo_hi, s1_hazard_lo_lo}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo = {_s1_hazard_T_16, _s1_hazard_T_15}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi = {_s1_hazard_T_18, _s1_hazard_T_17}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi = {s1_hazard_hi_hi, s1_hazard_hi_lo}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_19 = {s1_hazard_hi, s1_hazard_lo}; // @[package.scala:45:27] wire _s1_hazard_T_20 = _s1_hazard_T_19[0]; // @[package.scala:45:27] wire _s1_hazard_T_21 = _s1_hazard_T_19[1]; // @[package.scala:45:27] wire _s1_hazard_T_22 = _s1_hazard_T_19[2]; // @[package.scala:45:27] wire _s1_hazard_T_23 = _s1_hazard_T_19[3]; // @[package.scala:45:27] wire _s1_hazard_T_24 = _s1_hazard_T_19[4]; // @[package.scala:45:27] wire _s1_hazard_T_25 = _s1_hazard_T_19[5]; // @[package.scala:45:27] wire _s1_hazard_T_26 = _s1_hazard_T_19[6]; // @[package.scala:45:27] wire _s1_hazard_T_27 = _s1_hazard_T_19[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_1 = {_s1_hazard_T_21, _s1_hazard_T_20}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_1 = {_s1_hazard_T_23, _s1_hazard_T_22}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_1 = {s1_hazard_lo_hi_1, s1_hazard_lo_lo_1}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_1 = {_s1_hazard_T_25, _s1_hazard_T_24}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_1 = {_s1_hazard_T_27, _s1_hazard_T_26}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_1 = {s1_hazard_hi_hi_1, s1_hazard_hi_lo_1}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_28 = {s1_hazard_hi_1, s1_hazard_lo_1}; // @[DCache.scala:1182:52] wire _s1_hazard_T_29 = s1_mask_xwr[0]; // @[package.scala:211:50] wire _s1_hazard_T_91 = s1_mask_xwr[0]; // @[package.scala:211:50] wire _s1_hazard_T_37 = _s1_hazard_T_29; // @[package.scala:211:50] wire _s1_hazard_T_30 = s1_mask_xwr[1]; // @[package.scala:211:50] wire _s1_hazard_T_92 = s1_mask_xwr[1]; // @[package.scala:211:50] wire _s1_hazard_T_38 = _s1_hazard_T_30; // @[package.scala:211:50] wire _s1_hazard_T_31 = s1_mask_xwr[2]; // @[package.scala:211:50] wire _s1_hazard_T_93 = s1_mask_xwr[2]; // @[package.scala:211:50] wire _s1_hazard_T_39 = _s1_hazard_T_31; // @[package.scala:211:50] wire _s1_hazard_T_32 = s1_mask_xwr[3]; // @[package.scala:211:50] wire _s1_hazard_T_94 = s1_mask_xwr[3]; // @[package.scala:211:50] wire _s1_hazard_T_40 = _s1_hazard_T_32; // @[package.scala:211:50] wire _s1_hazard_T_33 = s1_mask_xwr[4]; // @[package.scala:211:50] wire _s1_hazard_T_95 = s1_mask_xwr[4]; // @[package.scala:211:50] wire _s1_hazard_T_41 = _s1_hazard_T_33; // @[package.scala:211:50] wire _s1_hazard_T_34 = s1_mask_xwr[5]; // @[package.scala:211:50] wire _s1_hazard_T_96 = s1_mask_xwr[5]; // @[package.scala:211:50] wire _s1_hazard_T_42 = _s1_hazard_T_34; // @[package.scala:211:50] wire _s1_hazard_T_35 = s1_mask_xwr[6]; // @[package.scala:211:50] wire _s1_hazard_T_97 = s1_mask_xwr[6]; // @[package.scala:211:50] wire _s1_hazard_T_43 = _s1_hazard_T_35; // @[package.scala:211:50] wire _s1_hazard_T_36 = s1_mask_xwr[7]; // @[package.scala:211:50] wire _s1_hazard_T_98 = s1_mask_xwr[7]; // @[package.scala:211:50] wire _s1_hazard_T_44 = _s1_hazard_T_36; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_2 = {_s1_hazard_T_38, _s1_hazard_T_37}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_2 = {_s1_hazard_T_40, _s1_hazard_T_39}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_2 = {s1_hazard_lo_hi_2, s1_hazard_lo_lo_2}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_2 = {_s1_hazard_T_42, _s1_hazard_T_41}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_2 = {_s1_hazard_T_44, _s1_hazard_T_43}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_2 = {s1_hazard_hi_hi_2, s1_hazard_hi_lo_2}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_45 = {s1_hazard_hi_2, s1_hazard_lo_2}; // @[package.scala:45:27] wire _s1_hazard_T_46 = _s1_hazard_T_45[0]; // @[package.scala:45:27] wire _s1_hazard_T_47 = _s1_hazard_T_45[1]; // @[package.scala:45:27] wire _s1_hazard_T_48 = _s1_hazard_T_45[2]; // @[package.scala:45:27] wire _s1_hazard_T_49 = _s1_hazard_T_45[3]; // @[package.scala:45:27] wire _s1_hazard_T_50 = _s1_hazard_T_45[4]; // @[package.scala:45:27] wire _s1_hazard_T_51 = _s1_hazard_T_45[5]; // @[package.scala:45:27] wire _s1_hazard_T_52 = _s1_hazard_T_45[6]; // @[package.scala:45:27] wire _s1_hazard_T_53 = _s1_hazard_T_45[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_3 = {_s1_hazard_T_47, _s1_hazard_T_46}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_3 = {_s1_hazard_T_49, _s1_hazard_T_48}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_3 = {s1_hazard_lo_hi_3, s1_hazard_lo_lo_3}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_3 = {_s1_hazard_T_51, _s1_hazard_T_50}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_3 = {_s1_hazard_T_53, _s1_hazard_T_52}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_3 = {s1_hazard_hi_hi_3, s1_hazard_hi_lo_3}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_54 = {s1_hazard_hi_3, s1_hazard_lo_3}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_55 = _s1_hazard_T_28 & _s1_hazard_T_54; // @[DCache.scala:562:38, :1182:52] wire _s1_hazard_T_56 = |_s1_hazard_T_55; // @[DCache.scala:562:{38,66}] wire [7:0] _s1_hazard_T_57 = pstore1_mask & s1_mask_xwr; // @[DCache.scala:496:31, :562:77] wire _s1_hazard_T_58 = |_s1_hazard_T_57; // @[DCache.scala:562:{77,92}] wire _s1_hazard_T_59 = s1_write ? _s1_hazard_T_56 : _s1_hazard_T_58; // @[DCache.scala:562:{8,66,92}] wire _s1_hazard_T_60 = _s1_hazard_T_2 & _s1_hazard_T_59; // @[DCache.scala:561:{31,65}, :562:8] wire _s1_hazard_T_61 = pstore1_valid_likely & _s1_hazard_T_60; // @[DCache.scala:505:51, :561:65, :564:27] wire [8:0] _s1_hazard_T_62 = pstore2_addr[11:3]; // @[DCache.scala:524:31, :561:9] wire _s1_hazard_T_64 = _s1_hazard_T_62 == _s1_hazard_T_63; // @[DCache.scala:561:{9,31,43}] wire _s1_hazard_T_65 = pstore2_storegen_mask[0]; // @[package.scala:211:50] wire _s1_hazard_T_73 = _s1_hazard_T_65; // @[package.scala:211:50] wire _s1_hazard_T_66 = pstore2_storegen_mask[1]; // @[package.scala:211:50] wire _s1_hazard_T_74 = _s1_hazard_T_66; // @[package.scala:211:50] wire _s1_hazard_T_67 = pstore2_storegen_mask[2]; // @[package.scala:211:50] wire _s1_hazard_T_75 = _s1_hazard_T_67; // @[package.scala:211:50] wire _s1_hazard_T_68 = pstore2_storegen_mask[3]; // @[package.scala:211:50] wire _s1_hazard_T_76 = _s1_hazard_T_68; // @[package.scala:211:50] wire _s1_hazard_T_69 = pstore2_storegen_mask[4]; // @[package.scala:211:50] wire _s1_hazard_T_77 = _s1_hazard_T_69; // @[package.scala:211:50] wire _s1_hazard_T_70 = pstore2_storegen_mask[5]; // @[package.scala:211:50] wire _s1_hazard_T_78 = _s1_hazard_T_70; // @[package.scala:211:50] wire _s1_hazard_T_71 = pstore2_storegen_mask[6]; // @[package.scala:211:50] wire _s1_hazard_T_79 = _s1_hazard_T_71; // @[package.scala:211:50] wire _s1_hazard_T_72 = pstore2_storegen_mask[7]; // @[package.scala:211:50] wire _s1_hazard_T_80 = _s1_hazard_T_72; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_4 = {_s1_hazard_T_74, _s1_hazard_T_73}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_4 = {_s1_hazard_T_76, _s1_hazard_T_75}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_4 = {s1_hazard_lo_hi_4, s1_hazard_lo_lo_4}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_4 = {_s1_hazard_T_78, _s1_hazard_T_77}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_4 = {_s1_hazard_T_80, _s1_hazard_T_79}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_4 = {s1_hazard_hi_hi_4, s1_hazard_hi_lo_4}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_81 = {s1_hazard_hi_4, s1_hazard_lo_4}; // @[package.scala:45:27] wire _s1_hazard_T_82 = _s1_hazard_T_81[0]; // @[package.scala:45:27] wire _s1_hazard_T_83 = _s1_hazard_T_81[1]; // @[package.scala:45:27] wire _s1_hazard_T_84 = _s1_hazard_T_81[2]; // @[package.scala:45:27] wire _s1_hazard_T_85 = _s1_hazard_T_81[3]; // @[package.scala:45:27] wire _s1_hazard_T_86 = _s1_hazard_T_81[4]; // @[package.scala:45:27] wire _s1_hazard_T_87 = _s1_hazard_T_81[5]; // @[package.scala:45:27] wire _s1_hazard_T_88 = _s1_hazard_T_81[6]; // @[package.scala:45:27] wire _s1_hazard_T_89 = _s1_hazard_T_81[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_5 = {_s1_hazard_T_83, _s1_hazard_T_82}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_5 = {_s1_hazard_T_85, _s1_hazard_T_84}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_5 = {s1_hazard_lo_hi_5, s1_hazard_lo_lo_5}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_5 = {_s1_hazard_T_87, _s1_hazard_T_86}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_5 = {_s1_hazard_T_89, _s1_hazard_T_88}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_5 = {s1_hazard_hi_hi_5, s1_hazard_hi_lo_5}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_90 = {s1_hazard_hi_5, s1_hazard_lo_5}; // @[DCache.scala:1182:52] wire _s1_hazard_T_99 = _s1_hazard_T_91; // @[package.scala:211:50] wire _s1_hazard_T_100 = _s1_hazard_T_92; // @[package.scala:211:50] wire _s1_hazard_T_101 = _s1_hazard_T_93; // @[package.scala:211:50] wire _s1_hazard_T_102 = _s1_hazard_T_94; // @[package.scala:211:50] wire _s1_hazard_T_103 = _s1_hazard_T_95; // @[package.scala:211:50] wire _s1_hazard_T_104 = _s1_hazard_T_96; // @[package.scala:211:50] wire _s1_hazard_T_105 = _s1_hazard_T_97; // @[package.scala:211:50] wire _s1_hazard_T_106 = _s1_hazard_T_98; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_6 = {_s1_hazard_T_100, _s1_hazard_T_99}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_6 = {_s1_hazard_T_102, _s1_hazard_T_101}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_6 = {s1_hazard_lo_hi_6, s1_hazard_lo_lo_6}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_6 = {_s1_hazard_T_104, _s1_hazard_T_103}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_6 = {_s1_hazard_T_106, _s1_hazard_T_105}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_6 = {s1_hazard_hi_hi_6, s1_hazard_hi_lo_6}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_107 = {s1_hazard_hi_6, s1_hazard_lo_6}; // @[package.scala:45:27] wire _s1_hazard_T_108 = _s1_hazard_T_107[0]; // @[package.scala:45:27] wire _s1_hazard_T_109 = _s1_hazard_T_107[1]; // @[package.scala:45:27] wire _s1_hazard_T_110 = _s1_hazard_T_107[2]; // @[package.scala:45:27] wire _s1_hazard_T_111 = _s1_hazard_T_107[3]; // @[package.scala:45:27] wire _s1_hazard_T_112 = _s1_hazard_T_107[4]; // @[package.scala:45:27] wire _s1_hazard_T_113 = _s1_hazard_T_107[5]; // @[package.scala:45:27] wire _s1_hazard_T_114 = _s1_hazard_T_107[6]; // @[package.scala:45:27] wire _s1_hazard_T_115 = _s1_hazard_T_107[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_7 = {_s1_hazard_T_109, _s1_hazard_T_108}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_7 = {_s1_hazard_T_111, _s1_hazard_T_110}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_7 = {s1_hazard_lo_hi_7, s1_hazard_lo_lo_7}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_7 = {_s1_hazard_T_113, _s1_hazard_T_112}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_7 = {_s1_hazard_T_115, _s1_hazard_T_114}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_7 = {s1_hazard_hi_hi_7, s1_hazard_hi_lo_7}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_116 = {s1_hazard_hi_7, s1_hazard_lo_7}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_117 = _s1_hazard_T_90 & _s1_hazard_T_116; // @[DCache.scala:562:38, :1182:52] wire _s1_hazard_T_118 = |_s1_hazard_T_117; // @[DCache.scala:562:{38,66}] wire [7:0] _s1_hazard_T_119 = pstore2_storegen_mask & s1_mask_xwr; // @[DCache.scala:531:19, :562:77] wire _s1_hazard_T_120 = |_s1_hazard_T_119; // @[DCache.scala:562:{77,92}] wire _s1_hazard_T_121 = s1_write ? _s1_hazard_T_118 : _s1_hazard_T_120; // @[DCache.scala:562:{8,66,92}] wire _s1_hazard_T_122 = _s1_hazard_T_64 & _s1_hazard_T_121; // @[DCache.scala:561:{31,65}, :562:8] wire _s1_hazard_T_123 = pstore2_valid & _s1_hazard_T_122; // @[DCache.scala:501:30, :561:65, :565:21] wire s1_hazard = _s1_hazard_T_61 | _s1_hazard_T_123; // @[DCache.scala:564:{27,69}, :565:21] wire s1_raw_hazard = s1_read & s1_hazard; // @[DCache.scala:564:69, :566:31] wire _T_68 = s1_valid & s1_raw_hazard; // @[DCache.scala:182:25, :566:31, :571:18] reg io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:38] assign _io_cpu_s2_nack_cause_raw_T_3 = io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:{38,54}] assign io_cpu_s2_nack_cause_raw_0 = _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:101:7, :574:54] wire _a_source_T = ~uncachedInFlight_0; // @[DCache.scala:236:33, :577:34] wire [1:0] _a_source_T_1 = {_a_source_T, 1'h0}; // @[DCache.scala:577:{34,59}] wire _a_source_T_2 = _a_source_T_1[0]; // @[OneHot.scala:48:45] wire _a_source_T_3 = _a_source_T_1[1]; // @[OneHot.scala:48:45] wire a_source = ~_a_source_T_2; // @[OneHot.scala:48:45] wire get_source = a_source; // @[Mux.scala:50:70] wire put_source = a_source; // @[Mux.scala:50:70] wire putpartial_source = a_source; // @[Mux.scala:50:70] wire atomics_a_source = a_source; // @[Mux.scala:50:70] wire atomics_a_1_source = a_source; // @[Mux.scala:50:70] wire atomics_a_2_source = a_source; // @[Mux.scala:50:70] wire atomics_a_3_source = a_source; // @[Mux.scala:50:70] wire atomics_a_4_source = a_source; // @[Mux.scala:50:70] wire atomics_a_5_source = a_source; // @[Mux.scala:50:70] wire atomics_a_6_source = a_source; // @[Mux.scala:50:70] wire atomics_a_7_source = a_source; // @[Mux.scala:50:70] wire atomics_a_8_source = a_source; // @[Mux.scala:50:70] wire a_sel_shiftAmount = a_source; // @[OneHot.scala:64:49] wire [39:0] acquire_address = {_acquire_address_T, 6'h0}; // @[DCache.scala:578:{38,49}] wire [127:0] a_data = {2{pstore1_data}}; // @[DCache.scala:494:31, :581:20] wire [127:0] put_data = a_data; // @[Edges.scala:480:17] wire [127:0] putpartial_data = a_data; // @[Edges.scala:500:17] wire [127:0] atomics_a_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_1_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_2_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_3_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_4_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_5_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_6_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_7_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_8_data = a_data; // @[Edges.scala:517:17] wire [3:0] _a_mask_T_1 = {_a_mask_T, 3'h0}; // @[package.scala:163:13] wire [22:0] a_mask = {15'h0, pstore1_mask} << _a_mask_T_1; // @[DCache.scala:496:31, :582:{29,90}] wire [39:0] _GEN_102 = {s2_req_addr[39:14], s2_req_addr[13:0] ^ 14'h3000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_4; // @[Parameters.scala:137:31] assign _get_legal_T_4 = _GEN_102; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_4; // @[Parameters.scala:137:31] assign _put_legal_T_4 = _GEN_102; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_4; // @[Parameters.scala:137:31] assign _putpartial_legal_T_4 = _GEN_102; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_6 = _get_legal_T_5 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46] wire _get_legal_T_8 = _get_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54] wire _get_legal_T_62 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_16 = _get_legal_T_15 & 41'h9A012000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46] wire _get_legal_T_18 = _get_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_103 = {s2_req_addr[39:17], s2_req_addr[16:0] ^ 17'h10000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_19; // @[Parameters.scala:137:31] assign _get_legal_T_19 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_24; // @[Parameters.scala:137:31] assign _get_legal_T_24 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_63; // @[Parameters.scala:137:31] assign _put_legal_T_63 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_63; // @[Parameters.scala:137:31] assign _putpartial_legal_T_63 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_35; // @[Parameters.scala:137:31] assign _atomics_legal_T_35 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_94; // @[Parameters.scala:137:31] assign _atomics_legal_T_94 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_153; // @[Parameters.scala:137:31] assign _atomics_legal_T_153 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_212; // @[Parameters.scala:137:31] assign _atomics_legal_T_212 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_271; // @[Parameters.scala:137:31] assign _atomics_legal_T_271 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_330; // @[Parameters.scala:137:31] assign _atomics_legal_T_330 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_389; // @[Parameters.scala:137:31] assign _atomics_legal_T_389 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_448; // @[Parameters.scala:137:31] assign _atomics_legal_T_448 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_507; // @[Parameters.scala:137:31] assign _atomics_legal_T_507 = _GEN_103; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_21 = _get_legal_T_20 & 41'h98013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46] wire _get_legal_T_23 = _get_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_26 = _get_legal_T_25 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46] wire _get_legal_T_28 = _get_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_104 = {s2_req_addr[39:26], s2_req_addr[25:0] ^ 26'h2000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_29; // @[Parameters.scala:137:31] assign _get_legal_T_29 = _GEN_104; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_24; // @[Parameters.scala:137:31] assign _put_legal_T_24 = _GEN_104; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_24; // @[Parameters.scala:137:31] assign _putpartial_legal_T_24 = _GEN_104; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_31 = _get_legal_T_30 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46] wire _get_legal_T_33 = _get_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_105 = {s2_req_addr[39:28], s2_req_addr[27:0] ^ 28'h8000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_34; // @[Parameters.scala:137:31] assign _get_legal_T_34 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_39; // @[Parameters.scala:137:31] assign _get_legal_T_39 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_34; // @[Parameters.scala:137:31] assign _put_legal_T_34 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_39; // @[Parameters.scala:137:31] assign _put_legal_T_39 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_34; // @[Parameters.scala:137:31] assign _putpartial_legal_T_34 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_39; // @[Parameters.scala:137:31] assign _putpartial_legal_T_39 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_45; // @[Parameters.scala:137:31] assign _atomics_legal_T_45 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_104; // @[Parameters.scala:137:31] assign _atomics_legal_T_104 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_163; // @[Parameters.scala:137:31] assign _atomics_legal_T_163 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_222; // @[Parameters.scala:137:31] assign _atomics_legal_T_222 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_281; // @[Parameters.scala:137:31] assign _atomics_legal_T_281 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_340; // @[Parameters.scala:137:31] assign _atomics_legal_T_340 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_399; // @[Parameters.scala:137:31] assign _atomics_legal_T_399 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_458; // @[Parameters.scala:137:31] assign _atomics_legal_T_458 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_517; // @[Parameters.scala:137:31] assign _atomics_legal_T_517 = _GEN_105; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_36 = _get_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46] wire _get_legal_T_38 = _get_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_41 = _get_legal_T_40 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46] wire _get_legal_T_43 = _get_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_106 = {s2_req_addr[39:29], s2_req_addr[28:0] ^ 29'h10000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_44; // @[Parameters.scala:137:31] assign _get_legal_T_44 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_44; // @[Parameters.scala:137:31] assign _put_legal_T_44 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_44; // @[Parameters.scala:137:31] assign _putpartial_legal_T_44 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_24; // @[Parameters.scala:137:31] assign _atomics_legal_T_24 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_83; // @[Parameters.scala:137:31] assign _atomics_legal_T_83 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_142; // @[Parameters.scala:137:31] assign _atomics_legal_T_142 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_201; // @[Parameters.scala:137:31] assign _atomics_legal_T_201 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_260; // @[Parameters.scala:137:31] assign _atomics_legal_T_260 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_319; // @[Parameters.scala:137:31] assign _atomics_legal_T_319 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_378; // @[Parameters.scala:137:31] assign _atomics_legal_T_378 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_437; // @[Parameters.scala:137:31] assign _atomics_legal_T_437 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_496; // @[Parameters.scala:137:31] assign _atomics_legal_T_496 = _GEN_106; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_46 = _get_legal_T_45 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46] wire _get_legal_T_48 = _get_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] assign io_cpu_s2_paddr_0 = s2_req_addr[31:0]; // @[DCache.scala:101:7, :339:19] wire [31:0] get_address = s2_req_addr[31:0]; // @[Edges.scala:460:17] wire [31:0] put_address = s2_req_addr[31:0]; // @[Edges.scala:480:17] wire [31:0] putpartial_address = s2_req_addr[31:0]; // @[Edges.scala:500:17] wire [31:0] atomics_a_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_1_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_2_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_3_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_4_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_5_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_6_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_7_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_8_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [39:0] _GEN_107 = {s2_req_addr[39:32], s2_req_addr[31:0] ^ 32'h80000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_49; // @[Parameters.scala:137:31] assign _get_legal_T_49 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_49; // @[Parameters.scala:137:31] assign _put_legal_T_49 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_49; // @[Parameters.scala:137:31] assign _putpartial_legal_T_49 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_50; // @[Parameters.scala:137:31] assign _atomics_legal_T_50 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_109; // @[Parameters.scala:137:31] assign _atomics_legal_T_109 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_168; // @[Parameters.scala:137:31] assign _atomics_legal_T_168 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_227; // @[Parameters.scala:137:31] assign _atomics_legal_T_227 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_286; // @[Parameters.scala:137:31] assign _atomics_legal_T_286 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_345; // @[Parameters.scala:137:31] assign _atomics_legal_T_345 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_404; // @[Parameters.scala:137:31] assign _atomics_legal_T_404 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_463; // @[Parameters.scala:137:31] assign _atomics_legal_T_463 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_522; // @[Parameters.scala:137:31] assign _atomics_legal_T_522 = _GEN_107; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_50 = {1'h0, _get_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_51 = _get_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_52 = _get_legal_T_51; // @[Parameters.scala:137:46] wire _get_legal_T_53 = _get_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_54 = _get_legal_T_18 | _get_legal_T_23; // @[Parameters.scala:685:42] wire _get_legal_T_55 = _get_legal_T_54 | _get_legal_T_28; // @[Parameters.scala:685:42] wire _get_legal_T_56 = _get_legal_T_55 | _get_legal_T_33; // @[Parameters.scala:685:42] wire _get_legal_T_57 = _get_legal_T_56 | _get_legal_T_38; // @[Parameters.scala:685:42] wire _get_legal_T_58 = _get_legal_T_57 | _get_legal_T_43; // @[Parameters.scala:685:42] wire _get_legal_T_59 = _get_legal_T_58 | _get_legal_T_48; // @[Parameters.scala:685:42] wire _get_legal_T_60 = _get_legal_T_59 | _get_legal_T_53; // @[Parameters.scala:685:42] wire _get_legal_T_61 = _get_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire get_legal = _get_legal_T_62 | _get_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [15:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_size; // @[Edges.scala:460:17] wire [15:0] get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_108 = {2'h0, s2_req_size}; // @[Edges.scala:463:15] assign get_size = _GEN_108; // @[Edges.scala:460:17, :463:15] wire [3:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_108; // @[Misc.scala:202:34] wire [3:0] put_size; // @[Edges.scala:480:17] assign put_size = _GEN_108; // @[Edges.scala:463:15, :480:17] wire [3:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _put_a_mask_sizeOH_T = _GEN_108; // @[Misc.scala:202:34] wire [3:0] putpartial_size; // @[Edges.scala:500:17] assign putpartial_size = _GEN_108; // @[Edges.scala:463:15, :500:17] wire [3:0] atomics_a_size; // @[Edges.scala:534:17] assign atomics_a_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17] assign atomics_a_1_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_3 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17] assign atomics_a_2_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_6 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17] assign atomics_a_3_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_9 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17] assign atomics_a_4_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_12 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17] assign atomics_a_5_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_15 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17] assign atomics_a_6_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_18 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17] assign atomics_a_7_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_21 = _GEN_108; // @[Misc.scala:202:34] wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17] assign atomics_a_8_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_24 = _GEN_108; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_size = get_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_sub_1_2 = get_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_a_mask_sub_sub_sub_nbit = ~get_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_sub_0_2 = get_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_sub_acc_T = get_a_mask_sub_sub_sub_size & get_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_sub_0_1 = _get_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _get_a_mask_sub_sub_sub_acc_T_1 = get_a_mask_sub_sub_sub_size & get_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_sub_1_1 = _get_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_1 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_2 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_3 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_4 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_5 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_6 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_7 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_8 = s2_req_addr[2]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_word_bypass_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26] wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_sub_0_2 & get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_sub_0_2 & get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_2_2 = get_a_mask_sub_sub_sub_1_2 & get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T_2 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_2_1 = get_a_mask_sub_sub_sub_1_1 | _get_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_3_2 = get_a_mask_sub_sub_sub_1_2 & get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_sub_acc_T_3 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_3_1 = get_a_mask_sub_sub_sub_1_1 | _get_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire put_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_1 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_2 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_3 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_4 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_5 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_6 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_7 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_8 = s2_req_addr[1]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T_3 = s2_req_addr[1]; // @[Misc.scala:210:26] wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_4_2 = get_a_mask_sub_sub_2_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_4 = get_a_mask_sub_size & get_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_4_1 = get_a_mask_sub_sub_2_1 | _get_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_5_2 = get_a_mask_sub_sub_2_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_5 = get_a_mask_sub_size & get_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_5_1 = get_a_mask_sub_sub_2_1 | _get_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_6_2 = get_a_mask_sub_sub_3_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_6 = get_a_mask_sub_size & get_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_6_1 = get_a_mask_sub_sub_3_1 | _get_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_7_2 = get_a_mask_sub_sub_3_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_7 = get_a_mask_sub_size & get_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_7_1 = get_a_mask_sub_sub_3_1 | _get_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire put_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_1 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_2 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_3 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_4 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_5 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_6 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_7 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_8 = s2_req_addr[0]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T_6 = s2_req_addr[0]; // @[Misc.scala:210:26] wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 | _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_1 = get_a_mask_sub_0_1 | _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_2 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_3 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_4 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_5 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_6 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_7 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_8 = get_a_mask_sub_4_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_8 = get_a_mask_size & get_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_8 = get_a_mask_sub_4_1 | _get_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_9 = get_a_mask_sub_4_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_9 = get_a_mask_size & get_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_9 = get_a_mask_sub_4_1 | _get_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_10 = get_a_mask_sub_5_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_10 = get_a_mask_size & get_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_10 = get_a_mask_sub_5_1 | _get_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_11 = get_a_mask_sub_5_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_11 = get_a_mask_size & get_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_11 = get_a_mask_sub_5_1 | _get_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_12 = get_a_mask_sub_6_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_12 = get_a_mask_size & get_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_12 = get_a_mask_sub_6_1 | _get_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_13 = get_a_mask_sub_6_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_13 = get_a_mask_size & get_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_13 = get_a_mask_sub_6_1 | _get_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_14 = get_a_mask_sub_7_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_14 = get_a_mask_size & get_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_14 = get_a_mask_sub_7_1 | _get_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_15 = get_a_mask_sub_7_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_15 = get_a_mask_size & get_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_15 = get_a_mask_sub_7_1 | _get_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo_lo = {get_a_mask_lo_lo_hi, get_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_lo_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo_hi = {get_a_mask_lo_hi_hi, get_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo_lo = {get_a_mask_acc_9, get_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_lo_hi = {get_a_mask_acc_11, get_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi_lo = {get_a_mask_hi_lo_hi, get_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_hi_lo = {get_a_mask_acc_13, get_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi_hi = {get_a_mask_acc_15, get_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi_hi = {get_a_mask_hi_hi_hi, get_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_6 = _put_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46] wire _put_legal_T_8 = _put_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54] wire _put_legal_T_69 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_16 = _put_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46] wire _put_legal_T_18 = _put_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_109 = {s2_req_addr[39:21], s2_req_addr[20:0] ^ 21'h100000}; // @[DCache.scala:339:19] wire [39:0] _put_legal_T_19; // @[Parameters.scala:137:31] assign _put_legal_T_19 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_19; // @[Parameters.scala:137:31] assign _putpartial_legal_T_19 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_9; // @[Parameters.scala:137:31] assign _atomics_legal_T_9 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_68; // @[Parameters.scala:137:31] assign _atomics_legal_T_68 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_127; // @[Parameters.scala:137:31] assign _atomics_legal_T_127 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_186; // @[Parameters.scala:137:31] assign _atomics_legal_T_186 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_245; // @[Parameters.scala:137:31] assign _atomics_legal_T_245 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_304; // @[Parameters.scala:137:31] assign _atomics_legal_T_304 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_363; // @[Parameters.scala:137:31] assign _atomics_legal_T_363 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_422; // @[Parameters.scala:137:31] assign _atomics_legal_T_422 = _GEN_109; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_481; // @[Parameters.scala:137:31] assign _atomics_legal_T_481 = _GEN_109; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_21 = _put_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46] wire _put_legal_T_23 = _put_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_26 = _put_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46] wire _put_legal_T_28 = _put_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_110 = {s2_req_addr[39:26], s2_req_addr[25:0] ^ 26'h2010000}; // @[DCache.scala:339:19] wire [39:0] _put_legal_T_29; // @[Parameters.scala:137:31] assign _put_legal_T_29 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_29; // @[Parameters.scala:137:31] assign _putpartial_legal_T_29 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_14; // @[Parameters.scala:137:31] assign _atomics_legal_T_14 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_73; // @[Parameters.scala:137:31] assign _atomics_legal_T_73 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_132; // @[Parameters.scala:137:31] assign _atomics_legal_T_132 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_191; // @[Parameters.scala:137:31] assign _atomics_legal_T_191 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_250; // @[Parameters.scala:137:31] assign _atomics_legal_T_250 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_309; // @[Parameters.scala:137:31] assign _atomics_legal_T_309 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_368; // @[Parameters.scala:137:31] assign _atomics_legal_T_368 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_427; // @[Parameters.scala:137:31] assign _atomics_legal_T_427 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_486; // @[Parameters.scala:137:31] assign _atomics_legal_T_486 = _GEN_110; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_31 = _put_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46] wire _put_legal_T_33 = _put_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_36 = _put_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46] wire _put_legal_T_38 = _put_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_40 = {1'h0, _put_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_41 = _put_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_42 = _put_legal_T_41; // @[Parameters.scala:137:46] wire _put_legal_T_43 = _put_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_45 = {1'h0, _put_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_46 = _put_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_47 = _put_legal_T_46; // @[Parameters.scala:137:46] wire _put_legal_T_48 = _put_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_50 = {1'h0, _put_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_51 = _put_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_52 = _put_legal_T_51; // @[Parameters.scala:137:46] wire _put_legal_T_53 = _put_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_54 = _put_legal_T_18 | _put_legal_T_23; // @[Parameters.scala:685:42] wire _put_legal_T_55 = _put_legal_T_54 | _put_legal_T_28; // @[Parameters.scala:685:42] wire _put_legal_T_56 = _put_legal_T_55 | _put_legal_T_33; // @[Parameters.scala:685:42] wire _put_legal_T_57 = _put_legal_T_56 | _put_legal_T_38; // @[Parameters.scala:685:42] wire _put_legal_T_58 = _put_legal_T_57 | _put_legal_T_43; // @[Parameters.scala:685:42] wire _put_legal_T_59 = _put_legal_T_58 | _put_legal_T_48; // @[Parameters.scala:685:42] wire _put_legal_T_60 = _put_legal_T_59 | _put_legal_T_53; // @[Parameters.scala:685:42] wire _put_legal_T_61 = _put_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [40:0] _put_legal_T_64 = {1'h0, _put_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_65 = _put_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_66 = _put_legal_T_65; // @[Parameters.scala:137:46] wire _put_legal_T_67 = _put_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_70 = _put_legal_T_69 | _put_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire put_legal = _put_legal_T_70; // @[Parameters.scala:686:26] wire [15:0] _put_a_mask_T; // @[Misc.scala:222:10] wire [15:0] put_mask; // @[Edges.scala:480:17] wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire put_a_mask_sub_sub_sub_size = put_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_sub_1_2 = put_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire put_a_mask_sub_sub_sub_nbit = ~put_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_sub_0_2 = put_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_sub_acc_T = put_a_mask_sub_sub_sub_size & put_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_sub_0_1 = _put_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _put_a_mask_sub_sub_sub_acc_T_1 = put_a_mask_sub_sub_sub_size & put_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_sub_1_1 = _put_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_sub_0_2 & put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_sub_0_2 & put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_2_2 = put_a_mask_sub_sub_sub_1_2 & put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T_2 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_2_1 = put_a_mask_sub_sub_sub_1_1 | _put_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_3_2 = put_a_mask_sub_sub_sub_1_2 & put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_sub_acc_T_3 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_3_1 = put_a_mask_sub_sub_sub_1_1 | _put_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_4_2 = put_a_mask_sub_sub_2_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_4 = put_a_mask_sub_size & put_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_4_1 = put_a_mask_sub_sub_2_1 | _put_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_5_2 = put_a_mask_sub_sub_2_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_5 = put_a_mask_sub_size & put_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_5_1 = put_a_mask_sub_sub_2_1 | _put_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_6_2 = put_a_mask_sub_sub_3_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_6 = put_a_mask_sub_size & put_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_6_1 = put_a_mask_sub_sub_3_1 | _put_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_7_2 = put_a_mask_sub_sub_3_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_7 = put_a_mask_sub_size & put_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_7_1 = put_a_mask_sub_sub_3_1 | _put_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc = put_a_mask_sub_0_1 | _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_1 = put_a_mask_sub_0_1 | _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_2 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_3 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_4 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_5 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_6 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_7 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_8 = put_a_mask_sub_4_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_8 = put_a_mask_size & put_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_8 = put_a_mask_sub_4_1 | _put_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_9 = put_a_mask_sub_4_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_9 = put_a_mask_size & put_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_9 = put_a_mask_sub_4_1 | _put_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_10 = put_a_mask_sub_5_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_10 = put_a_mask_size & put_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_10 = put_a_mask_sub_5_1 | _put_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_11 = put_a_mask_sub_5_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_11 = put_a_mask_size & put_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_11 = put_a_mask_sub_5_1 | _put_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_12 = put_a_mask_sub_6_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_12 = put_a_mask_size & put_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_12 = put_a_mask_sub_6_1 | _put_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_13 = put_a_mask_sub_6_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_13 = put_a_mask_size & put_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_13 = put_a_mask_sub_6_1 | _put_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_14 = put_a_mask_sub_7_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_14 = put_a_mask_size & put_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_14 = put_a_mask_sub_7_1 | _put_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_15 = put_a_mask_sub_7_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_15 = put_a_mask_size & put_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_15 = put_a_mask_sub_7_1 | _put_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] put_a_mask_lo_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo_lo = {put_a_mask_lo_lo_hi, put_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_lo_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo_hi = {put_a_mask_lo_hi_hi, put_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_lo_lo = {put_a_mask_acc_9, put_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_lo_hi = {put_a_mask_acc_11, put_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi_lo = {put_a_mask_hi_lo_hi, put_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_hi_lo = {put_a_mask_acc_13, put_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_hi_hi = {put_a_mask_acc_15, put_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi_hi = {put_a_mask_hi_hi_hi, put_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10] assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _putpartial_legal_T_5 = {1'h0, _putpartial_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_6 = _putpartial_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_7 = _putpartial_legal_T_6; // @[Parameters.scala:137:46] wire _putpartial_legal_T_8 = _putpartial_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_9 = _putpartial_legal_T_8; // @[Parameters.scala:684:54] wire _putpartial_legal_T_69 = _putpartial_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _putpartial_legal_T_15 = {1'h0, _putpartial_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_16 = _putpartial_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_17 = _putpartial_legal_T_16; // @[Parameters.scala:137:46] wire _putpartial_legal_T_18 = _putpartial_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_20 = {1'h0, _putpartial_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_21 = _putpartial_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_22 = _putpartial_legal_T_21; // @[Parameters.scala:137:46] wire _putpartial_legal_T_23 = _putpartial_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_25 = {1'h0, _putpartial_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_26 = _putpartial_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_27 = _putpartial_legal_T_26; // @[Parameters.scala:137:46] wire _putpartial_legal_T_28 = _putpartial_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_30 = {1'h0, _putpartial_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_31 = _putpartial_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_32 = _putpartial_legal_T_31; // @[Parameters.scala:137:46] wire _putpartial_legal_T_33 = _putpartial_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_35 = {1'h0, _putpartial_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_36 = _putpartial_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_37 = _putpartial_legal_T_36; // @[Parameters.scala:137:46] wire _putpartial_legal_T_38 = _putpartial_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_40 = {1'h0, _putpartial_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_41 = _putpartial_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_42 = _putpartial_legal_T_41; // @[Parameters.scala:137:46] wire _putpartial_legal_T_43 = _putpartial_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_45 = {1'h0, _putpartial_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_46 = _putpartial_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_47 = _putpartial_legal_T_46; // @[Parameters.scala:137:46] wire _putpartial_legal_T_48 = _putpartial_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_50 = {1'h0, _putpartial_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_51 = _putpartial_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_52 = _putpartial_legal_T_51; // @[Parameters.scala:137:46] wire _putpartial_legal_T_53 = _putpartial_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_54 = _putpartial_legal_T_18 | _putpartial_legal_T_23; // @[Parameters.scala:685:42] wire _putpartial_legal_T_55 = _putpartial_legal_T_54 | _putpartial_legal_T_28; // @[Parameters.scala:685:42] wire _putpartial_legal_T_56 = _putpartial_legal_T_55 | _putpartial_legal_T_33; // @[Parameters.scala:685:42] wire _putpartial_legal_T_57 = _putpartial_legal_T_56 | _putpartial_legal_T_38; // @[Parameters.scala:685:42] wire _putpartial_legal_T_58 = _putpartial_legal_T_57 | _putpartial_legal_T_43; // @[Parameters.scala:685:42] wire _putpartial_legal_T_59 = _putpartial_legal_T_58 | _putpartial_legal_T_48; // @[Parameters.scala:685:42] wire _putpartial_legal_T_60 = _putpartial_legal_T_59 | _putpartial_legal_T_53; // @[Parameters.scala:685:42] wire _putpartial_legal_T_61 = _putpartial_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [40:0] _putpartial_legal_T_64 = {1'h0, _putpartial_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_65 = _putpartial_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_66 = _putpartial_legal_T_65; // @[Parameters.scala:137:46] wire _putpartial_legal_T_67 = _putpartial_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_70 = _putpartial_legal_T_69 | _putpartial_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire putpartial_legal = _putpartial_legal_T_70; // @[Parameters.scala:686:26] wire [15:0] putpartial_mask; // @[Edges.scala:500:17] assign putpartial_mask = a_mask[15:0]; // @[Edges.scala:500:17, :508:15] wire [40:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46] wire _atomics_legal_T_8 = _atomics_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46] wire _atomics_legal_T_13 = _atomics_legal_T_12 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46] wire _atomics_legal_T_18 = _atomics_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_111 = {s2_req_addr[39:28], s2_req_addr[27:0] ^ 28'hC000000}; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_19; // @[Parameters.scala:137:31] assign _atomics_legal_T_19 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_78; // @[Parameters.scala:137:31] assign _atomics_legal_T_78 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_137; // @[Parameters.scala:137:31] assign _atomics_legal_T_137 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_196; // @[Parameters.scala:137:31] assign _atomics_legal_T_196 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_255; // @[Parameters.scala:137:31] assign _atomics_legal_T_255 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_314; // @[Parameters.scala:137:31] assign _atomics_legal_T_314 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_373; // @[Parameters.scala:137:31] assign _atomics_legal_T_373 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_432; // @[Parameters.scala:137:31] assign _atomics_legal_T_432 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_491; // @[Parameters.scala:137:31] assign _atomics_legal_T_491 = _GEN_111; // @[Parameters.scala:137:31] wire [40:0] _atomics_legal_T_20 = {1'h0, _atomics_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_21 = _atomics_legal_T_20 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_22 = _atomics_legal_T_21; // @[Parameters.scala:137:46] wire _atomics_legal_T_23 = _atomics_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_26 = _atomics_legal_T_25 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_27 = _atomics_legal_T_26; // @[Parameters.scala:137:46] wire _atomics_legal_T_28 = _atomics_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_29 = _atomics_legal_T_8 | _atomics_legal_T_13; // @[Parameters.scala:685:42] wire _atomics_legal_T_30 = _atomics_legal_T_29 | _atomics_legal_T_18; // @[Parameters.scala:685:42] wire _atomics_legal_T_31 = _atomics_legal_T_30 | _atomics_legal_T_23; // @[Parameters.scala:685:42] wire _atomics_legal_T_32 = _atomics_legal_T_31 | _atomics_legal_T_28; // @[Parameters.scala:685:42] wire _atomics_legal_T_33 = _atomics_legal_T_32; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_57 = _atomics_legal_T_33; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_36 = {1'h0, _atomics_legal_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_37 = _atomics_legal_T_36 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_38 = _atomics_legal_T_37; // @[Parameters.scala:137:46] wire _atomics_legal_T_39 = _atomics_legal_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_46 = {1'h0, _atomics_legal_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_47 = _atomics_legal_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_48 = _atomics_legal_T_47; // @[Parameters.scala:137:46] wire _atomics_legal_T_49 = _atomics_legal_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_51 = {1'h0, _atomics_legal_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_52 = _atomics_legal_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_53 = _atomics_legal_T_52; // @[Parameters.scala:137:46] wire _atomics_legal_T_54 = _atomics_legal_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_55 = _atomics_legal_T_49 | _atomics_legal_T_54; // @[Parameters.scala:685:42] wire _atomics_legal_T_56 = _atomics_legal_T_55; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_58 = _atomics_legal_T_57; // @[Parameters.scala:686:26] wire atomics_legal = _atomics_legal_T_58 | _atomics_legal_T_56; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T; // @[Misc.scala:222:10] wire [15:0] atomics_a_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size = atomics_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2 = atomics_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit = ~atomics_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2 = atomics_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T = atomics_a_mask_sub_sub_sub_size & atomics_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1 = _atomics_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_sub_size & atomics_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_sub_0_2 & atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_sub_0_2 & atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2 = atomics_a_mask_sub_sub_sub_1_2 & atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1 = atomics_a_mask_sub_sub_sub_1_1 | _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2 = atomics_a_mask_sub_sub_sub_1_2 & atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1 = atomics_a_mask_sub_sub_sub_1_1 | _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2 = atomics_a_mask_sub_sub_2_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size & atomics_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1 = atomics_a_mask_sub_sub_2_1 | _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2 = atomics_a_mask_sub_sub_2_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size & atomics_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1 = atomics_a_mask_sub_sub_2_1 | _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2 = atomics_a_mask_sub_sub_3_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size & atomics_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1 = atomics_a_mask_sub_sub_3_1 | _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2 = atomics_a_mask_sub_sub_3_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size & atomics_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1 = atomics_a_mask_sub_sub_3_1 | _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_8 = atomics_a_mask_sub_4_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_8 = atomics_a_mask_sub_4_1 | _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_9 = atomics_a_mask_sub_4_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_9 = atomics_a_mask_sub_4_1 | _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_10 = atomics_a_mask_sub_5_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_10 = atomics_a_mask_sub_5_1 | _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_11 = atomics_a_mask_sub_5_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_11 = atomics_a_mask_sub_5_1 | _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_12 = atomics_a_mask_sub_6_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_12 = atomics_a_mask_sub_6_1 | _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_13 = atomics_a_mask_sub_6_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_13 = atomics_a_mask_sub_6_1 | _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_14 = atomics_a_mask_sub_7_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_14 = atomics_a_mask_sub_7_1 | _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_15 = atomics_a_mask_sub_7_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_15 = atomics_a_mask_sub_7_1 | _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo = {atomics_a_mask_lo_lo_hi, atomics_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi = {atomics_a_mask_lo_hi_hi, atomics_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo = {atomics_a_mask_hi_lo_hi, atomics_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi = {atomics_a_mask_hi_hi_hi, atomics_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10] assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_64 = {1'h0, _atomics_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_65 = _atomics_legal_T_64 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_66 = _atomics_legal_T_65; // @[Parameters.scala:137:46] wire _atomics_legal_T_67 = _atomics_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_69 = {1'h0, _atomics_legal_T_68}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_70 = _atomics_legal_T_69 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_71 = _atomics_legal_T_70; // @[Parameters.scala:137:46] wire _atomics_legal_T_72 = _atomics_legal_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_74 = {1'h0, _atomics_legal_T_73}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_75 = _atomics_legal_T_74 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_76 = _atomics_legal_T_75; // @[Parameters.scala:137:46] wire _atomics_legal_T_77 = _atomics_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_79 = {1'h0, _atomics_legal_T_78}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_80 = _atomics_legal_T_79 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:137:46] wire _atomics_legal_T_82 = _atomics_legal_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46] wire _atomics_legal_T_87 = _atomics_legal_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_88 = _atomics_legal_T_67 | _atomics_legal_T_72; // @[Parameters.scala:685:42] wire _atomics_legal_T_89 = _atomics_legal_T_88 | _atomics_legal_T_77; // @[Parameters.scala:685:42] wire _atomics_legal_T_90 = _atomics_legal_T_89 | _atomics_legal_T_82; // @[Parameters.scala:685:42] wire _atomics_legal_T_91 = _atomics_legal_T_90 | _atomics_legal_T_87; // @[Parameters.scala:685:42] wire _atomics_legal_T_92 = _atomics_legal_T_91; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_116 = _atomics_legal_T_92; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_95 = {1'h0, _atomics_legal_T_94}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_96 = _atomics_legal_T_95 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_97 = _atomics_legal_T_96; // @[Parameters.scala:137:46] wire _atomics_legal_T_98 = _atomics_legal_T_97 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_105 = {1'h0, _atomics_legal_T_104}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_106 = _atomics_legal_T_105 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_107 = _atomics_legal_T_106; // @[Parameters.scala:137:46] wire _atomics_legal_T_108 = _atomics_legal_T_107 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_110 = {1'h0, _atomics_legal_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_111 = _atomics_legal_T_110 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_112 = _atomics_legal_T_111; // @[Parameters.scala:137:46] wire _atomics_legal_T_113 = _atomics_legal_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_114 = _atomics_legal_T_108 | _atomics_legal_T_113; // @[Parameters.scala:685:42] wire _atomics_legal_T_115 = _atomics_legal_T_114; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_117 = _atomics_legal_T_116; // @[Parameters.scala:686:26] wire atomics_legal_1 = _atomics_legal_T_117 | _atomics_legal_T_115; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [15:0] atomics_a_1_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_1 = atomics_a_mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_1 = atomics_a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_1 = atomics_a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_sub_size_1 & atomics_a_mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_sub_size_1 & atomics_a_mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_sub_0_2_1 & atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_sub_0_2_1 & atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_1 = atomics_a_mask_sub_sub_sub_1_2_1 & atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_1 = atomics_a_mask_sub_sub_sub_1_1_1 | _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_1 = atomics_a_mask_sub_sub_sub_1_2_1 & atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_1 = atomics_a_mask_sub_sub_sub_1_1_1 | _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_1 = atomics_a_mask_sub_sub_2_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_1 = atomics_a_mask_sub_sub_2_1_1 | _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_1 = atomics_a_mask_sub_sub_2_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_1 = atomics_a_mask_sub_sub_2_1_1 | _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_1 = atomics_a_mask_sub_sub_3_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_1 = atomics_a_mask_sub_sub_3_1_1 | _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_1 = atomics_a_mask_sub_sub_3_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_1 = atomics_a_mask_sub_sub_3_1_1 | _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_1 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_1 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_1 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_1 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_1 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_1 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_1 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_1 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_24 = atomics_a_mask_sub_4_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_1 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_24 = atomics_a_mask_sub_4_1_1 | _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_25 = atomics_a_mask_sub_4_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_1 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_25 = atomics_a_mask_sub_4_1_1 | _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_26 = atomics_a_mask_sub_5_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_1 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_26 = atomics_a_mask_sub_5_1_1 | _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_27 = atomics_a_mask_sub_5_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_1 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_27 = atomics_a_mask_sub_5_1_1 | _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_28 = atomics_a_mask_sub_6_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_1 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_28 = atomics_a_mask_sub_6_1_1 | _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_29 = atomics_a_mask_sub_6_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_1 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_29 = atomics_a_mask_sub_6_1_1 | _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_30 = atomics_a_mask_sub_7_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_1 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_30 = atomics_a_mask_sub_7_1_1 | _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_31 = atomics_a_mask_sub_7_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_1 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_31 = atomics_a_mask_sub_7_1_1 | _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_1 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_1 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_lo_lo_hi_1, atomics_a_mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_1 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_1 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_lo_hi_hi_1, atomics_a_mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_1 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_1 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_hi_lo_hi_1, atomics_a_mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_1 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_1 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_hi_hi_hi_1, atomics_a_mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10] assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_123 = {1'h0, _atomics_legal_T_122}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_124 = _atomics_legal_T_123 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_125 = _atomics_legal_T_124; // @[Parameters.scala:137:46] wire _atomics_legal_T_126 = _atomics_legal_T_125 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_128 = {1'h0, _atomics_legal_T_127}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_129 = _atomics_legal_T_128 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_130 = _atomics_legal_T_129; // @[Parameters.scala:137:46] wire _atomics_legal_T_131 = _atomics_legal_T_130 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_133 = {1'h0, _atomics_legal_T_132}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_134 = _atomics_legal_T_133 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_135 = _atomics_legal_T_134; // @[Parameters.scala:137:46] wire _atomics_legal_T_136 = _atomics_legal_T_135 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_138 = {1'h0, _atomics_legal_T_137}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_139 = _atomics_legal_T_138 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_140 = _atomics_legal_T_139; // @[Parameters.scala:137:46] wire _atomics_legal_T_141 = _atomics_legal_T_140 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_143 = {1'h0, _atomics_legal_T_142}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_144 = _atomics_legal_T_143 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_145 = _atomics_legal_T_144; // @[Parameters.scala:137:46] wire _atomics_legal_T_146 = _atomics_legal_T_145 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_147 = _atomics_legal_T_126 | _atomics_legal_T_131; // @[Parameters.scala:685:42] wire _atomics_legal_T_148 = _atomics_legal_T_147 | _atomics_legal_T_136; // @[Parameters.scala:685:42] wire _atomics_legal_T_149 = _atomics_legal_T_148 | _atomics_legal_T_141; // @[Parameters.scala:685:42] wire _atomics_legal_T_150 = _atomics_legal_T_149 | _atomics_legal_T_146; // @[Parameters.scala:685:42] wire _atomics_legal_T_151 = _atomics_legal_T_150; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_175 = _atomics_legal_T_151; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_154 = {1'h0, _atomics_legal_T_153}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_155 = _atomics_legal_T_154 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_156 = _atomics_legal_T_155; // @[Parameters.scala:137:46] wire _atomics_legal_T_157 = _atomics_legal_T_156 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_164 = {1'h0, _atomics_legal_T_163}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_165 = _atomics_legal_T_164 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_166 = _atomics_legal_T_165; // @[Parameters.scala:137:46] wire _atomics_legal_T_167 = _atomics_legal_T_166 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_169 = {1'h0, _atomics_legal_T_168}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_170 = _atomics_legal_T_169 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_171 = _atomics_legal_T_170; // @[Parameters.scala:137:46] wire _atomics_legal_T_172 = _atomics_legal_T_171 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_173 = _atomics_legal_T_167 | _atomics_legal_T_172; // @[Parameters.scala:685:42] wire _atomics_legal_T_174 = _atomics_legal_T_173; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_176 = _atomics_legal_T_175; // @[Parameters.scala:686:26] wire atomics_legal_2 = _atomics_legal_T_176 | _atomics_legal_T_174; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [15:0] atomics_a_2_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_2 = atomics_a_mask_sizeOH_2[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_2 = atomics_a_mask_sub_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_2 = atomics_a_mask_sub_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_sub_size_2 & atomics_a_mask_sub_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_2 = _atomics_a_mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_sub_size_2 & atomics_a_mask_sub_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_2 = _atomics_a_mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_sub_0_2_2 & atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_sub_0_2_2 & atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_2 = atomics_a_mask_sub_sub_sub_1_2_2 & atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_2 = atomics_a_mask_sub_sub_sub_1_1_2 | _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_2 = atomics_a_mask_sub_sub_sub_1_2_2 & atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_2 = atomics_a_mask_sub_sub_sub_1_1_2 | _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_2 = atomics_a_mask_sub_sub_2_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_4_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_2 = atomics_a_mask_sub_sub_2_1_2 | _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_2 = atomics_a_mask_sub_sub_2_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_5_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_2 = atomics_a_mask_sub_sub_2_1_2 | _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_2 = atomics_a_mask_sub_sub_3_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_6_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_2 = atomics_a_mask_sub_sub_3_1_2 | _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_2 = atomics_a_mask_sub_sub_3_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_7_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_2 = atomics_a_mask_sub_sub_3_1_2 | _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_2 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_2 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_2 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_2 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_2 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_2 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_2 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_2 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_40 = atomics_a_mask_sub_4_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_2 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_40 = atomics_a_mask_sub_4_1_2 | _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_41 = atomics_a_mask_sub_4_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_2 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_41 = atomics_a_mask_sub_4_1_2 | _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_42 = atomics_a_mask_sub_5_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_2 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_42 = atomics_a_mask_sub_5_1_2 | _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_43 = atomics_a_mask_sub_5_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_2 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_43 = atomics_a_mask_sub_5_1_2 | _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_44 = atomics_a_mask_sub_6_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_2 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_44 = atomics_a_mask_sub_6_1_2 | _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_45 = atomics_a_mask_sub_6_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_2 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_45 = atomics_a_mask_sub_6_1_2 | _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_46 = atomics_a_mask_sub_7_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_2 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_46 = atomics_a_mask_sub_7_1_2 | _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_47 = atomics_a_mask_sub_7_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_2 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_47 = atomics_a_mask_sub_7_1_2 | _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_2 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_2 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_lo_lo_hi_2, atomics_a_mask_lo_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_2 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_2 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_lo_hi_hi_2, atomics_a_mask_lo_hi_lo_2}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_2 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_2 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_hi_lo_hi_2, atomics_a_mask_hi_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_2 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_2 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_hi_hi_hi_2, atomics_a_mask_hi_hi_lo_2}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10] assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_182 = {1'h0, _atomics_legal_T_181}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_183 = _atomics_legal_T_182 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_184 = _atomics_legal_T_183; // @[Parameters.scala:137:46] wire _atomics_legal_T_185 = _atomics_legal_T_184 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_187 = {1'h0, _atomics_legal_T_186}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_188 = _atomics_legal_T_187 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_189 = _atomics_legal_T_188; // @[Parameters.scala:137:46] wire _atomics_legal_T_190 = _atomics_legal_T_189 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_192 = {1'h0, _atomics_legal_T_191}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_193 = _atomics_legal_T_192 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_194 = _atomics_legal_T_193; // @[Parameters.scala:137:46] wire _atomics_legal_T_195 = _atomics_legal_T_194 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_197 = {1'h0, _atomics_legal_T_196}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_198 = _atomics_legal_T_197 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_199 = _atomics_legal_T_198; // @[Parameters.scala:137:46] wire _atomics_legal_T_200 = _atomics_legal_T_199 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_202 = {1'h0, _atomics_legal_T_201}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_203 = _atomics_legal_T_202 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_204 = _atomics_legal_T_203; // @[Parameters.scala:137:46] wire _atomics_legal_T_205 = _atomics_legal_T_204 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_206 = _atomics_legal_T_185 | _atomics_legal_T_190; // @[Parameters.scala:685:42] wire _atomics_legal_T_207 = _atomics_legal_T_206 | _atomics_legal_T_195; // @[Parameters.scala:685:42] wire _atomics_legal_T_208 = _atomics_legal_T_207 | _atomics_legal_T_200; // @[Parameters.scala:685:42] wire _atomics_legal_T_209 = _atomics_legal_T_208 | _atomics_legal_T_205; // @[Parameters.scala:685:42] wire _atomics_legal_T_210 = _atomics_legal_T_209; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_234 = _atomics_legal_T_210; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_213 = {1'h0, _atomics_legal_T_212}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_214 = _atomics_legal_T_213 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_215 = _atomics_legal_T_214; // @[Parameters.scala:137:46] wire _atomics_legal_T_216 = _atomics_legal_T_215 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_223 = {1'h0, _atomics_legal_T_222}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_224 = _atomics_legal_T_223 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_225 = _atomics_legal_T_224; // @[Parameters.scala:137:46] wire _atomics_legal_T_226 = _atomics_legal_T_225 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_228 = {1'h0, _atomics_legal_T_227}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_229 = _atomics_legal_T_228 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_230 = _atomics_legal_T_229; // @[Parameters.scala:137:46] wire _atomics_legal_T_231 = _atomics_legal_T_230 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_232 = _atomics_legal_T_226 | _atomics_legal_T_231; // @[Parameters.scala:685:42] wire _atomics_legal_T_233 = _atomics_legal_T_232; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_235 = _atomics_legal_T_234; // @[Parameters.scala:686:26] wire atomics_legal_3 = _atomics_legal_T_235 | _atomics_legal_T_233; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [15:0] atomics_a_3_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_3 = atomics_a_mask_sizeOH_3[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_3 = atomics_a_mask_sub_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_3 = atomics_a_mask_sub_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_sub_size_3 & atomics_a_mask_sub_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_3 = _atomics_a_mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_sub_size_3 & atomics_a_mask_sub_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_3 = _atomics_a_mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_sub_0_2_3 & atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_sub_0_2_3 & atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_3 = atomics_a_mask_sub_sub_sub_1_2_3 & atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_3 = atomics_a_mask_sub_sub_sub_1_1_3 | _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_3 = atomics_a_mask_sub_sub_sub_1_2_3 & atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_3 = atomics_a_mask_sub_sub_sub_1_1_3 | _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_3 = atomics_a_mask_sub_sub_2_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_4_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_3 = atomics_a_mask_sub_sub_2_1_3 | _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_3 = atomics_a_mask_sub_sub_2_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_5_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_3 = atomics_a_mask_sub_sub_2_1_3 | _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_3 = atomics_a_mask_sub_sub_3_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_6_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_3 = atomics_a_mask_sub_sub_3_1_3 | _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_3 = atomics_a_mask_sub_sub_3_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_7_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_3 = atomics_a_mask_sub_sub_3_1_3 | _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_3 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_3 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_3 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_3 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_3 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_3 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_3 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_3 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_56 = atomics_a_mask_sub_4_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_3 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_56 = atomics_a_mask_sub_4_1_3 | _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_57 = atomics_a_mask_sub_4_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_3 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_57 = atomics_a_mask_sub_4_1_3 | _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_58 = atomics_a_mask_sub_5_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_3 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_58 = atomics_a_mask_sub_5_1_3 | _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_59 = atomics_a_mask_sub_5_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_3 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_59 = atomics_a_mask_sub_5_1_3 | _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_60 = atomics_a_mask_sub_6_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_3 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_60 = atomics_a_mask_sub_6_1_3 | _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_61 = atomics_a_mask_sub_6_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_3 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_61 = atomics_a_mask_sub_6_1_3 | _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_62 = atomics_a_mask_sub_7_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_3 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_62 = atomics_a_mask_sub_7_1_3 | _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_63 = atomics_a_mask_sub_7_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_3 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_63 = atomics_a_mask_sub_7_1_3 | _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_3 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_3 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_lo_lo_hi_3, atomics_a_mask_lo_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_3 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_3 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_lo_hi_hi_3, atomics_a_mask_lo_hi_lo_3}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_3 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_3 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_hi_lo_hi_3, atomics_a_mask_hi_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_3 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_3 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_hi_hi_hi_3, atomics_a_mask_hi_hi_lo_3}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10] assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_241 = {1'h0, _atomics_legal_T_240}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_242 = _atomics_legal_T_241 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_243 = _atomics_legal_T_242; // @[Parameters.scala:137:46] wire _atomics_legal_T_244 = _atomics_legal_T_243 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_246 = {1'h0, _atomics_legal_T_245}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_247 = _atomics_legal_T_246 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_248 = _atomics_legal_T_247; // @[Parameters.scala:137:46] wire _atomics_legal_T_249 = _atomics_legal_T_248 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_251 = {1'h0, _atomics_legal_T_250}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_252 = _atomics_legal_T_251 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_253 = _atomics_legal_T_252; // @[Parameters.scala:137:46] wire _atomics_legal_T_254 = _atomics_legal_T_253 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_256 = {1'h0, _atomics_legal_T_255}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_257 = _atomics_legal_T_256 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_258 = _atomics_legal_T_257; // @[Parameters.scala:137:46] wire _atomics_legal_T_259 = _atomics_legal_T_258 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_261 = {1'h0, _atomics_legal_T_260}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_262 = _atomics_legal_T_261 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_263 = _atomics_legal_T_262; // @[Parameters.scala:137:46] wire _atomics_legal_T_264 = _atomics_legal_T_263 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_265 = _atomics_legal_T_244 | _atomics_legal_T_249; // @[Parameters.scala:685:42] wire _atomics_legal_T_266 = _atomics_legal_T_265 | _atomics_legal_T_254; // @[Parameters.scala:685:42] wire _atomics_legal_T_267 = _atomics_legal_T_266 | _atomics_legal_T_259; // @[Parameters.scala:685:42] wire _atomics_legal_T_268 = _atomics_legal_T_267 | _atomics_legal_T_264; // @[Parameters.scala:685:42] wire _atomics_legal_T_269 = _atomics_legal_T_268; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_293 = _atomics_legal_T_269; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_272 = {1'h0, _atomics_legal_T_271}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_273 = _atomics_legal_T_272 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_274 = _atomics_legal_T_273; // @[Parameters.scala:137:46] wire _atomics_legal_T_275 = _atomics_legal_T_274 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_282 = {1'h0, _atomics_legal_T_281}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_283 = _atomics_legal_T_282 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_284 = _atomics_legal_T_283; // @[Parameters.scala:137:46] wire _atomics_legal_T_285 = _atomics_legal_T_284 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_287 = {1'h0, _atomics_legal_T_286}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_288 = _atomics_legal_T_287 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_289 = _atomics_legal_T_288; // @[Parameters.scala:137:46] wire _atomics_legal_T_290 = _atomics_legal_T_289 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_291 = _atomics_legal_T_285 | _atomics_legal_T_290; // @[Parameters.scala:685:42] wire _atomics_legal_T_292 = _atomics_legal_T_291; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_294 = _atomics_legal_T_293; // @[Parameters.scala:686:26] wire atomics_legal_4 = _atomics_legal_T_294 | _atomics_legal_T_292; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [15:0] atomics_a_4_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_4 = atomics_a_mask_sizeOH_4[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_4 = atomics_a_mask_sub_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_4 = atomics_a_mask_sub_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_sub_size_4 & atomics_a_mask_sub_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_4 = _atomics_a_mask_sub_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_sub_size_4 & atomics_a_mask_sub_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_4 = _atomics_a_mask_sub_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_sub_0_2_4 & atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_sub_0_2_4 & atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_4 = atomics_a_mask_sub_sub_sub_1_2_4 & atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_18 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_4 = atomics_a_mask_sub_sub_sub_1_1_4 | _atomics_a_mask_sub_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_4 = atomics_a_mask_sub_sub_sub_1_2_4 & atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_19 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_4 = atomics_a_mask_sub_sub_sub_1_1_4 | _atomics_a_mask_sub_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_4 = atomics_a_mask_sub_sub_2_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_36 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_4_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_4 = atomics_a_mask_sub_sub_2_1_4 | _atomics_a_mask_sub_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_4 = atomics_a_mask_sub_sub_2_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_37 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_5_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_4 = atomics_a_mask_sub_sub_2_1_4 | _atomics_a_mask_sub_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_4 = atomics_a_mask_sub_sub_3_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_38 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_6_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_4 = atomics_a_mask_sub_sub_3_1_4 | _atomics_a_mask_sub_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_4 = atomics_a_mask_sub_sub_3_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_39 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_7_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_4 = atomics_a_mask_sub_sub_3_1_4 | _atomics_a_mask_sub_acc_T_39; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_4 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_4 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_4 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_4 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_4 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_4 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_4 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_4 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_72 = atomics_a_mask_sub_4_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_72 = atomics_a_mask_size_4 & atomics_a_mask_eq_72; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_72 = atomics_a_mask_sub_4_1_4 | _atomics_a_mask_acc_T_72; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_73 = atomics_a_mask_sub_4_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_73 = atomics_a_mask_size_4 & atomics_a_mask_eq_73; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_73 = atomics_a_mask_sub_4_1_4 | _atomics_a_mask_acc_T_73; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_74 = atomics_a_mask_sub_5_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_74 = atomics_a_mask_size_4 & atomics_a_mask_eq_74; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_74 = atomics_a_mask_sub_5_1_4 | _atomics_a_mask_acc_T_74; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_75 = atomics_a_mask_sub_5_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_75 = atomics_a_mask_size_4 & atomics_a_mask_eq_75; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_75 = atomics_a_mask_sub_5_1_4 | _atomics_a_mask_acc_T_75; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_76 = atomics_a_mask_sub_6_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_76 = atomics_a_mask_size_4 & atomics_a_mask_eq_76; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_76 = atomics_a_mask_sub_6_1_4 | _atomics_a_mask_acc_T_76; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_77 = atomics_a_mask_sub_6_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_77 = atomics_a_mask_size_4 & atomics_a_mask_eq_77; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_77 = atomics_a_mask_sub_6_1_4 | _atomics_a_mask_acc_T_77; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_78 = atomics_a_mask_sub_7_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_78 = atomics_a_mask_size_4 & atomics_a_mask_eq_78; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_78 = atomics_a_mask_sub_7_1_4 | _atomics_a_mask_acc_T_78; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_79 = atomics_a_mask_sub_7_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_79 = atomics_a_mask_size_4 & atomics_a_mask_eq_79; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_79 = atomics_a_mask_sub_7_1_4 | _atomics_a_mask_acc_T_79; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_4 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_4 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_lo_lo_hi_4, atomics_a_mask_lo_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_4 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_4 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_lo_hi_hi_4, atomics_a_mask_lo_hi_lo_4}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_4 = {atomics_a_mask_acc_73, atomics_a_mask_acc_72}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_4 = {atomics_a_mask_acc_75, atomics_a_mask_acc_74}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_hi_lo_hi_4, atomics_a_mask_hi_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_4 = {atomics_a_mask_acc_77, atomics_a_mask_acc_76}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_4 = {atomics_a_mask_acc_79, atomics_a_mask_acc_78}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_hi_hi_hi_4, atomics_a_mask_hi_hi_lo_4}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10] assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_300 = {1'h0, _atomics_legal_T_299}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_301 = _atomics_legal_T_300 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_302 = _atomics_legal_T_301; // @[Parameters.scala:137:46] wire _atomics_legal_T_303 = _atomics_legal_T_302 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_305 = {1'h0, _atomics_legal_T_304}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_306 = _atomics_legal_T_305 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_307 = _atomics_legal_T_306; // @[Parameters.scala:137:46] wire _atomics_legal_T_308 = _atomics_legal_T_307 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_310 = {1'h0, _atomics_legal_T_309}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_311 = _atomics_legal_T_310 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_312 = _atomics_legal_T_311; // @[Parameters.scala:137:46] wire _atomics_legal_T_313 = _atomics_legal_T_312 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_315 = {1'h0, _atomics_legal_T_314}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_316 = _atomics_legal_T_315 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_317 = _atomics_legal_T_316; // @[Parameters.scala:137:46] wire _atomics_legal_T_318 = _atomics_legal_T_317 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_320 = {1'h0, _atomics_legal_T_319}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_321 = _atomics_legal_T_320 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_322 = _atomics_legal_T_321; // @[Parameters.scala:137:46] wire _atomics_legal_T_323 = _atomics_legal_T_322 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_324 = _atomics_legal_T_303 | _atomics_legal_T_308; // @[Parameters.scala:685:42] wire _atomics_legal_T_325 = _atomics_legal_T_324 | _atomics_legal_T_313; // @[Parameters.scala:685:42] wire _atomics_legal_T_326 = _atomics_legal_T_325 | _atomics_legal_T_318; // @[Parameters.scala:685:42] wire _atomics_legal_T_327 = _atomics_legal_T_326 | _atomics_legal_T_323; // @[Parameters.scala:685:42] wire _atomics_legal_T_328 = _atomics_legal_T_327; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_352 = _atomics_legal_T_328; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_331 = {1'h0, _atomics_legal_T_330}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_332 = _atomics_legal_T_331 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_333 = _atomics_legal_T_332; // @[Parameters.scala:137:46] wire _atomics_legal_T_334 = _atomics_legal_T_333 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_341 = {1'h0, _atomics_legal_T_340}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_342 = _atomics_legal_T_341 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_343 = _atomics_legal_T_342; // @[Parameters.scala:137:46] wire _atomics_legal_T_344 = _atomics_legal_T_343 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_346 = {1'h0, _atomics_legal_T_345}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_347 = _atomics_legal_T_346 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_348 = _atomics_legal_T_347; // @[Parameters.scala:137:46] wire _atomics_legal_T_349 = _atomics_legal_T_348 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_350 = _atomics_legal_T_344 | _atomics_legal_T_349; // @[Parameters.scala:685:42] wire _atomics_legal_T_351 = _atomics_legal_T_350; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_353 = _atomics_legal_T_352; // @[Parameters.scala:686:26] wire atomics_legal_5 = _atomics_legal_T_353 | _atomics_legal_T_351; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [15:0] atomics_a_5_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_5 = atomics_a_mask_sizeOH_5[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_5 = atomics_a_mask_sub_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_5 = atomics_a_mask_sub_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_sub_size_5 & atomics_a_mask_sub_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_5 = _atomics_a_mask_sub_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_sub_size_5 & atomics_a_mask_sub_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_5 = _atomics_a_mask_sub_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_sub_0_2_5 & atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_20 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_sub_0_2_5 & atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_21 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_5 = atomics_a_mask_sub_sub_sub_1_2_5 & atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_22 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_5 = atomics_a_mask_sub_sub_sub_1_1_5 | _atomics_a_mask_sub_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_5 = atomics_a_mask_sub_sub_sub_1_2_5 & atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_23 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_5 = atomics_a_mask_sub_sub_sub_1_1_5 | _atomics_a_mask_sub_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_40 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_41 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_42 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_43 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_5 = atomics_a_mask_sub_sub_2_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_44 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_4_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_5 = atomics_a_mask_sub_sub_2_1_5 | _atomics_a_mask_sub_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_5 = atomics_a_mask_sub_sub_2_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_45 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_5_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_5 = atomics_a_mask_sub_sub_2_1_5 | _atomics_a_mask_sub_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_5 = atomics_a_mask_sub_sub_3_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_46 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_6_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_5 = atomics_a_mask_sub_sub_3_1_5 | _atomics_a_mask_sub_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_5 = atomics_a_mask_sub_sub_3_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_47 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_7_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_5 = atomics_a_mask_sub_sub_3_1_5 | _atomics_a_mask_sub_acc_T_47; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_80 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_80 = atomics_a_mask_size_5 & atomics_a_mask_eq_80; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_80 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_80; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_81 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_81 = atomics_a_mask_size_5 & atomics_a_mask_eq_81; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_81 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_81; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_82 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_82 = atomics_a_mask_size_5 & atomics_a_mask_eq_82; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_82 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_82; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_83 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_83 = atomics_a_mask_size_5 & atomics_a_mask_eq_83; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_83 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_83; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_84 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_84 = atomics_a_mask_size_5 & atomics_a_mask_eq_84; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_84 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_84; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_85 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_85 = atomics_a_mask_size_5 & atomics_a_mask_eq_85; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_85 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_85; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_86 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_86 = atomics_a_mask_size_5 & atomics_a_mask_eq_86; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_86 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_86; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_87 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_87 = atomics_a_mask_size_5 & atomics_a_mask_eq_87; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_87 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_87; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_88 = atomics_a_mask_sub_4_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_88 = atomics_a_mask_size_5 & atomics_a_mask_eq_88; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_88 = atomics_a_mask_sub_4_1_5 | _atomics_a_mask_acc_T_88; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_89 = atomics_a_mask_sub_4_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_89 = atomics_a_mask_size_5 & atomics_a_mask_eq_89; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_89 = atomics_a_mask_sub_4_1_5 | _atomics_a_mask_acc_T_89; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_90 = atomics_a_mask_sub_5_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_90 = atomics_a_mask_size_5 & atomics_a_mask_eq_90; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_90 = atomics_a_mask_sub_5_1_5 | _atomics_a_mask_acc_T_90; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_91 = atomics_a_mask_sub_5_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_91 = atomics_a_mask_size_5 & atomics_a_mask_eq_91; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_91 = atomics_a_mask_sub_5_1_5 | _atomics_a_mask_acc_T_91; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_92 = atomics_a_mask_sub_6_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_92 = atomics_a_mask_size_5 & atomics_a_mask_eq_92; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_92 = atomics_a_mask_sub_6_1_5 | _atomics_a_mask_acc_T_92; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_93 = atomics_a_mask_sub_6_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_93 = atomics_a_mask_size_5 & atomics_a_mask_eq_93; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_93 = atomics_a_mask_sub_6_1_5 | _atomics_a_mask_acc_T_93; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_94 = atomics_a_mask_sub_7_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_94 = atomics_a_mask_size_5 & atomics_a_mask_eq_94; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_94 = atomics_a_mask_sub_7_1_5 | _atomics_a_mask_acc_T_94; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_95 = atomics_a_mask_sub_7_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_95 = atomics_a_mask_size_5 & atomics_a_mask_eq_95; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_95 = atomics_a_mask_sub_7_1_5 | _atomics_a_mask_acc_T_95; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_5 = {atomics_a_mask_acc_81, atomics_a_mask_acc_80}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_5 = {atomics_a_mask_acc_83, atomics_a_mask_acc_82}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_lo_lo_hi_5, atomics_a_mask_lo_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_5 = {atomics_a_mask_acc_85, atomics_a_mask_acc_84}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_5 = {atomics_a_mask_acc_87, atomics_a_mask_acc_86}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_lo_hi_hi_5, atomics_a_mask_lo_hi_lo_5}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_5 = {atomics_a_mask_acc_89, atomics_a_mask_acc_88}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_5 = {atomics_a_mask_acc_91, atomics_a_mask_acc_90}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_hi_lo_hi_5, atomics_a_mask_hi_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_5 = {atomics_a_mask_acc_93, atomics_a_mask_acc_92}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_5 = {atomics_a_mask_acc_95, atomics_a_mask_acc_94}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_hi_hi_hi_5, atomics_a_mask_hi_hi_lo_5}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10] assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_359 = {1'h0, _atomics_legal_T_358}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_360 = _atomics_legal_T_359 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_361 = _atomics_legal_T_360; // @[Parameters.scala:137:46] wire _atomics_legal_T_362 = _atomics_legal_T_361 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_364 = {1'h0, _atomics_legal_T_363}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_365 = _atomics_legal_T_364 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_366 = _atomics_legal_T_365; // @[Parameters.scala:137:46] wire _atomics_legal_T_367 = _atomics_legal_T_366 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_369 = {1'h0, _atomics_legal_T_368}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_370 = _atomics_legal_T_369 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_371 = _atomics_legal_T_370; // @[Parameters.scala:137:46] wire _atomics_legal_T_372 = _atomics_legal_T_371 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_374 = {1'h0, _atomics_legal_T_373}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_375 = _atomics_legal_T_374 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_376 = _atomics_legal_T_375; // @[Parameters.scala:137:46] wire _atomics_legal_T_377 = _atomics_legal_T_376 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_379 = {1'h0, _atomics_legal_T_378}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_380 = _atomics_legal_T_379 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_381 = _atomics_legal_T_380; // @[Parameters.scala:137:46] wire _atomics_legal_T_382 = _atomics_legal_T_381 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_383 = _atomics_legal_T_362 | _atomics_legal_T_367; // @[Parameters.scala:685:42] wire _atomics_legal_T_384 = _atomics_legal_T_383 | _atomics_legal_T_372; // @[Parameters.scala:685:42] wire _atomics_legal_T_385 = _atomics_legal_T_384 | _atomics_legal_T_377; // @[Parameters.scala:685:42] wire _atomics_legal_T_386 = _atomics_legal_T_385 | _atomics_legal_T_382; // @[Parameters.scala:685:42] wire _atomics_legal_T_387 = _atomics_legal_T_386; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_411 = _atomics_legal_T_387; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_390 = {1'h0, _atomics_legal_T_389}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_391 = _atomics_legal_T_390 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_392 = _atomics_legal_T_391; // @[Parameters.scala:137:46] wire _atomics_legal_T_393 = _atomics_legal_T_392 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_400 = {1'h0, _atomics_legal_T_399}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_401 = _atomics_legal_T_400 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_402 = _atomics_legal_T_401; // @[Parameters.scala:137:46] wire _atomics_legal_T_403 = _atomics_legal_T_402 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_405 = {1'h0, _atomics_legal_T_404}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_406 = _atomics_legal_T_405 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_407 = _atomics_legal_T_406; // @[Parameters.scala:137:46] wire _atomics_legal_T_408 = _atomics_legal_T_407 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_409 = _atomics_legal_T_403 | _atomics_legal_T_408; // @[Parameters.scala:685:42] wire _atomics_legal_T_410 = _atomics_legal_T_409; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_412 = _atomics_legal_T_411; // @[Parameters.scala:686:26] wire atomics_legal_6 = _atomics_legal_T_412 | _atomics_legal_T_410; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [15:0] atomics_a_6_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_6 = atomics_a_mask_sizeOH_6[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_6 = atomics_a_mask_sub_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_6 = atomics_a_mask_sub_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_sub_size_6 & atomics_a_mask_sub_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_6 = _atomics_a_mask_sub_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_sub_size_6 & atomics_a_mask_sub_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_6 = _atomics_a_mask_sub_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_sub_0_2_6 & atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_24 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_sub_0_2_6 & atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_25 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_6 = atomics_a_mask_sub_sub_sub_1_2_6 & atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_26 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_6 = atomics_a_mask_sub_sub_sub_1_1_6 | _atomics_a_mask_sub_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_6 = atomics_a_mask_sub_sub_sub_1_2_6 & atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_27 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_6 = atomics_a_mask_sub_sub_sub_1_1_6 | _atomics_a_mask_sub_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_48 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_49 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_50 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_51 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_6 = atomics_a_mask_sub_sub_2_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_52 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_4_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_6 = atomics_a_mask_sub_sub_2_1_6 | _atomics_a_mask_sub_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_6 = atomics_a_mask_sub_sub_2_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_53 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_5_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_6 = atomics_a_mask_sub_sub_2_1_6 | _atomics_a_mask_sub_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_6 = atomics_a_mask_sub_sub_3_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_54 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_6_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_6 = atomics_a_mask_sub_sub_3_1_6 | _atomics_a_mask_sub_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_6 = atomics_a_mask_sub_sub_3_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_55 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_7_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_6 = atomics_a_mask_sub_sub_3_1_6 | _atomics_a_mask_sub_acc_T_55; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_96 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_96 = atomics_a_mask_size_6 & atomics_a_mask_eq_96; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_96 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_96; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_97 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_97 = atomics_a_mask_size_6 & atomics_a_mask_eq_97; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_97 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_97; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_98 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_98 = atomics_a_mask_size_6 & atomics_a_mask_eq_98; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_98 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_98; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_99 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_99 = atomics_a_mask_size_6 & atomics_a_mask_eq_99; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_99 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_99; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_100 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_100 = atomics_a_mask_size_6 & atomics_a_mask_eq_100; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_100 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_100; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_101 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_101 = atomics_a_mask_size_6 & atomics_a_mask_eq_101; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_101 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_101; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_102 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_102 = atomics_a_mask_size_6 & atomics_a_mask_eq_102; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_102 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_102; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_103 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_103 = atomics_a_mask_size_6 & atomics_a_mask_eq_103; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_103 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_103; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_104 = atomics_a_mask_sub_4_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_104 = atomics_a_mask_size_6 & atomics_a_mask_eq_104; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_104 = atomics_a_mask_sub_4_1_6 | _atomics_a_mask_acc_T_104; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_105 = atomics_a_mask_sub_4_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_105 = atomics_a_mask_size_6 & atomics_a_mask_eq_105; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_105 = atomics_a_mask_sub_4_1_6 | _atomics_a_mask_acc_T_105; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_106 = atomics_a_mask_sub_5_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_106 = atomics_a_mask_size_6 & atomics_a_mask_eq_106; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_106 = atomics_a_mask_sub_5_1_6 | _atomics_a_mask_acc_T_106; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_107 = atomics_a_mask_sub_5_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_107 = atomics_a_mask_size_6 & atomics_a_mask_eq_107; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_107 = atomics_a_mask_sub_5_1_6 | _atomics_a_mask_acc_T_107; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_108 = atomics_a_mask_sub_6_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_108 = atomics_a_mask_size_6 & atomics_a_mask_eq_108; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_108 = atomics_a_mask_sub_6_1_6 | _atomics_a_mask_acc_T_108; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_109 = atomics_a_mask_sub_6_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_109 = atomics_a_mask_size_6 & atomics_a_mask_eq_109; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_109 = atomics_a_mask_sub_6_1_6 | _atomics_a_mask_acc_T_109; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_110 = atomics_a_mask_sub_7_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_110 = atomics_a_mask_size_6 & atomics_a_mask_eq_110; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_110 = atomics_a_mask_sub_7_1_6 | _atomics_a_mask_acc_T_110; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_111 = atomics_a_mask_sub_7_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_111 = atomics_a_mask_size_6 & atomics_a_mask_eq_111; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_111 = atomics_a_mask_sub_7_1_6 | _atomics_a_mask_acc_T_111; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_6 = {atomics_a_mask_acc_97, atomics_a_mask_acc_96}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_6 = {atomics_a_mask_acc_99, atomics_a_mask_acc_98}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_lo_lo_hi_6, atomics_a_mask_lo_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_6 = {atomics_a_mask_acc_101, atomics_a_mask_acc_100}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_6 = {atomics_a_mask_acc_103, atomics_a_mask_acc_102}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_lo_hi_hi_6, atomics_a_mask_lo_hi_lo_6}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_6 = {atomics_a_mask_acc_105, atomics_a_mask_acc_104}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_6 = {atomics_a_mask_acc_107, atomics_a_mask_acc_106}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_hi_lo_hi_6, atomics_a_mask_hi_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_6 = {atomics_a_mask_acc_109, atomics_a_mask_acc_108}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_6 = {atomics_a_mask_acc_111, atomics_a_mask_acc_110}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_hi_hi_hi_6, atomics_a_mask_hi_hi_lo_6}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10] assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_418 = {1'h0, _atomics_legal_T_417}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_419 = _atomics_legal_T_418 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_420 = _atomics_legal_T_419; // @[Parameters.scala:137:46] wire _atomics_legal_T_421 = _atomics_legal_T_420 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_423 = {1'h0, _atomics_legal_T_422}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_424 = _atomics_legal_T_423 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_425 = _atomics_legal_T_424; // @[Parameters.scala:137:46] wire _atomics_legal_T_426 = _atomics_legal_T_425 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_428 = {1'h0, _atomics_legal_T_427}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_429 = _atomics_legal_T_428 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_430 = _atomics_legal_T_429; // @[Parameters.scala:137:46] wire _atomics_legal_T_431 = _atomics_legal_T_430 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_433 = {1'h0, _atomics_legal_T_432}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_434 = _atomics_legal_T_433 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_435 = _atomics_legal_T_434; // @[Parameters.scala:137:46] wire _atomics_legal_T_436 = _atomics_legal_T_435 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_438 = {1'h0, _atomics_legal_T_437}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_439 = _atomics_legal_T_438 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_440 = _atomics_legal_T_439; // @[Parameters.scala:137:46] wire _atomics_legal_T_441 = _atomics_legal_T_440 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_442 = _atomics_legal_T_421 | _atomics_legal_T_426; // @[Parameters.scala:685:42] wire _atomics_legal_T_443 = _atomics_legal_T_442 | _atomics_legal_T_431; // @[Parameters.scala:685:42] wire _atomics_legal_T_444 = _atomics_legal_T_443 | _atomics_legal_T_436; // @[Parameters.scala:685:42] wire _atomics_legal_T_445 = _atomics_legal_T_444 | _atomics_legal_T_441; // @[Parameters.scala:685:42] wire _atomics_legal_T_446 = _atomics_legal_T_445; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_470 = _atomics_legal_T_446; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_449 = {1'h0, _atomics_legal_T_448}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_450 = _atomics_legal_T_449 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_451 = _atomics_legal_T_450; // @[Parameters.scala:137:46] wire _atomics_legal_T_452 = _atomics_legal_T_451 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_459 = {1'h0, _atomics_legal_T_458}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_460 = _atomics_legal_T_459 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_461 = _atomics_legal_T_460; // @[Parameters.scala:137:46] wire _atomics_legal_T_462 = _atomics_legal_T_461 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_464 = {1'h0, _atomics_legal_T_463}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_465 = _atomics_legal_T_464 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_466 = _atomics_legal_T_465; // @[Parameters.scala:137:46] wire _atomics_legal_T_467 = _atomics_legal_T_466 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_468 = _atomics_legal_T_462 | _atomics_legal_T_467; // @[Parameters.scala:685:42] wire _atomics_legal_T_469 = _atomics_legal_T_468; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_471 = _atomics_legal_T_470; // @[Parameters.scala:686:26] wire atomics_legal_7 = _atomics_legal_T_471 | _atomics_legal_T_469; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [15:0] atomics_a_7_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_7 = atomics_a_mask_sizeOH_7[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_7 = atomics_a_mask_sub_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_7 = atomics_a_mask_sub_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_sub_size_7 & atomics_a_mask_sub_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_7 = _atomics_a_mask_sub_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_sub_size_7 & atomics_a_mask_sub_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_7 = _atomics_a_mask_sub_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_sub_0_2_7 & atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_28 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_sub_0_2_7 & atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_29 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_7 = atomics_a_mask_sub_sub_sub_1_2_7 & atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_30 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_7 = atomics_a_mask_sub_sub_sub_1_1_7 | _atomics_a_mask_sub_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_7 = atomics_a_mask_sub_sub_sub_1_2_7 & atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_31 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_7 = atomics_a_mask_sub_sub_sub_1_1_7 | _atomics_a_mask_sub_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_56 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_57 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_58 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_59 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_7 = atomics_a_mask_sub_sub_2_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_60 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_4_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_7 = atomics_a_mask_sub_sub_2_1_7 | _atomics_a_mask_sub_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_7 = atomics_a_mask_sub_sub_2_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_61 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_5_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_7 = atomics_a_mask_sub_sub_2_1_7 | _atomics_a_mask_sub_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_7 = atomics_a_mask_sub_sub_3_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_62 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_6_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_7 = atomics_a_mask_sub_sub_3_1_7 | _atomics_a_mask_sub_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_7 = atomics_a_mask_sub_sub_3_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_63 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_7_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_7 = atomics_a_mask_sub_sub_3_1_7 | _atomics_a_mask_sub_acc_T_63; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_112 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_112 = atomics_a_mask_size_7 & atomics_a_mask_eq_112; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_112 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_112; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_113 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_113 = atomics_a_mask_size_7 & atomics_a_mask_eq_113; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_113 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_113; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_114 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_114 = atomics_a_mask_size_7 & atomics_a_mask_eq_114; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_114 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_114; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_115 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_115 = atomics_a_mask_size_7 & atomics_a_mask_eq_115; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_115 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_115; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_116 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_116 = atomics_a_mask_size_7 & atomics_a_mask_eq_116; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_116 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_116; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_117 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_117 = atomics_a_mask_size_7 & atomics_a_mask_eq_117; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_117 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_117; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_118 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_118 = atomics_a_mask_size_7 & atomics_a_mask_eq_118; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_118 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_118; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_119 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_119 = atomics_a_mask_size_7 & atomics_a_mask_eq_119; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_119 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_119; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_120 = atomics_a_mask_sub_4_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_120 = atomics_a_mask_size_7 & atomics_a_mask_eq_120; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_120 = atomics_a_mask_sub_4_1_7 | _atomics_a_mask_acc_T_120; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_121 = atomics_a_mask_sub_4_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_121 = atomics_a_mask_size_7 & atomics_a_mask_eq_121; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_121 = atomics_a_mask_sub_4_1_7 | _atomics_a_mask_acc_T_121; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_122 = atomics_a_mask_sub_5_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_122 = atomics_a_mask_size_7 & atomics_a_mask_eq_122; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_122 = atomics_a_mask_sub_5_1_7 | _atomics_a_mask_acc_T_122; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_123 = atomics_a_mask_sub_5_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_123 = atomics_a_mask_size_7 & atomics_a_mask_eq_123; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_123 = atomics_a_mask_sub_5_1_7 | _atomics_a_mask_acc_T_123; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_124 = atomics_a_mask_sub_6_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_124 = atomics_a_mask_size_7 & atomics_a_mask_eq_124; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_124 = atomics_a_mask_sub_6_1_7 | _atomics_a_mask_acc_T_124; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_125 = atomics_a_mask_sub_6_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_125 = atomics_a_mask_size_7 & atomics_a_mask_eq_125; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_125 = atomics_a_mask_sub_6_1_7 | _atomics_a_mask_acc_T_125; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_126 = atomics_a_mask_sub_7_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_126 = atomics_a_mask_size_7 & atomics_a_mask_eq_126; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_126 = atomics_a_mask_sub_7_1_7 | _atomics_a_mask_acc_T_126; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_127 = atomics_a_mask_sub_7_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_127 = atomics_a_mask_size_7 & atomics_a_mask_eq_127; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_127 = atomics_a_mask_sub_7_1_7 | _atomics_a_mask_acc_T_127; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_7 = {atomics_a_mask_acc_113, atomics_a_mask_acc_112}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_7 = {atomics_a_mask_acc_115, atomics_a_mask_acc_114}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_lo_lo_hi_7, atomics_a_mask_lo_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_7 = {atomics_a_mask_acc_117, atomics_a_mask_acc_116}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_7 = {atomics_a_mask_acc_119, atomics_a_mask_acc_118}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_lo_hi_hi_7, atomics_a_mask_lo_hi_lo_7}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_7 = {atomics_a_mask_acc_121, atomics_a_mask_acc_120}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_7 = {atomics_a_mask_acc_123, atomics_a_mask_acc_122}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_hi_lo_hi_7, atomics_a_mask_hi_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_7 = {atomics_a_mask_acc_125, atomics_a_mask_acc_124}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_7 = {atomics_a_mask_acc_127, atomics_a_mask_acc_126}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_hi_hi_hi_7, atomics_a_mask_hi_hi_lo_7}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10] assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_477 = {1'h0, _atomics_legal_T_476}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_478 = _atomics_legal_T_477 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_479 = _atomics_legal_T_478; // @[Parameters.scala:137:46] wire _atomics_legal_T_480 = _atomics_legal_T_479 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_482 = {1'h0, _atomics_legal_T_481}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_483 = _atomics_legal_T_482 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_484 = _atomics_legal_T_483; // @[Parameters.scala:137:46] wire _atomics_legal_T_485 = _atomics_legal_T_484 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_487 = {1'h0, _atomics_legal_T_486}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_488 = _atomics_legal_T_487 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_489 = _atomics_legal_T_488; // @[Parameters.scala:137:46] wire _atomics_legal_T_490 = _atomics_legal_T_489 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_492 = {1'h0, _atomics_legal_T_491}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_493 = _atomics_legal_T_492 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_494 = _atomics_legal_T_493; // @[Parameters.scala:137:46] wire _atomics_legal_T_495 = _atomics_legal_T_494 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_497 = {1'h0, _atomics_legal_T_496}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_498 = _atomics_legal_T_497 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_499 = _atomics_legal_T_498; // @[Parameters.scala:137:46] wire _atomics_legal_T_500 = _atomics_legal_T_499 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_501 = _atomics_legal_T_480 | _atomics_legal_T_485; // @[Parameters.scala:685:42] wire _atomics_legal_T_502 = _atomics_legal_T_501 | _atomics_legal_T_490; // @[Parameters.scala:685:42] wire _atomics_legal_T_503 = _atomics_legal_T_502 | _atomics_legal_T_495; // @[Parameters.scala:685:42] wire _atomics_legal_T_504 = _atomics_legal_T_503 | _atomics_legal_T_500; // @[Parameters.scala:685:42] wire _atomics_legal_T_505 = _atomics_legal_T_504; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_529 = _atomics_legal_T_505; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_508 = {1'h0, _atomics_legal_T_507}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_509 = _atomics_legal_T_508 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_510 = _atomics_legal_T_509; // @[Parameters.scala:137:46] wire _atomics_legal_T_511 = _atomics_legal_T_510 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_518 = {1'h0, _atomics_legal_T_517}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_519 = _atomics_legal_T_518 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_520 = _atomics_legal_T_519; // @[Parameters.scala:137:46] wire _atomics_legal_T_521 = _atomics_legal_T_520 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_523 = {1'h0, _atomics_legal_T_522}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_524 = _atomics_legal_T_523 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_525 = _atomics_legal_T_524; // @[Parameters.scala:137:46] wire _atomics_legal_T_526 = _atomics_legal_T_525 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_527 = _atomics_legal_T_521 | _atomics_legal_T_526; // @[Parameters.scala:685:42] wire _atomics_legal_T_528 = _atomics_legal_T_527; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_530 = _atomics_legal_T_529; // @[Parameters.scala:686:26] wire atomics_legal_8 = _atomics_legal_T_530 | _atomics_legal_T_528; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [15:0] atomics_a_8_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_8 = atomics_a_mask_sizeOH_8[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_8 = atomics_a_mask_sub_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_8 = atomics_a_mask_sub_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_sub_size_8 & atomics_a_mask_sub_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_8 = _atomics_a_mask_sub_sub_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_sub_size_8 & atomics_a_mask_sub_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_8 = _atomics_a_mask_sub_sub_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_sub_0_2_8 & atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_32 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_sub_0_2_8 & atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_33 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_8 = atomics_a_mask_sub_sub_sub_1_2_8 & atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_34 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_8 = atomics_a_mask_sub_sub_sub_1_1_8 | _atomics_a_mask_sub_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_8 = atomics_a_mask_sub_sub_sub_1_2_8 & atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_35 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_8 = atomics_a_mask_sub_sub_sub_1_1_8 | _atomics_a_mask_sub_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_64 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_65 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_66 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_67 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_8 = atomics_a_mask_sub_sub_2_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_68 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_4_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_8 = atomics_a_mask_sub_sub_2_1_8 | _atomics_a_mask_sub_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_8 = atomics_a_mask_sub_sub_2_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_69 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_5_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_8 = atomics_a_mask_sub_sub_2_1_8 | _atomics_a_mask_sub_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_8 = atomics_a_mask_sub_sub_3_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_70 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_6_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_8 = atomics_a_mask_sub_sub_3_1_8 | _atomics_a_mask_sub_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_8 = atomics_a_mask_sub_sub_3_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_71 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_7_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_8 = atomics_a_mask_sub_sub_3_1_8 | _atomics_a_mask_sub_acc_T_71; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_128 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_128 = atomics_a_mask_size_8 & atomics_a_mask_eq_128; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_128 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_128; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_129 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_129 = atomics_a_mask_size_8 & atomics_a_mask_eq_129; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_129 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_129; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_130 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_130 = atomics_a_mask_size_8 & atomics_a_mask_eq_130; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_130 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_130; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_131 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_131 = atomics_a_mask_size_8 & atomics_a_mask_eq_131; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_131 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_131; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_132 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_132 = atomics_a_mask_size_8 & atomics_a_mask_eq_132; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_132 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_132; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_133 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_133 = atomics_a_mask_size_8 & atomics_a_mask_eq_133; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_133 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_133; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_134 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_134 = atomics_a_mask_size_8 & atomics_a_mask_eq_134; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_134 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_134; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_135 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_135 = atomics_a_mask_size_8 & atomics_a_mask_eq_135; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_135 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_135; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_136 = atomics_a_mask_sub_4_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_136 = atomics_a_mask_size_8 & atomics_a_mask_eq_136; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_136 = atomics_a_mask_sub_4_1_8 | _atomics_a_mask_acc_T_136; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_137 = atomics_a_mask_sub_4_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_137 = atomics_a_mask_size_8 & atomics_a_mask_eq_137; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_137 = atomics_a_mask_sub_4_1_8 | _atomics_a_mask_acc_T_137; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_138 = atomics_a_mask_sub_5_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_138 = atomics_a_mask_size_8 & atomics_a_mask_eq_138; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_138 = atomics_a_mask_sub_5_1_8 | _atomics_a_mask_acc_T_138; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_139 = atomics_a_mask_sub_5_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_139 = atomics_a_mask_size_8 & atomics_a_mask_eq_139; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_139 = atomics_a_mask_sub_5_1_8 | _atomics_a_mask_acc_T_139; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_140 = atomics_a_mask_sub_6_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_140 = atomics_a_mask_size_8 & atomics_a_mask_eq_140; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_140 = atomics_a_mask_sub_6_1_8 | _atomics_a_mask_acc_T_140; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_141 = atomics_a_mask_sub_6_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_141 = atomics_a_mask_size_8 & atomics_a_mask_eq_141; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_141 = atomics_a_mask_sub_6_1_8 | _atomics_a_mask_acc_T_141; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_142 = atomics_a_mask_sub_7_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_142 = atomics_a_mask_size_8 & atomics_a_mask_eq_142; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_142 = atomics_a_mask_sub_7_1_8 | _atomics_a_mask_acc_T_142; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_143 = atomics_a_mask_sub_7_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_143 = atomics_a_mask_size_8 & atomics_a_mask_eq_143; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_143 = atomics_a_mask_sub_7_1_8 | _atomics_a_mask_acc_T_143; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_8 = {atomics_a_mask_acc_129, atomics_a_mask_acc_128}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_8 = {atomics_a_mask_acc_131, atomics_a_mask_acc_130}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_lo_lo_hi_8, atomics_a_mask_lo_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_8 = {atomics_a_mask_acc_133, atomics_a_mask_acc_132}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_8 = {atomics_a_mask_acc_135, atomics_a_mask_acc_134}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_lo_hi_hi_8, atomics_a_mask_lo_hi_lo_8}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_8 = {atomics_a_mask_acc_137, atomics_a_mask_acc_136}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_8 = {atomics_a_mask_acc_139, atomics_a_mask_acc_138}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_hi_lo_hi_8, atomics_a_mask_hi_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_8 = {atomics_a_mask_acc_141, atomics_a_mask_acc_140}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_8 = {atomics_a_mask_acc_143, atomics_a_mask_acc_142}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_hi_hi_hi_8, atomics_a_mask_hi_hi_lo_8}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10] assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [2:0] _GEN_112 = _atomics_T ? 3'h3 : 3'h0; // @[DCache.scala:587:81] wire [2:0] _atomics_T_1_opcode; // @[DCache.scala:587:81] assign _atomics_T_1_opcode = _GEN_112; // @[DCache.scala:587:81] wire [2:0] _atomics_T_1_param; // @[DCache.scala:587:81] assign _atomics_T_1_param = _GEN_112; // @[DCache.scala:587:81] wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17] wire _atomics_T_1_source = _atomics_T & atomics_a_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17] wire [15:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 16'h0; // @[Edges.scala:534:17] wire [127:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 128'h0; // @[Edges.scala:534:17] wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17] wire _atomics_T_3_source = _atomics_T_2 ? atomics_a_1_source : _atomics_T_1_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17] wire _atomics_T_5_source = _atomics_T_4 ? atomics_a_2_source : _atomics_T_3_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17] wire _atomics_T_7_source = _atomics_T_6 ? atomics_a_3_source : _atomics_T_5_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17] wire _atomics_T_9_source = _atomics_T_8 ? atomics_a_4_source : _atomics_T_7_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17] wire _atomics_T_11_source = _atomics_T_10 ? atomics_a_5_source : _atomics_T_9_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17] wire _atomics_T_13_source = _atomics_T_12 ? atomics_a_6_source : _atomics_T_11_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17] wire _atomics_T_15_source = _atomics_T_14 ? atomics_a_7_source : _atomics_T_13_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17] wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[DCache.scala:587:81] wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[DCache.scala:587:81] wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17] wire atomics_source = _atomics_T_16 ? atomics_a_8_source : _atomics_T_15_source; // @[Edges.scala:517:17] wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17] wire [15:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17] wire [127:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17] wire [39:0] _tl_out_a_valid_T_1 = {s2_req_addr[39:32], s2_req_addr[31:0] ^ release_ack_addr}; // @[DCache.scala:227:29, :339:19, :606:43] wire [14:0] _tl_out_a_valid_T_2 = _tl_out_a_valid_T_1[20:6]; // @[DCache.scala:606:{43,62}] wire _tl_out_a_valid_T_3 = _tl_out_a_valid_T_2 == 15'h0; // @[DCache.scala:582:29, :606:{62,118}] wire _tl_out_a_valid_T_4 = release_ack_wait & _tl_out_a_valid_T_3; // @[DCache.scala:226:33, :606:{27,118}] wire _tl_out_a_valid_T_5 = ~_tl_out_a_valid_T_4; // @[DCache.scala:606:{8,27}] wire _tl_out_a_valid_T_6 = s2_valid_cached_miss & _tl_out_a_valid_T_5; // @[DCache.scala:425:60, :605:29, :606:8] wire _tl_out_a_valid_T_7 = ~release_ack_wait; // @[DCache.scala:226:33, :607:47] wire _tl_out_a_valid_T_10 = ~s2_victim_dirty; // @[Misc.scala:38:9] wire _tl_out_a_valid_T_11 = _tl_out_a_valid_T_10; // @[DCache.scala:607:{88,91}] wire _tl_out_a_valid_T_12 = _tl_out_a_valid_T_6 & _tl_out_a_valid_T_11; // @[DCache.scala:605:29, :606:127, :607:88] wire _tl_out_a_valid_T_13 = s2_valid_uncached_pending | _tl_out_a_valid_T_12; // @[DCache.scala:430:64, :604:32, :606:127] assign _tl_out_a_valid_T_14 = _tl_out_a_valid_T_13; // @[DCache.scala:603:37, :604:32] assign tl_out_a_valid = _tl_out_a_valid_T_14; // @[DCache.scala:159:22, :603:37] wire _tl_out_a_bits_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47, :608:24] wire [39:0] _tl_out_a_bits_T_2 = {_tl_out_a_bits_T_1, 6'h0}; // @[DCache.scala:1210:{39,60}] wire [39:0] _tl_out_a_bits_legal_T_1 = _tl_out_a_bits_T_2; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_2 = {1'h0, _tl_out_a_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_3 = _tl_out_a_bits_legal_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_4 = _tl_out_a_bits_legal_T_3; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_5 = _tl_out_a_bits_legal_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _tl_out_a_bits_legal_T_6 = {_tl_out_a_bits_T_2[39:17], _tl_out_a_bits_T_2[16:0] ^ 17'h10000}; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_7 = {1'h0, _tl_out_a_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_8 = _tl_out_a_bits_legal_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_9 = _tl_out_a_bits_legal_T_8; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_10 = _tl_out_a_bits_legal_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _tl_out_a_bits_legal_T_11 = {_tl_out_a_bits_T_2[39:28], _tl_out_a_bits_T_2[27:0] ^ 28'hC000000}; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_12 = {1'h0, _tl_out_a_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_13 = _tl_out_a_bits_legal_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_14 = _tl_out_a_bits_legal_T_13; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_15 = _tl_out_a_bits_legal_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _tl_out_a_bits_legal_T_16 = _tl_out_a_bits_legal_T_5 | _tl_out_a_bits_legal_T_10; // @[Parameters.scala:685:42] wire _tl_out_a_bits_legal_T_17 = _tl_out_a_bits_legal_T_16 | _tl_out_a_bits_legal_T_15; // @[Parameters.scala:685:42] wire [39:0] _tl_out_a_bits_legal_T_21 = {_tl_out_a_bits_T_2[39:28], _tl_out_a_bits_T_2[27:0] ^ 28'h8000000}; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_22 = {1'h0, _tl_out_a_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_23 = _tl_out_a_bits_legal_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_24 = _tl_out_a_bits_legal_T_23; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_25 = _tl_out_a_bits_legal_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] tl_out_a_bits_a_address = _tl_out_a_bits_T_2[31:0]; // @[Edges.scala:346:17] wire [39:0] _tl_out_a_bits_legal_T_26 = {_tl_out_a_bits_T_2[39:32], tl_out_a_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [40:0] _tl_out_a_bits_legal_T_27 = {1'h0, _tl_out_a_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_28 = _tl_out_a_bits_legal_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_29 = _tl_out_a_bits_legal_T_28; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_30 = _tl_out_a_bits_legal_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _tl_out_a_bits_legal_T_31 = _tl_out_a_bits_legal_T_25 | _tl_out_a_bits_legal_T_30; // @[Parameters.scala:685:42] wire _tl_out_a_bits_legal_T_32 = _tl_out_a_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire tl_out_a_bits_legal = _tl_out_a_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] wire [2:0] tl_out_a_bits_a_param; // @[Edges.scala:346:17] assign tl_out_a_bits_a_param = {1'h0, s2_grow_param}; // @[Misc.scala:35:36] wire tl_out_a_bits_a_mask_sub_sub_sub_bit = _tl_out_a_bits_T_2[3]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_sub_sub_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_sub_sub_sub_nbit = ~tl_out_a_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_sub_sub_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_sub_bit = _tl_out_a_bits_T_2[2]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_sub_sub_nbit = ~tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_sub_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_sub_sub_acc_T = tl_out_a_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_sub_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_sub_sub_acc_T_1 = tl_out_a_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_sub_sub_2_2 = tl_out_a_bits_a_mask_sub_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_sub_sub_acc_T_2 = tl_out_a_bits_a_mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_sub_sub_3_2 = tl_out_a_bits_a_mask_sub_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_sub_sub_acc_T_3 = tl_out_a_bits_a_mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_sub_bit = _tl_out_a_bits_T_2[1]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_sub_nbit = ~tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_sub_2_2 = tl_out_a_bits_a_mask_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_3_2 = tl_out_a_bits_a_mask_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_sub_4_2 = tl_out_a_bits_a_mask_sub_sub_2_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_5_2 = tl_out_a_bits_a_mask_sub_sub_2_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_sub_6_2 = tl_out_a_bits_a_mask_sub_sub_3_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_7_2 = tl_out_a_bits_a_mask_sub_sub_3_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_bit = _tl_out_a_bits_T_2[0]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_nbit = ~tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_eq = tl_out_a_bits_a_mask_sub_0_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T = tl_out_a_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_1 = tl_out_a_bits_a_mask_sub_0_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_1 = tl_out_a_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_2 = tl_out_a_bits_a_mask_sub_1_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_2 = tl_out_a_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_3 = tl_out_a_bits_a_mask_sub_1_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_3 = tl_out_a_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_4 = tl_out_a_bits_a_mask_sub_2_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_4 = tl_out_a_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_5 = tl_out_a_bits_a_mask_sub_2_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_5 = tl_out_a_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_6 = tl_out_a_bits_a_mask_sub_3_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_6 = tl_out_a_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_7 = tl_out_a_bits_a_mask_sub_3_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_7 = tl_out_a_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_8 = tl_out_a_bits_a_mask_sub_4_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_8 = tl_out_a_bits_a_mask_eq_8; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_9 = tl_out_a_bits_a_mask_sub_4_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_9 = tl_out_a_bits_a_mask_eq_9; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_10 = tl_out_a_bits_a_mask_sub_5_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_10 = tl_out_a_bits_a_mask_eq_10; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_11 = tl_out_a_bits_a_mask_sub_5_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_11 = tl_out_a_bits_a_mask_eq_11; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_12 = tl_out_a_bits_a_mask_sub_6_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_12 = tl_out_a_bits_a_mask_eq_12; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_13 = tl_out_a_bits_a_mask_sub_6_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_13 = tl_out_a_bits_a_mask_eq_13; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_14 = tl_out_a_bits_a_mask_sub_7_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_14 = tl_out_a_bits_a_mask_eq_14; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_15 = tl_out_a_bits_a_mask_sub_7_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_15 = tl_out_a_bits_a_mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _tl_out_a_bits_T_3 = ~s2_write; // @[DCache.scala:609:9] wire _tl_out_a_bits_T_5 = ~s2_read; // @[DCache.scala:611:9] wire [2:0] _tl_out_a_bits_T_6_opcode = _tl_out_a_bits_T_5 ? 3'h0 : atomics_opcode; // @[DCache.scala:587:81, :611:{8,9}] wire [2:0] _tl_out_a_bits_T_6_param = _tl_out_a_bits_T_5 ? 3'h0 : atomics_param; // @[DCache.scala:587:81, :611:{8,9}] wire [3:0] _tl_out_a_bits_T_6_size = _tl_out_a_bits_T_5 ? put_size : atomics_size; // @[Edges.scala:480:17] wire _tl_out_a_bits_T_6_source = _tl_out_a_bits_T_5 ? put_source : atomics_source; // @[Edges.scala:480:17] wire [31:0] _tl_out_a_bits_T_6_address = _tl_out_a_bits_T_5 ? put_address : atomics_address; // @[Edges.scala:480:17] wire [15:0] _tl_out_a_bits_T_6_mask = _tl_out_a_bits_T_5 ? put_mask : atomics_mask; // @[Edges.scala:480:17] wire [127:0] _tl_out_a_bits_T_6_data = _tl_out_a_bits_T_5 ? put_data : atomics_data; // @[Edges.scala:480:17] wire [2:0] _tl_out_a_bits_T_7_opcode = _tl_out_a_bits_T_4 ? 3'h1 : _tl_out_a_bits_T_6_opcode; // @[DCache.scala:610:{8,20}, :611:8] wire [2:0] _tl_out_a_bits_T_7_param = _tl_out_a_bits_T_4 ? 3'h0 : _tl_out_a_bits_T_6_param; // @[DCache.scala:610:{8,20}, :611:8] wire [3:0] _tl_out_a_bits_T_7_size = _tl_out_a_bits_T_4 ? putpartial_size : _tl_out_a_bits_T_6_size; // @[Edges.scala:500:17] wire _tl_out_a_bits_T_7_source = _tl_out_a_bits_T_4 ? putpartial_source : _tl_out_a_bits_T_6_source; // @[Edges.scala:500:17] wire [31:0] _tl_out_a_bits_T_7_address = _tl_out_a_bits_T_4 ? putpartial_address : _tl_out_a_bits_T_6_address; // @[Edges.scala:500:17] wire [15:0] _tl_out_a_bits_T_7_mask = _tl_out_a_bits_T_4 ? putpartial_mask : _tl_out_a_bits_T_6_mask; // @[Edges.scala:500:17] wire [127:0] _tl_out_a_bits_T_7_data = _tl_out_a_bits_T_4 ? putpartial_data : _tl_out_a_bits_T_6_data; // @[Edges.scala:500:17] wire [2:0] _tl_out_a_bits_T_8_opcode = _tl_out_a_bits_T_3 ? 3'h4 : _tl_out_a_bits_T_7_opcode; // @[DCache.scala:609:{8,9}, :610:8] wire [2:0] _tl_out_a_bits_T_8_param = _tl_out_a_bits_T_3 ? 3'h0 : _tl_out_a_bits_T_7_param; // @[DCache.scala:609:{8,9}, :610:8] wire [3:0] _tl_out_a_bits_T_8_size = _tl_out_a_bits_T_3 ? get_size : _tl_out_a_bits_T_7_size; // @[Edges.scala:460:17] wire _tl_out_a_bits_T_8_source = _tl_out_a_bits_T_3 ? get_source : _tl_out_a_bits_T_7_source; // @[Edges.scala:460:17] wire [31:0] _tl_out_a_bits_T_8_address = _tl_out_a_bits_T_3 ? get_address : _tl_out_a_bits_T_7_address; // @[Edges.scala:460:17] wire [15:0] _tl_out_a_bits_T_8_mask = _tl_out_a_bits_T_3 ? get_mask : _tl_out_a_bits_T_7_mask; // @[Edges.scala:460:17] wire [127:0] _tl_out_a_bits_T_8_data = _tl_out_a_bits_T_3 ? 128'h0 : _tl_out_a_bits_T_7_data; // @[DCache.scala:609:{8,9}, :610:8] assign _tl_out_a_bits_T_9_opcode = _tl_out_a_bits_T ? 3'h6 : _tl_out_a_bits_T_8_opcode; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_param = _tl_out_a_bits_T ? tl_out_a_bits_a_param : _tl_out_a_bits_T_8_param; // @[Edges.scala:346:17] assign _tl_out_a_bits_T_9_size = _tl_out_a_bits_T ? 4'h6 : _tl_out_a_bits_T_8_size; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_source = ~_tl_out_a_bits_T & _tl_out_a_bits_T_8_source; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_address = _tl_out_a_bits_T ? tl_out_a_bits_a_address : _tl_out_a_bits_T_8_address; // @[Edges.scala:346:17] assign _tl_out_a_bits_T_9_mask = _tl_out_a_bits_T ? 16'hFFFF : _tl_out_a_bits_T_8_mask; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_data = _tl_out_a_bits_T ? 128'h0 : _tl_out_a_bits_T_8_data; // @[DCache.scala:608:{23,24}, :609:8] assign tl_out_a_bits_opcode = _tl_out_a_bits_T_9_opcode; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_param = _tl_out_a_bits_T_9_param; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_size = _tl_out_a_bits_T_9_size; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_source = _tl_out_a_bits_T_9_source; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_address = _tl_out_a_bits_T_9_address; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_mask = _tl_out_a_bits_T_9_mask; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_data = _tl_out_a_bits_T_9_data; // @[DCache.scala:159:22, :608:23] wire [1:0] _a_sel_T = 2'h1 << a_sel_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _a_sel_T_1 = _a_sel_T; // @[OneHot.scala:65:{12,27}] wire a_sel = _a_sel_T_1[1]; // @[OneHot.scala:65:27] wire _io_cpu_perf_acquire_T = tl_out_a_ready & tl_out_a_valid; // @[Decoupled.scala:51:35] wire [4:0] _uncachedReqs_0_cmd_T_1 = {_uncachedReqs_0_cmd_T, 4'h1}; // @[DCache.scala:637:{37,49}] wire [4:0] _uncachedReqs_0_cmd_T_2 = s2_write ? _uncachedReqs_0_cmd_T_1 : 5'h0; // @[DCache.scala:637:{23,37}] wire _T_90 = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35] wire _io_cpu_replay_next_T; // @[Decoupled.scala:51:35] assign _io_cpu_replay_next_T = _T_90; // @[Decoupled.scala:51:35] wire _io_cpu_perf_blocked_near_end_of_refill_T; // @[Decoupled.scala:51:35] assign _io_cpu_perf_blocked_near_end_of_refill_T = _T_90; // @[Decoupled.scala:51:35] wire _io_errors_bus_valid_T; // @[Decoupled.scala:51:35] assign _io_errors_bus_valid_T = _T_90; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << nodeOut_d_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] r_beats1_decode = _r_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire r_beats1_opdata = nodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [7:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] r_counter; // @[Edges.scala:229:27] wire [8:0] _r_counter1_T = {1'h0, r_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] r_counter1 = _r_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = r_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_done = d_last & _T_90; // @[Decoupled.scala:51:35] wire [7:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _r_counter_T = d_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] d_address_inc = {r_4, 4'h0}; // @[Edges.scala:234:25, :269:29] wire grantIsUncachedData = nodeOut_d_bits_opcode == 3'h1; // @[package.scala:16:47] wire grantIsUncached = grantIsUncachedData | nodeOut_d_bits_opcode == 3'h0 | nodeOut_d_bits_opcode == 3'h2; // @[package.scala:16:47, :81:59] wire _tl_d_data_encoded_T_17 = io_ptw_customCSRs_csrs_0_value_0[9]; // @[CustomCSRs.scala:47:65] wire _tl_d_data_encoded_T_18 = ~_tl_d_data_encoded_T_17; // @[CustomCSRs.scala:47:65] wire _tl_d_data_encoded_T_19 = nodeOut_d_bits_corrupt & _tl_d_data_encoded_T_18; // @[DCache.scala:663:{77,80}] wire _tl_d_data_encoded_T_20 = ~grantIsUncached; // @[package.scala:81:59] wire _tl_d_data_encoded_T_21 = _tl_d_data_encoded_T_19 & _tl_d_data_encoded_T_20; // @[DCache.scala:663:{77,126,129}] wire [15:0] tl_d_data_encoded_lo_lo_lo_1 = {_tl_d_data_encoded_T_23, _tl_d_data_encoded_T_22}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_lo_hi_1 = {_tl_d_data_encoded_T_25, _tl_d_data_encoded_T_24}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo_lo_1 = {tl_d_data_encoded_lo_lo_hi_1, tl_d_data_encoded_lo_lo_lo_1}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_lo_hi_lo_1 = {_tl_d_data_encoded_T_27, _tl_d_data_encoded_T_26}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_hi_hi_1 = {_tl_d_data_encoded_T_29, _tl_d_data_encoded_T_28}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo_hi_1 = {tl_d_data_encoded_lo_hi_hi_1, tl_d_data_encoded_lo_hi_lo_1}; // @[package.scala:45:27] wire [63:0] tl_d_data_encoded_lo_1 = {tl_d_data_encoded_lo_hi_1, tl_d_data_encoded_lo_lo_1}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_lo_lo_1 = {_tl_d_data_encoded_T_31, _tl_d_data_encoded_T_30}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_lo_hi_1 = {_tl_d_data_encoded_T_33, _tl_d_data_encoded_T_32}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi_lo_1 = {tl_d_data_encoded_hi_lo_hi_1, tl_d_data_encoded_hi_lo_lo_1}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_hi_lo_1 = {_tl_d_data_encoded_T_35, _tl_d_data_encoded_T_34}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_hi_hi_1 = {_tl_d_data_encoded_T_37, _tl_d_data_encoded_T_36}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi_hi_1 = {tl_d_data_encoded_hi_hi_hi_1, tl_d_data_encoded_hi_hi_lo_1}; // @[package.scala:45:27] wire [63:0] tl_d_data_encoded_hi_1 = {tl_d_data_encoded_hi_hi_1, tl_d_data_encoded_hi_lo_1}; // @[package.scala:45:27] assign _tl_d_data_encoded_T_38 = {tl_d_data_encoded_hi_1, tl_d_data_encoded_lo_1}; // @[package.scala:45:27] assign tl_d_data_encoded = _tl_d_data_encoded_T_38; // @[package.scala:45:27] wire _grantIsCached_T = nodeOut_d_bits_opcode == 3'h4; // @[package.scala:16:47] wire _GEN_113 = nodeOut_d_bits_opcode == 3'h5; // @[package.scala:16:47] wire _grantIsCached_T_1; // @[package.scala:16:47] assign _grantIsCached_T_1 = _GEN_113; // @[package.scala:16:47] wire grantIsRefill; // @[DCache.scala:666:29] assign grantIsRefill = _GEN_113; // @[package.scala:16:47] wire grantIsCached = _grantIsCached_T | _grantIsCached_T_1; // @[package.scala:16:47, :81:59] wire grantIsVoluntary = nodeOut_d_bits_opcode == 3'h6; // @[DCache.scala:665:32] reg grantInProgress; // @[DCache.scala:667:32] reg [2:0] blockProbeAfterGrantCount; // @[DCache.scala:668:42] wire [3:0] _blockProbeAfterGrantCount_T = {1'h0, blockProbeAfterGrantCount} - 4'h1; // @[DCache.scala:668:42, :669:99] wire [2:0] _blockProbeAfterGrantCount_T_1 = _blockProbeAfterGrantCount_T[2:0]; // @[DCache.scala:669:99] wire _T_115 = release_state == 4'h6; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_1; // @[package.scala:16:47] assign _canAcceptCachedGrant_T_1 = _T_115; // @[package.scala:16:47] wire _metaArb_io_in_4_valid_T; // @[package.scala:16:47] assign _metaArb_io_in_4_valid_T = _T_115; // @[package.scala:16:47] wire _T_119 = release_state == 4'h9; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_2; // @[package.scala:16:47] assign _canAcceptCachedGrant_T_2 = _T_119; // @[package.scala:16:47] wire _nodeOut_c_valid_T_1; // @[DCache.scala:810:91] assign _nodeOut_c_valid_T_1 = _T_119; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_3 = _canAcceptCachedGrant_T | _canAcceptCachedGrant_T_1; // @[package.scala:16:47, :81:59] wire _canAcceptCachedGrant_T_4 = _canAcceptCachedGrant_T_3 | _canAcceptCachedGrant_T_2; // @[package.scala:16:47, :81:59] wire canAcceptCachedGrant = ~_canAcceptCachedGrant_T_4; // @[package.scala:81:59] wire _nodeOut_d_ready_T = ~d_first; // @[Edges.scala:231:25] wire _nodeOut_d_ready_T_1 = _nodeOut_d_ready_T | nodeOut_e_ready; // @[DCache.scala:671:{41,50}] wire _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T_1 & canAcceptCachedGrant; // @[DCache.scala:670:30, :671:{50,69}] wire _nodeOut_d_ready_T_3 = ~grantIsCached | _nodeOut_d_ready_T_2; // @[package.scala:81:59] wire [1:0] _uncachedRespIdxOH_T = 2'h1 << uncachedRespIdxOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _uncachedRespIdxOH_T_1 = _uncachedRespIdxOH_T; // @[OneHot.scala:65:{12,27}] wire uncachedRespIdxOH = _uncachedRespIdxOH_T_1[1]; // @[OneHot.scala:65:27] wire _uncachedResp_T = uncachedRespIdxOH; // @[Mux.scala:32:36] wire _GEN_114 = _T_90 & grantIsCached; // @[Decoupled.scala:51:35] assign replace = _GEN_114 & d_last; // @[Replacement.scala:37:29, :38:11] wire _T_82 = uncachedRespIdxOH & d_last; // @[Edges.scala:232:33] assign s1_data_way = ~_T_90 | grantIsCached | ~(grantIsUncached & grantIsUncachedData) ? {1'h0, _s1_data_way_T} : 9'h100; // @[Decoupled.scala:51:35] wire [27:0] _s2_req_addr_dontCareBits_T = s1_paddr[31:4]; // @[DCache.scala:298:21, :701:41] wire [31:0] s2_req_addr_dontCareBits = {_s2_req_addr_dontCareBits_T, 4'h0}; // @[DCache.scala:701:{41,55}] wire [3:0] _s2_req_addr_T = uncachedResp_addr[3:0]; // @[DCache.scala:238:30, :702:45] wire [31:0] _s2_req_addr_T_1 = {s2_req_addr_dontCareBits[31:4], s2_req_addr_dontCareBits[3:0] | _s2_req_addr_T}; // @[DCache.scala:701:55, :702:{26,45}] wire _nodeOut_e_valid_T = nodeOut_d_valid & d_first; // @[Edges.scala:231:25] wire _nodeOut_e_valid_T_1 = _nodeOut_e_valid_T & grantIsCached; // @[package.scala:81:59] wire _nodeOut_e_valid_T_2 = _nodeOut_e_valid_T_1 & canAcceptCachedGrant; // @[DCache.scala:670:30, :714:{47,64}] assign nodeOut_e_bits_sink = nodeOut_e_bits_e_sink; // @[Edges.scala:451:17] wire _dataArb_io_in_1_valid_T = nodeOut_d_valid & grantIsRefill; // @[DCache.scala:666:29, :721:44] wire _dataArb_io_in_1_valid_T_1 = _dataArb_io_in_1_valid_T & canAcceptCachedGrant; // @[DCache.scala:670:30, :721:{44,61}] wire _T_98 = grantIsRefill & ~dataArb_io_in_1_ready; // @[DCache.scala:152:28, :666:29, :722:{23,26}] assign nodeOut_e_valid = ~_T_98 & _nodeOut_e_valid_T_2; // @[DCache.scala:714:{18,64}, :722:{23,51}, :723:20] wire [33:0] _dataArb_io_in_1_bits_addr_T = s2_vaddr[39:6]; // @[DCache.scala:351:21, :728:46] wire [39:0] _dataArb_io_in_1_bits_addr_T_1 = {_dataArb_io_in_1_bits_addr_T, 6'h0}; // @[DCache.scala:728:{46,57}] wire [39:0] _dataArb_io_in_1_bits_addr_T_2 = {_dataArb_io_in_1_bits_addr_T_1[39:12], _dataArb_io_in_1_bits_addr_T_1[11:0] | d_address_inc}; // @[Edges.scala:269:29] assign dataArb_io_in_1_bits_addr = _dataArb_io_in_1_bits_addr_T_2[11:0]; // @[DCache.scala:152:28, :728:{32,67}] wire _metaArb_io_in_3_valid_T = grantIsCached & d_done; // @[package.scala:81:59] wire _metaArb_io_in_3_valid_T_1 = ~nodeOut_d_bits_denied; // @[DCache.scala:741:56] assign _metaArb_io_in_3_valid_T_2 = _metaArb_io_in_3_valid_T & _metaArb_io_in_3_valid_T_1; // @[DCache.scala:741:{43,53,56}] assign metaArb_io_in_3_valid = _metaArb_io_in_3_valid_T_2; // @[DCache.scala:135:28, :741:53] assign metaArb_io_in_3_bits_idx = _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:135:28, :744:40] assign _metaArb_io_in_3_bits_addr_T_2 = {_metaArb_io_in_3_bits_addr_T, _metaArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:745:{36,58,80}] assign metaArb_io_in_3_bits_addr = _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:135:28, :745:36] wire _metaArb_io_in_3_bits_data_c_cat_T_2 = _metaArb_io_in_3_bits_data_c_cat_T | _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _metaArb_io_in_3_bits_data_c_cat_T_4 = _metaArb_io_in_3_bits_data_c_cat_T_2 | _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _metaArb_io_in_3_bits_data_c_cat_T_9 = _metaArb_io_in_3_bits_data_c_cat_T_5 | _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_10 = _metaArb_io_in_3_bits_data_c_cat_T_9 | _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_11 = _metaArb_io_in_3_bits_data_c_cat_T_10 | _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_17 = _metaArb_io_in_3_bits_data_c_cat_T_12 | _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_18 = _metaArb_io_in_3_bits_data_c_cat_T_17 | _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_19 = _metaArb_io_in_3_bits_data_c_cat_T_18 | _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_20 = _metaArb_io_in_3_bits_data_c_cat_T_19 | _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_21 = _metaArb_io_in_3_bits_data_c_cat_T_11 | _metaArb_io_in_3_bits_data_c_cat_T_20; // @[package.scala:81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_22 = _metaArb_io_in_3_bits_data_c_cat_T_4 | _metaArb_io_in_3_bits_data_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _metaArb_io_in_3_bits_data_c_cat_T_25 = _metaArb_io_in_3_bits_data_c_cat_T_23 | _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _metaArb_io_in_3_bits_data_c_cat_T_27 = _metaArb_io_in_3_bits_data_c_cat_T_25 | _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _metaArb_io_in_3_bits_data_c_cat_T_32 = _metaArb_io_in_3_bits_data_c_cat_T_28 | _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_33 = _metaArb_io_in_3_bits_data_c_cat_T_32 | _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_34 = _metaArb_io_in_3_bits_data_c_cat_T_33 | _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_40 = _metaArb_io_in_3_bits_data_c_cat_T_35 | _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_41 = _metaArb_io_in_3_bits_data_c_cat_T_40 | _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_42 = _metaArb_io_in_3_bits_data_c_cat_T_41 | _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_43 = _metaArb_io_in_3_bits_data_c_cat_T_42 | _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_44 = _metaArb_io_in_3_bits_data_c_cat_T_34 | _metaArb_io_in_3_bits_data_c_cat_T_43; // @[package.scala:81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_45 = _metaArb_io_in_3_bits_data_c_cat_T_27 | _metaArb_io_in_3_bits_data_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _metaArb_io_in_3_bits_data_c_cat_T_47 = _metaArb_io_in_3_bits_data_c_cat_T_45 | _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _metaArb_io_in_3_bits_data_c_cat_T_49 = _metaArb_io_in_3_bits_data_c_cat_T_47 | _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] metaArb_io_in_3_bits_data_c = {_metaArb_io_in_3_bits_data_c_cat_T_22, _metaArb_io_in_3_bits_data_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _metaArb_io_in_3_bits_data_T_1 = {metaArb_io_in_3_bits_data_c, nodeOut_d_bits_param}; // @[Metadata.scala:29:18, :84:18] wire _metaArb_io_in_3_bits_data_T_10 = _metaArb_io_in_3_bits_data_T_1 == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_11 = {1'h0, _metaArb_io_in_3_bits_data_T_10}; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_12 = _metaArb_io_in_3_bits_data_T_1 == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_13 = _metaArb_io_in_3_bits_data_T_12 ? 2'h2 : _metaArb_io_in_3_bits_data_T_11; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_14 = _metaArb_io_in_3_bits_data_T_1 == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_15 = _metaArb_io_in_3_bits_data_T_14 ? 2'h2 : _metaArb_io_in_3_bits_data_T_13; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_16 = _metaArb_io_in_3_bits_data_T_1 == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_17 = _metaArb_io_in_3_bits_data_T_16 ? 2'h3 : _metaArb_io_in_3_bits_data_T_15; // @[Metadata.scala:84:38] wire [1:0] metaArb_io_in_3_bits_data_meta_state = _metaArb_io_in_3_bits_data_T_17; // @[Metadata.scala:84:38, :160:20] wire [1:0] metaArb_io_in_3_bits_data_meta_1_coh_state = metaArb_io_in_3_bits_data_meta_state; // @[Metadata.scala:160:20] wire [19:0] metaArb_io_in_3_bits_data_meta_1_tag; // @[HellaCache.scala:305:20] assign metaArb_io_in_3_bits_data_meta_1_tag = _metaArb_io_in_3_bits_data_T[19:0]; // @[HellaCache.scala:305:20, :306:14] assign _metaArb_io_in_3_bits_data_T_18 = {metaArb_io_in_3_bits_data_meta_1_coh_state, metaArb_io_in_3_bits_data_meta_1_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_3_bits_data = _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:135:28, :746:134] reg blockUncachedGrant; // @[DCache.scala:750:33] wire _T_100 = grantIsUncachedData & (blockUncachedGrant | s1_valid); // @[package.scala:16:47] assign nodeOut_d_ready = ~(_T_100 | _T_98) & _nodeOut_d_ready_T_3; // @[DCache.scala:671:{18,24}, :722:{23,51}, :724:20, :752:{31,68}, :753:22] assign io_cpu_req_ready_0 = _T_100 ? ~(nodeOut_d_valid | _T_10 | ~metaArb_io_in_7_ready | _T_4) & _io_cpu_req_ready_T_4 : ~(_T_10 | ~metaArb_io_in_7_ready | _T_4) & _io_cpu_req_ready_T_4; // @[DCache.scala:101:7, :135:28, :195:9, :233:{20,73}, :258:{33,45,64}, :267:{34,53}, :275:{27,53,79,98}, :752:{31,68}, :755:29, :756:26] wire _GEN_115 = _T_100 & nodeOut_d_valid; // @[DCache.scala:721:26, :752:{31,68}, :755:29, :757:32] assign dataArb_io_in_1_valid = _GEN_115 | _dataArb_io_in_1_valid_T_1; // @[DCache.scala:152:28, :721:{26,61}, :752:68, :755:29, :757:32] assign dataArb_io_in_1_bits_write = ~_T_100 | ~nodeOut_d_valid; // @[DCache.scala:152:28, :727:33, :752:{31,68}, :755:29, :758:37] wire _blockUncachedGrant_T = ~dataArb_io_in_1_ready; // @[DCache.scala:152:28, :722:26, :759:31] wire _block_probe_for_core_progress_T = |blockProbeAfterGrantCount; // @[DCache.scala:668:42, :669:35, :766:65] wire block_probe_for_core_progress = _block_probe_for_core_progress_T | lrscValid; // @[DCache.scala:473:29, :766:{65,71}] wire [31:0] _block_probe_for_pending_release_ack_T = nodeOut_b_bits_address ^ release_ack_addr; // @[DCache.scala:227:29, :767:88] wire [14:0] _block_probe_for_pending_release_ack_T_1 = _block_probe_for_pending_release_ack_T[20:6]; // @[DCache.scala:767:{88,107}] wire _block_probe_for_pending_release_ack_T_2 = _block_probe_for_pending_release_ack_T_1 == 15'h0; // @[DCache.scala:582:29, :767:{107,163}] wire block_probe_for_pending_release_ack = release_ack_wait & _block_probe_for_pending_release_ack_T_2; // @[DCache.scala:226:33, :767:{62,163}] wire _block_probe_for_ordering_T = releaseInFlight | block_probe_for_pending_release_ack; // @[DCache.scala:334:46, :767:62, :768:50] wire block_probe_for_ordering = _block_probe_for_ordering_T | grantInProgress; // @[DCache.scala:667:32, :768:{50,89}] wire _metaArb_io_in_6_valid_T = ~block_probe_for_core_progress; // @[DCache.scala:766:71, :769:48] wire _metaArb_io_in_6_valid_T_1 = _metaArb_io_in_6_valid_T | lrscBackingOff; // @[DCache.scala:474:40, :769:{48,79}] wire _metaArb_io_in_6_valid_T_2 = nodeOut_b_valid & _metaArb_io_in_6_valid_T_1; // @[DCache.scala:769:{44,79}] wire _nodeOut_b_ready_T = block_probe_for_core_progress | block_probe_for_ordering; // @[DCache.scala:766:71, :768:89, :770:79] wire _nodeOut_b_ready_T_1 = _nodeOut_b_ready_T | s1_valid; // @[DCache.scala:182:25, :770:{79,107}] wire _nodeOut_b_ready_T_2 = _nodeOut_b_ready_T_1 | s2_valid; // @[DCache.scala:331:25, :770:{107,119}] wire _nodeOut_b_ready_T_3 = ~_nodeOut_b_ready_T_2; // @[DCache.scala:770:{47,119}] assign _nodeOut_b_ready_T_4 = metaArb_io_in_6_ready & _nodeOut_b_ready_T_3; // @[DCache.scala:135:28, :770:{44,47}] assign nodeOut_b_ready = _nodeOut_b_ready_T_4; // @[DCache.scala:770:44] wire [5:0] _metaArb_io_in_6_bits_idx_T = nodeOut_b_bits_address[11:6]; // @[DCache.scala:1200:47] wire [7:0] _metaArb_io_in_6_bits_addr_T = io_cpu_req_bits_addr_0[39:32]; // @[DCache.scala:101:7, :773:58] wire [7:0] _metaArb_io_in_6_bits_addr_T_2 = io_cpu_req_bits_addr_0[39:32]; // @[DCache.scala:101:7, :773:58, :844:62] wire [39:0] _metaArb_io_in_6_bits_addr_T_1 = {_metaArb_io_in_6_bits_addr_T, nodeOut_b_bits_address}; // @[DCache.scala:773:{36,58}] assign _s1_victim_way_T = lfsr[2:0]; // @[PRNG.scala:95:17] assign s1_victim_way = _s1_victim_way_T; // @[package.scala:163:13] wire _T_134 = nodeOut_c_ready & nodeOut_c_valid; // @[Decoupled.scala:51:35] wire _releaseRejected_T; // @[Decoupled.scala:51:35] assign _releaseRejected_T = _T_134; // @[Decoupled.scala:51:35] wire _io_cpu_perf_release_T; // @[Decoupled.scala:51:35] assign _io_cpu_perf_release_T = _T_134; // @[Decoupled.scala:51:35] wire [26:0] _GEN_116 = 27'hFFF << nodeOut_c_bits_size; // @[package.scala:243:71] wire [26:0] _r_beats1_decode_T_3; // @[package.scala:243:71] assign _r_beats1_decode_T_3 = _GEN_116; // @[package.scala:243:71] wire [26:0] _io_cpu_perf_release_beats1_decode_T; // @[package.scala:243:71] assign _io_cpu_perf_release_beats1_decode_T = _GEN_116; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_4 = _r_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_5 = ~_r_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] r_beats1_decode_1 = _r_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire r_beats1_opdata_1 = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36] wire io_cpu_perf_release_beats1_opdata = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36] wire [7:0] r_beats1_1 = r_beats1_opdata_1 ? r_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] r_counter_1; // @[Edges.scala:229:27] wire [8:0] _r_counter1_T_1 = {1'h0, r_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] r_counter1_1 = _r_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire c_first = r_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T_2 = r_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_3 = r_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_last = _r_last_T_2 | _r_last_T_3; // @[Edges.scala:232:{25,33,43}] wire releaseDone = c_last & _T_134; // @[Decoupled.scala:51:35] wire [7:0] _r_count_T_1 = ~r_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_count = r_beats1_1 & _r_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _r_counter_T_1 = c_first ? r_beats1_1 : r_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _releaseRejected_T_2; // @[DCache.scala:803:44] wire releaseRejected; // @[DCache.scala:800:29] wire _s1_release_data_valid_T = dataArb_io_in_2_ready & _dataArb_io_in_2_valid_T_1; // @[Decoupled.scala:51:35] reg s1_release_data_valid; // @[DCache.scala:801:38] wire _s2_release_data_valid_T = ~releaseRejected; // @[DCache.scala:800:29, :802:64] wire _s2_release_data_valid_T_1 = s1_release_data_valid & _s2_release_data_valid_T; // @[DCache.scala:801:38, :802:{61,64}] reg s2_release_data_valid; // @[DCache.scala:802:38] wire _nodeOut_c_valid_T_3 = s2_release_data_valid; // @[DCache.scala:802:38, :810:44] wire _releaseRejected_T_1 = ~_releaseRejected_T; // @[Decoupled.scala:51:35] assign _releaseRejected_T_2 = s2_release_data_valid & _releaseRejected_T_1; // @[DCache.scala:802:38, :803:{44,47}] assign releaseRejected = _releaseRejected_T_2; // @[DCache.scala:800:29, :803:44] wire [8:0] _releaseDataBeat_T = {1'h0, c_count}; // @[Edges.scala:234:25] wire [1:0] _releaseDataBeat_T_1 = {1'h0, s2_release_data_valid}; // @[DCache.scala:802:38, :804:98] wire [2:0] _releaseDataBeat_T_2 = {2'h0, s1_release_data_valid} + {1'h0, _releaseDataBeat_T_1}; // @[DCache.scala:801:38, :804:{93,98}] wire [1:0] _releaseDataBeat_T_3 = _releaseDataBeat_T_2[1:0]; // @[DCache.scala:804:93] wire [1:0] _releaseDataBeat_T_4 = releaseRejected ? 2'h0 : _releaseDataBeat_T_3; // @[DCache.scala:800:29, :804:{48,93}] wire [9:0] _releaseDataBeat_T_5 = {1'h0, _releaseDataBeat_T} + {8'h0, _releaseDataBeat_T_4}; // @[DCache.scala:804:{28,43,48}] wire [8:0] releaseDataBeat = _releaseDataBeat_T_5[8:0]; // @[DCache.scala:804:43] wire _nodeOut_c_valid_T_4 = c_first & release_ack_wait; // @[Edges.scala:231:25] wire _nodeOut_c_valid_T_5 = ~_nodeOut_c_valid_T_4; // @[DCache.scala:810:{120,130}] wire _nodeOut_c_valid_T_6 = _nodeOut_c_valid_T_3 & _nodeOut_c_valid_T_5; // @[DCache.scala:810:{44,117,120}] wire [1:0] newCoh_state; // @[DCache.scala:812:27] wire [1:0] metaArb_io_in_4_bits_data_meta_coh_state = newCoh_state; // @[HellaCache.scala:305:20] wire _release_state_T_8 = s2_valid_flush_line | s2_flush_valid; // @[DCache.scala:363:51, :419:75, :817:34, :820:151] wire _discard_line_T = s2_req_size[1]; // @[DCache.scala:339:19, :818:60] wire _discard_line_T_1 = s2_valid_flush_line & _discard_line_T; // @[DCache.scala:419:75, :818:{46,60}] wire _discard_line_T_3 = s2_flush_valid & _discard_line_T_2; // @[DCache.scala:363:51, :818:{82,102}] wire discard_line = _discard_line_T_1 | _discard_line_T_3; // @[DCache.scala:818:{46,64,82}] wire _release_state_T = ~discard_line; // @[DCache.scala:818:64, :819:47] wire _release_state_T_1 = s2_victim_dirty & _release_state_T; // @[Misc.scala:38:9] wire _release_state_T_3 = ~release_ack_wait; // @[DCache.scala:226:33, :607:47, :820:57] wire _release_state_T_6 = |s2_victim_state_state; // @[Metadata.scala:50:45] wire _release_state_T_9 = ~s2_hit_valid; // @[Metadata.scala:50:45] wire _release_state_T_10 = s2_readwrite & _release_state_T_9; // @[DCache.scala:354:30, :820:{185,188}] wire _release_state_T_11 = _release_state_T_8 | _release_state_T_10; // @[DCache.scala:820:{151,169,185}] wire [3:0] _release_state_T_14 = _release_state_T_1 ? 4'h1 : 4'h6; // @[DCache.scala:819:{27,44}] wire [5:0] _probe_bits_T_1 = s2_req_addr[11:6]; // @[DCache.scala:339:19, :822:76] wire [25:0] _probe_bits_T_2 = {s2_victim_tag, _probe_bits_T_1}; // @[DCache.scala:433:26, :822:{49,76}] wire [31:0] _probe_bits_T_3 = {_probe_bits_T_2, 6'h0}; // @[DCache.scala:822:{49,96}] wire [31:0] probe_bits_res_address = _probe_bits_T_3; // @[DCache.scala:822:96, :1202:19] wire probeNack; // @[DCache.scala:825:34] wire [3:0] _release_state_T_15 = {1'h0, releaseDone, 2'h3}; // @[Edges.scala:233:22] wire _probeNack_T = ~releaseDone; // @[Edges.scala:233:22] assign probeNack = s2_prb_ack_data | (|s2_probe_state_state) | _probeNack_T; // @[Misc.scala:38:9] wire [3:0] _release_state_T_16 = releaseDone ? 4'h0 : 4'h5; // @[Edges.scala:233:22] assign s1_nack = s2_probe ? probeNack | _T_68 | _T_48 | _T_14 : _T_68 | _T_48 | _T_14; // @[DCache.scala:185:28, :276:{39,58,79}, :288:{75,85}, :333:25, :446:{24,82,92}, :571:{18,36,46}, :824:21, :825:34, :839:{24,34}] wire _T_110 = release_state == 4'h4; // @[DCache.scala:228:30, :841:25] assign metaArb_io_in_6_valid = _T_110 | _metaArb_io_in_6_valid_T_2; // @[DCache.scala:135:28, :769:{26,44}, :841:{25,44}, :842:30] assign metaArb_io_in_6_bits_idx = _T_110 ? _metaArb_io_in_6_bits_idx_T_1 : _metaArb_io_in_6_bits_idx_T; // @[DCache.scala:135:28, :772:29, :841:{25,44}, :843:33, :1200:47] wire [39:0] _metaArb_io_in_6_bits_addr_T_3 = {_metaArb_io_in_6_bits_addr_T_2, probe_bits_address}; // @[DCache.scala:184:29, :844:{40,62}] assign metaArb_io_in_6_bits_addr = _T_110 ? _metaArb_io_in_6_bits_addr_T_3 : _metaArb_io_in_6_bits_addr_T_1; // @[DCache.scala:135:28, :773:{30,36}, :841:{25,44}, :844:{34,40}] wire _T_111 = release_state == 4'h5; // @[DCache.scala:228:30, :850:25] wire _T_112 = release_state == 4'h3; // @[DCache.scala:228:30, :854:25] assign nodeOut_c_valid = _T_112 | _T_111 | s2_probe & ~s2_prb_ack_data | _nodeOut_c_valid_T_6; // @[Misc.scala:38:9] wire _GEN_117 = _T_112 | ~(~s2_probe | s2_prb_ack_data | ~(|s2_probe_state_state)); // @[Misc.scala:38:9] wire _T_118 = _T_114 | _T_115 | _T_119; // @[package.scala:16:47, :81:59] assign nodeOut_c_bits_opcode = _T_118 ? {2'h3, ~_T_119} : {2'h2, _inWriteback_T_1}; // @[package.scala:16:47, :81:59] assign nodeOut_c_bits_param = _T_118 ? (_T_119 ? nodeOut_c_bits_c_param : nodeOut_c_bits_c_1_param) : _inWriteback_T_1 ? dirtyReleaseMessage_param : _GEN_117 ? cleanReleaseMessage_param : 3'h5; // @[package.scala:16:47, :81:59] assign nodeOut_c_bits_size = _T_118 ? 4'h6 : _inWriteback_T_1 ? dirtyReleaseMessage_size : _GEN_117 ? cleanReleaseMessage_size : nackResponseMessage_size; // @[package.scala:16:47, :81:59] assign newCoh_state = _T_118 ? voluntaryNewCoh_state : probeNewCoh_state; // @[package.scala:81:59] assign releaseWay = _T_118 ? s2_victim_or_hit_way : s2_probe_way; // @[package.scala:81:59] wire _dataArb_io_in_2_valid_T = releaseDataBeat < 9'h4; // @[DCache.scala:804:43, :900:60] assign _dataArb_io_in_2_valid_T_1 = inWriteback & _dataArb_io_in_2_valid_T; // @[package.scala:81:59] assign dataArb_io_in_2_valid = _dataArb_io_in_2_valid_T_1; // @[DCache.scala:152:28, :900:41] wire [11:0] _dataArb_io_in_2_bits_addr_T_1 = {_dataArb_io_in_2_bits_addr_T, 6'h0}; // @[DCache.scala:903:55, :1200:47] wire [1:0] _dataArb_io_in_2_bits_addr_T_2 = releaseDataBeat[1:0]; // @[DCache.scala:804:43, :903:90] wire [5:0] _dataArb_io_in_2_bits_addr_T_3 = {_dataArb_io_in_2_bits_addr_T_2, 4'h0}; // @[DCache.scala:903:{90,117}] assign _dataArb_io_in_2_bits_addr_T_4 = {_dataArb_io_in_2_bits_addr_T_1[11:6], _dataArb_io_in_2_bits_addr_T_1[5:0] | _dataArb_io_in_2_bits_addr_T_3}; // @[DCache.scala:903:{55,72,117}] assign dataArb_io_in_2_bits_addr = _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:152:28, :903:72] wire _metaArb_io_in_4_valid_T_1 = release_state == 4'h7; // @[package.scala:16:47] assign _metaArb_io_in_4_valid_T_2 = _metaArb_io_in_4_valid_T | _metaArb_io_in_4_valid_T_1; // @[package.scala:16:47, :81:59] assign metaArb_io_in_4_valid = _metaArb_io_in_4_valid_T_2; // @[package.scala:81:59] assign metaArb_io_in_4_bits_idx = _metaArb_io_in_4_bits_idx_T; // @[DCache.scala:135:28, :1200:47] wire [11:0] _metaArb_io_in_4_bits_addr_T_1 = probe_bits_address[11:0]; // @[DCache.scala:184:29, :912:90] assign _metaArb_io_in_4_bits_addr_T_2 = {_metaArb_io_in_4_bits_addr_T, _metaArb_io_in_4_bits_addr_T_1}; // @[DCache.scala:912:{36,58,90}] assign metaArb_io_in_4_bits_addr = _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:135:28, :912:36] wire [19:0] _metaArb_io_in_4_bits_data_T = nodeOut_c_bits_address[31:12]; // @[DCache.scala:913:78] wire [19:0] metaArb_io_in_4_bits_data_meta_tag = _metaArb_io_in_4_bits_data_T; // @[HellaCache.scala:305:20] assign _metaArb_io_in_4_bits_data_T_1 = {metaArb_io_in_4_bits_data_meta_coh_state, metaArb_io_in_4_bits_data_meta_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_4_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_5_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_6_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_7_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] wire _io_cpu_s2_uncached_T = ~s2_hit; // @[Misc.scala:35:9] assign _io_cpu_s2_uncached_T_1 = s2_uncached & _io_cpu_s2_uncached_T; // @[DCache.scala:424:39, :920:{37,40}] assign io_cpu_s2_uncached_0 = _io_cpu_s2_uncached_T_1; // @[DCache.scala:101:7, :920:37] wire _io_cpu_ordered_T_2 = ~s2_req_no_xcpt; // @[DCache.scala:339:19, :929:72] wire _io_cpu_ordered_T_3 = s2_valid & _io_cpu_ordered_T_2; // @[DCache.scala:331:25, :929:{69,72}] wire _io_cpu_ordered_T_4 = _io_cpu_ordered_T_1 | _io_cpu_ordered_T_3; // @[DCache.scala:929:{32,57,69}] wire _io_cpu_ordered_T_5 = _io_cpu_ordered_T_4 | cached_grant_wait; // @[DCache.scala:223:34, :929:{57,94}] wire _io_cpu_ordered_T_7 = _io_cpu_ordered_T_5 | _io_cpu_ordered_T_6; // @[DCache.scala:929:{94,115,142}] assign _io_cpu_ordered_T_8 = ~_io_cpu_ordered_T_7; // @[DCache.scala:929:{21,115}] assign io_cpu_ordered_0 = _io_cpu_ordered_T_8; // @[DCache.scala:101:7, :929:21] wire _io_cpu_store_pending_T_2 = _io_cpu_store_pending_T | _io_cpu_store_pending_T_1; // @[Consts.scala:90:{32,42,49}] wire _io_cpu_store_pending_T_4 = _io_cpu_store_pending_T_2 | _io_cpu_store_pending_T_3; // @[Consts.scala:90:{42,59,66}] wire _io_cpu_store_pending_T_9 = _io_cpu_store_pending_T_5 | _io_cpu_store_pending_T_6; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_10 = _io_cpu_store_pending_T_9 | _io_cpu_store_pending_T_7; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_11 = _io_cpu_store_pending_T_10 | _io_cpu_store_pending_T_8; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_17 = _io_cpu_store_pending_T_12 | _io_cpu_store_pending_T_13; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_18 = _io_cpu_store_pending_T_17 | _io_cpu_store_pending_T_14; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_19 = _io_cpu_store_pending_T_18 | _io_cpu_store_pending_T_15; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_20 = _io_cpu_store_pending_T_19 | _io_cpu_store_pending_T_16; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_21 = _io_cpu_store_pending_T_11 | _io_cpu_store_pending_T_20; // @[package.scala:81:59] wire _io_cpu_store_pending_T_22 = _io_cpu_store_pending_T_4 | _io_cpu_store_pending_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _io_cpu_store_pending_T_23 = cached_grant_wait & _io_cpu_store_pending_T_22; // @[DCache.scala:223:34, :930:46] assign _io_cpu_store_pending_T_25 = _io_cpu_store_pending_T_23 | _io_cpu_store_pending_T_24; // @[DCache.scala:930:{46,70,97}] assign io_cpu_store_pending_0 = _io_cpu_store_pending_T_25; // @[DCache.scala:101:7, :930:70] wire _s1_xcpt_valid_T_2 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :932:68] wire s1_xcpt_valid = _s1_xcpt_valid_T_1 & _s1_xcpt_valid_T_2; // @[DCache.scala:932:{40,65,68}] reg io_cpu_s2_xcpt_REG; // @[DCache.scala:933:32] wire _io_cpu_s2_xcpt_T_miss = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_miss; // @[DCache.scala:342:24, :933:{24,32}] wire [31:0] _io_cpu_s2_xcpt_T_paddr = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_paddr : 32'h0; // @[DCache.scala:342:24, :933:{24,32}] wire [39:0] _io_cpu_s2_xcpt_T_gpa = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_gpa : 40'h0; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_pf_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_pf_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_pf_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ae_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ae_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_ae_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ma_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ma_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_cacheable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_must_alloc = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_prefetchable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24, :933:{24,32}] wire [1:0] _io_cpu_s2_xcpt_T_size = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_size : 2'h0; // @[DCache.scala:342:24, :933:{24,32}] wire [4:0] _io_cpu_s2_xcpt_T_cmd = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_cmd : 5'h0; // @[DCache.scala:342:24, :933:{24,32}] assign io_cpu_s2_xcpt_pf_ld_0 = _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_pf_st_0 = _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ae_ld_0 = _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ae_st_0 = _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ma_ld_0 = _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ma_st_0 = _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:101:7, :933:24] wire _s1_uncached_data_word_T = s1_uncached_data_word_word_idx; // @[package.scala:39:86, :163:13] wire [63:0] s1_uncached_data_word_words_0 = nodeOut_d_bits_data[63:0]; // @[package.scala:211:50] wire [63:0] s1_uncached_data_word_words_1 = nodeOut_d_bits_data[127:64]; // @[package.scala:211:50] wire [63:0] s1_uncached_data_word = _s1_uncached_data_word_T ? s1_uncached_data_word_words_1 : s1_uncached_data_word_words_0; // @[package.scala:39:{76,86}, :211:50] reg [63:0] s2_uncached_data_word; // @[DCache.scala:947:40] reg doUncachedResp; // @[DCache.scala:948:31] assign io_cpu_resp_bits_replay_0 = doUncachedResp; // @[DCache.scala:101:7, :948:31] wire _io_cpu_resp_valid_T = s2_valid_hit_pre_data_ecc | doUncachedResp; // @[DCache.scala:420:69, :948:31, :949:51] assign _io_cpu_resp_valid_T_2 = _io_cpu_resp_valid_T; // @[DCache.scala:949:{51,70}] assign io_cpu_resp_valid_0 = _io_cpu_resp_valid_T_2; // @[DCache.scala:101:7, :949:70] wire _io_cpu_replay_next_T_1 = _io_cpu_replay_next_T & grantIsUncachedData; // @[Decoupled.scala:51:35] assign _io_cpu_replay_next_T_3 = _io_cpu_replay_next_T_1; // @[DCache.scala:950:{39,62}] assign io_cpu_replay_next_0 = _io_cpu_replay_next_T_3; // @[DCache.scala:101:7, :950:62]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_61( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1138 = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1138 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1138 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1138 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1138 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_1138 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1184 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1153 = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1153 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1153 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1153 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1238 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1238 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1238 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1238 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first | last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first | last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB || !io.status.bits.blockB) assert (!io.status.bits.nestC || !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe || !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid || io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid || io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty || request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) | Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid || meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U || !(request.opcode === PutFullData || request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r || p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c || m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read || clean release can lead to this state eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_D, true) // MMIO write || dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done | probe_bit probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst || last_probe w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst || last_probe w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U) w_pprobeack := w_pprobeack || set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U || io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f || p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read || clean release can lead to this state bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_D, true) // MMIO write || dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid || (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT || new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
module MSHR_10( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire excluded_client = 1'h0; // @[MSHR.scala:279:28] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _io_schedule_bits_b_bits_clients_T = 1'h1; // @[MSHR.scala:289:53] wire _last_probe_T_1 = 1'h1; // @[MSHR.scala:459:66] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [6:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 7'h20; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 7'h20; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 7'h20; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_278( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_22 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Breakpoint.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile.{CoreBundle, HasCoreParameters} import freechips.rocketchip.util._ class BPControl(implicit p: Parameters) extends CoreBundle()(p) { val ttype = UInt(4.W) val dmode = Bool() val maskmax = UInt(6.W) val reserved = UInt((xLen - (if (coreParams.useBPWatch) 26 else 24)).W) val action = UInt((if (coreParams.useBPWatch) 3 else 1).W) val chain = Bool() val zero = UInt(2.W) val tmatch = UInt(2.W) val m = Bool() val h = Bool() val s = Bool() val u = Bool() val x = Bool() val w = Bool() val r = Bool() def tType = 2 def maskMax = 4 def enabled(mstatus: MStatus) = !mstatus.debug && Cat(m, h, s, u)(mstatus.prv) } class TExtra(implicit p: Parameters) extends CoreBundle()(p) { def mvalueBits: Int = if (xLen == 32) coreParams.mcontextWidth min 6 else coreParams.mcontextWidth min 13 def svalueBits: Int = if (xLen == 32) coreParams.scontextWidth min 16 else coreParams.scontextWidth min 34 def mselectPos: Int = if (xLen == 32) 25 else 50 def mvaluePos : Int = mselectPos + 1 def sselectPos: Int = 0 def svaluePos : Int = 2 val mvalue = UInt(mvalueBits.W) val mselect = Bool() val pad2 = UInt((mselectPos - svalueBits - 2).W) val svalue = UInt(svalueBits.W) val pad1 = UInt(1.W) val sselect = Bool() } class BP(implicit p: Parameters) extends CoreBundle()(p) { val control = new BPControl val address = UInt(vaddrBits.W) val textra = new TExtra def contextMatch(mcontext: UInt, scontext: UInt) = (if (coreParams.mcontextWidth > 0) (!textra.mselect || (mcontext(textra.mvalueBits-1,0) === textra.mvalue)) else true.B) && (if (coreParams.scontextWidth > 0) (!textra.sselect || (scontext(textra.svalueBits-1,0) === textra.svalue)) else true.B) def mask(dummy: Int = 0) = (0 until control.maskMax-1).scanLeft(control.tmatch(0))((m, i) => m && address(i)).asUInt def pow2AddressMatch(x: UInt) = (~x | mask()) === (~address | mask()) def rangeAddressMatch(x: UInt) = (x >= address) ^ control.tmatch(0) def addressMatch(x: UInt) = Mux(control.tmatch(1), rangeAddressMatch(x), pow2AddressMatch(x)) } class BPWatch (val n: Int) extends Bundle() { val valid = Vec(n, Bool()) val rvalid = Vec(n, Bool()) val wvalid = Vec(n, Bool()) val ivalid = Vec(n, Bool()) val action = UInt(3.W) } class BreakpointUnit(n: Int)(implicit val p: Parameters) extends Module with HasCoreParameters { val io = IO(new Bundle { val status = Input(new MStatus()) val bp = Input(Vec(n, new BP)) val pc = Input(UInt(vaddrBits.W)) val ea = Input(UInt(vaddrBits.W)) val mcontext = Input(UInt(coreParams.mcontextWidth.W)) val scontext = Input(UInt(coreParams.scontextWidth.W)) val xcpt_if = Output(Bool()) val xcpt_ld = Output(Bool()) val xcpt_st = Output(Bool()) val debug_if = Output(Bool()) val debug_ld = Output(Bool()) val debug_st = Output(Bool()) val bpwatch = Output(Vec(n, new BPWatch(1))) }) io.xcpt_if := false.B io.xcpt_ld := false.B io.xcpt_st := false.B io.debug_if := false.B io.debug_ld := false.B io.debug_st := false.B (io.bpwatch zip io.bp).foldLeft((true.B, true.B, true.B)) { case ((ri, wi, xi), (bpw, bp)) => val en = bp.control.enabled(io.status) val cx = bp.contextMatch(io.mcontext, io.scontext) val r = en && bp.control.r && bp.addressMatch(io.ea) && cx val w = en && bp.control.w && bp.addressMatch(io.ea) && cx val x = en && bp.control.x && bp.addressMatch(io.pc) && cx val end = !bp.control.chain val action = bp.control.action bpw.action := action bpw.valid(0) := false.B bpw.rvalid(0) := false.B bpw.wvalid(0) := false.B bpw.ivalid(0) := false.B when (end && r && ri) { io.xcpt_ld := (action === 0.U); io.debug_ld := (action === 1.U); bpw.valid(0) := true.B; bpw.rvalid(0) := true.B } when (end && w && wi) { io.xcpt_st := (action === 0.U); io.debug_st := (action === 1.U); bpw.valid(0) := true.B; bpw.wvalid(0) := true.B } when (end && x && xi) { io.xcpt_if := (action === 0.U); io.debug_if := (action === 1.U); bpw.valid(0) := true.B; bpw.ivalid(0) := true.B } (end || r, end || w, end || x) } }
module BreakpointUnit_6( // @[Breakpoint.scala:79:7] input clock, // @[Breakpoint.scala:79:7] input reset, // @[Breakpoint.scala:79:7] input io_status_debug, // @[Breakpoint.scala:80:14] input io_status_cease, // @[Breakpoint.scala:80:14] input io_status_wfi, // @[Breakpoint.scala:80:14] input [31:0] io_status_isa, // @[Breakpoint.scala:80:14] input [1:0] io_status_dprv, // @[Breakpoint.scala:80:14] input io_status_dv, // @[Breakpoint.scala:80:14] input [1:0] io_status_prv, // @[Breakpoint.scala:80:14] input io_status_v, // @[Breakpoint.scala:80:14] input io_status_sd, // @[Breakpoint.scala:80:14] input io_status_mpv, // @[Breakpoint.scala:80:14] input io_status_gva, // @[Breakpoint.scala:80:14] input io_status_tsr, // @[Breakpoint.scala:80:14] input io_status_tw, // @[Breakpoint.scala:80:14] input io_status_tvm, // @[Breakpoint.scala:80:14] input io_status_mxr, // @[Breakpoint.scala:80:14] input io_status_sum, // @[Breakpoint.scala:80:14] input io_status_mprv, // @[Breakpoint.scala:80:14] input [1:0] io_status_fs, // @[Breakpoint.scala:80:14] input [1:0] io_status_mpp, // @[Breakpoint.scala:80:14] input io_status_spp, // @[Breakpoint.scala:80:14] input io_status_mpie, // @[Breakpoint.scala:80:14] input io_status_spie, // @[Breakpoint.scala:80:14] input io_status_mie, // @[Breakpoint.scala:80:14] input io_status_sie, // @[Breakpoint.scala:80:14] input io_bp_0_control_dmode, // @[Breakpoint.scala:80:14] input io_bp_0_control_action, // @[Breakpoint.scala:80:14] input [1:0] io_bp_0_control_tmatch, // @[Breakpoint.scala:80:14] input io_bp_0_control_m, // @[Breakpoint.scala:80:14] input io_bp_0_control_s, // @[Breakpoint.scala:80:14] input io_bp_0_control_u, // @[Breakpoint.scala:80:14] input io_bp_0_control_x, // @[Breakpoint.scala:80:14] input io_bp_0_control_w, // @[Breakpoint.scala:80:14] input io_bp_0_control_r, // @[Breakpoint.scala:80:14] input [38:0] io_bp_0_address, // @[Breakpoint.scala:80:14] input [47:0] io_bp_0_textra_pad2, // @[Breakpoint.scala:80:14] input io_bp_0_textra_pad1, // @[Breakpoint.scala:80:14] input [38:0] io_pc, // @[Breakpoint.scala:80:14] input [38:0] io_ea, // @[Breakpoint.scala:80:14] output io_xcpt_if, // @[Breakpoint.scala:80:14] output io_xcpt_ld, // @[Breakpoint.scala:80:14] output io_xcpt_st, // @[Breakpoint.scala:80:14] output io_debug_if, // @[Breakpoint.scala:80:14] output io_debug_ld, // @[Breakpoint.scala:80:14] output io_debug_st, // @[Breakpoint.scala:80:14] output io_bpwatch_0_rvalid_0, // @[Breakpoint.scala:80:14] output io_bpwatch_0_wvalid_0, // @[Breakpoint.scala:80:14] output io_bpwatch_0_ivalid_0 // @[Breakpoint.scala:80:14] ); wire io_status_debug_0 = io_status_debug; // @[Breakpoint.scala:79:7] wire io_status_cease_0 = io_status_cease; // @[Breakpoint.scala:79:7] wire io_status_wfi_0 = io_status_wfi; // @[Breakpoint.scala:79:7] wire [31:0] io_status_isa_0 = io_status_isa; // @[Breakpoint.scala:79:7] wire [1:0] io_status_dprv_0 = io_status_dprv; // @[Breakpoint.scala:79:7] wire io_status_dv_0 = io_status_dv; // @[Breakpoint.scala:79:7] wire [1:0] io_status_prv_0 = io_status_prv; // @[Breakpoint.scala:79:7] wire io_status_v_0 = io_status_v; // @[Breakpoint.scala:79:7] wire io_status_sd_0 = io_status_sd; // @[Breakpoint.scala:79:7] wire io_status_mpv_0 = io_status_mpv; // @[Breakpoint.scala:79:7] wire io_status_gva_0 = io_status_gva; // @[Breakpoint.scala:79:7] wire io_status_tsr_0 = io_status_tsr; // @[Breakpoint.scala:79:7] wire io_status_tw_0 = io_status_tw; // @[Breakpoint.scala:79:7] wire io_status_tvm_0 = io_status_tvm; // @[Breakpoint.scala:79:7] wire io_status_mxr_0 = io_status_mxr; // @[Breakpoint.scala:79:7] wire io_status_sum_0 = io_status_sum; // @[Breakpoint.scala:79:7] wire io_status_mprv_0 = io_status_mprv; // @[Breakpoint.scala:79:7] wire [1:0] io_status_fs_0 = io_status_fs; // @[Breakpoint.scala:79:7] wire [1:0] io_status_mpp_0 = io_status_mpp; // @[Breakpoint.scala:79:7] wire io_status_spp_0 = io_status_spp; // @[Breakpoint.scala:79:7] wire io_status_mpie_0 = io_status_mpie; // @[Breakpoint.scala:79:7] wire io_status_spie_0 = io_status_spie; // @[Breakpoint.scala:79:7] wire io_status_mie_0 = io_status_mie; // @[Breakpoint.scala:79:7] wire io_status_sie_0 = io_status_sie; // @[Breakpoint.scala:79:7] wire io_bp_0_control_dmode_0 = io_bp_0_control_dmode; // @[Breakpoint.scala:79:7] wire io_bp_0_control_action_0 = io_bp_0_control_action; // @[Breakpoint.scala:79:7] wire [1:0] io_bp_0_control_tmatch_0 = io_bp_0_control_tmatch; // @[Breakpoint.scala:79:7] wire io_bp_0_control_m_0 = io_bp_0_control_m; // @[Breakpoint.scala:79:7] wire io_bp_0_control_s_0 = io_bp_0_control_s; // @[Breakpoint.scala:79:7] wire io_bp_0_control_u_0 = io_bp_0_control_u; // @[Breakpoint.scala:79:7] wire io_bp_0_control_x_0 = io_bp_0_control_x; // @[Breakpoint.scala:79:7] wire io_bp_0_control_w_0 = io_bp_0_control_w; // @[Breakpoint.scala:79:7] wire io_bp_0_control_r_0 = io_bp_0_control_r; // @[Breakpoint.scala:79:7] wire [38:0] io_bp_0_address_0 = io_bp_0_address; // @[Breakpoint.scala:79:7] wire [47:0] io_bp_0_textra_pad2_0 = io_bp_0_textra_pad2; // @[Breakpoint.scala:79:7] wire io_bp_0_textra_pad1_0 = io_bp_0_textra_pad1; // @[Breakpoint.scala:79:7] wire [38:0] io_pc_0 = io_pc; // @[Breakpoint.scala:79:7] wire [38:0] io_ea_0 = io_ea; // @[Breakpoint.scala:79:7] wire [1:0] io_status_sxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14] wire [1:0] io_status_uxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14] wire cx = 1'h1; // @[Breakpoint.scala:55:126] wire end_0 = 1'h1; // @[Breakpoint.scala:109:15] wire [39:0] io_bp_0_control_reserved = 40'h0; // @[Breakpoint.scala:79:7, :80:14] wire [5:0] io_bp_0_control_maskmax = 6'h4; // @[Breakpoint.scala:79:7, :80:14] wire [3:0] io_bp_0_control_ttype = 4'h2; // @[Breakpoint.scala:79:7, :80:14] wire [1:0] io_status_xs = 2'h0; // @[Breakpoint.scala:79:7, :80:14] wire [1:0] io_status_vs = 2'h0; // @[Breakpoint.scala:79:7, :80:14] wire [1:0] io_bp_0_control_zero = 2'h0; // @[Breakpoint.scala:79:7, :80:14] wire [7:0] io_status_zero1 = 8'h0; // @[Breakpoint.scala:79:7, :80:14] wire io_status_mbe = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_sbe = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_sd_rv32 = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_ube = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_upie = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_hie = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_uie = 1'h0; // @[Breakpoint.scala:79:7] wire io_bp_0_control_chain = 1'h0; // @[Breakpoint.scala:79:7] wire io_bp_0_control_h = 1'h0; // @[Breakpoint.scala:79:7] wire io_bp_0_textra_mselect = 1'h0; // @[Breakpoint.scala:79:7] wire io_bp_0_textra_sselect = 1'h0; // @[Breakpoint.scala:79:7] wire [22:0] io_status_zero2 = 23'h0; // @[Breakpoint.scala:79:7, :80:14] wire _io_debug_ld_T = io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :118:84] wire _io_debug_st_T = io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :119:84] wire _io_debug_if_T = io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :120:84] wire r; // @[Breakpoint.scala:106:58] wire w; // @[Breakpoint.scala:107:58] wire x; // @[Breakpoint.scala:108:58] wire io_bpwatch_0_valid_0; // @[Breakpoint.scala:79:7] wire io_bpwatch_0_rvalid_0_0; // @[Breakpoint.scala:79:7] wire io_bpwatch_0_wvalid_0_0; // @[Breakpoint.scala:79:7] wire io_bpwatch_0_ivalid_0_0; // @[Breakpoint.scala:79:7] wire [2:0] io_bpwatch_0_action; // @[Breakpoint.scala:79:7] wire io_xcpt_if_0; // @[Breakpoint.scala:79:7] wire io_xcpt_ld_0; // @[Breakpoint.scala:79:7] wire io_xcpt_st_0; // @[Breakpoint.scala:79:7] wire io_debug_if_0; // @[Breakpoint.scala:79:7] wire io_debug_ld_0; // @[Breakpoint.scala:79:7] wire io_debug_st_0; // @[Breakpoint.scala:79:7] wire _en_T = ~io_status_debug_0; // @[Breakpoint.scala:30:35, :79:7] wire [1:0] en_lo = {io_bp_0_control_s_0, io_bp_0_control_u_0}; // @[Breakpoint.scala:30:56, :79:7] wire [1:0] en_hi = {io_bp_0_control_m_0, 1'h0}; // @[Breakpoint.scala:30:56, :79:7] wire [3:0] _en_T_1 = {en_hi, en_lo}; // @[Breakpoint.scala:30:56] wire [3:0] _en_T_2 = _en_T_1 >> io_status_prv_0; // @[Breakpoint.scala:30:{56,68}, :79:7] wire _en_T_3 = _en_T_2[0]; // @[Breakpoint.scala:30:68] wire en = _en_T & _en_T_3; // @[Breakpoint.scala:30:{35,50,68}] wire _r_T = en & io_bp_0_control_r_0; // @[Breakpoint.scala:30:50, :79:7, :106:16] wire _r_T_1 = io_bp_0_control_tmatch_0[1]; // @[Breakpoint.scala:68:23, :79:7] wire _w_T_1 = io_bp_0_control_tmatch_0[1]; // @[Breakpoint.scala:68:23, :79:7] wire _x_T_1 = io_bp_0_control_tmatch_0[1]; // @[Breakpoint.scala:68:23, :79:7] wire _GEN = io_ea_0 >= io_bp_0_address_0; // @[Breakpoint.scala:65:8, :79:7] wire _r_T_2; // @[Breakpoint.scala:65:8] assign _r_T_2 = _GEN; // @[Breakpoint.scala:65:8] wire _w_T_2; // @[Breakpoint.scala:65:8] assign _w_T_2 = _GEN; // @[Breakpoint.scala:65:8] wire _r_T_3 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:65:36, :79:7] wire _r_T_6 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7] wire _r_T_16 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7] wire _w_T_3 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:65:36, :79:7] wire _w_T_6 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7] wire _w_T_16 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7] wire _x_T_3 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:65:36, :79:7] wire _x_T_6 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7] wire _x_T_16 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7] wire _r_T_4 = _r_T_2 ^ _r_T_3; // @[Breakpoint.scala:65:{8,20,36}] wire [38:0] _r_T_5 = ~io_ea_0; // @[Breakpoint.scala:62:6, :79:7] wire _r_T_7 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7] wire _r_T_17 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7] wire _w_T_7 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7] wire _w_T_17 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7] wire _x_T_7 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7] wire _x_T_17 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7] wire _r_T_8 = _r_T_6 & _r_T_7; // @[Breakpoint.scala:59:{56,73,83}] wire _r_T_9 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7] wire _r_T_19 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7] wire _w_T_9 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7] wire _w_T_19 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7] wire _x_T_9 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7] wire _x_T_19 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7] wire _r_T_10 = _r_T_8 & _r_T_9; // @[Breakpoint.scala:59:{73,83}] wire _r_T_11 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7] wire _r_T_21 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7] wire _w_T_11 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7] wire _w_T_21 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7] wire _x_T_11 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7] wire _x_T_21 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7] wire _r_T_12 = _r_T_10 & _r_T_11; // @[Breakpoint.scala:59:{73,83}] wire [1:0] r_lo = {_r_T_8, _r_T_6}; // @[package.scala:45:27] wire [1:0] r_hi = {_r_T_12, _r_T_10}; // @[package.scala:45:27] wire [3:0] _r_T_13 = {r_hi, r_lo}; // @[package.scala:45:27] wire [38:0] _r_T_14 = {_r_T_5[38:4], _r_T_5[3:0] | _r_T_13}; // @[package.scala:45:27] wire [38:0] _r_T_15 = ~io_bp_0_address_0; // @[Breakpoint.scala:62:24, :79:7] wire _r_T_18 = _r_T_16 & _r_T_17; // @[Breakpoint.scala:59:{56,73,83}] wire _r_T_20 = _r_T_18 & _r_T_19; // @[Breakpoint.scala:59:{73,83}] wire _r_T_22 = _r_T_20 & _r_T_21; // @[Breakpoint.scala:59:{73,83}] wire [1:0] r_lo_1 = {_r_T_18, _r_T_16}; // @[package.scala:45:27] wire [1:0] r_hi_1 = {_r_T_22, _r_T_20}; // @[package.scala:45:27] wire [3:0] _r_T_23 = {r_hi_1, r_lo_1}; // @[package.scala:45:27] wire [38:0] _r_T_24 = {_r_T_15[38:4], _r_T_15[3:0] | _r_T_23}; // @[package.scala:45:27] wire _r_T_25 = _r_T_14 == _r_T_24; // @[Breakpoint.scala:62:{9,19,33}] wire _r_T_26 = _r_T_1 ? _r_T_4 : _r_T_25; // @[Breakpoint.scala:62:19, :65:20, :68:{8,23}] wire _r_T_27 = _r_T & _r_T_26; // @[Breakpoint.scala:68:8, :106:{16,32}] assign r = _r_T_27; // @[Breakpoint.scala:106:{32,58}] assign io_bpwatch_0_rvalid_0_0 = r; // @[Breakpoint.scala:79:7, :106:58] wire _w_T = en & io_bp_0_control_w_0; // @[Breakpoint.scala:30:50, :79:7, :107:16] wire _w_T_4 = _w_T_2 ^ _w_T_3; // @[Breakpoint.scala:65:{8,20,36}] wire [38:0] _w_T_5 = ~io_ea_0; // @[Breakpoint.scala:62:6, :79:7] wire _w_T_8 = _w_T_6 & _w_T_7; // @[Breakpoint.scala:59:{56,73,83}] wire _w_T_10 = _w_T_8 & _w_T_9; // @[Breakpoint.scala:59:{73,83}] wire _w_T_12 = _w_T_10 & _w_T_11; // @[Breakpoint.scala:59:{73,83}] wire [1:0] w_lo = {_w_T_8, _w_T_6}; // @[package.scala:45:27] wire [1:0] w_hi = {_w_T_12, _w_T_10}; // @[package.scala:45:27] wire [3:0] _w_T_13 = {w_hi, w_lo}; // @[package.scala:45:27] wire [38:0] _w_T_14 = {_w_T_5[38:4], _w_T_5[3:0] | _w_T_13}; // @[package.scala:45:27] wire [38:0] _w_T_15 = ~io_bp_0_address_0; // @[Breakpoint.scala:62:24, :79:7] wire _w_T_18 = _w_T_16 & _w_T_17; // @[Breakpoint.scala:59:{56,73,83}] wire _w_T_20 = _w_T_18 & _w_T_19; // @[Breakpoint.scala:59:{73,83}] wire _w_T_22 = _w_T_20 & _w_T_21; // @[Breakpoint.scala:59:{73,83}] wire [1:0] w_lo_1 = {_w_T_18, _w_T_16}; // @[package.scala:45:27] wire [1:0] w_hi_1 = {_w_T_22, _w_T_20}; // @[package.scala:45:27] wire [3:0] _w_T_23 = {w_hi_1, w_lo_1}; // @[package.scala:45:27] wire [38:0] _w_T_24 = {_w_T_15[38:4], _w_T_15[3:0] | _w_T_23}; // @[package.scala:45:27] wire _w_T_25 = _w_T_14 == _w_T_24; // @[Breakpoint.scala:62:{9,19,33}] wire _w_T_26 = _w_T_1 ? _w_T_4 : _w_T_25; // @[Breakpoint.scala:62:19, :65:20, :68:{8,23}] wire _w_T_27 = _w_T & _w_T_26; // @[Breakpoint.scala:68:8, :107:{16,32}] assign w = _w_T_27; // @[Breakpoint.scala:107:{32,58}] assign io_bpwatch_0_wvalid_0_0 = w; // @[Breakpoint.scala:79:7, :107:58] wire _x_T = en & io_bp_0_control_x_0; // @[Breakpoint.scala:30:50, :79:7, :108:16] wire _x_T_2 = io_pc_0 >= io_bp_0_address_0; // @[Breakpoint.scala:65:8, :79:7] wire _x_T_4 = _x_T_2 ^ _x_T_3; // @[Breakpoint.scala:65:{8,20,36}] wire [38:0] _x_T_5 = ~io_pc_0; // @[Breakpoint.scala:62:6, :79:7] wire _x_T_8 = _x_T_6 & _x_T_7; // @[Breakpoint.scala:59:{56,73,83}] wire _x_T_10 = _x_T_8 & _x_T_9; // @[Breakpoint.scala:59:{73,83}] wire _x_T_12 = _x_T_10 & _x_T_11; // @[Breakpoint.scala:59:{73,83}] wire [1:0] x_lo = {_x_T_8, _x_T_6}; // @[package.scala:45:27] wire [1:0] x_hi = {_x_T_12, _x_T_10}; // @[package.scala:45:27] wire [3:0] _x_T_13 = {x_hi, x_lo}; // @[package.scala:45:27] wire [38:0] _x_T_14 = {_x_T_5[38:4], _x_T_5[3:0] | _x_T_13}; // @[package.scala:45:27] wire [38:0] _x_T_15 = ~io_bp_0_address_0; // @[Breakpoint.scala:62:24, :79:7] wire _x_T_18 = _x_T_16 & _x_T_17; // @[Breakpoint.scala:59:{56,73,83}] wire _x_T_20 = _x_T_18 & _x_T_19; // @[Breakpoint.scala:59:{73,83}] wire _x_T_22 = _x_T_20 & _x_T_21; // @[Breakpoint.scala:59:{73,83}] wire [1:0] x_lo_1 = {_x_T_18, _x_T_16}; // @[package.scala:45:27] wire [1:0] x_hi_1 = {_x_T_22, _x_T_20}; // @[package.scala:45:27] wire [3:0] _x_T_23 = {x_hi_1, x_lo_1}; // @[package.scala:45:27] wire [38:0] _x_T_24 = {_x_T_15[38:4], _x_T_15[3:0] | _x_T_23}; // @[package.scala:45:27] wire _x_T_25 = _x_T_14 == _x_T_24; // @[Breakpoint.scala:62:{9,19,33}] wire _x_T_26 = _x_T_1 ? _x_T_4 : _x_T_25; // @[Breakpoint.scala:62:19, :65:20, :68:{8,23}] wire _x_T_27 = _x_T & _x_T_26; // @[Breakpoint.scala:68:8, :108:{16,32}] assign x = _x_T_27; // @[Breakpoint.scala:108:{32,58}] assign io_bpwatch_0_ivalid_0_0 = x; // @[Breakpoint.scala:79:7, :108:58] assign io_bpwatch_0_action = {2'h0, io_bp_0_control_action_0}; // @[Breakpoint.scala:79:7, :80:14, :112:16] wire _io_xcpt_ld_T = ~io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :118:51] assign io_xcpt_ld_0 = r & _io_xcpt_ld_T; // @[Breakpoint.scala:79:7, :97:14, :106:58, :118:{27,40,51}] assign io_debug_ld_0 = r & _io_debug_ld_T; // @[Breakpoint.scala:79:7, :100:15, :106:58, :118:{27,73,84}] wire _io_xcpt_st_T = ~io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :118:51, :119:51] assign io_xcpt_st_0 = w & _io_xcpt_st_T; // @[Breakpoint.scala:79:7, :98:14, :107:58, :119:{27,40,51}] assign io_debug_st_0 = w & _io_debug_st_T; // @[Breakpoint.scala:79:7, :101:15, :107:58, :119:{27,73,84}] wire _io_xcpt_if_T = ~io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :118:51, :120:51] assign io_xcpt_if_0 = x & _io_xcpt_if_T; // @[Breakpoint.scala:79:7, :96:14, :108:58, :120:{27,40,51}] assign io_debug_if_0 = x & _io_debug_if_T; // @[Breakpoint.scala:79:7, :99:15, :108:58, :120:{27,73,84}] assign io_bpwatch_0_valid_0 = x | w | r; // @[Breakpoint.scala:79:7, :106:58, :107:58, :108:58, :118:27, :119:{27,107}, :120:{27,107}] assign io_xcpt_if = io_xcpt_if_0; // @[Breakpoint.scala:79:7] assign io_xcpt_ld = io_xcpt_ld_0; // @[Breakpoint.scala:79:7] assign io_xcpt_st = io_xcpt_st_0; // @[Breakpoint.scala:79:7] assign io_debug_if = io_debug_if_0; // @[Breakpoint.scala:79:7] assign io_debug_ld = io_debug_ld_0; // @[Breakpoint.scala:79:7] assign io_debug_st = io_debug_st_0; // @[Breakpoint.scala:79:7] assign io_bpwatch_0_rvalid_0 = io_bpwatch_0_rvalid_0_0; // @[Breakpoint.scala:79:7] assign io_bpwatch_0_wvalid_0 = io_bpwatch_0_wvalid_0_0; // @[Breakpoint.scala:79:7] assign io_bpwatch_0_ivalid_0 = io_bpwatch_0_ivalid_0_0; // @[Breakpoint.scala:79:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_41( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_58 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_189( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_341 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }
module NoCMonitor_28( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 2'h0; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_EntryData_69( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File Counters.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ // Produces 0-width value when counting to 1 class ZCounter(val n: Int) { val value = RegInit(0.U(log2Ceil(n).W)) def inc(): Bool = { if (n == 1) true.B else { val wrap = value === (n-1).U value := Mux(!isPow2(n).B && wrap, 0.U, value + 1.U) wrap } } } object ZCounter { def apply(n: Int) = new ZCounter(n) def apply(cond: Bool, n: Int): (UInt, Bool) = { val c = new ZCounter(n) var wrap: Bool = null when (cond) { wrap = c.inc() } (c.value, cond && wrap) } } object TwoWayCounter { def apply(up: Bool, down: Bool, max: Int): UInt = { val cnt = RegInit(0.U(log2Up(max + 1).W)) when (up && !down) { cnt := cnt + 1.U } when (down && !up) { cnt := cnt - 1.U } cnt } } // a counter that clock gates most of its MSBs using the LSB carry-out case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true, inhibit: Bool = false.B) { private val isWide = width > (2 * inc.getWidth) private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width private val small = if (reset) RegInit(0.U(smallWidth.W)) else Reg(UInt(smallWidth.W)) private val nextSmall = small +& inc when (!inhibit) { small := nextSmall } private val large = if (isWide) { val r = if (reset) RegInit(0.U((width - smallWidth).W)) else Reg(UInt((width - smallWidth).W)) when (nextSmall(smallWidth) && !inhibit) { r := r + 1.U } r } else null val value = if (isWide) Cat(large, small) else small lazy val carryOut = { val lo = (small ^ nextSmall) >> 1 if (!isWide) lo else { val hi = Mux(nextSmall(smallWidth), large ^ (large +& 1.U), 0.U) >> 1 Cat(hi, lo) } } def := (x: UInt) = { small := x if (isWide) large := x >> smallWidth } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File PMP.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Ceil} import org.chipsalliance.cde.config._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class PMPConfig extends Bundle { val l = Bool() val res = UInt(2.W) val a = UInt(2.W) val x = Bool() val w = Bool() val r = Bool() } object PMP { def lgAlign = 2 def apply(reg: PMPReg): PMP = { val pmp = Wire(new PMP()(reg.p)) pmp.cfg := reg.cfg pmp.addr := reg.addr pmp.mask := pmp.computeMask pmp } } class PMPReg(implicit p: Parameters) extends CoreBundle()(p) { val cfg = new PMPConfig val addr = UInt((paddrBits - PMP.lgAlign).W) def reset(): Unit = { cfg.a := 0.U cfg.l := 0.U } def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else { val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U Mux(napot, addr | (mask >> 1), ~(~addr | mask)) } def napot = cfg.a(1) def torNotNAPOT = cfg.a(0) def tor = !napot && torNotNAPOT def cfgLocked = cfg.l def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor } class PMP(implicit p: Parameters) extends PMPReg { val mask = UInt(paddrBits.W) import PMP._ def computeMask = { val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign) Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U) } private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U) private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = { def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U if (lgMaxSize <= pmpGranularity.log2) { eval(x, comparand, mask) } else { // break up the circuit; the MSB part will be CSE'd val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize) val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize) val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0)) msbMatch && lsbMatch } } private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = { if (lgMaxSize <= pmpGranularity.log2) { x < comparand } else { // break up the circuit; the MSB part will be CSE'd val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize) val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0) msbsLess || (msbsEqual && lsbsLess) } } private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) = !boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize) private def upperBoundMatch(x: UInt, lgMaxSize: Int) = boundMatch(x, 0.U, lgMaxSize) private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) = prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize) private def pow2Homogeneous(x: UInt, pgLevel: UInt) = { val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel) maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel)) } private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i => f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits) } private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = { val beginsAfterLower = !(x < prev.comparand) val beginsAfterUpper = !(x < comparand) val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel) val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask) val endsBeforeUpper = (x & pgMask) < (comparand & pgMask) endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper) } // returns whether this PMP completely contains, or contains none of, a page def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool = Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev)) // returns whether this matching PMP fully contains the access def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else { val lsbMask = UIntToOH1(lgSize, lgMaxSize) val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U val rangeAligned = !(straddlesLowerBound || straddlesUpperBound) val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U Mux(napot, pow2Aligned, rangeAligned) } // returns whether this PMP matches at least one byte of the access def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev)) } class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) { def apply(addr: UInt, pgLevel: UInt): Bool = { pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) => (h && pmp.homogeneous(addr, pgLevel, prev), pmp) }._1 } } class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module with HasCoreParameters { override def desiredName = s"PMPChecker_s${lgMaxSize}" val io = IO(new Bundle { val prv = Input(UInt(PRV.SZ.W)) val pmp = Input(Vec(nPMPs, new PMP)) val addr = Input(UInt(paddrBits.W)) val size = Input(UInt(log2Ceil(lgMaxSize + 1).W)) val r = Output(Bool()) val w = Output(Bool()) val x = Output(Bool()) }) val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U val pmp0 = WireInit(0.U.asTypeOf(new PMP)) pmp0.cfg.r := default pmp0.cfg.w := default pmp0.cfg.x := default val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) => val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP) val ignore = default && !pmp.cfg.l val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP) for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting") property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting") // Not including Write and no Read permission as the combination is reserved for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty) property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting") for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) { property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access") property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit") } val cur = WireInit(pmp) cur.cfg.r := aligned && (pmp.cfg.r || ignore) cur.cfg.w := aligned && (pmp.cfg.w || ignore) cur.cfg.x := aligned && (pmp.cfg.x || ignore) Mux(hit, cur, prev) } io.r := res.cfg.r io.w := res.cfg.w io.x := res.cfg.x } File CSR.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.LinkedHashMap import Instructions._ import CustomInstructions._ class MStatus extends Bundle { // not truly part of mstatus, but convenient val debug = Bool() val cease = Bool() val wfi = Bool() val isa = UInt(32.W) val dprv = UInt(PRV.SZ.W) // effective prv for data accesses val dv = Bool() // effective v for data accesses val prv = UInt(PRV.SZ.W) val v = Bool() val sd = Bool() val zero2 = UInt(23.W) val mpv = Bool() val gva = Bool() val mbe = Bool() val sbe = Bool() val sxl = UInt(2.W) val uxl = UInt(2.W) val sd_rv32 = Bool() val zero1 = UInt(8.W) val tsr = Bool() val tw = Bool() val tvm = Bool() val mxr = Bool() val sum = Bool() val mprv = Bool() val xs = UInt(2.W) val fs = UInt(2.W) val mpp = UInt(2.W) val vs = UInt(2.W) val spp = UInt(1.W) val mpie = Bool() val ube = Bool() val spie = Bool() val upie = Bool() val mie = Bool() val hie = Bool() val sie = Bool() val uie = Bool() } class MNStatus extends Bundle { val mpp = UInt(2.W) val zero3 = UInt(3.W) val mpv = Bool() val zero2 = UInt(3.W) val mie = Bool() val zero1 = UInt(3.W) } class HStatus extends Bundle { val zero6 = UInt(30.W) val vsxl = UInt(2.W) val zero5 = UInt(9.W) val vtsr = Bool() val vtw = Bool() val vtvm = Bool() val zero3 = UInt(2.W) val vgein = UInt(6.W) val zero2 = UInt(2.W) val hu = Bool() val spvp = Bool() val spv = Bool() val gva = Bool() val vsbe = Bool() val zero1 = UInt(5.W) } class DCSR extends Bundle { val xdebugver = UInt(2.W) val zero4 = UInt(2.W) val zero3 = UInt(12.W) val ebreakm = Bool() val ebreakh = Bool() val ebreaks = Bool() val ebreaku = Bool() val zero2 = Bool() val stopcycle = Bool() val stoptime = Bool() val cause = UInt(3.W) val v = Bool() val zero1 = UInt(2.W) val step = Bool() val prv = UInt(PRV.SZ.W) } class MIP(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val lip = Vec(coreParams.nLocalInterrupts, Bool()) val zero1 = Bool() val debug = Bool() // keep in sync with CSR.debugIntCause val rocc = Bool() val sgeip = Bool() val meip = Bool() val vseip = Bool() val seip = Bool() val ueip = Bool() val mtip = Bool() val vstip = Bool() val stip = Bool() val utip = Bool() val msip = Bool() val vssip = Bool() val ssip = Bool() val usip = Bool() } class Envcfg extends Bundle { val stce = Bool() // only for menvcfg/henvcfg val pbmte = Bool() // only for menvcfg/henvcfg val zero54 = UInt(54.W) val cbze = Bool() val cbcfe = Bool() val cbie = UInt(2.W) val zero3 = UInt(3.W) val fiom = Bool() def write(wdata: UInt) { val new_envcfg = wdata.asTypeOf(new Envcfg) fiom := new_envcfg.fiom // only FIOM is writable currently } } class PTBR(implicit p: Parameters) extends CoreBundle()(p) { def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0) def pgLevelsToMode(i: Int) = (xLen, i) match { case (32, 2) => 1 case (64, x) if x >= 3 && x <= 6 => x + 5 } val (modeBits, maxASIdBits) = xLen match { case 32 => (1, 9) case 64 => (4, 16) } require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen) val mode = UInt(modeBits.W) val asid = UInt(maxASIdBits.W) val ppn = UInt((maxPAddrBits - pgIdxBits).W) } object PRV { val SZ = 2 val U = 0 val S = 1 val H = 2 val M = 3 } object CSR { // commands val SZ = 3 def X = BitPat.dontCare(SZ) def N = 0.U(SZ.W) def R = 2.U(SZ.W) def I = 4.U(SZ.W) def W = 5.U(SZ.W) def S = 6.U(SZ.W) def C = 7.U(SZ.W) // mask a CSR cmd with a valid bit def maskCmd(valid: Bool, cmd: UInt): UInt = { // all commands less than CSR.I are treated by CSRFile as NOPs cmd & ~Mux(valid, 0.U, CSR.I) } val ADDRSZ = 12 def modeLSB: Int = 8 def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ) def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB) def busErrorIntCause = 128 def debugIntCause = 14 // keep in sync with MIP.debug def debugTriggerCause = { val res = debugIntCause require(!(Causes.all contains res)) res } def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause def rnmiBEUCause = 12 val firstCtr = CSRs.cycle val firstCtrH = CSRs.cycleh val firstHPC = CSRs.hpmcounter3 val firstHPCH = CSRs.hpmcounter3h val firstHPE = CSRs.mhpmevent3 val firstMHPC = CSRs.mhpmcounter3 val firstMHPCH = CSRs.mhpmcounter3h val firstHPM = 3 val nCtr = 32 val nHPM = nCtr - firstHPM val hpmWidth = 40 val maxPMPs = 16 } class PerfCounterIO(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val eventSel = Output(UInt(xLen.W)) val inc = Input(UInt(log2Ceil(1+retireWidth).W)) } class TracedInstruction(implicit p: Parameters) extends CoreBundle { val valid = Bool() val iaddr = UInt(coreMaxAddrBits.W) val insn = UInt(iLen.W) val priv = UInt(3.W) val exception = Bool() val interrupt = Bool() val cause = UInt(xLen.W) val tval = UInt((coreMaxAddrBits max iLen).W) val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W)) } class TraceAux extends Bundle { val enable = Bool() val stall = Bool() } class CSRDecodeIO(implicit p: Parameters) extends CoreBundle { val inst = Input(UInt(iLen.W)) def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0) val fp_illegal = Output(Bool()) val vector_illegal = Output(Bool()) val fp_csr = Output(Bool()) val vector_csr = Output(Bool()) val rocc_illegal = Output(Bool()) val read_illegal = Output(Bool()) val write_illegal = Output(Bool()) val write_flush = Output(Bool()) val system_illegal = Output(Bool()) val virtual_access_illegal = Output(Bool()) val virtual_system_illegal = Output(Bool()) } class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val ungated_clock = Input(Clock()) val interrupts = Input(new CoreInterrupts(hasBeu)) val hartid = Input(UInt(hartIdLen.W)) val rw = new Bundle { val addr = Input(UInt(CSR.ADDRSZ.W)) val cmd = Input(Bits(CSR.SZ.W)) val rdata = Output(Bits(xLen.W)) val wdata = Input(Bits(xLen.W)) } val decode = Vec(decodeWidth, new CSRDecodeIO) val csr_stall = Output(Bool()) // stall retire for wfi val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall val eret = Output(Bool()) val singleStep = Output(Bool()) val status = Output(new MStatus()) val hstatus = Output(new HStatus()) val gstatus = Output(new MStatus()) val ptbr = Output(new PTBR()) val hgatp = Output(new PTBR()) val vsatp = Output(new PTBR()) val evec = Output(UInt(vaddrBitsExtended.W)) val exception = Input(Bool()) val retire = Input(UInt(log2Up(1+retireWidth).W)) val cause = Input(UInt(xLen.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val tval = Input(UInt(vaddrBitsExtended.W)) val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W)) val mhtinst_read_pseudo = Input(Bool()) val gva = Input(Bool()) val time = Output(UInt(xLen.W)) val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W))) val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool())) val rocc_interrupt = Input(Bool()) val interrupt = Output(Bool()) val interrupt_cause = Output(UInt(xLen.W)) val bp = Output(Vec(nBreakpoints, new BP)) val pmp = Output(Vec(nPMPs, new PMP)) val counters = Vec(nPerfCounters, new PerfCounterIO) val csrw_counter = Output(UInt(CSR.nCtr.W)) val inhibit_cycle = Output(Bool()) val inst = Input(Vec(retireWidth, UInt(iLen.W))) val trace = Output(Vec(retireWidth, new TracedInstruction)) val mcontext = Output(UInt(coreParams.mcontextWidth.W)) val scontext = Output(UInt(coreParams.scontextWidth.W)) val fiom = Output(Bool()) val vector = usingVector.option(new Bundle { val vconfig = Output(new VConfig()) val vstart = Output(UInt(maxVLMax.log2.W)) val vxrm = Output(UInt(2.W)) val set_vs_dirty = Input(Bool()) val set_vconfig = Flipped(Valid(new VConfig)) val set_vstart = Flipped(Valid(vstart)) val set_vxsat = Input(Bool()) }) } class VConfig(implicit p: Parameters) extends CoreBundle { val vl = UInt((maxVLMax.log2 + 1).W) val vtype = new VType } object VType { def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = { val res = 0.U.asTypeOf(new VType) val in = that.asTypeOf(res) val vill = (in.max_vsew.U < in.vsew) || !in.lmul_ok || in.reserved =/= 0.U || in.vill when (!vill || ignore_vill.B) { res := in res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0) } res.reserved := 0.U res.vill := vill res } def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt = VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero) } class VType(implicit p: Parameters) extends CoreBundle { val vill = Bool() val reserved = UInt((xLen - 9).W) val vma = Bool() val vta = Bool() val vsew = UInt(3.W) val vlmul_sign = Bool() val vlmul_mag = UInt(2.W) def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt @deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9") def vlmul: UInt = vlmul_mag def max_vsew = log2Ceil(eLen/8) def max_vlmul = (1 << vlmul_mag.getWidth) - 1 def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B) def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1 def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U) def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = { val atLeastMaxVLMax = useMax || Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U) val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0) val atLeastVLMax = atLeastMaxVLMax || (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR val isZero = vill || useZero Mux(!isZero && atLeastVLMax, vlMax, 0.U) | Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U) } } class CSRFile( perfEventSets: EventSets = new EventSets(Seq()), customCSRs: Seq[CustomCSR] = Nil, roccCSRs: Seq[CustomCSR] = Nil, hasBeu: Boolean = false)(implicit p: Parameters) extends CoreModule()(p) with HasCoreParameters { val io = IO(new CSRFileIO(hasBeu) { val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO) val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO) }) io.rw_stall := false.B val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := PRV.M.U reset_mstatus.prv := PRV.M.U reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U) val reg_mstatus = RegInit(reset_mstatus) val new_prv = WireDefault(reg_mstatus.prv) reg_mstatus.prv := legalizePrivilege(new_prv) val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR())) reset_dcsr.xdebugver := 1.U reset_dcsr.prv := PRV.M.U val reg_dcsr = RegInit(reset_dcsr) val (supported_interrupts, delegable_interrupts) = { val sup = Wire(new MIP) sup.usip := false.B sup.ssip := usingSupervisor.B sup.vssip := usingHypervisor.B sup.msip := true.B sup.utip := false.B sup.stip := usingSupervisor.B sup.vstip := usingHypervisor.B sup.mtip := true.B sup.ueip := false.B sup.seip := usingSupervisor.B sup.vseip := usingHypervisor.B sup.meip := true.B sup.sgeip := false.B sup.rocc := usingRoCC.B sup.debug := false.B sup.zero1 := false.B sup.lip foreach { _ := true.B } val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U val del = WireDefault(sup) del.msip := false.B del.mtip := false.B del.meip := false.B (sup.asUInt | supported_high_interrupts, del.asUInt) } val delegable_base_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_page_fault, Causes.breakpoint, Causes.load_page_fault, Causes.store_page_fault, Causes.misaligned_load, Causes.misaligned_store, Causes.illegal_instruction, Causes.user_ecall, ) val delegable_hypervisor_exceptions = Seq( Causes.virtual_supervisor_ecall, Causes.fetch_guest_page_fault, Causes.load_guest_page_fault, Causes.virtual_instruction, Causes.store_guest_page_fault, ) val delegable_exceptions = ( delegable_base_exceptions ++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq()) ).map(1 << _).sum.U val hs_delegable_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_access, Causes.illegal_instruction, Causes.breakpoint, Causes.misaligned_load, Causes.load_access, Causes.misaligned_store, Causes.store_access, Causes.user_ecall, Causes.fetch_page_fault, Causes.load_page_fault, Causes.store_page_fault).map(1 << _).sum.U val (hs_delegable_interrupts, mideleg_always_hs) = { val always = WireDefault(0.U.asTypeOf(new MIP())) always.vssip := usingHypervisor.B always.vstip := usingHypervisor.B always.vseip := usingHypervisor.B val deleg = WireDefault(always) deleg.lip.foreach { _ := usingHypervisor.B } (deleg.asUInt, always.asUInt) } val reg_debug = RegInit(false.B) val reg_dpc = Reg(UInt(vaddrBitsExtended.W)) val reg_dscratch0 = Reg(UInt(xLen.W)) val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W))) val reg_singleStepped = Reg(Bool()) val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W))) val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W))) val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W)) val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP)) val reg_pmp = Reg(Vec(nPMPs, new PMPReg)) val reg_mie = Reg(UInt(xLen.W)) val (reg_mideleg, read_mideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_interrupts | mideleg_always_hs, 0.U)) } val (reg_medeleg, read_medeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U)) } val reg_mip = Reg(new MIP) val reg_mepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mcause = RegInit(0.U(xLen.W)) val reg_mtval = Reg(UInt(vaddrBitsExtended.W)) val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W)) val reg_mscratch = Reg(Bits(xLen.W)) val mtvecWidth = paddrBits min xLen val reg_mtvec = mtvecInit match { case Some(addr) => RegInit(addr.U(mtvecWidth.W)) case None => Reg(UInt(mtvecWidth.W)) } val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus())) reset_mnstatus.mpp := PRV.M.U val reg_mnscratch = Reg(Bits(xLen.W)) val reg_mnepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mncause = RegInit(0.U(xLen.W)) val reg_mnstatus = RegInit(reset_mnstatus) val reg_rnmie = RegInit(true.B) val nmie = reg_rnmie val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U val (reg_mcounteren, read_mcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingUser.B, reg & delegable_counters, 0.U)) } val (reg_scounteren, read_scounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U)) } val (reg_hideleg, read_hideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U)) } val (reg_hedeleg, read_hedeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U)) } val hs_delegable_counters = delegable_counters val (reg_hcounteren, read_hcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U)) } val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus)) val reg_hgatp = Reg(new PTBR) val reg_htval = Reg(reg_mtval2.cloneType) val read_hvip = reg_mip.asUInt & hs_delegable_interrupts val read_hie = reg_mie & hs_delegable_interrupts val (reg_vstvec, read_vstvec) = { val reg = Reg(UInt(vaddrBitsExtended.W)) (reg, formTVec(reg).sextTo(xLen)) } val reg_vsstatus = Reg(new MStatus) val reg_vsscratch = Reg(Bits(xLen.W)) val reg_vsepc = Reg(UInt(vaddrBitsExtended.W)) val reg_vscause = Reg(Bits(xLen.W)) val reg_vstval = Reg(UInt(vaddrBitsExtended.W)) val reg_vsatp = Reg(new PTBR) val reg_sepc = Reg(UInt(vaddrBitsExtended.W)) val reg_scause = Reg(Bits(xLen.W)) val reg_stval = Reg(UInt(vaddrBitsExtended.W)) val reg_sscratch = Reg(Bits(xLen.W)) val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W)) val reg_satp = Reg(new PTBR) val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) } val reg_fflags = Reg(UInt(5.W)) val reg_frm = Reg(UInt(3.W)) val reg_vconfig = usingVector.option(Reg(new VConfig)) val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W))) val reg_vxsat = usingVector.option(Reg(Bool())) val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W))) val reg_mtinst_read_pseudo = Reg(Bool()) val reg_htinst_read_pseudo = Reg(Bool()) // XLEN=32: 0x00002000 // XLEN=64: 0x00003000 val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W))) val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W)) io.inhibit_cycle := reg_mcountinhibit(0) val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2)) val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0)) else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) } val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W))) (io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e } val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) => WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) } val mip = WireDefault(reg_mip) mip.lip := (io.interrupts.lip: Seq[Bool]) mip.mtip := io.interrupts.mtip mip.msip := io.interrupts.msip mip.meip := io.interrupts.meip // seip is the OR of reg_mip.seip and the actual line from the PLIC io.interrupts.seip.foreach { mip.seip := reg_mip.seip || _ } // Simimlar sort of thing would apply if the PLIC had a VSEIP line: //io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip || _ } mip.rocc := io.rocc_interrupt val read_mip = mip.asUInt & supported_interrupts val read_hip = read_mip & hs_delegable_interrupts val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U)) val pending_interrupts = high_interrupts | (read_mip & reg_mie) val d_interrupts = io.interrupts.debug << CSR.debugIntCause val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi => (((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) | io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U), !io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B) val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U || reg_mstatus.mie), ~(~pending_interrupts | read_mideleg), 0.U) val s_interrupts = Mux(nmie && (reg_mstatus.v || reg_mstatus.prv < PRV.S.U || (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U) val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U || reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U) val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts)) val interruptMSB = BigInt(1) << (xLen-1) val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt io.interrupt := (anyInterrupt && !io.singleStep || reg_singleStepped) && !(reg_debug || io.status.cease) io.interrupt_cause := interruptCause io.bp := reg_bp take nBreakpoints io.mcontext := reg_mcontext.getOrElse(0.U) io.scontext := reg_scontext.getOrElse(0.U) io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) || (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) || (reg_mstatus.v && reg_henvcfg.fiom) io.pmp := reg_pmp.map(PMP(_)) val isaMaskString = (if (usingMulDiv) "M" else "") + (if (usingAtomics) "A" else "") + (if (fLen >= 32) "F" else "") + (if (fLen >= 64) "D" else "") + (if (coreParams.hasV) "V" else "") + (if (usingCompressed) "C" else "") val isaString = (if (coreParams.useRVE) "E" else "I") + isaMaskString + (if (customIsaExt.isDefined || usingRoCC) "X" else "") + (if (usingSupervisor) "S" else "") + (if (usingHypervisor) "H" else "") + (if (usingUser) "U" else "") val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) | isaStringToMask(isaString) val reg_misa = RegInit(isaMax.U) val read_mstatus = io.status.asUInt.extract(xLen-1,0) val read_mtvec = formTVec(reg_mtvec).padTo(xLen) val read_stvec = formTVec(reg_stvec).sextTo(xLen) val read_mapping = LinkedHashMap[Int,Bits]( CSRs.tselect -> reg_tselect, CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt, CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen), CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt, CSRs.misa -> reg_misa, CSRs.mstatus -> read_mstatus, CSRs.mtvec -> read_mtvec, CSRs.mip -> read_mip, CSRs.mie -> reg_mie, CSRs.mscratch -> reg_mscratch, CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen), CSRs.mtval -> reg_mtval.sextTo(xLen), CSRs.mcause -> reg_mcause, CSRs.mhartid -> io.hartid) val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.dcsr -> reg_dcsr.asUInt, CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen), CSRs.dscratch0 -> reg_dscratch0.asUInt) ++ reg_dscratch1.map(r => CSRs.dscratch1 -> r) val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus())) read_mnstatus.mpp := reg_mnstatus.mpp read_mnstatus.mpv := reg_mnstatus.mpv read_mnstatus.mie := reg_rnmie val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits]( CustomCSRs.mnscratch -> reg_mnscratch, CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen), CustomCSRs.mncause -> reg_mncause, CustomCSRs.mnstatus -> read_mnstatus.asUInt) val context_csrs = LinkedHashMap[Int,Bits]() ++ reg_mcontext.map(r => CSRs.mcontext -> r) ++ reg_scontext.map(r => CSRs.scontext -> r) val read_fcsr = Cat(reg_frm, reg_fflags) val fp_csrs = LinkedHashMap[Int,Bits]() ++ usingFPU.option(CSRs.fflags -> reg_fflags) ++ usingFPU.option(CSRs.frm -> reg_frm) ++ (usingFPU || usingVector).option(CSRs.fcsr -> read_fcsr) val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U)) val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.vxsat -> reg_vxsat.get, CSRs.vxrm -> reg_vxrm.get, CSRs.vcsr -> read_vcsr, CSRs.vstart -> reg_vstart.get, CSRs.vtype -> reg_vconfig.get.vtype.asUInt, CSRs.vl -> reg_vconfig.get.vl, CSRs.vlenb -> (vLen / 8).U) read_mapping ++= debug_csrs read_mapping ++= nmi_csrs read_mapping ++= context_csrs read_mapping ++= fp_csrs read_mapping ++= vector_csrs if (coreParams.haveBasicCounters) { read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit read_mapping += CSRs.mcycle -> reg_cycle read_mapping += CSRs.minstret -> reg_instret for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U) zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) { read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN if (xLen == 32) { read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh } } if (usingUser) { read_mapping += CSRs.mcounteren -> read_mcounteren } read_mapping += CSRs.cycle -> reg_cycle read_mapping += CSRs.instret -> reg_instret if (xLen == 32) { read_mapping += CSRs.mcycleh -> (reg_cycle >> 32) read_mapping += CSRs.minstreth -> (reg_instret >> 32) read_mapping += CSRs.cycleh -> (reg_cycle >> 32) read_mapping += CSRs.instreth -> (reg_instret >> 32) } } if (usingUser) { read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt if (xLen == 32) read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32) } val sie_mask = { val sgeip_mask = WireInit(0.U.asTypeOf(new MIP)) sgeip_mask.sgeip := true.B read_mideleg & ~(hs_delegable_interrupts | sgeip_mask.asUInt) } if (usingSupervisor) { val read_sie = reg_mie & sie_mask val read_sip = read_mip & sie_mask val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus)) read_sstatus.sd := io.status.sd read_sstatus.uxl := io.status.uxl read_sstatus.sd_rv32 := io.status.sd_rv32 read_sstatus.mxr := io.status.mxr read_sstatus.sum := io.status.sum read_sstatus.xs := io.status.xs read_sstatus.fs := io.status.fs read_sstatus.vs := io.status.vs read_sstatus.spp := io.status.spp read_sstatus.spie := io.status.spie read_sstatus.sie := io.status.sie read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0) read_mapping += CSRs.sip -> read_sip.asUInt read_mapping += CSRs.sie -> read_sie.asUInt read_mapping += CSRs.sscratch -> reg_sscratch read_mapping += CSRs.scause -> reg_scause read_mapping += CSRs.stval -> reg_stval.sextTo(xLen) read_mapping += CSRs.satp -> reg_satp.asUInt read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen) read_mapping += CSRs.stvec -> read_stvec read_mapping += CSRs.scounteren -> read_scounteren read_mapping += CSRs.mideleg -> read_mideleg read_mapping += CSRs.medeleg -> read_medeleg read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt } val pmpCfgPerCSR = xLen / new PMPConfig().getWidth def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR) if (reg_pmp.nonEmpty) { require(reg_pmp.size <= CSR.maxPMPs) val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP)) for (i <- 0 until read_pmp.size by pmpCfgPerCSR) read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt for ((pmp, i) <- read_pmp.zipWithIndex) read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr } // implementation-defined CSRs def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = { require(csr.mask >= 0 && csr.mask.bitLength <= xLen) require(!read_mapping.contains(csr.id)) val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W))) val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U csr_io.ren := read when (read && csr_io.stall) { io.rw_stall := true.B } read_mapping += csr.id -> reg reg } val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2)) val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2)) if (usingHypervisor) { read_mapping += CSRs.mtinst -> read_mtinst read_mapping += CSRs.mtval2 -> reg_mtval2 val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.hstatus -> read_hstatus read_mapping += CSRs.hedeleg -> read_hedeleg read_mapping += CSRs.hideleg -> read_hideleg read_mapping += CSRs.hcounteren-> read_hcounteren read_mapping += CSRs.hgatp -> reg_hgatp.asUInt read_mapping += CSRs.hip -> read_hip read_mapping += CSRs.hie -> read_hie read_mapping += CSRs.hvip -> read_hvip read_mapping += CSRs.hgeie -> 0.U read_mapping += CSRs.hgeip -> 0.U read_mapping += CSRs.htval -> reg_htval read_mapping += CSRs.htinst -> read_htinst read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt if (xLen == 32) read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32) val read_vsie = (read_hie & read_hideleg) >> 1 val read_vsip = (read_hip & read_hideleg) >> 1 val read_vsepc = readEPC(reg_vsepc).sextTo(xLen) val read_vstval = reg_vstval.sextTo(xLen) val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.vsstatus -> read_vsstatus read_mapping += CSRs.vsip -> read_vsip read_mapping += CSRs.vsie -> read_vsie read_mapping += CSRs.vsscratch -> reg_vsscratch read_mapping += CSRs.vscause -> reg_vscause read_mapping += CSRs.vstval -> read_vstval read_mapping += CSRs.vsatp -> reg_vsatp.asUInt read_mapping += CSRs.vsepc -> read_vsepc read_mapping += CSRs.vstvec -> read_vstvec } // mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U)) val decoded_addr = { val addr = Cat(io.status.v, io.rw.addr) val pats = for (((k, _), i) <- read_mapping.zipWithIndex) yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B))) val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats) val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap for ((k, v) <- unvirtualized_mapping) yield k -> { val alt: Option[Bool] = CSR.mode(k) match { // hcontext was assigned an unfortunate address; it lives where a // hypothetical vscontext will live. Exclude them from the S/VS remapping. // (on separate lines so scala-lint doesnt do something stupid) case _ if k == CSRs.scontext => None case _ if k == CSRs.hcontext => None // When V=1, if a corresponding VS CSR exists, access it instead... case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB)) // ...and don't access the original S-mode version. case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B) case _ => None } alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v) } } val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata) val system_insn = io.rw.cmd === CSR.I val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU) val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N), EBREAK-> List(N,Y,N,N,N,N,N,N,N), MRET-> List(N,N,Y,N,N,N,N,N,N), CEASE-> List(N,N,N,Y,N,N,N,N,N), WFI-> List(N,N,N,N,Y,N,N,N,N)) ++ usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++ coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++ usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++ usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++ usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++ (if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq()) val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = { val insn = ECALL.value.U | (io.rw.addr << 20) DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool) } for (io_dec <- io.decode) { val addr = io_dec.inst(31, 20) def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_||_) def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U)) val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil = DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool) val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) || addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U)) val allow_wfi = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !reg_mstatus.tw && (!reg_mstatus.v || !reg_hstatus.vtw) val allow_sfence_vma = (!usingVM).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) val allow_hfence_vvma = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U) val allow_hlsv = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U || reg_hstatus.hu) val allow_sret = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0) val allow_counter = (reg_mstatus.prv > PRV.S.U || read_mcounteren(counter_addr)) && (!usingSupervisor.B || reg_mstatus.prv >= PRV.S.U || read_scounteren(counter_addr)) && (!usingHypervisor.B || !reg_mstatus.v || read_hcounteren(counter_addr)) io_dec.fp_illegal := io.status.fs === 0.U || reg_mstatus.v && reg_vsstatus.fs === 0.U || !reg_misa('f'-'a') io_dec.vector_illegal := io.status.vs === 0.U || reg_mstatus.v && reg_vsstatus.vs === 0.U || !reg_misa('v'-'a') io_dec.fp_csr := decodeFast(fp_csrs.keys.toList) io_dec.vector_csr := decodeFast(vector_csrs.keys.toList) io_dec.rocc_illegal := io.status.xs === 0.U || reg_mstatus.v && reg_vsstatus.xs === 0.U || !reg_misa('x'-'a') val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) || usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U val csr_exists = decodeAny(read_mapping) io_dec.read_illegal := !csr_addr_legal || !csr_exists || ((addr === CSRs.satp.U || addr === CSRs.hgatp.U) && !allow_sfence_vma) || is_counter && !allow_counter || decodeFast(debug_csrs.keys.toList) && !reg_debug || decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal || io_dec.fp_csr && io_dec.fp_illegal io_dec.write_illegal := addr(11,10).andR io_dec.write_flush := { val addr_m = addr | (PRV.M.U << CSR.modeLSB) !(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U) } io_dec.system_illegal := !csr_addr_legal && !is_hlsv || is_wfi && !allow_wfi || is_ret && !allow_sret || is_ret && addr(10) && addr(7) && !reg_debug || (is_sfence || is_hfence_gvma) && !allow_sfence_vma || is_hfence_vvma && !allow_hfence_vvma || is_hlsv && !allow_hlsv io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && ( CSR.mode(addr) === PRV.H.U || is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) || !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) || CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) || addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm) io_dec.virtual_system_illegal := reg_mstatus.v && ( is_hfence_vvma || is_hfence_gvma || is_hlsv || is_wfi && (!reg_mstatus.prv(0) || !reg_mstatus.tw && reg_hstatus.vtw) || is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) || reg_hstatus.vtsr) || is_sfence && (!reg_mstatus.prv(0) || reg_hstatus.vtvm)) } val cause = Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv), Mux[UInt](insn_break, Causes.breakpoint.U, io.cause)) val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0) val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0) val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv) val trapToDebug = usingDebug.B && (reg_singleStepped || causeIsDebugInt || causeIsDebugTrigger || causeIsDebugBreak || reg_debug) val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800)) val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808)) val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U) val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs)) val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs)) def mtvecBaseAlign = 2 def mtvecInterruptAlign = { require(reg_mip.getWidth <= xLen) log2Ceil(xLen) } val notDebugTVec = { val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec) val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset) val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign) } val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U || cause_lsbs === CSR.rnmiBEUCause.U) val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U val causeIsNmi = causeIsRnmiInt val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U) val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U) val trapToNmiInt = usingNMI.B && causeIsNmi val trapToNmiXcpt = usingNMI.B && !nmie val trapToNmi = trapToNmiInt || trapToNmiXcpt val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1 val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec)) io.evec := tvec io.ptbr := reg_satp io.hgatp := reg_hgatp io.vsatp := reg_vsatp io.eret := insn_call || insn_break || insn_ret io.singleStep := reg_dcsr.step && !reg_debug io.status := reg_mstatus io.status.sd := io.status.fs.andR || io.status.xs.andR || io.status.vs.andR io.status.debug := reg_debug io.status.isa := reg_misa io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv) io.status.dv := reg_mstatus.v || Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B) io.status.sd_rv32 := (xLen == 32).B && io.status.sd io.status.mpv := reg_mstatus.mpv io.status.gva := reg_mstatus.gva io.hstatus := reg_hstatus io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.gstatus := reg_vsstatus io.gstatus.sd := io.gstatus.fs.andR || io.gstatus.xs.andR || io.gstatus.vs.andR io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd val exception = insn_call || insn_break || io.exception assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive") when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B } when (pending_interrupts.orR || io.interrupts.debug || exception) { reg_wfi := false.B } io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } ) when (io.retire(0) || exception) { reg_singleStepped := true.B } when (!io.singleStep) { reg_singleStepped := false.B } assert(!io.singleStep || io.retire <= 1.U) assert(!reg_singleStepped || io.retire === 0.U) val epc = formEPC(io.pc) val tval = Mux(insn_break, epc, io.tval) when (exception) { when (trapToDebug) { when (!reg_debug) { reg_mstatus.v := false.B reg_debug := true.B reg_dpc := epc reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U))) reg_dcsr.prv := trimPrivilege(reg_mstatus.prv) reg_dcsr.v := reg_mstatus.v new_prv := PRV.M.U } }.elsewhen (trapToNmiInt) { when (reg_rnmie) { reg_mstatus.v := false.B reg_mnstatus.mpv := reg_mstatus.v reg_rnmie := false.B reg_mnepc := epc reg_mncause := (BigInt(1) << (xLen-1)).U | Mux(causeIsRnmiBEU, 3.U, 2.U) reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv) new_prv := PRV.M.U } }.elsewhen (delegateVS && nmie) { reg_mstatus.v := true.B reg_vsstatus.spp := reg_mstatus.prv reg_vsepc := epc reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause) reg_vstval := tval reg_vsstatus.spie := reg_vsstatus.sie reg_vsstatus.sie := false.B new_prv := PRV.S.U }.elsewhen (delegate && nmie) { reg_mstatus.v := false.B reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp) reg_hstatus.gva := io.gva reg_hstatus.spv := reg_mstatus.v reg_sepc := epc reg_scause := cause reg_stval := tval reg_htval := io.htval reg_htinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.spie := reg_mstatus.sie reg_mstatus.spp := reg_mstatus.prv reg_mstatus.sie := false.B new_prv := PRV.S.U }.otherwise { reg_mstatus.v := false.B reg_mstatus.mpv := reg_mstatus.v reg_mstatus.gva := io.gva reg_mepc := epc reg_mcause := cause reg_mtval := tval reg_mtval2 := io.htval reg_mtinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.mpie := reg_mstatus.mie reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv) reg_mstatus.mie := false.B new_prv := PRV.M.U } } for (i <- 0 until supported_interrupts.getWidth) { val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"INTERRUPT_M_$i") property.cover(en && delegable && delegate, s"INTERRUPT_S_$i") } for (i <- 0 until xLen) { val supported_exceptions: BigInt = 0x8fe | (if (usingCompressed && !coreParams.misaWritable) 0 else 1) | (if (usingUser) 0x100 else 0) | (if (usingSupervisor) 0x200 else 0) | (if (usingVM) 0xb000 else 0) if (((supported_exceptions >> i) & 1) != 0) { val en = exception && cause === i.U val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"EXCEPTION_M_$i") property.cover(en && delegable && delegate, s"EXCEPTION_S_$i") } } when (insn_ret) { val ret_prv = WireInit(UInt(), DontCare) when (usingSupervisor.B && !io.rw.addr(9)) { when (!reg_mstatus.v) { reg_mstatus.sie := reg_mstatus.spie reg_mstatus.spie := true.B reg_mstatus.spp := PRV.U.U ret_prv := reg_mstatus.spp reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv io.evec := readEPC(reg_sepc) reg_hstatus.spv := false.B }.otherwise { reg_vsstatus.sie := reg_vsstatus.spie reg_vsstatus.spie := true.B reg_vsstatus.spp := PRV.U.U ret_prv := reg_vsstatus.spp reg_mstatus.v := usingHypervisor.B io.evec := readEPC(reg_vsepc) } }.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) { ret_prv := reg_dcsr.prv reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U reg_debug := false.B io.evec := readEPC(reg_dpc) }.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) { ret_prv := reg_mnstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U reg_rnmie := true.B io.evec := readEPC(reg_mnepc) }.otherwise { reg_mstatus.mie := reg_mstatus.mpie reg_mstatus.mpie := true.B reg_mstatus.mpp := legalizePrivilege(PRV.U.U) reg_mstatus.mpv := false.B ret_prv := reg_mstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U io.evec := readEPC(reg_mepc) } new_prv := ret_prv when (usingUser.B && ret_prv <= PRV.S.U) { reg_mstatus.mprv := false.B } } io.time := reg_cycle io.csr_stall := reg_wfi || io.status.cease io.status.cease := RegEnable(true.B, false.B, insn_cease) io.status.wfi := reg_wfi for ((io, reg) <- io.customCSRs zip reg_custom) { io.wen := false.B io.wdata := wdata io.value := reg } for ((io, reg) <- io.roccCSRs zip reg_rocc) { io.wen := false.B io.wdata := wdata io.value := reg } io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) // cover access to register val coverable_counters = read_mapping.filterNot { case (k, _) => k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM } coverable_counters.foreach( {case (k, v) => { when (!k.U(11,10).andR) { // Cover points for RW CSR registers property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } .otherwise { // Cover points for RO CSR registers property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } }}) val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B)) io.vector.foreach { vio => when (set_vs_dirty) { assert(reg_mstatus.vs > 0.U) when (reg_mstatus.v) { reg_vsstatus.vs := 3.U } reg_mstatus.vs := 3.U } } val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B)) if (coreParams.haveFSDirty) { when (set_fs_dirty) { assert(reg_mstatus.fs > 0.U) when (reg_mstatus.v) { reg_vsstatus.fs := 3.U } reg_mstatus.fs := 3.U } } io.fcsr_rm := reg_frm when (io.fcsr_flags.valid) { reg_fflags := reg_fflags | io.fcsr_flags.bits set_fs_dirty := true.B } io.vector.foreach { vio => when (vio.set_vxsat) { reg_vxsat.get := true.B set_vs_dirty := true.B } } val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) || io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U) when (csr_wen) { val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB */ val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_)) when (decoded_addr(CSRs.mstatus)) { val new_mstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.mie := new_mstatus.mie reg_mstatus.mpie := new_mstatus.mpie if (usingUser) { reg_mstatus.mprv := new_mstatus.mprv reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp) if (usingSupervisor) { reg_mstatus.spp := new_mstatus.spp reg_mstatus.spie := new_mstatus.spie reg_mstatus.sie := new_mstatus.sie reg_mstatus.tw := new_mstatus.tw reg_mstatus.tsr := new_mstatus.tsr } if (usingVM) { reg_mstatus.mxr := new_mstatus.mxr reg_mstatus.sum := new_mstatus.sum reg_mstatus.tvm := new_mstatus.tvm } if (usingHypervisor) { reg_mstatus.mpv := new_mstatus.mpv reg_mstatus.gva := new_mstatus.gva } } if (usingSupervisor || usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs) reg_mstatus.vs := formVS(new_mstatus.vs) } when (decoded_addr(CSRs.misa)) { val mask = isaStringToMask(isaMaskString).U(xLen.W) val f = wdata('f' - 'a') // suppress write if it would cause the next fetch to be misaligned when (!usingCompressed.B || !io.pc(1) || wdata('c' - 'a')) { if (coreParams.misaWritable) reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask } } when (decoded_addr(CSRs.mip)) { // MIP should be modified based on the value in reg_mip, not the value // in read_mip, since read_mip.seip is the OR of reg_mip.seip and // io.interrupts.seip. We don't want the value on the PLIC line to // inadvertently be OR'd into read_mip.seip. val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP) if (usingSupervisor) { reg_mip.ssip := new_mip.ssip reg_mip.stip := new_mip.stip reg_mip.seip := new_mip.seip } if (usingHypervisor) { reg_mip.vssip := new_mip.vssip } } when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts } when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) } when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata } if (mtvecWritable) when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata } when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U } when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata } if (usingNMI) { val new_mnstatus = wdata.asTypeOf(new MNStatus()) when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata } when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) } when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U } when (decoded_addr(CustomCSRs.mnstatus)) { reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp) reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv reg_rnmie := reg_rnmie | new_mnstatus.mie // mnie bit settable but not clearable from software } } for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) { writeCounter(i + CSR.firstMHPC, c, wdata) when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) } } if (coreParams.haveBasicCounters) { when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero writeCounter(CSRs.mcycle, reg_cycle, wdata) writeCounter(CSRs.minstret, reg_instret, wdata) } if (usingFPU) { when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata } when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata } when (decoded_addr(CSRs.fcsr)) { set_fs_dirty := true.B reg_fflags := wdata reg_frm := wdata >> reg_fflags.getWidth } } if (usingDebug) { when (decoded_addr(CSRs.dcsr)) { val new_dcsr = wdata.asTypeOf(new DCSR()) reg_dcsr.step := new_dcsr.step reg_dcsr.ebreakm := new_dcsr.ebreakm if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv) if (usingHypervisor) reg_dcsr.v := new_dcsr.v } when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) } when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata } reg_dscratch1.foreach { r => when (decoded_addr(CSRs.dscratch1)) { r := wdata } } } if (usingSupervisor) { when (decoded_addr(CSRs.sstatus)) { val new_sstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.sie := new_sstatus.sie reg_mstatus.spie := new_sstatus.spie reg_mstatus.spp := new_sstatus.spp reg_mstatus.fs := formFS(new_sstatus.fs) reg_mstatus.vs := formVS(new_sstatus.vs) if (usingVM) { reg_mstatus.mxr := new_sstatus.mxr reg_mstatus.sum := new_sstatus.sum } } when (decoded_addr(CSRs.sip)) { val new_sip = ((read_mip & ~read_mideleg) | (wdata & read_mideleg)).asTypeOf(new MIP()) reg_mip.ssip := new_sip.ssip } when (decoded_addr(CSRs.satp)) { if (usingVM) { val new_satp = wdata.asTypeOf(new PTBR()) when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) { reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_|_).U reg_satp.ppn := new_satp.ppn(ppnBits-1,0) if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0) } } } when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) | (wdata & sie_mask) } when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata } when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) } when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata } when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask } when (decoded_addr(CSRs.stval)) { reg_stval := wdata } when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata } when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata } when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata } when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) } } if (usingHypervisor) { when (decoded_addr(CSRs.hstatus)) { val new_hstatus = wdata.asTypeOf(new HStatus()) reg_hstatus.gva := new_hstatus.gva reg_hstatus.spv := new_hstatus.spv reg_hstatus.spvp := new_hstatus.spvp reg_hstatus.hu := new_hstatus.hu reg_hstatus.vtvm := new_hstatus.vtvm reg_hstatus.vtw := new_hstatus.vtw reg_hstatus.vtsr := new_hstatus.vtsr reg_hstatus.vsxl := new_hstatus.vsxl } when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata } when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata } when (decoded_addr(CSRs.hgatp)) { val new_hgatp = wdata.asTypeOf(new PTBR()) val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_)) when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) { reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_|_).U } reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W)) if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0) } when (decoded_addr(CSRs.hip)) { val new_hip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_hip.vssip } when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts) } when (decoded_addr(CSRs.hvip)) { val new_sip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_sip.vssip reg_mip.vstip := new_sip.vstip reg_mip.vseip := new_sip.vseip } when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata } when (decoded_addr(CSRs.htval)) { reg_htval := wdata } when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata } val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12)) when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo } when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo } when (decoded_addr(CSRs.vsstatus)) { val new_vsstatus = wdata.asTypeOf(new MStatus()) reg_vsstatus.sie := new_vsstatus.sie reg_vsstatus.spie := new_vsstatus.spie reg_vsstatus.spp := new_vsstatus.spp reg_vsstatus.mxr := new_vsstatus.mxr reg_vsstatus.sum := new_vsstatus.sum reg_vsstatus.fs := formFS(new_vsstatus.fs) reg_vsstatus.vs := formVS(new_vsstatus.vs) } when (decoded_addr(CSRs.vsip)) { val new_vsip = ((read_hip & ~read_hideleg) | ((wdata << 1) & read_hideleg)).asTypeOf(new MIP()) reg_mip.vssip := new_vsip.vssip } when (decoded_addr(CSRs.vsatp)) { val new_vsatp = wdata.asTypeOf(new PTBR()) val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U)) when (mode_ok) { reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_|_).U } when (mode_ok || !reg_mstatus.v) { reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0) if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0) } } when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) | ((wdata << 1) & read_hideleg) } when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata } when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) } when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata } when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask } when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata } when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) } } if (usingUser) { when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata } when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) } } if (nBreakpoints > 0) { when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata } for ((bp, i) <- reg_bp.zipWithIndex) { when (i.U === reg_tselect && (!bp.control.dmode || reg_debug)) { when (decoded_addr(CSRs.tdata2)) { bp.address := wdata } when (decoded_addr(CSRs.tdata3)) { if (coreParams.mcontextWidth > 0) { bp.textra.mselect := wdata(bp.textra.mselectPos) bp.textra.mvalue := wdata >> bp.textra.mvaluePos } if (coreParams.scontextWidth > 0) { bp.textra.sselect := wdata(bp.textra.sselectPos) bp.textra.svalue := wdata >> bp.textra.svaluePos } } when (decoded_addr(CSRs.tdata1)) { bp.control := wdata.asTypeOf(bp.control) val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control) val dMode = newBPC.dmode && reg_debug && (prevDMode || !prevChain) bp.control.dmode := dMode when (dMode || (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U } bp.control.chain := newBPC.chain && !(prevChain || nextChain) && (dMode || !nextDMode) } } } } reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }} reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }} if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) { require(xLen % pmp.cfg.getWidth == 0) when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) { val newCfg = (wdata >> ((i * pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig()) pmp.cfg := newCfg // disallow unreadable but writable PMPs pmp.cfg.w := newCfg.w && newCfg.r // can't select a=NA4 with coarse-grained PMPs if (pmpGranularity.log2 > PMP.lgAlign) pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR) } when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) { pmp.addr := wdata } } def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (decoded_addr(csr.id)) { reg := (wdata & mask) | (reg & ~mask) io.wen := true.B } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { writeCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { writeCustomCSR(io, csr, reg) } if (usingVector) { when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata } when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata } when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata } when (decoded_addr(CSRs.vcsr)) { set_vs_dirty := true.B reg_vxsat.get := wdata reg_vxrm.get := wdata >> 1 } } } def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (io.set) { reg := (io.sdata & mask) | (reg & ~mask) } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { setCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { setCustomCSR(io, csr, reg) } io.vector.map { vio => when (vio.set_vconfig.valid) { // user of CSRFile is responsible for set_vs_dirty in this case assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax) reg_vconfig.get := vio.set_vconfig.bits } when (vio.set_vstart.valid) { set_vs_dirty := true.B reg_vstart.get := vio.set_vstart.bits } vio.vstart := reg_vstart.get vio.vconfig := reg_vconfig.get vio.vxrm := reg_vxrm.get when (reset.asBool) { reg_vconfig.get.vl := 0.U reg_vconfig.get.vtype := 0.U.asTypeOf(new VType) reg_vconfig.get.vtype.vill := true.B } } when(reset.asBool) { reg_satp.mode := 0.U reg_vsatp.mode := 0.U reg_hgatp.mode := 0.U } if (!usingVM) { reg_satp.mode := 0.U reg_satp.ppn := 0.U reg_satp.asid := 0.U } if (!usingHypervisor) { reg_vsatp.mode := 0.U reg_vsatp.ppn := 0.U reg_vsatp.asid := 0.U reg_hgatp.mode := 0.U reg_hgatp.ppn := 0.U reg_hgatp.asid := 0.U } if (!(asIdBits > 0)) { reg_satp.asid := 0.U reg_vsatp.asid := 0.U } if (!(vmIdBits > 0)) { reg_hgatp.asid := 0.U } reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U) if (nBreakpoints <= 1) reg_tselect := 0.U for (bpc <- reg_bp map {_.control}) { bpc.ttype := bpc.tType.U bpc.maskmax := bpc.maskMax.U bpc.reserved := 0.U bpc.zero := 0.U bpc.h := false.B if (!usingSupervisor) bpc.s := false.B if (!usingUser) bpc.u := false.B if (!usingSupervisor && !usingUser) bpc.m := true.B when (reset.asBool) { bpc.action := 0.U bpc.dmode := false.B bpc.chain := false.B bpc.r := false.B bpc.w := false.B bpc.x := false.B } } for (bpx <- reg_bp map {_.textra}) { if (coreParams.mcontextWidth == 0) bpx.mselect := false.B if (coreParams.scontextWidth == 0) bpx.sselect := false.B } for (bp <- reg_bp drop nBreakpoints) bp := 0.U.asTypeOf(new BP()) for (pmp <- reg_pmp) { pmp.cfg.res := 0.U when (reset.asBool) { pmp.reset() } } for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) { t.exception := io.retire >= i.U && exception t.valid := io.retire > i.U || t.exception t.insn := insn t.iaddr := io.pc t.priv := Cat(reg_debug, reg_mstatus.prv) t.cause := cause t.interrupt := cause(xLen-1) t.tval := io.tval t.wdata.foreach(_ := DontCare) } def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = { val nonstandard = supported_interrupts.getWidth-1 to 12 by -1 // MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4) val priority = nonstandard ++ standard val masks = masksIn.reverse val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_||_) val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U)))) (any, which) } def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = { (Mux(cmd(1), rdata, 0.U) | wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U) } def legalizePrivilege(priv: UInt): UInt = if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv) else if (usingUser) Fill(2, priv(0)) else PRV.M.U def trimPrivilege(priv: UInt): UInt = if (usingSupervisor) priv else legalizePrivilege(priv) def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { if (xLen == 32) { val hi = lo + CSRs.mcycleh - CSRs.mcycle when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } } else { when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) } } } def formEPC(x: UInt) = ~(~x | (if (usingCompressed) 1.U else 3.U)) def readEPC(x: UInt) = ~(~x | Mux(reg_misa('c' - 'a'), 1.U, 3.U)) def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) | 2).U, 2.U) def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_) def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR) def formVS(vs: UInt) = if (usingVector) vs else 0.U }
module CSRFile( // @[CSR.scala:377:7] input clock, // @[CSR.scala:377:7] input reset, // @[CSR.scala:377:7] input io_ungated_clock, // @[CSR.scala:384:14] input io_interrupts_debug, // @[CSR.scala:384:14] input io_interrupts_mtip, // @[CSR.scala:384:14] input io_interrupts_msip, // @[CSR.scala:384:14] input io_interrupts_meip, // @[CSR.scala:384:14] input io_interrupts_seip, // @[CSR.scala:384:14] input io_hartid, // @[CSR.scala:384:14] input [11:0] io_rw_addr, // @[CSR.scala:384:14] input [2:0] io_rw_cmd, // @[CSR.scala:384:14] output [63:0] io_rw_rdata, // @[CSR.scala:384:14] input [63:0] io_rw_wdata, // @[CSR.scala:384:14] input [31:0] io_decode_0_inst, // @[CSR.scala:384:14] output io_decode_0_fp_illegal, // @[CSR.scala:384:14] output io_decode_0_vector_illegal, // @[CSR.scala:384:14] output io_decode_0_fp_csr, // @[CSR.scala:384:14] output io_decode_0_vector_csr, // @[CSR.scala:384:14] output io_decode_0_read_illegal, // @[CSR.scala:384:14] output io_decode_0_write_illegal, // @[CSR.scala:384:14] output io_decode_0_write_flush, // @[CSR.scala:384:14] output io_decode_0_system_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_access_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_system_illegal, // @[CSR.scala:384:14] output io_csr_stall, // @[CSR.scala:384:14] output io_eret, // @[CSR.scala:384:14] output io_singleStep, // @[CSR.scala:384:14] output io_status_debug, // @[CSR.scala:384:14] output io_status_cease, // @[CSR.scala:384:14] output io_status_wfi, // @[CSR.scala:384:14] output [31:0] io_status_isa, // @[CSR.scala:384:14] output [1:0] io_status_dprv, // @[CSR.scala:384:14] output io_status_dv, // @[CSR.scala:384:14] output [1:0] io_status_prv, // @[CSR.scala:384:14] output io_status_v, // @[CSR.scala:384:14] output io_status_sd, // @[CSR.scala:384:14] output io_status_mpv, // @[CSR.scala:384:14] output io_status_gva, // @[CSR.scala:384:14] output io_status_tsr, // @[CSR.scala:384:14] output io_status_tw, // @[CSR.scala:384:14] output io_status_tvm, // @[CSR.scala:384:14] output io_status_mxr, // @[CSR.scala:384:14] output io_status_sum, // @[CSR.scala:384:14] output io_status_mprv, // @[CSR.scala:384:14] output [1:0] io_status_fs, // @[CSR.scala:384:14] output [1:0] io_status_mpp, // @[CSR.scala:384:14] output [1:0] io_status_vs, // @[CSR.scala:384:14] output io_status_spp, // @[CSR.scala:384:14] output io_status_mpie, // @[CSR.scala:384:14] output io_status_spie, // @[CSR.scala:384:14] output io_status_mie, // @[CSR.scala:384:14] output io_status_sie, // @[CSR.scala:384:14] output io_hstatus_spvp, // @[CSR.scala:384:14] output io_hstatus_spv, // @[CSR.scala:384:14] output io_hstatus_gva, // @[CSR.scala:384:14] output io_gstatus_debug, // @[CSR.scala:384:14] output io_gstatus_cease, // @[CSR.scala:384:14] output io_gstatus_wfi, // @[CSR.scala:384:14] output [31:0] io_gstatus_isa, // @[CSR.scala:384:14] output [1:0] io_gstatus_dprv, // @[CSR.scala:384:14] output io_gstatus_dv, // @[CSR.scala:384:14] output [1:0] io_gstatus_prv, // @[CSR.scala:384:14] output io_gstatus_v, // @[CSR.scala:384:14] output [22:0] io_gstatus_zero2, // @[CSR.scala:384:14] output io_gstatus_mpv, // @[CSR.scala:384:14] output io_gstatus_gva, // @[CSR.scala:384:14] output io_gstatus_mbe, // @[CSR.scala:384:14] output io_gstatus_sbe, // @[CSR.scala:384:14] output [1:0] io_gstatus_sxl, // @[CSR.scala:384:14] output [7:0] io_gstatus_zero1, // @[CSR.scala:384:14] output io_gstatus_tsr, // @[CSR.scala:384:14] output io_gstatus_tw, // @[CSR.scala:384:14] output io_gstatus_tvm, // @[CSR.scala:384:14] output io_gstatus_mxr, // @[CSR.scala:384:14] output io_gstatus_sum, // @[CSR.scala:384:14] output io_gstatus_mprv, // @[CSR.scala:384:14] output [1:0] io_gstatus_fs, // @[CSR.scala:384:14] output [1:0] io_gstatus_mpp, // @[CSR.scala:384:14] output io_gstatus_spp, // @[CSR.scala:384:14] output io_gstatus_mpie, // @[CSR.scala:384:14] output io_gstatus_ube, // @[CSR.scala:384:14] output io_gstatus_spie, // @[CSR.scala:384:14] output io_gstatus_upie, // @[CSR.scala:384:14] output io_gstatus_mie, // @[CSR.scala:384:14] output io_gstatus_hie, // @[CSR.scala:384:14] output io_gstatus_sie, // @[CSR.scala:384:14] output io_gstatus_uie, // @[CSR.scala:384:14] output [3:0] io_ptbr_mode, // @[CSR.scala:384:14] output [43:0] io_ptbr_ppn, // @[CSR.scala:384:14] output [39:0] io_evec, // @[CSR.scala:384:14] input io_exception, // @[CSR.scala:384:14] input io_retire, // @[CSR.scala:384:14] input [63:0] io_cause, // @[CSR.scala:384:14] input [39:0] io_pc, // @[CSR.scala:384:14] input [39:0] io_tval, // @[CSR.scala:384:14] input [39:0] io_htval, // @[CSR.scala:384:14] input io_mhtinst_read_pseudo, // @[CSR.scala:384:14] input io_gva, // @[CSR.scala:384:14] output [63:0] io_time, // @[CSR.scala:384:14] output [2:0] io_fcsr_rm, // @[CSR.scala:384:14] input io_fcsr_flags_valid, // @[CSR.scala:384:14] input [4:0] io_fcsr_flags_bits, // @[CSR.scala:384:14] output io_interrupt, // @[CSR.scala:384:14] output [63:0] io_interrupt_cause, // @[CSR.scala:384:14] output io_bp_0_control_dmode, // @[CSR.scala:384:14] output io_bp_0_control_action, // @[CSR.scala:384:14] output [1:0] io_bp_0_control_tmatch, // @[CSR.scala:384:14] output io_bp_0_control_m, // @[CSR.scala:384:14] output io_bp_0_control_s, // @[CSR.scala:384:14] output io_bp_0_control_u, // @[CSR.scala:384:14] output io_bp_0_control_x, // @[CSR.scala:384:14] output io_bp_0_control_w, // @[CSR.scala:384:14] output io_bp_0_control_r, // @[CSR.scala:384:14] output [38:0] io_bp_0_address, // @[CSR.scala:384:14] output [47:0] io_bp_0_textra_pad2, // @[CSR.scala:384:14] output io_bp_0_textra_pad1, // @[CSR.scala:384:14] output io_pmp_0_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_0_cfg_a, // @[CSR.scala:384:14] output io_pmp_0_cfg_x, // @[CSR.scala:384:14] output io_pmp_0_cfg_w, // @[CSR.scala:384:14] output io_pmp_0_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_0_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_0_mask, // @[CSR.scala:384:14] output io_pmp_1_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_1_cfg_a, // @[CSR.scala:384:14] output io_pmp_1_cfg_x, // @[CSR.scala:384:14] output io_pmp_1_cfg_w, // @[CSR.scala:384:14] output io_pmp_1_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_1_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_1_mask, // @[CSR.scala:384:14] output io_pmp_2_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_2_cfg_a, // @[CSR.scala:384:14] output io_pmp_2_cfg_x, // @[CSR.scala:384:14] output io_pmp_2_cfg_w, // @[CSR.scala:384:14] output io_pmp_2_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_2_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_2_mask, // @[CSR.scala:384:14] output io_pmp_3_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_3_cfg_a, // @[CSR.scala:384:14] output io_pmp_3_cfg_x, // @[CSR.scala:384:14] output io_pmp_3_cfg_w, // @[CSR.scala:384:14] output io_pmp_3_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_3_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_3_mask, // @[CSR.scala:384:14] output io_pmp_4_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_4_cfg_a, // @[CSR.scala:384:14] output io_pmp_4_cfg_x, // @[CSR.scala:384:14] output io_pmp_4_cfg_w, // @[CSR.scala:384:14] output io_pmp_4_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_4_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_4_mask, // @[CSR.scala:384:14] output io_pmp_5_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_5_cfg_a, // @[CSR.scala:384:14] output io_pmp_5_cfg_x, // @[CSR.scala:384:14] output io_pmp_5_cfg_w, // @[CSR.scala:384:14] output io_pmp_5_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_5_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_5_mask, // @[CSR.scala:384:14] output io_pmp_6_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_6_cfg_a, // @[CSR.scala:384:14] output io_pmp_6_cfg_x, // @[CSR.scala:384:14] output io_pmp_6_cfg_w, // @[CSR.scala:384:14] output io_pmp_6_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_6_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_6_mask, // @[CSR.scala:384:14] output io_pmp_7_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_7_cfg_a, // @[CSR.scala:384:14] output io_pmp_7_cfg_x, // @[CSR.scala:384:14] output io_pmp_7_cfg_w, // @[CSR.scala:384:14] output io_pmp_7_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_7_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_7_mask, // @[CSR.scala:384:14] output io_inhibit_cycle, // @[CSR.scala:384:14] input [31:0] io_inst_0, // @[CSR.scala:384:14] output io_trace_0_valid, // @[CSR.scala:384:14] output [39:0] io_trace_0_iaddr, // @[CSR.scala:384:14] output [31:0] io_trace_0_insn, // @[CSR.scala:384:14] output [2:0] io_trace_0_priv, // @[CSR.scala:384:14] output io_trace_0_exception, // @[CSR.scala:384:14] output io_trace_0_interrupt, // @[CSR.scala:384:14] output [63:0] io_trace_0_cause, // @[CSR.scala:384:14] output [39:0] io_trace_0_tval, // @[CSR.scala:384:14] output [12:0] io_vector_vconfig_vl, // @[CSR.scala:384:14] output io_vector_vconfig_vtype_vill, // @[CSR.scala:384:14] output [54:0] io_vector_vconfig_vtype_reserved, // @[CSR.scala:384:14] output io_vector_vconfig_vtype_vma, // @[CSR.scala:384:14] output io_vector_vconfig_vtype_vta, // @[CSR.scala:384:14] output [2:0] io_vector_vconfig_vtype_vsew, // @[CSR.scala:384:14] output io_vector_vconfig_vtype_vlmul_sign, // @[CSR.scala:384:14] output [1:0] io_vector_vconfig_vtype_vlmul_mag, // @[CSR.scala:384:14] output [11:0] io_vector_vstart, // @[CSR.scala:384:14] output [1:0] io_vector_vxrm, // @[CSR.scala:384:14] input io_vector_set_vs_dirty, // @[CSR.scala:384:14] input io_vector_set_vconfig_valid, // @[CSR.scala:384:14] input [12:0] io_vector_set_vconfig_bits_vl, // @[CSR.scala:384:14] input io_vector_set_vconfig_bits_vtype_vill, // @[CSR.scala:384:14] input [54:0] io_vector_set_vconfig_bits_vtype_reserved, // @[CSR.scala:384:14] input io_vector_set_vconfig_bits_vtype_vma, // @[CSR.scala:384:14] input io_vector_set_vconfig_bits_vtype_vta, // @[CSR.scala:384:14] input [2:0] io_vector_set_vconfig_bits_vtype_vsew, // @[CSR.scala:384:14] input io_vector_set_vconfig_bits_vtype_vlmul_sign, // @[CSR.scala:384:14] input [1:0] io_vector_set_vconfig_bits_vtype_vlmul_mag, // @[CSR.scala:384:14] input io_vector_set_vstart_valid, // @[CSR.scala:384:14] output io_customCSRs_0_ren, // @[CSR.scala:384:14] output io_customCSRs_0_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_value, // @[CSR.scala:384:14] output io_customCSRs_1_ren, // @[CSR.scala:384:14] output io_customCSRs_1_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_1_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_1_value, // @[CSR.scala:384:14] output io_customCSRs_2_ren, // @[CSR.scala:384:14] output io_customCSRs_2_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_2_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_2_value, // @[CSR.scala:384:14] output io_customCSRs_3_ren, // @[CSR.scala:384:14] output io_customCSRs_3_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_3_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_3_value // @[CSR.scala:384:14] ); wire io_status_sie_0; // @[CSR.scala:377:7] wire io_status_spie_0; // @[CSR.scala:377:7] wire io_status_spp_0; // @[CSR.scala:377:7] wire [1:0] io_status_vs_0; // @[CSR.scala:377:7] wire [1:0] io_status_fs_0; // @[CSR.scala:377:7] wire io_status_sum_0; // @[CSR.scala:377:7] wire io_status_mxr_0; // @[CSR.scala:377:7] wire io_status_sd_0; // @[CSR.scala:377:7] wire io_ungated_clock_0 = io_ungated_clock; // @[CSR.scala:377:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[CSR.scala:377:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[CSR.scala:377:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[CSR.scala:377:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[CSR.scala:377:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[CSR.scala:377:7] wire io_hartid_0 = io_hartid; // @[CSR.scala:377:7] wire [11:0] io_rw_addr_0 = io_rw_addr; // @[CSR.scala:377:7] wire [2:0] io_rw_cmd_0 = io_rw_cmd; // @[CSR.scala:377:7] wire [63:0] io_rw_wdata_0 = io_rw_wdata; // @[CSR.scala:377:7] wire [31:0] io_decode_0_inst_0 = io_decode_0_inst; // @[CSR.scala:377:7] wire io_exception_0 = io_exception; // @[CSR.scala:377:7] wire io_retire_0 = io_retire; // @[CSR.scala:377:7] wire [63:0] io_cause_0 = io_cause; // @[CSR.scala:377:7] wire [39:0] io_pc_0 = io_pc; // @[CSR.scala:377:7] wire [39:0] io_tval_0 = io_tval; // @[CSR.scala:377:7] wire [39:0] io_htval_0 = io_htval; // @[CSR.scala:377:7] wire io_mhtinst_read_pseudo_0 = io_mhtinst_read_pseudo; // @[CSR.scala:377:7] wire io_gva_0 = io_gva; // @[CSR.scala:377:7] wire io_fcsr_flags_valid_0 = io_fcsr_flags_valid; // @[CSR.scala:377:7] wire [4:0] io_fcsr_flags_bits_0 = io_fcsr_flags_bits; // @[CSR.scala:377:7] wire [31:0] io_inst_0_0 = io_inst_0; // @[CSR.scala:377:7] wire io_vector_set_vs_dirty_0 = io_vector_set_vs_dirty; // @[CSR.scala:377:7] wire io_vector_set_vconfig_valid_0 = io_vector_set_vconfig_valid; // @[CSR.scala:377:7] wire [12:0] io_vector_set_vconfig_bits_vl_0 = io_vector_set_vconfig_bits_vl; // @[CSR.scala:377:7] wire io_vector_set_vconfig_bits_vtype_vill_0 = io_vector_set_vconfig_bits_vtype_vill; // @[CSR.scala:377:7] wire [54:0] io_vector_set_vconfig_bits_vtype_reserved_0 = io_vector_set_vconfig_bits_vtype_reserved; // @[CSR.scala:377:7] wire io_vector_set_vconfig_bits_vtype_vma_0 = io_vector_set_vconfig_bits_vtype_vma; // @[CSR.scala:377:7] wire io_vector_set_vconfig_bits_vtype_vta_0 = io_vector_set_vconfig_bits_vtype_vta; // @[CSR.scala:377:7] wire [2:0] io_vector_set_vconfig_bits_vtype_vsew_0 = io_vector_set_vconfig_bits_vtype_vsew; // @[CSR.scala:377:7] wire io_vector_set_vconfig_bits_vtype_vlmul_sign_0 = io_vector_set_vconfig_bits_vtype_vlmul_sign; // @[CSR.scala:377:7] wire [1:0] io_vector_set_vconfig_bits_vtype_vlmul_mag_0 = io_vector_set_vconfig_bits_vtype_vlmul_mag; // @[CSR.scala:377:7] wire io_vector_set_vstart_valid_0 = io_vector_set_vstart_valid; // @[CSR.scala:377:7] wire io_decode_0_rocc_illegal = 1'h1; // @[CSR.scala:377:7] wire io_gstatus_sd = 1'h1; // @[CSR.scala:377:7] wire sup_meip = 1'h1; // @[CSR.scala:406:19] wire sup_seip = 1'h1; // @[CSR.scala:406:19] wire sup_mtip = 1'h1; // @[CSR.scala:406:19] wire sup_stip = 1'h1; // @[CSR.scala:406:19] wire sup_msip = 1'h1; // @[CSR.scala:406:19] wire sup_ssip = 1'h1; // @[CSR.scala:406:19] wire del_seip = 1'h1; // @[CSR.scala:426:26] wire del_stip = 1'h1; // @[CSR.scala:426:26] wire del_ssip = 1'h1; // @[CSR.scala:426:26] wire read_mnstatus_mie = 1'h1; // @[CSR.scala:675:31] wire sie_mask_sgeip_mask_sgeip = 1'h1; // @[CSR.scala:748:30] wire _allow_wfi_T_4 = 1'h1; // @[CSR.scala:906:112] wire _allow_wfi_T_5 = 1'h1; // @[CSR.scala:906:109] wire allow_hfence_vvma = 1'h1; // @[CSR.scala:908:50] wire allow_hlsv = 1'h1; // @[CSR.scala:909:43] wire _allow_counter_T_11 = 1'h1; // @[CSR.scala:914:8] wire _allow_counter_T_13 = 1'h1; // @[CSR.scala:914:27] wire _allow_counter_T_16 = 1'h1; // @[CSR.scala:914:45] wire _io_decode_0_fp_illegal_T_1 = 1'h1; // @[CSR.scala:915:83] wire _io_decode_0_rocc_illegal_T = 1'h1; // @[CSR.scala:919:41] wire _io_decode_0_rocc_illegal_T_1 = 1'h1; // @[CSR.scala:919:85] wire _io_decode_0_rocc_illegal_T_3 = 1'h1; // @[CSR.scala:919:49] wire _io_decode_0_rocc_illegal_T_6 = 1'h1; // @[CSR.scala:919:93] wire _io_gstatus_sd_T_3 = 1'h1; // @[CSR.scala:1016:78] wire _io_gstatus_sd_T_4 = 1'h1; // @[CSR.scala:1016:61] wire _en_T_7 = 1'h1; // @[CSR.scala:1096:71] wire delegable_1 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_19 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_31 = 1'h1; // @[CSR.scala:1096:71] wire delegable_5 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_43 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_55 = 1'h1; // @[CSR.scala:1096:71] wire delegable_9 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_67 = 1'h1; // @[CSR.scala:1096:71] wire delegable_16 = 1'h1; // @[CSR.scala:1109:67] wire delegable_18 = 1'h1; // @[CSR.scala:1109:67] wire delegable_19 = 1'h1; // @[CSR.scala:1109:67] wire delegable_20 = 1'h1; // @[CSR.scala:1109:67] wire delegable_22 = 1'h1; // @[CSR.scala:1109:67] wire delegable_24 = 1'h1; // @[CSR.scala:1109:67] wire delegable_27 = 1'h1; // @[CSR.scala:1109:67] wire delegable_28 = 1'h1; // @[CSR.scala:1109:67] wire delegable_29 = 1'h1; // @[CSR.scala:1109:67] wire _csr_wen_T_5 = 1'h1; // @[CSR.scala:1222:59] wire _dMode_T_1 = 1'h1; // @[CSR.scala:1478:68] wire _dMode_T_2 = 1'h1; // @[CSR.scala:1478:65] wire _reg_bp_0_control_chain_T = 1'h1; // @[CSR.scala:1481:61] wire _dMode_T_4 = 1'h1; // @[CSR.scala:1478:68] wire _dMode_T_5 = 1'h1; // @[CSR.scala:1478:65] wire _reg_bp_1_control_chain_T = 1'h1; // @[CSR.scala:1481:61] wire _io_trace_0_exception_T = 1'h1; // @[CSR.scala:1620:30] wire [22:0] io_status_zero2 = 23'h0; // @[CSR.scala:377:7] wire [22:0] io_gstatus_zero2_0 = 23'h0; // @[CSR.scala:377:7] wire [22:0] _reset_mstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:391:47] wire [22:0] reset_mstatus_zero2 = 23'h0; // @[CSR.scala:391:34] wire [22:0] _read_sstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:755:48] wire [22:0] read_sstatus_zero2 = 23'h0; // @[CSR.scala:755:35] wire io_rw_stall = 1'h0; // @[CSR.scala:377:7] wire io_status_mbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_status_ube = 1'h0; // @[CSR.scala:377:7] wire io_status_upie = 1'h0; // @[CSR.scala:377:7] wire io_status_hie = 1'h0; // @[CSR.scala:377:7] wire io_status_uie = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtsr = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtw = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtvm = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_hu = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vsbe = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_debug_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_cease_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_wfi_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_dv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_v_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_gva_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mbe_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sbe_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tsr_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tw_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tvm_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mxr_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sum_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mprv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_ube_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_upie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_hie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_uie_0 = 1'h0; // @[CSR.scala:377:7] wire io_rocc_interrupt = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_control_chain = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_control_h = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_mselect = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_pad1_0 = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_sselect = 1'h0; // @[CSR.scala:377:7] wire io_vector_set_vxsat = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_2_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_2_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_3_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_3_set = 1'h0; // @[CSR.scala:377:7] wire _reset_mstatus_WIRE_debug = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_cease = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_wfi = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_dv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_v = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_gva = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tsr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tw = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tvm = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mxr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sum = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mprv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spp = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_ube = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_upie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_hie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_uie = 1'h0; // @[CSR.scala:391:47] wire reset_mstatus_debug = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_cease = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_wfi = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_dv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_v = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_gva = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd_rv32 = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tsr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tw = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tvm = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mxr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sum = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mprv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spp = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_ube = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_upie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_hie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_uie = 1'h0; // @[CSR.scala:391:34] wire _reset_dcsr_WIRE_ebreakm = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreakh = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaks = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaku = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_zero2 = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stopcycle = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stoptime = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_v = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_step = 1'h0; // @[CSR.scala:400:44] wire reset_dcsr_ebreakm = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreakh = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaks = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaku = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_zero2 = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stopcycle = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stoptime = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_v = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_step = 1'h0; // @[CSR.scala:400:31] wire sup_zero1 = 1'h0; // @[CSR.scala:406:19] wire sup_debug = 1'h0; // @[CSR.scala:406:19] wire sup_rocc = 1'h0; // @[CSR.scala:406:19] wire sup_sgeip = 1'h0; // @[CSR.scala:406:19] wire sup_vseip = 1'h0; // @[CSR.scala:406:19] wire sup_ueip = 1'h0; // @[CSR.scala:406:19] wire sup_vstip = 1'h0; // @[CSR.scala:406:19] wire sup_utip = 1'h0; // @[CSR.scala:406:19] wire sup_vssip = 1'h0; // @[CSR.scala:406:19] wire sup_usip = 1'h0; // @[CSR.scala:406:19] wire del_zero1 = 1'h0; // @[CSR.scala:426:26] wire del_debug = 1'h0; // @[CSR.scala:426:26] wire del_rocc = 1'h0; // @[CSR.scala:426:26] wire del_sgeip = 1'h0; // @[CSR.scala:426:26] wire del_meip = 1'h0; // @[CSR.scala:426:26] wire del_vseip = 1'h0; // @[CSR.scala:426:26] wire del_ueip = 1'h0; // @[CSR.scala:426:26] wire del_mtip = 1'h0; // @[CSR.scala:426:26] wire del_vstip = 1'h0; // @[CSR.scala:426:26] wire del_utip = 1'h0; // @[CSR.scala:426:26] wire del_msip = 1'h0; // @[CSR.scala:426:26] wire del_vssip = 1'h0; // @[CSR.scala:426:26] wire del_usip = 1'h0; // @[CSR.scala:426:26] wire hi_hi_hi_hi = 1'h0; // @[CSR.scala:431:10] wire hi_hi_hi_hi_1 = 1'h0; // @[CSR.scala:431:50] wire _always_WIRE_zero1 = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_debug = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_rocc = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_sgeip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_meip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vseip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_seip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ueip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_mtip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vstip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_stip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_utip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_msip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_usip = 1'h0; // @[CSR.scala:471:42] wire always_zero1 = 1'h0; // @[CSR.scala:471:29] wire always_debug = 1'h0; // @[CSR.scala:471:29] wire always_rocc = 1'h0; // @[CSR.scala:471:29] wire always_sgeip = 1'h0; // @[CSR.scala:471:29] wire always_meip = 1'h0; // @[CSR.scala:471:29] wire always_vseip = 1'h0; // @[CSR.scala:471:29] wire always_seip = 1'h0; // @[CSR.scala:471:29] wire always_ueip = 1'h0; // @[CSR.scala:471:29] wire always_mtip = 1'h0; // @[CSR.scala:471:29] wire always_vstip = 1'h0; // @[CSR.scala:471:29] wire always_stip = 1'h0; // @[CSR.scala:471:29] wire always_utip = 1'h0; // @[CSR.scala:471:29] wire always_msip = 1'h0; // @[CSR.scala:471:29] wire always_vssip = 1'h0; // @[CSR.scala:471:29] wire always_ssip = 1'h0; // @[CSR.scala:471:29] wire always_usip = 1'h0; // @[CSR.scala:471:29] wire deleg_zero1 = 1'h0; // @[CSR.scala:476:28] wire deleg_debug = 1'h0; // @[CSR.scala:476:28] wire deleg_rocc = 1'h0; // @[CSR.scala:476:28] wire deleg_sgeip = 1'h0; // @[CSR.scala:476:28] wire deleg_meip = 1'h0; // @[CSR.scala:476:28] wire deleg_vseip = 1'h0; // @[CSR.scala:476:28] wire deleg_seip = 1'h0; // @[CSR.scala:476:28] wire deleg_ueip = 1'h0; // @[CSR.scala:476:28] wire deleg_mtip = 1'h0; // @[CSR.scala:476:28] wire deleg_vstip = 1'h0; // @[CSR.scala:476:28] wire deleg_stip = 1'h0; // @[CSR.scala:476:28] wire deleg_utip = 1'h0; // @[CSR.scala:476:28] wire deleg_msip = 1'h0; // @[CSR.scala:476:28] wire deleg_vssip = 1'h0; // @[CSR.scala:476:28] wire deleg_ssip = 1'h0; // @[CSR.scala:476:28] wire deleg_usip = 1'h0; // @[CSR.scala:476:28] wire hi_hi_hi_hi_2 = 1'h0; // @[CSR.scala:479:12] wire hi_hi_hi_hi_3 = 1'h0; // @[CSR.scala:479:27] wire _reset_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:516:48] wire _reset_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:516:48] wire reset_mnstatus_mpv = 1'h0; // @[CSR.scala:516:35] wire reset_mnstatus_mie = 1'h0; // @[CSR.scala:516:35] wire _reg_menvcfg_WIRE_stce = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:525:41] wire _reg_senvcfg_WIRE_stce = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:526:41] wire _reg_henvcfg_WIRE_stce = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:527:41] wire _reg_hstatus_WIRE_vtsr = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtw = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtvm = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_hu = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spvp = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spv = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_gva = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vsbe = 1'h0; // @[CSR.scala:552:41] wire read_hvip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:555:27] wire mip_zero1 = 1'h0; // @[CSR.scala:600:24] wire mip_debug = 1'h0; // @[CSR.scala:600:24] wire mip_rocc = 1'h0; // @[CSR.scala:600:24] wire mip_sgeip = 1'h0; // @[CSR.scala:600:24] wire mip_vseip = 1'h0; // @[CSR.scala:600:24] wire mip_ueip = 1'h0; // @[CSR.scala:600:24] wire mip_vstip = 1'h0; // @[CSR.scala:600:24] wire mip_utip = 1'h0; // @[CSR.scala:600:24] wire mip_vssip = 1'h0; // @[CSR.scala:600:24] wire mip_usip = 1'h0; // @[CSR.scala:600:24] wire _any_T_47 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_48 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_49 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_50 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_51 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_52 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_53 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_54 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_55 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_56 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_57 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_58 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_59 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_60 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_61 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_62 = 1'h0; // @[CSR.scala:1637:76] wire _which_T_47 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_48 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_49 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_50 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_51 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_52 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_53 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_54 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_55 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_56 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_57 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_58 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_59 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_60 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_61 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_62 = 1'h0; // @[CSR.scala:1638:91] wire _io_fiom_T_5 = 1'h0; // @[CSR.scala:631:131] wire _pmp_mask_base_T_2 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_5 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_8 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_11 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_14 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_17 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_20 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_23 = 1'h0; // @[PMP.scala:57:62] wire read_mapping_lo_hi_1 = 1'h0; // @[CSR.scala:657:47] wire read_mapping_hi_hi_1 = 1'h0; // @[CSR.scala:657:47] wire _read_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:675:44] wire _read_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:675:44] wire read_mnstatus_mpv = 1'h0; // @[CSR.scala:675:31] wire _sie_mask_sgeip_mask_WIRE_zero1 = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_debug = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_rocc = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_sgeip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_meip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vseip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_seip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ueip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_mtip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vstip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_stip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_utip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_msip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_usip = 1'h0; // @[CSR.scala:748:43] wire sie_mask_sgeip_mask_zero1 = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_debug = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_rocc = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_meip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vseip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_seip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ueip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_mtip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vstip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_stip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_utip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_msip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_usip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_hi_hi_hi_hi = 1'h0; // @[CSR.scala:750:59] wire _read_sstatus_WIRE_debug = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_cease = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_wfi = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_dv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_v = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sd = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mpv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_gva = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mbe = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sbe = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tsr = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tw = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tvm = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mxr = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sum = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mprv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_spp = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mpie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_ube = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_spie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_upie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_hie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_uie = 1'h0; // @[CSR.scala:755:48] wire read_sstatus_debug = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_cease = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_wfi = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_dv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_v = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mpv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_gva = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mbe = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_sbe = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_sd_rv32 = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tsr = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tw = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tvm = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mprv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mpie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_ube = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_upie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_hie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_uie = 1'h0; // @[CSR.scala:755:35] wire read_pmp_15_cfg_l = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_x = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_w = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_r = 1'h0; // @[CSR.scala:787:59] wire _reg_custom_T = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_1 = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_2 = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_3 = 1'h0; // @[CSR.scala:801:16] wire _allow_counter_T_4 = 1'h0; // @[CSR.scala:913:8] wire _io_decode_0_vector_illegal_T_1 = 1'h0; // @[CSR.scala:916:87] wire _io_decode_0_vector_illegal_T_2 = 1'h0; // @[CSR.scala:916:68] wire _csr_addr_legal_T_3 = 1'h0; // @[CSR.scala:921:25] wire _csr_addr_legal_T_5 = 1'h0; // @[CSR.scala:921:43] wire _csr_addr_legal_T_8 = 1'h0; // @[CSR.scala:921:74] wire _io_decode_0_system_illegal_T_20 = 1'h0; // @[CSR.scala:940:25] wire _io_decode_0_system_illegal_T_21 = 1'h0; // @[CSR.scala:940:22] wire _io_decode_0_system_illegal_T_23 = 1'h0; // @[CSR.scala:941:18] wire _io_decode_0_system_illegal_T_24 = 1'h0; // @[CSR.scala:941:15] wire _io_decode_0_virtual_access_illegal_T_27 = 1'h0; // @[CSR.scala:947:50] wire _io_decode_0_virtual_system_illegal_T_5 = 1'h0; // @[CSR.scala:953:57] wire trapToNmiInt = 1'h0; // @[CSR.scala:990:33] wire _trapToNmiXcpt_T = 1'h0; // @[CSR.scala:991:37] wire trapToNmiXcpt = 1'h0; // @[CSR.scala:991:34] wire trapToNmi = 1'h0; // @[CSR.scala:992:32] wire _nmiTVec_T = 1'h0; // @[CSR.scala:993:21] wire _nmiTVec_T_1 = 1'h0; // @[CSR.scala:993:58] wire _io_status_sd_T_1 = 1'h0; // @[CSR.scala:1003:53] wire _io_status_sd_rv32_T = 1'h0; // @[CSR.scala:1010:39] wire _io_gstatus_sd_T_1 = 1'h0; // @[CSR.scala:1016:56] wire _io_gstatus_sd_rv32_T = 1'h0; // @[CSR.scala:1018:40] wire _en_T_1 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_2 = 1'h0; // @[CSR.scala:1096:24] wire en = 1'h0; // @[CSR.scala:1096:79] wire delegable = 1'h0; // @[CSR.scala:1097:65] wire _en_T_13 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_14 = 1'h0; // @[CSR.scala:1096:24] wire en_2 = 1'h0; // @[CSR.scala:1096:79] wire delegable_2 = 1'h0; // @[CSR.scala:1097:65] wire delegable_3 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_25 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_26 = 1'h0; // @[CSR.scala:1096:24] wire en_4 = 1'h0; // @[CSR.scala:1096:79] wire delegable_4 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_37 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_38 = 1'h0; // @[CSR.scala:1096:24] wire en_6 = 1'h0; // @[CSR.scala:1096:79] wire delegable_6 = 1'h0; // @[CSR.scala:1097:65] wire delegable_7 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_49 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_50 = 1'h0; // @[CSR.scala:1096:24] wire en_8 = 1'h0; // @[CSR.scala:1096:79] wire delegable_8 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_61 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_62 = 1'h0; // @[CSR.scala:1096:24] wire en_10 = 1'h0; // @[CSR.scala:1096:79] wire delegable_10 = 1'h0; // @[CSR.scala:1097:65] wire delegable_11 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_73 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_74 = 1'h0; // @[CSR.scala:1096:24] wire en_12 = 1'h0; // @[CSR.scala:1096:79] wire delegable_12 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_79 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_80 = 1'h0; // @[CSR.scala:1096:24] wire en_13 = 1'h0; // @[CSR.scala:1096:79] wire delegable_13 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_85 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_86 = 1'h0; // @[CSR.scala:1096:24] wire en_14 = 1'h0; // @[CSR.scala:1096:79] wire delegable_14 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_91 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_92 = 1'h0; // @[CSR.scala:1096:24] wire en_15 = 1'h0; // @[CSR.scala:1096:79] wire delegable_15 = 1'h0; // @[CSR.scala:1097:65] wire delegable_17 = 1'h0; // @[CSR.scala:1109:67] wire delegable_21 = 1'h0; // @[CSR.scala:1109:67] wire delegable_23 = 1'h0; // @[CSR.scala:1109:67] wire delegable_25 = 1'h0; // @[CSR.scala:1109:67] wire delegable_26 = 1'h0; // @[CSR.scala:1109:67] wire _reg_mstatus_v_T = 1'h0; // @[CSR.scala:1123:44] wire _reg_mstatus_v_T_1 = 1'h0; // @[CSR.scala:1136:42] wire _reg_mstatus_v_T_3 = 1'h0; // @[CSR.scala:1136:56] wire _reg_mstatus_v_T_4 = 1'h0; // @[CSR.scala:1141:42] wire _reg_mstatus_v_T_5 = 1'h0; // @[CSR.scala:1141:82] wire _reg_mstatus_v_T_6 = 1'h0; // @[CSR.scala:1141:62] wire _reg_mstatus_mpp_T = 1'h0; // @[CSR.scala:1647:35] wire _reg_mstatus_mpp_T_1 = 1'h0; // @[CSR.scala:1647:29] wire _reg_mstatus_v_T_7 = 1'h0; // @[CSR.scala:1150:42] wire _reg_mstatus_v_T_9 = 1'h0; // @[CSR.scala:1150:61] wire _io_rw_rdata_T = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_30 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_31 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_32 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_33 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_34 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_35 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_36 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_37 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_38 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_39 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_40 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_41 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_42 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_43 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_44 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_45 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_46 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_48 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_49 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_50 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_51 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_52 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_54 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_55 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_56 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_57 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_58 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_59 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_60 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_61 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_62 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_63 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_64 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_66 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_67 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_68 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_69 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_70 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_71 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_72 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_73 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_74 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_75 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_76 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_77 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_78 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_79 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_80 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_81 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_82 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_83 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_84 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_85 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_86 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_87 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_88 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_89 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_90 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_91 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_92 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_93 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_94 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_95 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_96 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_97 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_98 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_99 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_100 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_101 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_102 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_103 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_104 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_105 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_106 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_107 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_108 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_109 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_110 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_111 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_112 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_113 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_114 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_115 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_116 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_156 = 1'h0; // @[Mux.scala:30:73] wire new_mip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:1271:59] wire _reg_bp_0_control_chain_T_1 = 1'h0; // @[CSR.scala:1481:49] wire _reg_bp_0_control_chain_T_2 = 1'h0; // @[CSR.scala:1481:46] wire _reg_bp_0_control_chain_T_3 = 1'h0; // @[CSR.scala:1481:88] wire _reg_bp_0_control_chain_T_5 = 1'h0; // @[CSR.scala:1481:75] wire _reg_bp_1_control_chain_T_1 = 1'h0; // @[CSR.scala:1481:49] wire _reg_bp_1_control_chain_T_2 = 1'h0; // @[CSR.scala:1481:46] wire _reg_bp_1_control_chain_T_3 = 1'h0; // @[CSR.scala:1481:88] wire _reg_bp_1_control_chain_T_5 = 1'h0; // @[CSR.scala:1481:75] wire _reg_vconfig_vtype_WIRE_vill = 1'h0; // @[CSR.scala:1557:44] wire _reg_vconfig_vtype_WIRE_vma = 1'h0; // @[CSR.scala:1557:44] wire _reg_vconfig_vtype_WIRE_vta = 1'h0; // @[CSR.scala:1557:44] wire _reg_vconfig_vtype_WIRE_vlmul_sign = 1'h0; // @[CSR.scala:1557:44] wire _reg_bp_1_WIRE_control_dmode = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_action = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_chain = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_m = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_h = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_s = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_u = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_x = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_w = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_r = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_mselect = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_pad1 = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_sselect = 1'h0; // @[CSR.scala:1613:23] wire [7:0] io_status_zero1 = 8'h0; // @[CSR.scala:377:7] wire [7:0] io_gstatus_zero1_0 = 8'h0; // @[CSR.scala:377:7] wire [7:0] _reset_mstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:391:47] wire [7:0] reset_mstatus_zero1 = 8'h0; // @[CSR.scala:391:34] wire [7:0] lo_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] hi_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] lo_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] hi_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] sie_mask_lo = 8'h0; // @[CSR.scala:750:59] wire [7:0] _read_sstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:755:48] wire [7:0] read_sstatus_zero1 = 8'h0; // @[CSR.scala:755:35] wire [1:0] io_status_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero3 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero2 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_dprv_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_prv_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_sxl_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_fs_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_mpp_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_bp_0_control_zero = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] _reset_mstatus_WIRE_dprv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_prv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_sxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_uxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_xs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_fs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_mpp = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_vs = 2'h0; // @[CSR.scala:391:47] wire [1:0] reset_mstatus_dprv = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_sxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_uxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_xs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_fs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_vs = 2'h0; // @[CSR.scala:391:34] wire [1:0] _reset_dcsr_WIRE_xdebugver = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero4 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero1 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_prv = 2'h0; // @[CSR.scala:400:44] wire [1:0] reset_dcsr_zero4 = 2'h0; // @[CSR.scala:400:31] wire [1:0] reset_dcsr_zero1 = 2'h0; // @[CSR.scala:400:31] wire [1:0] hi_hi_lo = 2'h0; // @[CSR.scala:431:10] wire [1:0] hi_hi_hi = 2'h0; // @[CSR.scala:431:10] wire [1:0] lo_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_lo_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] _reset_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:516:48] wire [1:0] _reg_menvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:525:41] wire [1:0] _reg_senvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:526:41] wire [1:0] _reg_henvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:527:41] wire [1:0] _reg_hstatus_WIRE_vsxl = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero3 = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero2 = 2'h0; // @[CSR.scala:552:41] wire [1:0] read_hvip_lo_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_lo_hi_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_lo = 2'h0; // @[CSR.scala:555:27] wire [1:0] pmp_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] debug_csrs_lo_hi_hi = 2'h0; // @[CSR.scala:670:27] wire [1:0] _read_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:675:44] wire [1:0] hi_hi_4 = 2'h0; // @[CSR.scala:742:49] wire [1:0] sie_mask_lo_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] _read_sstatus_WIRE_dprv = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_prv = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_sxl = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_uxl = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_xs = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_fs = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_mpp = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_vs = 2'h0; // @[CSR.scala:755:48] wire [1:0] read_sstatus_dprv = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_prv = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_sxl = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_xs = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_mpp = 2'h0; // @[CSR.scala:755:35] wire [1:0] lo_lo_lo_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] lo_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_lo_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_hi_6 = 2'h0; // @[CSR.scala:780:49] wire [1:0] read_pmp_15_cfg_res = 2'h0; // @[CSR.scala:787:59] wire [1:0] read_pmp_15_cfg_a = 2'h0; // @[CSR.scala:787:59] wire [1:0] lo_hi_16 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_17 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_18 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_19 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_20 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_21 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_22 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_23 = 2'h0; // @[package.scala:45:36] wire [1:0] decoded_orMatrixOutputs_lo_lo = 2'h0; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_lo_lo_1 = 2'h0; // @[pla.scala:102:36] wire [1:0] nmiTVec = 2'h0; // @[CSR.scala:993:62] wire [1:0] new_mip_lo_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_lo_hi_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_hi_lo = 2'h0; // @[CSR.scala:1271:59] wire [1:0] newBPC_lo_lo_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_lo_hi_lo_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_lo_hi_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_hi_lo_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] _reg_vconfig_vtype_WIRE_vlmul_mag = 2'h0; // @[CSR.scala:1557:44] wire [1:0] _reg_bp_1_WIRE_control_zero = 2'h0; // @[CSR.scala:1613:23] wire [1:0] _reg_bp_1_WIRE_control_tmatch = 2'h0; // @[CSR.scala:1613:23] wire [29:0] io_hstatus_zero6 = 30'h0; // @[CSR.scala:377:7] wire [29:0] _reg_hstatus_WIRE_zero6 = 30'h0; // @[CSR.scala:552:41] wire [29:0] read_pmp_15_addr = 30'h0; // @[CSR.scala:787:59] wire [29:0] _io_rw_rdata_T_144 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_145 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_146 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_147 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_148 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_149 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_150 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_151 = 30'h0; // @[Mux.scala:30:73] wire [8:0] io_hstatus_zero5 = 9'h0; // @[CSR.scala:377:7] wire [8:0] _reg_hstatus_WIRE_zero5 = 9'h0; // @[CSR.scala:552:41] wire [8:0] hi_lo_lo_lo = 9'h0; // @[CSR.scala:768:51] wire [5:0] io_hstatus_vgein = 6'h0; // @[CSR.scala:377:7] wire [5:0] _reg_hstatus_WIRE_vgein = 6'h0; // @[CSR.scala:552:41] wire [5:0] hi_lo_hi_4 = 6'h0; // @[CSR.scala:768:51] wire [5:0] newBPC_hi_lo_1 = 6'h0; // @[CSR.scala:1477:67] wire [5:0] _reg_bp_1_WIRE_control_maskmax = 6'h0; // @[CSR.scala:1613:23] wire [4:0] io_hstatus_zero1 = 5'h0; // @[CSR.scala:377:7] wire [4:0] _reg_hstatus_WIRE_zero1 = 5'h0; // @[CSR.scala:552:41] wire [4:0] hi_19 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_20 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_21 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_22 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_23 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_24 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_25 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_26 = 5'h0; // @[package.scala:45:36] wire [4:0] newBPC_hi_hi_hi_1 = 5'h0; // @[CSR.scala:1477:67] wire [1:0] io_gstatus_vs = 2'h3; // @[CSR.scala:377:7] wire [1:0] reset_mstatus_prv = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_mpp = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_dcsr_prv = 2'h3; // @[CSR.scala:400:31] wire [1:0] reset_mnstatus_mpp = 2'h3; // @[CSR.scala:516:35] wire [1:0] read_mnstatus_mpp = 2'h3; // @[CSR.scala:675:31] wire [15:0] io_ptbr_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] io_hgatp_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] io_vsatp_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] hs_delegable_interrupts = 16'h0; // @[CSR.scala:479:12] wire [15:0] mideleg_always_hs = 16'h0; // @[CSR.scala:479:27] wire [15:0] read_hvip = 16'h0; // @[CSR.scala:555:34] wire [15:0] read_hip = 16'h0; // @[CSR.scala:611:27] wire [15:0] lo_lo_8 = 16'h0; // @[package.scala:45:27] wire [15:0] lo_hi_24 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_lo_8 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_hi_24 = 16'h0; // @[package.scala:45:27] wire [15:0] _en_T = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_12 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_2 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_3 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_24 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_4 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_36 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_6 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_7 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_48 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_8 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_60 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_10 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_11 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_72 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_12 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_78 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_13 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_84 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_14 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_90 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_15 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_17 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_21 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_23 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_25 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_26 = 16'h0; // @[CSR.scala:1109:45] wire [3:0] io_hgatp_mode = 4'h0; // @[CSR.scala:377:7] wire [3:0] io_vsatp_mode = 4'h0; // @[CSR.scala:377:7] wire [3:0] hi_hi = 4'h0; // @[CSR.scala:431:10] wire [3:0] hi_hi_1 = 4'h0; // @[CSR.scala:431:50] wire [3:0] lo_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] lo_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] sie_mask_lo_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_lo_hi = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] hi_hi_lo_hi = 4'h0; // @[CSR.scala:768:51] wire [3:0] newBPC_lo_hi_1 = 4'h0; // @[CSR.scala:1477:67] wire [3:0] newBPC_hi_lo_lo_1 = 4'h0; // @[CSR.scala:1477:67] wire [3:0] _reg_bp_1_WIRE_control_ttype = 4'h0; // @[CSR.scala:1613:23] wire [43:0] io_hgatp_ppn = 44'h0; // @[CSR.scala:377:7] wire [43:0] io_vsatp_ppn = 44'h0; // @[CSR.scala:377:7] wire [3:0] io_bp_0_control_ttype = 4'h2; // @[CSR.scala:377:7] wire [3:0] lo_lo_1 = 4'h2; // @[CSR.scala:431:50] wire [3:0] lo_hi_1 = 4'h2; // @[CSR.scala:431:50] wire [3:0] hi_lo_1 = 4'h2; // @[CSR.scala:431:50] wire [5:0] io_bp_0_control_maskmax = 6'h4; // @[CSR.scala:377:7] wire [39:0] io_bp_0_control_reserved = 40'h0; // @[CSR.scala:377:7] wire [39:0] _reg_bp_1_WIRE_control_reserved = 40'h0; // @[CSR.scala:1613:23] wire [2:0] _reset_dcsr_WIRE_cause = 3'h0; // @[CSR.scala:400:44] wire [2:0] reset_dcsr_cause = 3'h0; // @[CSR.scala:400:31] wire [2:0] _reset_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:516:48] wire [2:0] reset_mnstatus_zero3 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero2 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero1 = 3'h0; // @[CSR.scala:516:35] wire [2:0] _reg_menvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:525:41] wire [2:0] _reg_senvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:526:41] wire [2:0] _reg_henvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:527:41] wire [2:0] _read_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:675:44] wire [2:0] read_mnstatus_zero3 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero2 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero1 = 3'h0; // @[CSR.scala:675:31] wire [2:0] lo_hi_4 = 3'h0; // @[CSR.scala:742:49] wire [2:0] hi_lo_hi_lo = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_hi_hi_hi_4 = 3'h0; // @[CSR.scala:768:51] wire [2:0] lo_hi_6 = 3'h0; // @[CSR.scala:780:49] wire [2:0] lo_16 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_16 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_17 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_17 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_18 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_18 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_19 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_19 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_20 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_20 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_21 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_21 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_22 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_22 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_23 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_23 = 3'h0; // @[package.scala:45:36] wire [2:0] newBPC_lo_lo_1 = 3'h0; // @[CSR.scala:1477:67] wire [2:0] _reg_vconfig_vtype_WIRE_vsew = 3'h0; // @[CSR.scala:1557:44] wire [54:0] hi_lo_4 = 55'h0; // @[CSR.scala:742:49] wire [54:0] hi_lo_6 = 55'h0; // @[CSR.scala:780:49] wire [54:0] _reg_vconfig_vtype_WIRE_reserved = 55'h0; // @[CSR.scala:1557:44] wire [63:0] io_customCSRs_0_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_2_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_3_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] read_hideleg = 64'h0; // @[CSR.scala:541:14] wire [63:0] read_hedeleg = 64'h0; // @[CSR.scala:545:14] wire [63:0] read_hie = 64'h0; // @[CSR.scala:556:26] wire [63:0] read_vstvec = 64'h0; // @[package.scala:132:15] wire [63:0] _vs_interrupts_T_6 = 64'h0; // @[CSR.scala:622:153] wire [63:0] vs_interrupts = 64'h0; // @[CSR.scala:622:26] wire [63:0] _io_rw_rdata_T_135 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _newBPC_T_24 = 64'h0; // @[CSR.scala:1477:67] wire [63:0] _newBPC_T_26 = 64'h0; // @[CSR.scala:1643:9] wire [63:0] _reg_custom_1_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_2_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_3_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_0_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_1_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_2_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_3_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [56:0] hi_6 = 57'h0; // @[CSR.scala:742:49] wire [56:0] hi_9 = 57'h0; // @[CSR.scala:780:49] wire [56:0] newBPC_hi_1 = 57'h0; // @[CSR.scala:1477:67] wire [50:0] newBPC_hi_hi_1 = 51'h0; // @[CSR.scala:1477:67] wire [45:0] newBPC_hi_hi_lo_1 = 46'h0; // @[CSR.scala:1477:67] wire [6:0] newBPC_lo_1 = 7'h0; // @[CSR.scala:1477:67] wire [45:0] read_mapping_hi_hi_lo = 46'h40000000000; // @[CSR.scala:655:48] wire [45:0] newBPC_hi_hi_lo = 46'h40000000000; // @[CSR.scala:1477:67] wire [3:0] _which_T_64 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_65 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_66 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_67 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_68 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_69 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_70 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_71 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_72 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_73 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_74 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_75 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_76 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_77 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_78 = 4'h4; // @[Mux.scala:50:70] wire [3:0] debug_csrs_hi_hi_hi = 4'h4; // @[CSR.scala:670:27] wire [2:0] read_mstatus_hi_lo_hi_lo = 3'h2; // @[CSR.scala:649:32] wire [47:0] io_bp_0_textra_pad2_0 = 48'h0; // @[CSR.scala:377:7] wire [47:0] _reg_bp_1_WIRE_textra_pad2 = 48'h0; // @[CSR.scala:1613:23] wire [38:0] _read_stvec_T_2 = 39'h0; // @[package.scala:174:46] wire [38:0] _reg_bp_1_WIRE_address = 39'h0; // @[CSR.scala:1613:23] wire [1:0] io_status_sxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_status_uxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_hstatus_vsxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_gstatus_uxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] lo_lo_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_lo_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] lo_hi_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] hi_lo_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] read_sstatus_uxl = 2'h2; // @[CSR.scala:755:35] wire [11:0] io_vector_set_vstart_bits = 12'h0; // @[CSR.scala:377:7] wire [11:0] _reset_dcsr_WIRE_zero3 = 12'h0; // @[CSR.scala:400:44] wire [11:0] reset_dcsr_zero3 = 12'h0; // @[CSR.scala:400:31] wire [63:0] _s_interrupts_T_7 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:621:168] wire [63:0] _reg_custom_1_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_2_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_3_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_1_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_2_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_3_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_0_T_1 = 64'hFFFFFFFFFFFFFDF7; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_0_T_5 = 64'hFFFFFFFFFFFFFDF7; // @[CSR.scala:1531:41] wire [63:0] _reg_mcountinhibit_T = 64'hFFFFFFFFFFFFFFFD; // @[CSR.scala:1306:78] wire [63:0] _reg_misa_T_6 = 64'hFFFFFFFFFFDFEFD2; // @[CSR.scala:1263:75] wire [15:0] _sie_mask_T = 16'h1000; // @[CSR.scala:750:59] wire [15:0] _sie_mask_T_1 = 16'h1000; // @[CSR.scala:750:46] wire [15:0] _delegable_T_27 = 16'h1000; // @[CSR.scala:1109:45] wire [15:0] _en_T_18 = 16'h8; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_19 = 16'h8; // @[CSR.scala:1109:45] wire [63:0] _en_T_94 = 64'h800000000000000F; // @[CSR.scala:1096:120] wire [63:0] _en_T_88 = 64'h800000000000000E; // @[CSR.scala:1096:120] wire [63:0] _en_T_82 = 64'h800000000000000D; // @[CSR.scala:1096:120] wire [63:0] _en_T_76 = 64'h800000000000000C; // @[CSR.scala:1096:120] wire [63:0] _en_T_70 = 64'h800000000000000B; // @[CSR.scala:1096:120] wire [15:0] _en_T_66 = 16'h800; // @[CSR.scala:1096:49] wire [63:0] _en_T_64 = 64'h800000000000000A; // @[CSR.scala:1096:120] wire [15:0] _en_T_54 = 16'h200; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_9 = 16'h200; // @[CSR.scala:1097:43] wire [63:0] _en_T_58 = 64'h8000000000000009; // @[CSR.scala:1096:120] wire [63:0] _en_T_52 = 64'h8000000000000008; // @[CSR.scala:1096:120] wire [63:0] _en_T_46 = 64'h8000000000000007; // @[CSR.scala:1096:120] wire [15:0] _en_T_42 = 16'h80; // @[CSR.scala:1096:49] wire [63:0] _en_T_40 = 64'h8000000000000006; // @[CSR.scala:1096:120] wire [15:0] _en_T_30 = 16'h20; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_5 = 16'h20; // @[CSR.scala:1097:43] wire [63:0] _en_T_34 = 64'h8000000000000005; // @[CSR.scala:1096:120] wire [63:0] _en_T_28 = 64'h8000000000000004; // @[CSR.scala:1096:120] wire [63:0] _en_T_22 = 64'h8000000000000003; // @[CSR.scala:1096:120] wire [63:0] _en_T_16 = 64'h8000000000000002; // @[CSR.scala:1096:120] wire [15:0] _en_T_6 = 16'h2; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_1 = 16'h2; // @[CSR.scala:1097:43] wire [63:0] _en_T_10 = 64'h8000000000000001; // @[CSR.scala:1096:120] wire [63:0] _interruptCause_T_2 = 64'h8000000000000000; // @[CSR.scala:625:39] wire [63:0] _en_T_4 = 64'h8000000000000000; // @[CSR.scala:1096:120] wire [64:0] _interruptCause_T_1 = 65'h8000000000000000; // @[CSR.scala:625:39] wire [64:0] _en_T_3 = 65'h8000000000000000; // @[CSR.scala:1096:120] wire [9:0] _io_decode_0_write_flush_addr_m_T = 10'h300; // @[CSR.scala:932:36] wire [31:0] io_gstatus_isa_0 = 32'h0; // @[CSR.scala:377:7] wire [31:0] _reset_mstatus_WIRE_isa = 32'h0; // @[CSR.scala:391:47] wire [31:0] reset_mstatus_isa = 32'h0; // @[CSR.scala:391:34] wire [31:0] read_hcounteren = 32'h0; // @[CSR.scala:550:14] wire [31:0] _read_mtvec_T_2 = 32'h0; // @[package.scala:174:46] wire [31:0] _read_sstatus_WIRE_isa = 32'h0; // @[CSR.scala:755:48] wire [31:0] read_sstatus_isa = 32'h0; // @[CSR.scala:755:35] wire [31:0] read_pmp_15_mask = 32'h0; // @[CSR.scala:787:59] wire [31:0] lo_24 = 32'h0; // @[package.scala:45:27] wire [31:0] hi_27 = 32'h0; // @[package.scala:45:27] wire [36:0] hi_hi_hi_4 = 37'h0; // @[CSR.scala:768:51] wire [33:0] hi_hi_hi_lo = 34'h0; // @[CSR.scala:768:51] wire [17:0] hi_lo_5 = 18'h800; // @[CSR.scala:768:51] wire [11:0] hi_lo_lo_4 = 12'h800; // @[CSR.scala:768:51] wire [2:0] _which_T_63 = 3'h4; // @[Mux.scala:50:70] wire [2:0] read_mstatus_hi_lo_lo_hi = 3'h4; // @[CSR.scala:649:32] wire [2:0] hi_lo_lo_hi = 3'h4; // @[CSR.scala:768:51] wire [15:0] _sie_mask_T_2 = 16'hEFFF; // @[CSR.scala:750:20] wire [7:0] sie_mask_hi = 8'h10; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_hi = 4'h1; // @[CSR.scala:750:59] wire [1:0] reset_dcsr_xdebugver = 2'h1; // @[CSR.scala:400:31] wire [1:0] sie_mask_hi_hi_lo = 2'h1; // @[CSR.scala:750:59] wire [53:0] _reg_menvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:525:41] wire [53:0] _reg_senvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:526:41] wire [53:0] _reg_henvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:527:41] wire [15:0] delegable_interrupts = 16'h222; // @[CSR.scala:431:50] wire [7:0] hi_1 = 8'h2; // @[CSR.scala:431:50] wire [7:0] lo_1 = 8'h22; // @[CSR.scala:431:50] wire [15:0] supported_interrupts = 16'hAAA; // @[CSR.scala:431:17] wire [7:0] hi = 8'hA; // @[CSR.scala:431:10] wire [3:0] lo_lo = 4'hA; // @[CSR.scala:431:10] wire [3:0] lo_hi = 4'hA; // @[CSR.scala:431:10] wire [3:0] hi_lo = 4'hA; // @[CSR.scala:431:10] wire [7:0] lo = 8'hAA; // @[CSR.scala:431:10] wire [15:0] _delegable_T_28 = 16'h2000; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_24 = 16'h100; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_22 = 16'h40; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_20 = 16'h10; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_18 = 16'h4; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_16 = 16'h1; // @[CSR.scala:1109:45] wire [64:0] _en_T_93 = 65'h800000000000000F; // @[CSR.scala:1096:120] wire [64:0] _en_T_87 = 65'h800000000000000E; // @[CSR.scala:1096:120] wire [64:0] _en_T_81 = 65'h800000000000000D; // @[CSR.scala:1096:120] wire [64:0] _en_T_75 = 65'h800000000000000C; // @[CSR.scala:1096:120] wire [64:0] _en_T_69 = 65'h800000000000000B; // @[CSR.scala:1096:120] wire [64:0] _en_T_63 = 65'h800000000000000A; // @[CSR.scala:1096:120] wire [64:0] _en_T_57 = 65'h8000000000000009; // @[CSR.scala:1096:120] wire [64:0] _en_T_51 = 65'h8000000000000008; // @[CSR.scala:1096:120] wire [64:0] _en_T_45 = 65'h8000000000000007; // @[CSR.scala:1096:120] wire [64:0] _en_T_39 = 65'h8000000000000006; // @[CSR.scala:1096:120] wire [64:0] _en_T_33 = 65'h8000000000000005; // @[CSR.scala:1096:120] wire [64:0] _en_T_27 = 65'h8000000000000004; // @[CSR.scala:1096:120] wire [64:0] _en_T_21 = 65'h8000000000000003; // @[CSR.scala:1096:120] wire [64:0] _en_T_15 = 65'h8000000000000002; // @[CSR.scala:1096:120] wire [64:0] _en_T_9 = 65'h8000000000000001; // @[CSR.scala:1096:120] wire [62:0] _interruptCause_T = 63'h0; // @[CSR.scala:625:50] wire [15:0] _delegable_T_29 = 16'h8000; // @[CSR.scala:1109:45] wire [39:0] _io_evec_T_15 = 40'hFFFFFFFFFF; // @[CSR.scala:1665:28] wire [48:0] read_mapping_hi_1 = 49'h0; // @[CSR.scala:657:47] wire mip_mtip = io_interrupts_mtip_0; // @[CSR.scala:377:7, :600:24] wire mip_msip = io_interrupts_msip_0; // @[CSR.scala:377:7, :600:24] wire mip_meip = io_interrupts_meip_0; // @[CSR.scala:377:7, :600:24] wire [63:0] _io_rw_rdata_WIRE; // @[Mux.scala:30:73] wire [63:0] _newBPC_T_27 = io_rw_wdata_0; // @[CSR.scala:377:7, :1643:30] wire [31:0] decoded_plaInput_1 = io_decode_0_inst_0; // @[pla.scala:77:22] wire _io_decode_0_fp_illegal_T_6; // @[CSR.scala:915:91] wire _io_decode_0_vector_illegal_T_6; // @[CSR.scala:916:95] wire _io_decode_0_fp_csr_T; // @[Decode.scala:55:116] wire _io_decode_0_vector_csr_T; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_20; // @[CSR.scala:928:68] wire _io_decode_0_write_illegal_T_1; // @[CSR.scala:930:41] wire _io_decode_0_write_flush_T_3; // @[CSR.scala:933:7] wire _io_decode_0_system_illegal_T_25; // @[CSR.scala:940:44] wire _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:943:66] wire _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:949:52] wire _io_csr_stall_T; // @[CSR.scala:1161:27] wire _io_eret_T_1; // @[CSR.scala:1000:38] wire _io_singleStep_T_1; // @[CSR.scala:1001:34] wire [1:0] _io_status_dprv_T_2; // @[CSR.scala:1008:24] wire _io_status_dv_T_3; // @[CSR.scala:1009:33] wire _io_status_sd_T_4; // @[CSR.scala:1003:58] wire read_sstatus_sd = io_status_sd_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_mxr = io_status_mxr_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_sum = io_status_sum_0; // @[CSR.scala:377:7, :755:35] wire [1:0] read_sstatus_fs = io_status_fs_0; // @[CSR.scala:377:7, :755:35] wire [1:0] read_sstatus_vs = io_status_vs_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_spp = io_status_spp_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_spie = io_status_spie_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_sie = io_status_sie_0; // @[CSR.scala:377:7, :755:35] wire _io_trace_0_valid_T = io_retire_0; // @[CSR.scala:377:7, :1621:26] wire [39:0] io_trace_0_iaddr_0 = io_pc_0; // @[CSR.scala:377:7] wire [39:0] io_trace_0_tval_0 = io_tval_0; // @[CSR.scala:377:7] wire [63:0] value_1; // @[Counters.scala:55:30] wire _io_interrupt_T_5; // @[CSR.scala:626:73] wire [63:0] interruptCause; // @[CSR.scala:625:63] wire pmp_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_cfg_a; // @[PMP.scala:24:19] wire pmp_cfg_x; // @[PMP.scala:24:19] wire pmp_cfg_w; // @[PMP.scala:24:19] wire pmp_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_addr; // @[PMP.scala:24:19] wire [31:0] pmp_mask; // @[PMP.scala:24:19] wire pmp_1_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_a; // @[PMP.scala:24:19] wire pmp_1_cfg_x; // @[PMP.scala:24:19] wire pmp_1_cfg_w; // @[PMP.scala:24:19] wire pmp_1_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_1_addr; // @[PMP.scala:24:19] wire [31:0] pmp_1_mask; // @[PMP.scala:24:19] wire pmp_2_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_a; // @[PMP.scala:24:19] wire pmp_2_cfg_x; // @[PMP.scala:24:19] wire pmp_2_cfg_w; // @[PMP.scala:24:19] wire pmp_2_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_2_addr; // @[PMP.scala:24:19] wire [31:0] pmp_2_mask; // @[PMP.scala:24:19] wire pmp_3_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_a; // @[PMP.scala:24:19] wire pmp_3_cfg_x; // @[PMP.scala:24:19] wire pmp_3_cfg_w; // @[PMP.scala:24:19] wire pmp_3_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_3_addr; // @[PMP.scala:24:19] wire [31:0] pmp_3_mask; // @[PMP.scala:24:19] wire pmp_4_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_a; // @[PMP.scala:24:19] wire pmp_4_cfg_x; // @[PMP.scala:24:19] wire pmp_4_cfg_w; // @[PMP.scala:24:19] wire pmp_4_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_4_addr; // @[PMP.scala:24:19] wire [31:0] pmp_4_mask; // @[PMP.scala:24:19] wire pmp_5_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_a; // @[PMP.scala:24:19] wire pmp_5_cfg_x; // @[PMP.scala:24:19] wire pmp_5_cfg_w; // @[PMP.scala:24:19] wire pmp_5_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_5_addr; // @[PMP.scala:24:19] wire [31:0] pmp_5_mask; // @[PMP.scala:24:19] wire pmp_6_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_a; // @[PMP.scala:24:19] wire pmp_6_cfg_x; // @[PMP.scala:24:19] wire pmp_6_cfg_w; // @[PMP.scala:24:19] wire pmp_6_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_6_addr; // @[PMP.scala:24:19] wire [31:0] pmp_6_mask; // @[PMP.scala:24:19] wire pmp_7_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_a; // @[PMP.scala:24:19] wire pmp_7_cfg_x; // @[PMP.scala:24:19] wire pmp_7_cfg_w; // @[PMP.scala:24:19] wire pmp_7_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_7_addr; // @[PMP.scala:24:19] wire [31:0] pmp_7_mask; // @[PMP.scala:24:19] wire [31:0] _io_csrw_counter_T_11; // @[CSR.scala:1223:25] wire _io_inhibit_cycle_T; // @[CSR.scala:591:40] wire [31:0] io_trace_0_insn_0 = io_inst_0_0; // @[CSR.scala:377:7] wire _io_trace_0_valid_T_1; // @[CSR.scala:1621:32] wire [2:0] _io_trace_0_priv_T; // @[CSR.scala:1624:18] wire _io_trace_0_exception_T_1; // @[CSR.scala:1620:37] wire _io_trace_0_interrupt_T; // @[CSR.scala:1626:25] wire [63:0] cause; // @[CSR.scala:959:8] wire _io_fiom_T_6; // @[CSR.scala:631:113] wire reg_custom_read; // @[CSR.scala:799:36] wire [63:0] wdata; // @[CSR.scala:1643:39] wire reg_custom_read_1; // @[CSR.scala:799:36] wire reg_custom_read_2; // @[CSR.scala:799:36] wire reg_custom_read_3; // @[CSR.scala:799:36] wire [63:0] io_rw_rdata_0; // @[CSR.scala:377:7] wire io_decode_0_fp_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_vector_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_fp_csr_0; // @[CSR.scala:377:7] wire io_decode_0_vector_csr_0; // @[CSR.scala:377:7] wire io_decode_0_read_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_flush_0; // @[CSR.scala:377:7] wire io_decode_0_system_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_access_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_system_illegal_0; // @[CSR.scala:377:7] wire io_status_debug_0; // @[CSR.scala:377:7] wire io_status_cease_0; // @[CSR.scala:377:7] wire io_status_wfi_0; // @[CSR.scala:377:7] wire [31:0] io_status_isa_0; // @[CSR.scala:377:7] wire [1:0] io_status_dprv_0; // @[CSR.scala:377:7] wire io_status_dv_0; // @[CSR.scala:377:7] wire [1:0] io_status_prv_0; // @[CSR.scala:377:7] wire io_status_v_0; // @[CSR.scala:377:7] wire io_status_mpv_0; // @[CSR.scala:377:7] wire io_status_gva_0; // @[CSR.scala:377:7] wire io_status_tsr_0; // @[CSR.scala:377:7] wire io_status_tw_0; // @[CSR.scala:377:7] wire io_status_tvm_0; // @[CSR.scala:377:7] wire io_status_mprv_0; // @[CSR.scala:377:7] wire [1:0] io_status_mpp_0; // @[CSR.scala:377:7] wire io_status_mpie_0; // @[CSR.scala:377:7] wire io_status_mie_0; // @[CSR.scala:377:7] wire io_hstatus_spvp_0; // @[CSR.scala:377:7] wire io_hstatus_spv_0; // @[CSR.scala:377:7] wire io_hstatus_gva_0; // @[CSR.scala:377:7] wire io_gstatus_spp_0; // @[CSR.scala:377:7] wire io_gstatus_spie_0; // @[CSR.scala:377:7] wire io_gstatus_sie_0; // @[CSR.scala:377:7] wire [3:0] io_ptbr_mode_0; // @[CSR.scala:377:7] wire [43:0] io_ptbr_ppn_0; // @[CSR.scala:377:7] wire io_bp_0_control_dmode_0; // @[CSR.scala:377:7] wire io_bp_0_control_action_0; // @[CSR.scala:377:7] wire [1:0] io_bp_0_control_tmatch_0; // @[CSR.scala:377:7] wire io_bp_0_control_m_0; // @[CSR.scala:377:7] wire io_bp_0_control_s_0; // @[CSR.scala:377:7] wire io_bp_0_control_u_0; // @[CSR.scala:377:7] wire io_bp_0_control_x_0; // @[CSR.scala:377:7] wire io_bp_0_control_w_0; // @[CSR.scala:377:7] wire io_bp_0_control_r_0; // @[CSR.scala:377:7] wire [38:0] io_bp_0_address_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_0_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_0_mask_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_1_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_1_mask_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_2_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_2_mask_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_3_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_3_mask_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_4_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_4_mask_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_5_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_5_mask_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_6_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_6_mask_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_7_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_7_mask_0; // @[CSR.scala:377:7] wire io_trace_0_valid_0; // @[CSR.scala:377:7] wire [2:0] io_trace_0_priv_0; // @[CSR.scala:377:7] wire io_trace_0_exception_0; // @[CSR.scala:377:7] wire io_trace_0_interrupt_0; // @[CSR.scala:377:7] wire [63:0] io_trace_0_cause_0; // @[CSR.scala:377:7] wire io_vector_vconfig_vtype_vill_0; // @[CSR.scala:377:7] wire [54:0] io_vector_vconfig_vtype_reserved_0; // @[CSR.scala:377:7] wire io_vector_vconfig_vtype_vma_0; // @[CSR.scala:377:7] wire io_vector_vconfig_vtype_vta_0; // @[CSR.scala:377:7] wire [2:0] io_vector_vconfig_vtype_vsew_0; // @[CSR.scala:377:7] wire io_vector_vconfig_vtype_vlmul_sign_0; // @[CSR.scala:377:7] wire [1:0] io_vector_vconfig_vtype_vlmul_mag_0; // @[CSR.scala:377:7] wire [12:0] io_vector_vconfig_vl_0; // @[CSR.scala:377:7] wire [11:0] io_vector_vstart_0; // @[CSR.scala:377:7] wire [1:0] io_vector_vxrm_0; // @[CSR.scala:377:7] wire io_customCSRs_0_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_0_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_0_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_0_value_0; // @[CSR.scala:377:7] wire io_customCSRs_1_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_1_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_value_0; // @[CSR.scala:377:7] wire io_customCSRs_2_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_2_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_2_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_2_value_0; // @[CSR.scala:377:7] wire io_customCSRs_3_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_3_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_3_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_3_value_0; // @[CSR.scala:377:7] wire io_csr_stall_0; // @[CSR.scala:377:7] wire io_eret_0; // @[CSR.scala:377:7] wire io_singleStep_0; // @[CSR.scala:377:7] wire [39:0] io_evec_0; // @[CSR.scala:377:7] wire [63:0] io_time_0; // @[CSR.scala:377:7] wire [2:0] io_fcsr_rm_0; // @[CSR.scala:377:7] wire io_interrupt_0; // @[CSR.scala:377:7] wire [63:0] io_interrupt_cause_0; // @[CSR.scala:377:7] wire [31:0] io_csrw_counter; // @[CSR.scala:377:7] wire io_inhibit_cycle_0; // @[CSR.scala:377:7] wire io_fiom; // @[CSR.scala:377:7] reg [1:0] reg_mstatus_prv; // @[CSR.scala:395:28] assign io_status_prv_0 = reg_mstatus_prv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_v; // @[CSR.scala:395:28] assign io_status_v_0 = reg_mstatus_v; // @[CSR.scala:377:7, :395:28] wire _io_decode_0_rocc_illegal_T_2 = reg_mstatus_v; // @[CSR.scala:395:28, :919:66] reg reg_mstatus_mpv; // @[CSR.scala:395:28] assign io_status_mpv_0 = reg_mstatus_mpv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_gva; // @[CSR.scala:395:28] assign io_status_gva_0 = reg_mstatus_gva; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tsr; // @[CSR.scala:395:28] assign io_status_tsr_0 = reg_mstatus_tsr; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tw; // @[CSR.scala:395:28] assign io_status_tw_0 = reg_mstatus_tw; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tvm; // @[CSR.scala:395:28] assign io_status_tvm_0 = reg_mstatus_tvm; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mxr; // @[CSR.scala:395:28] assign io_status_mxr_0 = reg_mstatus_mxr; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_sum; // @[CSR.scala:395:28] assign io_status_sum_0 = reg_mstatus_sum; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mprv; // @[CSR.scala:395:28] assign io_status_mprv_0 = reg_mstatus_mprv; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_fs; // @[CSR.scala:395:28] assign io_status_fs_0 = reg_mstatus_fs; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_mpp; // @[CSR.scala:395:28] assign io_status_mpp_0 = reg_mstatus_mpp; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_vs; // @[CSR.scala:395:28] assign io_status_vs_0 = reg_mstatus_vs; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_spp; // @[CSR.scala:395:28] assign io_status_spp_0 = reg_mstatus_spp; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mpie; // @[CSR.scala:395:28] assign io_status_mpie_0 = reg_mstatus_mpie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_spie; // @[CSR.scala:395:28] assign io_status_spie_0 = reg_mstatus_spie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mie; // @[CSR.scala:395:28] assign io_status_mie_0 = reg_mstatus_mie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_sie; // @[CSR.scala:395:28] assign io_status_sie_0 = reg_mstatus_sie; // @[CSR.scala:377:7, :395:28] wire [1:0] new_prv; // @[CSR.scala:397:28] wire _reg_mstatus_prv_T = new_prv == 2'h2; // @[CSR.scala:397:28, :1647:35] wire [1:0] _reg_mstatus_prv_T_1 = _reg_mstatus_prv_T ? 2'h0 : new_prv; // @[CSR.scala:397:28, :1647:{29,35}] reg reg_dcsr_ebreakm; // @[CSR.scala:403:25] reg reg_dcsr_ebreaks; // @[CSR.scala:403:25] reg reg_dcsr_ebreaku; // @[CSR.scala:403:25] reg [2:0] reg_dcsr_cause; // @[CSR.scala:403:25] reg reg_dcsr_v; // @[CSR.scala:403:25] reg reg_dcsr_step; // @[CSR.scala:403:25] reg [1:0] reg_dcsr_prv; // @[CSR.scala:403:25] reg reg_debug; // @[CSR.scala:482:26] assign io_status_debug_0 = reg_debug; // @[CSR.scala:377:7, :482:26] reg [39:0] reg_dpc; // @[CSR.scala:483:20] reg [63:0] reg_dscratch0; // @[CSR.scala:484:26] reg reg_singleStepped; // @[CSR.scala:486:30] reg reg_bp_0_control_dmode; // @[CSR.scala:492:19] assign io_bp_0_control_dmode_0 = reg_bp_0_control_dmode; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_action; // @[CSR.scala:492:19] assign io_bp_0_control_action_0 = reg_bp_0_control_action; // @[CSR.scala:377:7, :492:19] reg [1:0] reg_bp_0_control_tmatch; // @[CSR.scala:492:19] assign io_bp_0_control_tmatch_0 = reg_bp_0_control_tmatch; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_m; // @[CSR.scala:492:19] assign io_bp_0_control_m_0 = reg_bp_0_control_m; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_s; // @[CSR.scala:492:19] assign io_bp_0_control_s_0 = reg_bp_0_control_s; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_u; // @[CSR.scala:492:19] assign io_bp_0_control_u_0 = reg_bp_0_control_u; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_x; // @[CSR.scala:492:19] assign io_bp_0_control_x_0 = reg_bp_0_control_x; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_w; // @[CSR.scala:492:19] assign io_bp_0_control_w_0 = reg_bp_0_control_w; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_r; // @[CSR.scala:492:19] assign io_bp_0_control_r_0 = reg_bp_0_control_r; // @[CSR.scala:377:7, :492:19] reg [38:0] reg_bp_0_address; // @[CSR.scala:492:19] assign io_bp_0_address_0 = reg_bp_0_address; // @[CSR.scala:377:7, :492:19] reg reg_pmp_0_cfg_l; // @[CSR.scala:493:20] assign pmp_cfg_l = reg_pmp_0_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala:493:20] assign pmp_cfg_a = reg_pmp_0_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_x; // @[CSR.scala:493:20] assign pmp_cfg_x = reg_pmp_0_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_w; // @[CSR.scala:493:20] assign pmp_cfg_w = reg_pmp_0_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_r; // @[CSR.scala:493:20] assign pmp_cfg_r = reg_pmp_0_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_0_addr; // @[CSR.scala:493:20] assign pmp_addr = reg_pmp_0_addr; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_l; // @[CSR.scala:493:20] assign pmp_1_cfg_l = reg_pmp_1_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala:493:20] assign pmp_1_cfg_a = reg_pmp_1_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_x; // @[CSR.scala:493:20] assign pmp_1_cfg_x = reg_pmp_1_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_w; // @[CSR.scala:493:20] assign pmp_1_cfg_w = reg_pmp_1_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_r; // @[CSR.scala:493:20] assign pmp_1_cfg_r = reg_pmp_1_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_1_addr; // @[CSR.scala:493:20] assign pmp_1_addr = reg_pmp_1_addr; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_l; // @[CSR.scala:493:20] assign pmp_2_cfg_l = reg_pmp_2_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala:493:20] assign pmp_2_cfg_a = reg_pmp_2_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_x; // @[CSR.scala:493:20] assign pmp_2_cfg_x = reg_pmp_2_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_w; // @[CSR.scala:493:20] assign pmp_2_cfg_w = reg_pmp_2_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_r; // @[CSR.scala:493:20] assign pmp_2_cfg_r = reg_pmp_2_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_2_addr; // @[CSR.scala:493:20] assign pmp_2_addr = reg_pmp_2_addr; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_l; // @[CSR.scala:493:20] assign pmp_3_cfg_l = reg_pmp_3_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala:493:20] assign pmp_3_cfg_a = reg_pmp_3_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_x; // @[CSR.scala:493:20] assign pmp_3_cfg_x = reg_pmp_3_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_w; // @[CSR.scala:493:20] assign pmp_3_cfg_w = reg_pmp_3_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_r; // @[CSR.scala:493:20] assign pmp_3_cfg_r = reg_pmp_3_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_3_addr; // @[CSR.scala:493:20] assign pmp_3_addr = reg_pmp_3_addr; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_l; // @[CSR.scala:493:20] assign pmp_4_cfg_l = reg_pmp_4_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala:493:20] assign pmp_4_cfg_a = reg_pmp_4_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_x; // @[CSR.scala:493:20] assign pmp_4_cfg_x = reg_pmp_4_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_w; // @[CSR.scala:493:20] assign pmp_4_cfg_w = reg_pmp_4_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_r; // @[CSR.scala:493:20] assign pmp_4_cfg_r = reg_pmp_4_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_4_addr; // @[CSR.scala:493:20] assign pmp_4_addr = reg_pmp_4_addr; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_l; // @[CSR.scala:493:20] assign pmp_5_cfg_l = reg_pmp_5_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala:493:20] assign pmp_5_cfg_a = reg_pmp_5_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_x; // @[CSR.scala:493:20] assign pmp_5_cfg_x = reg_pmp_5_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_w; // @[CSR.scala:493:20] assign pmp_5_cfg_w = reg_pmp_5_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_r; // @[CSR.scala:493:20] assign pmp_5_cfg_r = reg_pmp_5_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_5_addr; // @[CSR.scala:493:20] assign pmp_5_addr = reg_pmp_5_addr; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_l; // @[CSR.scala:493:20] assign pmp_6_cfg_l = reg_pmp_6_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala:493:20] assign pmp_6_cfg_a = reg_pmp_6_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_x; // @[CSR.scala:493:20] assign pmp_6_cfg_x = reg_pmp_6_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_w; // @[CSR.scala:493:20] assign pmp_6_cfg_w = reg_pmp_6_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_r; // @[CSR.scala:493:20] assign pmp_6_cfg_r = reg_pmp_6_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_6_addr; // @[CSR.scala:493:20] assign pmp_6_addr = reg_pmp_6_addr; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_l; // @[CSR.scala:493:20] assign pmp_7_cfg_l = reg_pmp_7_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala:493:20] assign pmp_7_cfg_a = reg_pmp_7_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_x; // @[CSR.scala:493:20] assign pmp_7_cfg_x = reg_pmp_7_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_w; // @[CSR.scala:493:20] assign pmp_7_cfg_w = reg_pmp_7_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_r; // @[CSR.scala:493:20] assign pmp_7_cfg_r = reg_pmp_7_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_7_addr; // @[CSR.scala:493:20] assign pmp_7_addr = reg_pmp_7_addr; // @[PMP.scala:24:19] reg [63:0] reg_mie; // @[CSR.scala:495:20] reg [63:0] reg_mideleg; // @[CSR.scala:497:18] wire [63:0] read_mideleg = {54'h0, reg_mideleg[9:1] & 9'h111, 1'h0}; // @[CSR.scala:497:18, :498:{14,38,61}] reg [63:0] reg_medeleg; // @[CSR.scala:501:18] wire [63:0] read_medeleg = {48'h0, reg_medeleg[15:0] & 16'hB15D}; // @[CSR.scala:501:18, :502:{14,38}] reg reg_mip_seip; // @[CSR.scala:504:20] reg reg_mip_stip; // @[CSR.scala:504:20] wire mip_stip = reg_mip_stip; // @[CSR.scala:504:20, :600:24] reg reg_mip_ssip; // @[CSR.scala:504:20] wire mip_ssip = reg_mip_ssip; // @[CSR.scala:504:20, :600:24] reg [39:0] reg_mepc; // @[CSR.scala:505:21] reg [63:0] reg_mcause; // @[CSR.scala:506:27] reg [39:0] reg_mtval; // @[CSR.scala:507:22] reg [39:0] reg_mtval2; // @[CSR.scala:508:23] reg [63:0] reg_mscratch; // @[CSR.scala:509:25] reg [31:0] reg_mtvec; // @[CSR.scala:512:31] reg reg_menvcfg_fiom; // @[CSR.scala:525:28] reg reg_senvcfg_fiom; // @[CSR.scala:526:28] reg [31:0] reg_mcounteren; // @[CSR.scala:531:18] wire [31:0] read_mcounteren = {29'h0, reg_mcounteren[2:0]}; // @[CSR.scala:531:18, :532:{14,32}] reg [31:0] reg_scounteren; // @[CSR.scala:535:18] wire [31:0] read_scounteren = {29'h0, reg_scounteren[2:0]}; // @[CSR.scala:535:18, :536:{14,38}] reg reg_hstatus_spvp; // @[CSR.scala:552:28] assign io_hstatus_spvp_0 = reg_hstatus_spvp; // @[CSR.scala:377:7, :552:28] reg reg_hstatus_spv; // @[CSR.scala:552:28] assign io_hstatus_spv_0 = reg_hstatus_spv; // @[CSR.scala:377:7, :552:28] reg reg_hstatus_gva; // @[CSR.scala:552:28] assign io_hstatus_gva_0 = reg_hstatus_gva; // @[CSR.scala:377:7, :552:28] reg [39:0] reg_htval; // @[CSR.scala:554:22] wire [1:0] _GEN = {reg_mip_ssip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_lo_lo_lo; // @[CSR.scala:555:27] assign read_hvip_lo_lo_lo = _GEN; // @[CSR.scala:555:27] wire [1:0] new_mip_lo_lo_lo; // @[CSR.scala:1271:59] assign new_mip_lo_lo_lo = _GEN; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_lo_lo = {read_hvip_lo_lo_hi, read_hvip_lo_lo_lo}; // @[CSR.scala:555:27] wire [1:0] _GEN_0 = {reg_mip_stip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_lo_hi_lo; // @[CSR.scala:555:27] assign read_hvip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27] wire [1:0] new_mip_lo_hi_lo; // @[CSR.scala:1271:59] assign new_mip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_lo_hi = {read_hvip_lo_hi_hi, read_hvip_lo_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_lo = {read_hvip_lo_hi, read_hvip_lo_lo}; // @[CSR.scala:555:27] wire [1:0] _GEN_1 = {reg_mip_seip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_hi_lo_lo; // @[CSR.scala:555:27] assign read_hvip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27] wire [1:0] new_mip_hi_lo_lo; // @[CSR.scala:1271:59] assign new_mip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_hi_lo = {read_hvip_hi_lo_hi, read_hvip_hi_lo_lo}; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_hi = {read_hvip_hi_hi_hi_hi, 1'h0}; // @[CSR.scala:555:27] wire [3:0] read_hvip_hi_hi = {read_hvip_hi_hi_hi, read_hvip_hi_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_hi = {read_hvip_hi_hi, read_hvip_hi_lo}; // @[CSR.scala:555:27] wire [15:0] _read_hvip_T = {read_hvip_hi, read_hvip_lo}; // @[CSR.scala:555:27] reg reg_vsstatus_spp; // @[CSR.scala:562:25] assign io_gstatus_spp_0 = reg_vsstatus_spp; // @[CSR.scala:377:7, :562:25] reg reg_vsstatus_spie; // @[CSR.scala:562:25] assign io_gstatus_spie_0 = reg_vsstatus_spie; // @[CSR.scala:377:7, :562:25] reg reg_vsstatus_sie; // @[CSR.scala:562:25] assign io_gstatus_sie_0 = reg_vsstatus_sie; // @[CSR.scala:377:7, :562:25] reg [39:0] reg_vsepc; // @[CSR.scala:564:22] reg [63:0] reg_vscause; // @[CSR.scala:565:24] reg [39:0] reg_vstval; // @[CSR.scala:566:23] reg [39:0] reg_sepc; // @[CSR.scala:569:21] reg [63:0] reg_scause; // @[CSR.scala:570:23] reg [39:0] reg_stval; // @[CSR.scala:571:22] reg [63:0] reg_sscratch; // @[CSR.scala:572:25] reg [38:0] reg_stvec; // @[CSR.scala:573:22] reg [3:0] reg_satp_mode; // @[CSR.scala:574:21] assign io_ptbr_mode_0 = reg_satp_mode; // @[CSR.scala:377:7, :574:21] reg [43:0] reg_satp_ppn; // @[CSR.scala:574:21] assign io_ptbr_ppn_0 = reg_satp_ppn; // @[CSR.scala:377:7, :574:21] reg reg_wfi; // @[CSR.scala:575:54] assign io_status_wfi_0 = reg_wfi; // @[CSR.scala:377:7, :575:54] reg [4:0] reg_fflags; // @[CSR.scala:577:23] reg [2:0] reg_frm; // @[CSR.scala:578:20] assign io_fcsr_rm_0 = reg_frm; // @[CSR.scala:377:7, :578:20] reg [12:0] reg_vconfig_vl; // @[CSR.scala:579:43] assign io_vector_vconfig_vl_0 = reg_vconfig_vl; // @[CSR.scala:377:7, :579:43] reg reg_vconfig_vtype_vill; // @[CSR.scala:579:43] assign io_vector_vconfig_vtype_vill_0 = reg_vconfig_vtype_vill; // @[CSR.scala:377:7, :579:43] reg [54:0] reg_vconfig_vtype_reserved; // @[CSR.scala:579:43] assign io_vector_vconfig_vtype_reserved_0 = reg_vconfig_vtype_reserved; // @[CSR.scala:377:7, :579:43] reg reg_vconfig_vtype_vma; // @[CSR.scala:579:43] assign io_vector_vconfig_vtype_vma_0 = reg_vconfig_vtype_vma; // @[CSR.scala:377:7, :579:43] reg reg_vconfig_vtype_vta; // @[CSR.scala:579:43] assign io_vector_vconfig_vtype_vta_0 = reg_vconfig_vtype_vta; // @[CSR.scala:377:7, :579:43] reg [2:0] reg_vconfig_vtype_vsew; // @[CSR.scala:579:43] assign io_vector_vconfig_vtype_vsew_0 = reg_vconfig_vtype_vsew; // @[CSR.scala:377:7, :579:43] reg reg_vconfig_vtype_vlmul_sign; // @[CSR.scala:579:43] assign io_vector_vconfig_vtype_vlmul_sign_0 = reg_vconfig_vtype_vlmul_sign; // @[CSR.scala:377:7, :579:43] reg [1:0] reg_vconfig_vtype_vlmul_mag; // @[CSR.scala:579:43] assign io_vector_vconfig_vtype_vlmul_mag_0 = reg_vconfig_vtype_vlmul_mag; // @[CSR.scala:377:7, :579:43] reg [11:0] reg_vstart; // @[CSR.scala:580:42] assign io_vector_vstart_0 = reg_vstart; // @[CSR.scala:377:7, :580:42] reg reg_vxsat; // @[CSR.scala:581:41] reg [1:0] reg_vxrm; // @[CSR.scala:582:40] assign io_vector_vxrm_0 = reg_vxrm; // @[CSR.scala:377:7, :582:40] reg reg_mtinst_read_pseudo; // @[CSR.scala:584:35] reg reg_htinst_read_pseudo; // @[CSR.scala:585:35] wire [1:0] hi_4 = {2{reg_mtinst_read_pseudo}}; // @[CSR.scala:584:35, :588:103] wire [13:0] read_mtinst = {hi_4, 12'h0}; // @[CSR.scala:588:103] wire [1:0] hi_5 = {2{reg_htinst_read_pseudo}}; // @[CSR.scala:585:35, :588:103] wire [13:0] read_htinst = {hi_5, 12'h0}; // @[CSR.scala:588:103] reg [2:0] reg_mcountinhibit; // @[CSR.scala:590:34] assign _io_inhibit_cycle_T = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40] wire x11 = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40, :594:98] assign io_inhibit_cycle_0 = _io_inhibit_cycle_T; // @[CSR.scala:377:7, :591:40] wire x3 = reg_mcountinhibit[2]; // @[CSR.scala:590:34, :592:75] reg [5:0] small_0; // @[Counters.scala:45:41] wire [6:0] nextSmall = {1'h0, small_0} + {6'h0, io_retire_0}; // @[Counters.scala:45:41, :46:33] wire _large_T_1 = ~x3; // @[Counters.scala:47:9, :51:36] reg [57:0] large_0; // @[Counters.scala:50:31] wire _large_T = nextSmall[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_2 = _large_T & _large_T_1; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T = {1'h0, large_0} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_1 = _large_r_T[57:0]; // @[Counters.scala:51:55] wire [63:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30] wire x10 = ~io_csr_stall_0; // @[CSR.scala:377:7, :594:56] reg [5:0] small_1; // @[Counters.scala:45:41] wire [6:0] nextSmall_1 = {1'h0, small_1} + {6'h0, x10}; // @[Counters.scala:45:41, :46:33] wire _large_T_4 = ~x11; // @[Counters.scala:47:9, :51:36] reg [57:0] large_1; // @[Counters.scala:50:31] wire _large_T_3 = nextSmall_1[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_5 = _large_T_3 & _large_T_4; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T_2 = {1'h0, large_1} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_3 = _large_r_T_2[57:0]; // @[Counters.scala:51:55] assign value_1 = {large_1, small_1}; // @[Counters.scala:45:41, :50:31, :55:30] assign io_time_0 = value_1; // @[Counters.scala:55:30] wire read_mip_hi_hi_hi_hi = mip_zero1; // @[CSR.scala:600:24, :610:22] wire _mip_seip_T; // @[CSR.scala:606:57] wire mip_seip; // @[CSR.scala:600:24] assign _mip_seip_T = reg_mip_seip | io_interrupts_seip_0; // @[CSR.scala:377:7, :504:20, :606:57] assign mip_seip = _mip_seip_T; // @[CSR.scala:600:24, :606:57] wire [1:0] read_mip_lo_lo_lo = {mip_ssip, mip_usip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_lo_hi = {mip_msip, mip_vssip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_lo = {read_mip_lo_lo_hi, read_mip_lo_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_lo_hi_lo = {mip_stip, mip_utip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_hi_hi = {mip_mtip, mip_vstip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_hi = {read_mip_lo_hi_hi, read_mip_lo_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_lo = {read_mip_lo_hi, read_mip_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_lo_lo = {mip_seip, mip_ueip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_lo_hi = {mip_meip, mip_vseip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_lo = {read_mip_hi_lo_hi, read_mip_hi_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_hi_lo = {1'h0, mip_sgeip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_hi_hi = {read_mip_hi_hi_hi_hi, mip_debug}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_hi = {read_mip_hi_hi_hi, read_mip_hi_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_hi = {read_mip_hi_hi, read_mip_hi_lo}; // @[CSR.scala:610:22] wire [15:0] _read_mip_T = {read_mip_hi, read_mip_lo}; // @[CSR.scala:610:22] wire [15:0] read_mip = _read_mip_T & 16'hAAA; // @[CSR.scala:610:{22,29}] wire [63:0] _pending_interrupts_T = {48'h0, reg_mie[15:0] & read_mip}; // @[CSR.scala:495:20, :610:29, :614:56] wire [63:0] pending_interrupts = _pending_interrupts_T; // @[CSR.scala:614:{44,56}] wire [14:0] d_interrupts = {io_interrupts_debug_0, 14'h0}; // @[CSR.scala:377:7, :615:42] wire _allow_wfi_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :906:61] wire _allow_sfence_vma_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :907:60] wire _allow_sret_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :910:62] wire _allow_counter_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :912:42] wire _m_interrupts_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51] wire _m_interrupts_T_1 = _m_interrupts_T | reg_mstatus_mie; // @[CSR.scala:395:28, :620:{51,62}] wire _m_interrupts_T_2 = _m_interrupts_T_1; // @[CSR.scala:620:{31,62}] wire [63:0] _m_interrupts_T_3 = ~pending_interrupts; // @[CSR.scala:614:44, :620:85] wire [63:0] _m_interrupts_T_4 = _m_interrupts_T_3 | read_mideleg; // @[CSR.scala:498:14, :620:{85,105}] wire [63:0] _m_interrupts_T_5 = ~_m_interrupts_T_4; // @[CSR.scala:620:{83,105}] wire [63:0] m_interrupts = _m_interrupts_T_2 ? _m_interrupts_T_5 : 64'h0; // @[CSR.scala:620:{25,31,83}] wire _GEN_2 = reg_mstatus_prv == 2'h0; // @[CSR.scala:395:28, :621:68] wire _s_interrupts_T; // @[CSR.scala:621:68] assign _s_interrupts_T = _GEN_2; // @[CSR.scala:621:68] wire _vs_interrupts_T; // @[CSR.scala:622:70] assign _vs_interrupts_T = _GEN_2; // @[CSR.scala:621:68, :622:70] wire _io_fiom_T_2; // @[CSR.scala:631:82] assign _io_fiom_T_2 = _GEN_2; // @[CSR.scala:621:68, :631:82] wire _s_interrupts_T_1 = reg_mstatus_v | _s_interrupts_T; // @[CSR.scala:395:28, :621:{49,68}] wire _GEN_3 = reg_mstatus_prv == 2'h1; // @[CSR.scala:395:28, :621:98] wire _s_interrupts_T_2; // @[CSR.scala:621:98] assign _s_interrupts_T_2 = _GEN_3; // @[CSR.scala:621:98] wire _vs_interrupts_T_1; // @[CSR.scala:622:99] assign _vs_interrupts_T_1 = _GEN_3; // @[CSR.scala:621:98, :622:99] wire _csr_addr_legal_T_4; // @[CSR.scala:921:62] assign _csr_addr_legal_T_4 = _GEN_3; // @[CSR.scala:621:98, :921:62] wire _s_interrupts_T_3 = _s_interrupts_T_2 & reg_mstatus_sie; // @[CSR.scala:395:28, :621:{98,110}] wire _s_interrupts_T_4 = _s_interrupts_T_1 | _s_interrupts_T_3; // @[CSR.scala:621:{49,78,110}] wire _s_interrupts_T_5 = _s_interrupts_T_4; // @[CSR.scala:621:{31,78}] wire [63:0] _s_interrupts_T_6 = pending_interrupts & read_mideleg; // @[CSR.scala:498:14, :614:44, :621:151] wire [63:0] _s_interrupts_T_8 = _s_interrupts_T_6; // @[CSR.scala:621:{151,166}] wire [63:0] s_interrupts = _s_interrupts_T_5 ? _s_interrupts_T_8 : 64'h0; // @[CSR.scala:621:{25,31,166}] wire _vs_interrupts_T_2 = _vs_interrupts_T_1 & reg_vsstatus_sie; // @[CSR.scala:562:25, :622:{99,111}] wire _vs_interrupts_T_3 = _vs_interrupts_T | _vs_interrupts_T_2; // @[CSR.scala:622:{70,80,111}] wire _vs_interrupts_T_4 = reg_mstatus_v & _vs_interrupts_T_3; // @[CSR.scala:395:28, :622:{50,80}] wire _vs_interrupts_T_5 = _vs_interrupts_T_4; // @[CSR.scala:622:{32,50}] wire _any_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76] wire _which_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76] wire _which_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76] wire _which_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76] wire _which_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76] wire _which_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76] wire _which_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76] wire _which_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76] wire _which_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76] wire _which_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76] wire _which_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76] wire _which_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76] wire _which_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76] wire _which_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76] wire _which_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76] wire _which_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76] wire _which_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76] wire _which_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76] wire _which_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76] wire _which_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76] wire _which_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76] wire _which_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76] wire _which_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76] wire _which_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76] wire _which_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76] wire _which_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76] wire _which_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76] wire _which_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76] wire _which_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76] wire _which_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76] wire _which_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76] wire _which_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76] wire _which_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76] wire _which_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76] wire _which_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76] wire _which_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76] wire _which_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76] wire _which_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76] wire _which_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76] wire _which_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76] wire _which_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76] wire _which_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76] wire _which_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76] wire _which_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76] wire _which_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76] wire _which_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76] wire _which_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76] wire _which_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_63 = _any_T | _any_T_1; // @[CSR.scala:1637:{76,90}] wire _any_T_64 = _any_T_63 | _any_T_2; // @[CSR.scala:1637:{76,90}] wire _any_T_65 = _any_T_64 | _any_T_3; // @[CSR.scala:1637:{76,90}] wire _any_T_66 = _any_T_65 | _any_T_4; // @[CSR.scala:1637:{76,90}] wire _any_T_67 = _any_T_66 | _any_T_5; // @[CSR.scala:1637:{76,90}] wire _any_T_68 = _any_T_67 | _any_T_6; // @[CSR.scala:1637:{76,90}] wire _any_T_69 = _any_T_68 | _any_T_7; // @[CSR.scala:1637:{76,90}] wire _any_T_70 = _any_T_69 | _any_T_8; // @[CSR.scala:1637:{76,90}] wire _any_T_71 = _any_T_70 | _any_T_9; // @[CSR.scala:1637:{76,90}] wire _any_T_72 = _any_T_71 | _any_T_10; // @[CSR.scala:1637:{76,90}] wire _any_T_73 = _any_T_72 | _any_T_11; // @[CSR.scala:1637:{76,90}] wire _any_T_74 = _any_T_73 | _any_T_12; // @[CSR.scala:1637:{76,90}] wire _any_T_75 = _any_T_74 | _any_T_13; // @[CSR.scala:1637:{76,90}] wire _any_T_76 = _any_T_75 | _any_T_14; // @[CSR.scala:1637:{76,90}] wire _any_T_77 = _any_T_76; // @[CSR.scala:1637:90] wire _any_T_78 = _any_T_77 | _any_T_15; // @[CSR.scala:1637:{76,90}] wire _any_T_79 = _any_T_78 | _any_T_16; // @[CSR.scala:1637:{76,90}] wire _any_T_80 = _any_T_79 | _any_T_17; // @[CSR.scala:1637:{76,90}] wire _any_T_81 = _any_T_80 | _any_T_18; // @[CSR.scala:1637:{76,90}] wire _any_T_82 = _any_T_81 | _any_T_19; // @[CSR.scala:1637:{76,90}] wire _any_T_83 = _any_T_82 | _any_T_20; // @[CSR.scala:1637:{76,90}] wire _any_T_84 = _any_T_83 | _any_T_21; // @[CSR.scala:1637:{76,90}] wire _any_T_85 = _any_T_84 | _any_T_22; // @[CSR.scala:1637:{76,90}] wire _any_T_86 = _any_T_85 | _any_T_23; // @[CSR.scala:1637:{76,90}] wire _any_T_87 = _any_T_86 | _any_T_24; // @[CSR.scala:1637:{76,90}] wire _any_T_88 = _any_T_87 | _any_T_25; // @[CSR.scala:1637:{76,90}] wire _any_T_89 = _any_T_88 | _any_T_26; // @[CSR.scala:1637:{76,90}] wire _any_T_90 = _any_T_89 | _any_T_27; // @[CSR.scala:1637:{76,90}] wire _any_T_91 = _any_T_90 | _any_T_28; // @[CSR.scala:1637:{76,90}] wire _any_T_92 = _any_T_91 | _any_T_29; // @[CSR.scala:1637:{76,90}] wire _any_T_93 = _any_T_92 | _any_T_30; // @[CSR.scala:1637:{76,90}] wire _any_T_94 = _any_T_93 | _any_T_31; // @[CSR.scala:1637:{76,90}] wire _any_T_95 = _any_T_94 | _any_T_32; // @[CSR.scala:1637:{76,90}] wire _any_T_96 = _any_T_95 | _any_T_33; // @[CSR.scala:1637:{76,90}] wire _any_T_97 = _any_T_96 | _any_T_34; // @[CSR.scala:1637:{76,90}] wire _any_T_98 = _any_T_97 | _any_T_35; // @[CSR.scala:1637:{76,90}] wire _any_T_99 = _any_T_98 | _any_T_36; // @[CSR.scala:1637:{76,90}] wire _any_T_100 = _any_T_99 | _any_T_37; // @[CSR.scala:1637:{76,90}] wire _any_T_101 = _any_T_100 | _any_T_38; // @[CSR.scala:1637:{76,90}] wire _any_T_102 = _any_T_101 | _any_T_39; // @[CSR.scala:1637:{76,90}] wire _any_T_103 = _any_T_102 | _any_T_40; // @[CSR.scala:1637:{76,90}] wire _any_T_104 = _any_T_103 | _any_T_41; // @[CSR.scala:1637:{76,90}] wire _any_T_105 = _any_T_104 | _any_T_42; // @[CSR.scala:1637:{76,90}] wire _any_T_106 = _any_T_105 | _any_T_43; // @[CSR.scala:1637:{76,90}] wire _any_T_107 = _any_T_106 | _any_T_44; // @[CSR.scala:1637:{76,90}] wire _any_T_108 = _any_T_107 | _any_T_45; // @[CSR.scala:1637:{76,90}] wire _any_T_109 = _any_T_108 | _any_T_46; // @[CSR.scala:1637:{76,90}] wire _any_T_110 = _any_T_109; // @[CSR.scala:1637:90] wire _any_T_111 = _any_T_110; // @[CSR.scala:1637:90] wire _any_T_112 = _any_T_111; // @[CSR.scala:1637:90] wire _any_T_113 = _any_T_112; // @[CSR.scala:1637:90] wire _any_T_114 = _any_T_113; // @[CSR.scala:1637:90] wire _any_T_115 = _any_T_114; // @[CSR.scala:1637:90] wire _any_T_116 = _any_T_115; // @[CSR.scala:1637:90] wire _any_T_117 = _any_T_116; // @[CSR.scala:1637:90] wire _any_T_118 = _any_T_117; // @[CSR.scala:1637:90] wire _any_T_119 = _any_T_118; // @[CSR.scala:1637:90] wire _any_T_120 = _any_T_119; // @[CSR.scala:1637:90] wire _any_T_121 = _any_T_120; // @[CSR.scala:1637:90] wire _any_T_122 = _any_T_121; // @[CSR.scala:1637:90] wire _any_T_123 = _any_T_122; // @[CSR.scala:1637:90] wire _any_T_124 = _any_T_123; // @[CSR.scala:1637:90] wire anyInterrupt = _any_T_124; // @[CSR.scala:1637:90] wire [3:0] _which_T_79 = {1'h0, ~_which_T_45, 2'h0}; // @[Mux.scala:50:70] wire [3:0] _which_T_80 = _which_T_44 ? 4'h8 : _which_T_79; // @[Mux.scala:50:70] wire [3:0] _which_T_81 = _which_T_43 ? 4'h6 : _which_T_80; // @[Mux.scala:50:70] wire [3:0] _which_T_82 = _which_T_42 ? 4'h2 : _which_T_81; // @[Mux.scala:50:70] wire [3:0] _which_T_83 = _which_T_41 ? 4'hA : _which_T_82; // @[Mux.scala:50:70] wire [3:0] _which_T_84 = _which_T_40 ? 4'h5 : _which_T_83; // @[Mux.scala:50:70] wire [3:0] _which_T_85 = _which_T_39 ? 4'h1 : _which_T_84; // @[Mux.scala:50:70] wire [3:0] _which_T_86 = _which_T_38 ? 4'h9 : _which_T_85; // @[Mux.scala:50:70] wire [3:0] _which_T_87 = _which_T_37 ? 4'h7 : _which_T_86; // @[Mux.scala:50:70] wire [3:0] _which_T_88 = _which_T_36 ? 4'h3 : _which_T_87; // @[Mux.scala:50:70] wire [3:0] _which_T_89 = _which_T_35 ? 4'hB : _which_T_88; // @[Mux.scala:50:70] wire [3:0] _which_T_90 = _which_T_34 ? 4'hC : _which_T_89; // @[Mux.scala:50:70] wire [3:0] _which_T_91 = _which_T_33 ? 4'hD : _which_T_90; // @[Mux.scala:50:70] wire [3:0] _which_T_92 = _which_T_32 ? 4'hE : _which_T_91; // @[Mux.scala:50:70] wire [3:0] _which_T_93 = _which_T_31 ? 4'hF : _which_T_92; // @[Mux.scala:50:70] wire [3:0] _which_T_94 = _which_T_30 ? 4'h4 : _which_T_93; // @[Mux.scala:50:70] wire [3:0] _which_T_95 = _which_T_29 ? 4'h0 : _which_T_94; // @[Mux.scala:50:70] wire [3:0] _which_T_96 = _which_T_28 ? 4'h8 : _which_T_95; // @[Mux.scala:50:70] wire [3:0] _which_T_97 = _which_T_27 ? 4'h6 : _which_T_96; // @[Mux.scala:50:70] wire [3:0] _which_T_98 = _which_T_26 ? 4'h2 : _which_T_97; // @[Mux.scala:50:70] wire [3:0] _which_T_99 = _which_T_25 ? 4'hA : _which_T_98; // @[Mux.scala:50:70] wire [3:0] _which_T_100 = _which_T_24 ? 4'h5 : _which_T_99; // @[Mux.scala:50:70] wire [3:0] _which_T_101 = _which_T_23 ? 4'h1 : _which_T_100; // @[Mux.scala:50:70] wire [3:0] _which_T_102 = _which_T_22 ? 4'h9 : _which_T_101; // @[Mux.scala:50:70] wire [3:0] _which_T_103 = _which_T_21 ? 4'h7 : _which_T_102; // @[Mux.scala:50:70] wire [3:0] _which_T_104 = _which_T_20 ? 4'h3 : _which_T_103; // @[Mux.scala:50:70] wire [3:0] _which_T_105 = _which_T_19 ? 4'hB : _which_T_104; // @[Mux.scala:50:70] wire [3:0] _which_T_106 = _which_T_18 ? 4'hC : _which_T_105; // @[Mux.scala:50:70] wire [3:0] _which_T_107 = _which_T_17 ? 4'hD : _which_T_106; // @[Mux.scala:50:70] wire [3:0] _which_T_108 = _which_T_16 ? 4'hE : _which_T_107; // @[Mux.scala:50:70] wire [3:0] _which_T_109 = _which_T_15 ? 4'hF : _which_T_108; // @[Mux.scala:50:70] wire [3:0] _which_T_110 = _which_T_109; // @[Mux.scala:50:70] wire [3:0] _which_T_111 = _which_T_14 ? 4'h4 : _which_T_110; // @[Mux.scala:50:70] wire [3:0] _which_T_112 = _which_T_13 ? 4'h0 : _which_T_111; // @[Mux.scala:50:70] wire [3:0] _which_T_113 = _which_T_12 ? 4'h8 : _which_T_112; // @[Mux.scala:50:70] wire [3:0] _which_T_114 = _which_T_11 ? 4'h6 : _which_T_113; // @[Mux.scala:50:70] wire [3:0] _which_T_115 = _which_T_10 ? 4'h2 : _which_T_114; // @[Mux.scala:50:70] wire [3:0] _which_T_116 = _which_T_9 ? 4'hA : _which_T_115; // @[Mux.scala:50:70] wire [3:0] _which_T_117 = _which_T_8 ? 4'h5 : _which_T_116; // @[Mux.scala:50:70] wire [3:0] _which_T_118 = _which_T_7 ? 4'h1 : _which_T_117; // @[Mux.scala:50:70] wire [3:0] _which_T_119 = _which_T_6 ? 4'h9 : _which_T_118; // @[Mux.scala:50:70] wire [3:0] _which_T_120 = _which_T_5 ? 4'h7 : _which_T_119; // @[Mux.scala:50:70] wire [3:0] _which_T_121 = _which_T_4 ? 4'h3 : _which_T_120; // @[Mux.scala:50:70] wire [3:0] _which_T_122 = _which_T_3 ? 4'hB : _which_T_121; // @[Mux.scala:50:70] wire [3:0] _which_T_123 = _which_T_2 ? 4'hC : _which_T_122; // @[Mux.scala:50:70] wire [3:0] _which_T_124 = _which_T_1 ? 4'hD : _which_T_123; // @[Mux.scala:50:70] wire [3:0] whichInterrupt = _which_T ? 4'hE : _which_T_124; // @[Mux.scala:50:70] wire [64:0] _interruptCause_T_3 = {61'h0, whichInterrupt} + 65'h8000000000000000; // @[Mux.scala:50:70] assign interruptCause = _interruptCause_T_3[63:0]; // @[CSR.scala:625:63] assign io_interrupt_cause_0 = interruptCause; // @[CSR.scala:377:7, :625:63] wire _io_interrupt_T = ~io_singleStep_0; // @[CSR.scala:377:7, :626:36] wire _io_interrupt_T_1 = anyInterrupt & _io_interrupt_T; // @[CSR.scala:626:{33,36}, :1637:90] wire _io_interrupt_T_2 = _io_interrupt_T_1 | reg_singleStepped; // @[CSR.scala:486:30, :626:{33,51}] wire _io_interrupt_T_3 = reg_debug | io_status_cease_0; // @[CSR.scala:377:7, :482:26, :626:88] wire _io_interrupt_T_4 = ~_io_interrupt_T_3; // @[CSR.scala:626:{76,88}] assign _io_interrupt_T_5 = _io_interrupt_T_2 & _io_interrupt_T_4; // @[CSR.scala:626:{51,73,76}] assign io_interrupt_0 = _io_interrupt_T_5; // @[CSR.scala:377:7, :626:73] wire _io_fiom_T = reg_mstatus_prv != 2'h3; // @[CSR.scala:395:28, :631:31] wire _io_fiom_T_1 = _io_fiom_T & reg_menvcfg_fiom; // @[CSR.scala:525:28, :631:{31,41}] wire _io_fiom_T_3 = _io_fiom_T_2 & reg_senvcfg_fiom; // @[CSR.scala:526:28, :631:{82,92}] wire _io_fiom_T_4 = _io_fiom_T_1 | _io_fiom_T_3; // @[CSR.scala:631:{41,62,92}] assign _io_fiom_T_6 = _io_fiom_T_4; // @[CSR.scala:631:{62,113}] assign io_fiom = _io_fiom_T_6; // @[CSR.scala:377:7, :631:113] assign io_pmp_0_cfg_l_0 = pmp_cfg_l; // @[PMP.scala:24:19] assign io_pmp_0_cfg_a_0 = pmp_cfg_a; // @[PMP.scala:24:19] assign io_pmp_0_cfg_x_0 = pmp_cfg_x; // @[PMP.scala:24:19] assign io_pmp_0_cfg_w_0 = pmp_cfg_w; // @[PMP.scala:24:19] assign io_pmp_0_cfg_r_0 = pmp_cfg_r; // @[PMP.scala:24:19] assign io_pmp_0_addr_0 = pmp_addr; // @[PMP.scala:24:19] assign io_pmp_0_mask_0 = pmp_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T = pmp_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_1 = {pmp_addr, _pmp_mask_base_T}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base = _pmp_mask_base_T_1; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T = {1'h0, pmp_mask_base} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_1 = _pmp_mask_T[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_2 = ~_pmp_mask_T_1; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_3 = pmp_mask_base & _pmp_mask_T_2; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_4 = {_pmp_mask_T_3, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_mask = _pmp_mask_T_4[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_1_cfg_l_0 = pmp_1_cfg_l; // @[PMP.scala:24:19] assign io_pmp_1_cfg_a_0 = pmp_1_cfg_a; // @[PMP.scala:24:19] assign io_pmp_1_cfg_x_0 = pmp_1_cfg_x; // @[PMP.scala:24:19] assign io_pmp_1_cfg_w_0 = pmp_1_cfg_w; // @[PMP.scala:24:19] assign io_pmp_1_cfg_r_0 = pmp_1_cfg_r; // @[PMP.scala:24:19] assign io_pmp_1_addr_0 = pmp_1_addr; // @[PMP.scala:24:19] assign io_pmp_1_mask_0 = pmp_1_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_3 = pmp_1_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_4 = {pmp_1_addr, _pmp_mask_base_T_3}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_1 = _pmp_mask_base_T_4; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_5 = {1'h0, pmp_mask_base_1} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_6 = _pmp_mask_T_5[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_7 = ~_pmp_mask_T_6; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_8 = pmp_mask_base_1 & _pmp_mask_T_7; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_9 = {_pmp_mask_T_8, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_1_mask = _pmp_mask_T_9[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_2_cfg_l_0 = pmp_2_cfg_l; // @[PMP.scala:24:19] assign io_pmp_2_cfg_a_0 = pmp_2_cfg_a; // @[PMP.scala:24:19] assign io_pmp_2_cfg_x_0 = pmp_2_cfg_x; // @[PMP.scala:24:19] assign io_pmp_2_cfg_w_0 = pmp_2_cfg_w; // @[PMP.scala:24:19] assign io_pmp_2_cfg_r_0 = pmp_2_cfg_r; // @[PMP.scala:24:19] assign io_pmp_2_addr_0 = pmp_2_addr; // @[PMP.scala:24:19] assign io_pmp_2_mask_0 = pmp_2_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_6 = pmp_2_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_7 = {pmp_2_addr, _pmp_mask_base_T_6}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_2 = _pmp_mask_base_T_7; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_10 = {1'h0, pmp_mask_base_2} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_11 = _pmp_mask_T_10[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_12 = ~_pmp_mask_T_11; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_13 = pmp_mask_base_2 & _pmp_mask_T_12; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_14 = {_pmp_mask_T_13, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_2_mask = _pmp_mask_T_14[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_3_cfg_l_0 = pmp_3_cfg_l; // @[PMP.scala:24:19] assign io_pmp_3_cfg_a_0 = pmp_3_cfg_a; // @[PMP.scala:24:19] assign io_pmp_3_cfg_x_0 = pmp_3_cfg_x; // @[PMP.scala:24:19] assign io_pmp_3_cfg_w_0 = pmp_3_cfg_w; // @[PMP.scala:24:19] assign io_pmp_3_cfg_r_0 = pmp_3_cfg_r; // @[PMP.scala:24:19] assign io_pmp_3_addr_0 = pmp_3_addr; // @[PMP.scala:24:19] assign io_pmp_3_mask_0 = pmp_3_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_9 = pmp_3_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_10 = {pmp_3_addr, _pmp_mask_base_T_9}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_3 = _pmp_mask_base_T_10; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_15 = {1'h0, pmp_mask_base_3} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_16 = _pmp_mask_T_15[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_17 = ~_pmp_mask_T_16; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_18 = pmp_mask_base_3 & _pmp_mask_T_17; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_19 = {_pmp_mask_T_18, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_3_mask = _pmp_mask_T_19[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_4_cfg_l_0 = pmp_4_cfg_l; // @[PMP.scala:24:19] assign io_pmp_4_cfg_a_0 = pmp_4_cfg_a; // @[PMP.scala:24:19] assign io_pmp_4_cfg_x_0 = pmp_4_cfg_x; // @[PMP.scala:24:19] assign io_pmp_4_cfg_w_0 = pmp_4_cfg_w; // @[PMP.scala:24:19] assign io_pmp_4_cfg_r_0 = pmp_4_cfg_r; // @[PMP.scala:24:19] assign io_pmp_4_addr_0 = pmp_4_addr; // @[PMP.scala:24:19] assign io_pmp_4_mask_0 = pmp_4_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_12 = pmp_4_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_13 = {pmp_4_addr, _pmp_mask_base_T_12}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_4 = _pmp_mask_base_T_13; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_20 = {1'h0, pmp_mask_base_4} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_21 = _pmp_mask_T_20[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_22 = ~_pmp_mask_T_21; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_23 = pmp_mask_base_4 & _pmp_mask_T_22; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_24 = {_pmp_mask_T_23, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_4_mask = _pmp_mask_T_24[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_5_cfg_l_0 = pmp_5_cfg_l; // @[PMP.scala:24:19] assign io_pmp_5_cfg_a_0 = pmp_5_cfg_a; // @[PMP.scala:24:19] assign io_pmp_5_cfg_x_0 = pmp_5_cfg_x; // @[PMP.scala:24:19] assign io_pmp_5_cfg_w_0 = pmp_5_cfg_w; // @[PMP.scala:24:19] assign io_pmp_5_cfg_r_0 = pmp_5_cfg_r; // @[PMP.scala:24:19] assign io_pmp_5_addr_0 = pmp_5_addr; // @[PMP.scala:24:19] assign io_pmp_5_mask_0 = pmp_5_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_15 = pmp_5_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_16 = {pmp_5_addr, _pmp_mask_base_T_15}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_5 = _pmp_mask_base_T_16; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_25 = {1'h0, pmp_mask_base_5} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_26 = _pmp_mask_T_25[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_27 = ~_pmp_mask_T_26; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_28 = pmp_mask_base_5 & _pmp_mask_T_27; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_29 = {_pmp_mask_T_28, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_5_mask = _pmp_mask_T_29[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_6_cfg_l_0 = pmp_6_cfg_l; // @[PMP.scala:24:19] assign io_pmp_6_cfg_a_0 = pmp_6_cfg_a; // @[PMP.scala:24:19] assign io_pmp_6_cfg_x_0 = pmp_6_cfg_x; // @[PMP.scala:24:19] assign io_pmp_6_cfg_w_0 = pmp_6_cfg_w; // @[PMP.scala:24:19] assign io_pmp_6_cfg_r_0 = pmp_6_cfg_r; // @[PMP.scala:24:19] assign io_pmp_6_addr_0 = pmp_6_addr; // @[PMP.scala:24:19] assign io_pmp_6_mask_0 = pmp_6_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_18 = pmp_6_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_19 = {pmp_6_addr, _pmp_mask_base_T_18}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_6 = _pmp_mask_base_T_19; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_30 = {1'h0, pmp_mask_base_6} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_31 = _pmp_mask_T_30[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_32 = ~_pmp_mask_T_31; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_33 = pmp_mask_base_6 & _pmp_mask_T_32; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_34 = {_pmp_mask_T_33, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_6_mask = _pmp_mask_T_34[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_7_cfg_l_0 = pmp_7_cfg_l; // @[PMP.scala:24:19] assign io_pmp_7_cfg_a_0 = pmp_7_cfg_a; // @[PMP.scala:24:19] assign io_pmp_7_cfg_x_0 = pmp_7_cfg_x; // @[PMP.scala:24:19] assign io_pmp_7_cfg_w_0 = pmp_7_cfg_w; // @[PMP.scala:24:19] assign io_pmp_7_cfg_r_0 = pmp_7_cfg_r; // @[PMP.scala:24:19] assign io_pmp_7_addr_0 = pmp_7_addr; // @[PMP.scala:24:19] assign io_pmp_7_mask_0 = pmp_7_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_21 = pmp_7_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_22 = {pmp_7_addr, _pmp_mask_base_T_21}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_7 = _pmp_mask_base_T_22; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_35 = {1'h0, pmp_mask_base_7} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_36 = _pmp_mask_T_35[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_37 = ~_pmp_mask_T_36; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_38 = pmp_mask_base_7 & _pmp_mask_T_37; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_39 = {_pmp_mask_T_38, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_7_mask = _pmp_mask_T_39[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] reg [63:0] reg_misa; // @[CSR.scala:648:25] wire [1:0] read_mstatus_lo_lo_lo_lo = {io_status_sie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_lo_lo_hi = {io_status_mie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_lo_lo = {read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_lo_hi_lo = {io_status_spie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_lo_hi_hi_hi = {io_status_spp_0, io_status_mpie_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_lo_hi_hi = {read_mstatus_lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [4:0] read_mstatus_lo_lo_hi = {read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_lo_lo = {read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo}; // @[CSR.scala:649:32] wire [3:0] read_mstatus_lo_hi_lo_lo = {io_status_mpp_0, io_status_vs_0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_hi_lo_hi = {2'h0, io_status_fs_0}; // @[CSR.scala:377:7, :649:32] wire [7:0] read_mstatus_lo_hi_lo = {read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_hi_hi_lo = {io_status_sum_0, io_status_mprv_0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_hi_hi_hi_hi = {io_status_tw_0, io_status_tvm_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_hi_hi_hi = {read_mstatus_lo_hi_hi_hi_hi, io_status_mxr_0}; // @[CSR.scala:377:7, :649:32] wire [4:0] read_mstatus_lo_hi_hi = {read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo}; // @[CSR.scala:649:32] wire [12:0] read_mstatus_lo_hi = {read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo}; // @[CSR.scala:649:32] wire [21:0] read_mstatus_lo = {read_mstatus_lo_hi, read_mstatus_lo_lo}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_hi_lo_lo_lo = {8'h0, io_status_tsr_0}; // @[CSR.scala:377:7, :649:32] wire [11:0] read_mstatus_hi_lo_lo = {3'h4, read_mstatus_hi_lo_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_hi_lo_hi_hi_hi = {io_status_mpv_0, io_status_gva_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_lo_hi_hi = {read_mstatus_hi_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [5:0] read_mstatus_hi_lo_hi = {read_mstatus_hi_lo_hi_hi, 3'h2}; // @[CSR.scala:649:32] wire [17:0] read_mstatus_hi_lo = {read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo}; // @[CSR.scala:649:32] wire [23:0] read_mstatus_hi_hi_lo_lo = {io_status_sd_0, 23'h0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_lo_hi_hi = {io_status_dv_0, io_status_prv_0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_hi_hi_lo_hi = {read_mstatus_hi_hi_lo_hi_hi, io_status_v_0}; // @[CSR.scala:377:7, :649:32] wire [27:0] read_mstatus_hi_hi_lo = {read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo}; // @[CSR.scala:649:32] wire [33:0] read_mstatus_hi_hi_hi_lo = {io_status_isa_0, io_status_dprv_0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_hi_hi_hi_hi_hi = {io_status_debug_0, io_status_cease_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_hi_hi = {read_mstatus_hi_hi_hi_hi_hi, io_status_wfi_0}; // @[CSR.scala:377:7, :649:32] wire [36:0] read_mstatus_hi_hi_hi = {read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo}; // @[CSR.scala:649:32] wire [64:0] read_mstatus_hi_hi = {read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo}; // @[CSR.scala:649:32] wire [82:0] read_mstatus_hi = {read_mstatus_hi_hi, read_mstatus_hi_lo}; // @[CSR.scala:649:32] wire [104:0] _read_mstatus_T = {read_mstatus_hi, read_mstatus_lo}; // @[CSR.scala:649:32] wire [63:0] read_mstatus = _read_mstatus_T[63:0]; // @[package.scala:163:13] wire _read_mtvec_T = reg_mtvec[0]; // @[CSR.scala:512:31, :1666:41] wire [7:0] _read_mtvec_T_1 = _read_mtvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}] wire [31:0] _read_mtvec_T_3 = {24'h0, _read_mtvec_T_1}; // @[package.scala:174:41] wire [31:0] _read_mtvec_T_4 = ~_read_mtvec_T_3; // @[package.scala:174:{37,41}] wire [31:0] _read_mtvec_T_5 = reg_mtvec & _read_mtvec_T_4; // @[package.scala:174:{35,37}] wire [63:0] read_mtvec = {32'h0, _read_mtvec_T_5}; // @[package.scala:138:15, :174:35] wire _read_stvec_T = reg_stvec[0]; // @[CSR.scala:573:22, :1666:41] wire [7:0] _read_stvec_T_1 = _read_stvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}] wire [38:0] _read_stvec_T_3 = {31'h0, _read_stvec_T_1}; // @[package.scala:174:41] wire [38:0] _read_stvec_T_4 = ~_read_stvec_T_3; // @[package.scala:174:{37,41}] wire [38:0] _read_stvec_T_5 = reg_stvec & _read_stvec_T_4; // @[package.scala:174:{35,37}] wire _read_stvec_T_6 = _read_stvec_T_5[38]; // @[package.scala:132:38, :174:35] wire [24:0] _read_stvec_T_7 = {25{_read_stvec_T_6}}; // @[package.scala:132:{20,38}] wire [63:0] read_stvec = {_read_stvec_T_7, _read_stvec_T_5}; // @[package.scala:132:{15,20}, :174:35] wire [1:0] _GEN_4 = {reg_bp_0_control_x, reg_bp_0_control_w}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_lo_lo_hi; // @[CSR.scala:655:48] assign read_mapping_lo_lo_hi = _GEN_4; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_lo_hi; // @[CSR.scala:1477:67] assign newBPC_lo_lo_hi = _GEN_4; // @[CSR.scala:655:48, :1477:67] wire [2:0] read_mapping_lo_lo = {read_mapping_lo_lo_hi, reg_bp_0_control_r}; // @[CSR.scala:492:19, :655:48] wire [1:0] _GEN_5 = {reg_bp_0_control_s, reg_bp_0_control_u}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_lo_hi_lo; // @[CSR.scala:655:48] assign read_mapping_lo_hi_lo = _GEN_5; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_hi_lo; // @[CSR.scala:1477:67] assign newBPC_lo_hi_lo = _GEN_5; // @[CSR.scala:655:48, :1477:67] wire [1:0] _GEN_6 = {reg_bp_0_control_m, 1'h0}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_lo_hi_hi; // @[CSR.scala:655:48] assign read_mapping_lo_hi_hi = _GEN_6; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_hi_hi; // @[CSR.scala:1477:67] assign newBPC_lo_hi_hi = _GEN_6; // @[CSR.scala:655:48, :1477:67] wire [3:0] read_mapping_lo_hi = {read_mapping_lo_hi_hi, read_mapping_lo_hi_lo}; // @[CSR.scala:655:48] wire [6:0] read_mapping_lo = {read_mapping_lo_hi, read_mapping_lo_lo}; // @[CSR.scala:655:48] wire [3:0] _GEN_7 = {2'h0, reg_bp_0_control_tmatch}; // @[CSR.scala:492:19, :655:48] wire [3:0] read_mapping_hi_lo_lo; // @[CSR.scala:655:48] assign read_mapping_hi_lo_lo = _GEN_7; // @[CSR.scala:655:48] wire [3:0] newBPC_hi_lo_lo; // @[CSR.scala:1477:67] assign newBPC_hi_lo_lo = _GEN_7; // @[CSR.scala:655:48, :1477:67] wire [1:0] _GEN_8 = {reg_bp_0_control_action, 1'h0}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_hi_lo_hi; // @[CSR.scala:655:48] assign read_mapping_hi_lo_hi = _GEN_8; // @[CSR.scala:655:48] wire [1:0] newBPC_hi_lo_hi; // @[CSR.scala:1477:67] assign newBPC_hi_lo_hi = _GEN_8; // @[CSR.scala:655:48, :1477:67] wire [5:0] read_mapping_hi_lo = {read_mapping_hi_lo_hi, read_mapping_hi_lo_lo}; // @[CSR.scala:655:48] wire [4:0] _GEN_9 = {4'h2, reg_bp_0_control_dmode}; // @[CSR.scala:492:19, :655:48] wire [4:0] read_mapping_hi_hi_hi; // @[CSR.scala:655:48] assign read_mapping_hi_hi_hi = _GEN_9; // @[CSR.scala:655:48] wire [4:0] newBPC_hi_hi_hi; // @[CSR.scala:1477:67] assign newBPC_hi_hi_hi = _GEN_9; // @[CSR.scala:655:48, :1477:67] wire [50:0] read_mapping_hi_hi = {read_mapping_hi_hi_hi, 46'h40000000000}; // @[CSR.scala:655:48] wire [56:0] read_mapping_hi = {read_mapping_hi_hi, read_mapping_hi_lo}; // @[CSR.scala:655:48] wire [63:0] read_mapping_1_2 = {read_mapping_hi, read_mapping_lo}; // @[CSR.scala:655:48] wire _read_mapping_T = reg_bp_0_address[38]; // @[package.scala:132:38] wire [24:0] _read_mapping_T_1 = {25{_read_mapping_T}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_2_2 = {_read_mapping_T_1, reg_bp_0_address}; // @[package.scala:132:{15,20}] wire [1:0] read_mapping_lo_1 = {read_mapping_lo_hi_1, 1'h0}; // @[CSR.scala:657:47] wire [50:0] read_mapping_3_2 = {read_mapping_hi_1, read_mapping_lo_1}; // @[CSR.scala:657:47] wire [39:0] _read_mapping_T_2 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28] wire _read_mapping_T_3 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _debug_csrs_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_6 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_11 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_16 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_21 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire [1:0] _read_mapping_T_4 = {~_read_mapping_T_3, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [39:0] _read_mapping_T_5 = {_read_mapping_T_2[39:2], _read_mapping_T_2[1:0] | _read_mapping_T_4}; // @[CSR.scala:1665:{28,31,36}] wire [39:0] _read_mapping_T_6 = ~_read_mapping_T_5; // @[CSR.scala:1665:{26,31}] wire _read_mapping_T_7 = _read_mapping_T_6[39]; // @[package.scala:132:38] wire [23:0] _read_mapping_T_8 = {24{_read_mapping_T_7}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_10_2 = {_read_mapping_T_8, _read_mapping_T_6}; // @[package.scala:132:{15,20}] wire _read_mapping_T_9 = reg_mtval[39]; // @[package.scala:132:38] wire [23:0] _read_mapping_T_10 = {24{_read_mapping_T_9}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_11_2 = {_read_mapping_T_10, reg_mtval}; // @[package.scala:132:{15,20}] wire [2:0] debug_csrs_lo_lo_hi = {2'h0, reg_dcsr_step}; // @[CSR.scala:403:25, :670:27] wire [4:0] debug_csrs_lo_lo = {debug_csrs_lo_lo_hi, reg_dcsr_prv}; // @[CSR.scala:403:25, :670:27] wire [3:0] debug_csrs_lo_hi_lo = {reg_dcsr_cause, reg_dcsr_v}; // @[CSR.scala:403:25, :670:27] wire [5:0] debug_csrs_lo_hi = {2'h0, debug_csrs_lo_hi_lo}; // @[CSR.scala:670:27] wire [10:0] debug_csrs_lo = {debug_csrs_lo_hi, debug_csrs_lo_lo}; // @[CSR.scala:670:27] wire [1:0] debug_csrs_hi_lo_lo = {reg_dcsr_ebreaku, 1'h0}; // @[CSR.scala:403:25, :670:27] wire [1:0] debug_csrs_hi_lo_hi = {1'h0, reg_dcsr_ebreaks}; // @[CSR.scala:403:25, :670:27] wire [3:0] debug_csrs_hi_lo = {debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo}; // @[CSR.scala:670:27] wire [12:0] debug_csrs_hi_hi_lo = {12'h0, reg_dcsr_ebreakm}; // @[CSR.scala:403:25, :670:27] wire [16:0] debug_csrs_hi_hi = {4'h4, debug_csrs_hi_hi_lo}; // @[CSR.scala:670:27] wire [20:0] debug_csrs_hi = {debug_csrs_hi_hi, debug_csrs_hi_lo}; // @[CSR.scala:670:27] wire [31:0] debug_csrs_0_2 = {debug_csrs_hi, debug_csrs_lo}; // @[CSR.scala:670:27] wire [39:0] _debug_csrs_T = ~reg_dpc; // @[CSR.scala:483:20, :1665:28] wire [1:0] _debug_csrs_T_2 = {~_debug_csrs_T_1, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [39:0] _debug_csrs_T_3 = {_debug_csrs_T[39:2], _debug_csrs_T[1:0] | _debug_csrs_T_2}; // @[CSR.scala:1665:{28,31,36}] wire [39:0] _debug_csrs_T_4 = ~_debug_csrs_T_3; // @[CSR.scala:1665:{26,31}] wire _debug_csrs_T_5 = _debug_csrs_T_4[39]; // @[package.scala:132:38] wire [23:0] _debug_csrs_T_6 = {24{_debug_csrs_T_5}}; // @[package.scala:132:{20,38}] wire [63:0] debug_csrs_1_2 = {_debug_csrs_T_6, _debug_csrs_T_4}; // @[package.scala:132:{15,20}] wire [7:0] read_fcsr = {reg_frm, reg_fflags}; // @[CSR.scala:577:23, :578:20, :689:22] wire [2:0] read_vcsr = {reg_vxrm, reg_vxsat}; // @[CSR.scala:581:41, :582:40, :695:22] wire [3:0] vector_csrs_lo_hi = {reg_vconfig_vtype_vsew, reg_vconfig_vtype_vlmul_sign}; // @[CSR.scala:579:43, :701:41] wire [5:0] vector_csrs_lo = {vector_csrs_lo_hi, reg_vconfig_vtype_vlmul_mag}; // @[CSR.scala:579:43, :701:41] wire [1:0] vector_csrs_hi_lo = {reg_vconfig_vtype_vma, reg_vconfig_vtype_vta}; // @[CSR.scala:579:43, :701:41] wire [55:0] vector_csrs_hi_hi = {reg_vconfig_vtype_vill, reg_vconfig_vtype_reserved}; // @[CSR.scala:579:43, :701:41] wire [57:0] vector_csrs_hi = {vector_csrs_hi_hi, vector_csrs_hi_lo}; // @[CSR.scala:701:41] wire [63:0] vector_csrs_4_2 = {vector_csrs_hi, vector_csrs_lo}; // @[CSR.scala:701:41] wire [3:0] lo_lo_4 = {3'h0, reg_menvcfg_fiom}; // @[CSR.scala:525:28, :742:49] wire [6:0] lo_4 = {3'h0, lo_lo_4}; // @[CSR.scala:742:49] wire [63:0] sie_mask = {48'h0, read_mideleg[15:0] & 16'hEFFF}; // @[CSR.scala:498:14, :750:18] wire [63:0] read_sie = reg_mie & sie_mask; // @[CSR.scala:495:20, :750:18, :753:28] wire [63:0] read_sip = {48'h0, sie_mask[15:0] & read_mip}; // @[CSR.scala:610:29, :750:18, :754:29] wire [1:0] lo_lo_lo_lo = {read_sstatus_sie, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [3:0] lo_lo_lo_4 = {2'h0, lo_lo_lo_lo}; // @[CSR.scala:768:51] wire [1:0] lo_lo_hi_lo = {read_sstatus_spie, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [1:0] lo_lo_hi_hi_hi = {read_sstatus_spp, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [2:0] lo_lo_hi_hi = {lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:768:51] wire [4:0] lo_lo_hi_4 = {lo_lo_hi_hi, lo_lo_hi_lo}; // @[CSR.scala:768:51] wire [8:0] lo_lo_5 = {lo_lo_hi_4, lo_lo_lo_4}; // @[CSR.scala:768:51] wire [3:0] lo_hi_lo_lo = {2'h0, read_sstatus_vs}; // @[CSR.scala:755:35, :768:51] wire [3:0] lo_hi_lo_hi = {2'h0, read_sstatus_fs}; // @[CSR.scala:755:35, :768:51] wire [7:0] lo_hi_lo_4 = {lo_hi_lo_hi, lo_hi_lo_lo}; // @[CSR.scala:768:51] wire [1:0] lo_hi_hi_lo = {read_sstatus_sum, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [2:0] lo_hi_hi_hi = {2'h0, read_sstatus_mxr}; // @[CSR.scala:755:35, :768:51] wire [4:0] lo_hi_hi_4 = {lo_hi_hi_hi, lo_hi_hi_lo}; // @[CSR.scala:768:51] wire [12:0] lo_hi_5 = {lo_hi_hi_4, lo_hi_lo_4}; // @[CSR.scala:768:51] wire [21:0] lo_5 = {lo_hi_5, lo_lo_5}; // @[CSR.scala:768:51] wire [23:0] hi_hi_lo_lo = {read_sstatus_sd, 23'h0}; // @[CSR.scala:755:35, :768:51] wire [27:0] hi_hi_lo_4 = {4'h0, hi_hi_lo_lo}; // @[CSR.scala:768:51] wire [64:0] hi_hi_5 = {37'h0, hi_hi_lo_4}; // @[CSR.scala:768:51] wire [82:0] hi_7 = {hi_hi_5, 18'h800}; // @[CSR.scala:768:51] wire [19:0] hi_8 = {reg_satp_mode, 16'h0}; // @[CSR.scala:574:21, :774:43] wire [39:0] _io_evec_T = ~reg_sepc; // @[CSR.scala:569:21, :1665:28] wire [39:0] _T_30 = ~{_io_evec_T[39:2], _io_evec_T[1:0] | {~(reg_misa[2]), 1'h1}}; // @[CSR.scala:648:25, :1665:{26,28,31,36,45}] wire [3:0] lo_lo_6 = {3'h0, reg_senvcfg_fiom}; // @[CSR.scala:526:28, :780:49] wire [6:0] lo_6 = {3'h0, lo_lo_6}; // @[CSR.scala:780:49] wire [1:0] lo_hi_7 = {reg_pmp_0_cfg_x, reg_pmp_0_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_7 = {lo_hi_7, reg_pmp_0_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_7 = {reg_pmp_0_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_10 = {hi_hi_7, reg_pmp_0_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_8 = {reg_pmp_1_cfg_x, reg_pmp_1_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_8 = {lo_hi_8, reg_pmp_1_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_8 = {reg_pmp_1_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_11 = {hi_hi_8, reg_pmp_1_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_9 = {reg_pmp_2_cfg_x, reg_pmp_2_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_9 = {lo_hi_9, reg_pmp_2_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_9 = {reg_pmp_2_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_12 = {hi_hi_9, reg_pmp_2_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_10 = {reg_pmp_3_cfg_x, reg_pmp_3_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_10 = {lo_hi_10, reg_pmp_3_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_10 = {reg_pmp_3_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_13 = {hi_hi_10, reg_pmp_3_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_11 = {reg_pmp_4_cfg_x, reg_pmp_4_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_11 = {lo_hi_11, reg_pmp_4_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_11 = {reg_pmp_4_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_14 = {hi_hi_11, reg_pmp_4_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_12 = {reg_pmp_5_cfg_x, reg_pmp_5_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_12 = {lo_hi_12, reg_pmp_5_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_12 = {reg_pmp_5_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_15 = {hi_hi_12, reg_pmp_5_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_13 = {reg_pmp_6_cfg_x, reg_pmp_6_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_13 = {lo_hi_13, reg_pmp_6_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_13 = {reg_pmp_6_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_16 = {hi_hi_13, reg_pmp_6_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_14 = {reg_pmp_7_cfg_x, reg_pmp_7_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_14 = {lo_hi_14, reg_pmp_7_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_14 = {reg_pmp_7_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_17 = {hi_hi_14, reg_pmp_7_cfg_a}; // @[package.scala:45:36] wire [15:0] lo_lo_7 = {hi_11, lo_8, hi_10, lo_7}; // @[package.scala:45:{27,36}] wire [15:0] lo_hi_15 = {hi_13, lo_10, hi_12, lo_9}; // @[package.scala:45:{27,36}] wire [31:0] lo_15 = {lo_hi_15, lo_lo_7}; // @[package.scala:45:27] wire [15:0] hi_lo_7 = {hi_15, lo_12, hi_14, lo_11}; // @[package.scala:45:{27,36}] wire [15:0] hi_hi_15 = {hi_17, lo_14, hi_16, lo_13}; // @[package.scala:45:{27,36}] wire [31:0] hi_18 = {hi_hi_15, hi_lo_7}; // @[package.scala:45:27] reg [63:0] reg_custom_0; // @[CSR.scala:798:43] assign io_customCSRs_0_value_0 = reg_custom_0; // @[CSR.scala:377:7, :798:43] wire _reg_custom_read_T = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_1 = io_rw_addr_0 == 12'h7C1; // @[CSR.scala:377:7, :799:50] assign reg_custom_read = _reg_custom_read_T & _reg_custom_read_T_1; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_0_ren_0 = reg_custom_read; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_1; // @[CSR.scala:798:43] assign io_customCSRs_1_value_0 = reg_custom_1; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_1_T_2 = reg_custom_1; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_1_T_6 = reg_custom_1; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_2 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_3 = io_rw_addr_0 == 12'hF12; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_1 = _reg_custom_read_T_2 & _reg_custom_read_T_3; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_1_ren_0 = reg_custom_read_1; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_2; // @[CSR.scala:798:43] assign io_customCSRs_2_value_0 = reg_custom_2; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_2_T_2 = reg_custom_2; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_2_T_6 = reg_custom_2; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_4 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_5 = io_rw_addr_0 == 12'hF11; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_2 = _reg_custom_read_T_4 & _reg_custom_read_T_5; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_2_ren_0 = reg_custom_read_2; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_3; // @[CSR.scala:798:43] assign io_customCSRs_3_value_0 = reg_custom_3; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_3_T_2 = reg_custom_3; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_3_T_6 = reg_custom_3; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_6 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_7 = io_rw_addr_0 == 12'hF13; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_3 = _reg_custom_read_T_6 & _reg_custom_read_T_7; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_3_ren_0 = reg_custom_read_3; // @[CSR.scala:377:7, :799:36] wire [12:0] decoded_addr_addr = {io_status_v_0, io_rw_addr_0}; // @[CSR.scala:377:7, :851:19] wire [11:0] decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22] wire [11:0] decoded_addr_decoded_decoded_invInputs = ~decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [156:0] decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [156:0] decoded_addr_decoded_decoded; // @[pla.scala:81:23] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_150 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_152 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_155 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_156 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_150 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_151 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_152 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_153 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_154 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_150 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_151 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_152 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_153 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_154 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_155 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_156 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_150 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_151 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_152 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_152 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_153 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_154 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_155 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_148 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_150 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_151 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_151 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_152 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_153 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_154 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_148 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_149 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_150 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_151 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_152 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_153 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_154 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_148 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_149 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_146 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_149 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T = {decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = decoded_addr_decoded_decoded_andMatrixOutputs_143_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_153 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_155 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_151 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_153 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_154 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = decoded_addr_decoded_decoded_andMatrixOutputs_139_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_150 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_154 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_156 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = decoded_addr_decoded_decoded_andMatrixOutputs_43_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = decoded_addr_decoded_decoded_andMatrixOutputs_29_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = decoded_addr_decoded_decoded_andMatrixOutputs_109_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_151_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = decoded_addr_decoded_decoded_andMatrixOutputs_151_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_155 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_156 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = decoded_addr_decoded_decoded_andMatrixOutputs_55_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_150 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_151 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_152 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_153 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_154 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = decoded_addr_decoded_decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = decoded_addr_decoded_decoded_andMatrixOutputs_92_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = decoded_addr_decoded_decoded_andMatrixOutputs_128_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = decoded_addr_decoded_decoded_andMatrixOutputs_28_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = decoded_addr_decoded_decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = decoded_addr_decoded_decoded_andMatrixOutputs_95_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = decoded_addr_decoded_decoded_andMatrixOutputs_62_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = decoded_addr_decoded_decoded_andMatrixOutputs_24_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = decoded_addr_decoded_decoded_andMatrixOutputs_120_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = decoded_addr_decoded_decoded_andMatrixOutputs_126_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = decoded_addr_decoded_decoded_andMatrixOutputs_77_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_150 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_149 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_150 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_151 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_152 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_151 = decoded_addr_decoded_decoded_andMatrixOutputs_118_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_152 = decoded_addr_decoded_decoded_andMatrixOutputs_107_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = decoded_addr_decoded_decoded_andMatrixOutputs_85_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = decoded_addr_decoded_decoded_andMatrixOutputs_30_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = decoded_addr_decoded_decoded_andMatrixOutputs_94_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_150 = decoded_addr_decoded_decoded_andMatrixOutputs_71_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = decoded_addr_decoded_decoded_andMatrixOutputs_87_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = decoded_addr_decoded_decoded_andMatrixOutputs_42_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_149 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_151 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = decoded_addr_decoded_decoded_andMatrixOutputs_36_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = decoded_addr_decoded_decoded_andMatrixOutputs_141_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = decoded_addr_decoded_decoded_andMatrixOutputs_58_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = decoded_addr_decoded_decoded_andMatrixOutputs_108_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = decoded_addr_decoded_decoded_andMatrixOutputs_113_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = decoded_addr_decoded_decoded_andMatrixOutputs_7_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = decoded_addr_decoded_decoded_andMatrixOutputs_49_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = decoded_addr_decoded_decoded_andMatrixOutputs_146_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = decoded_addr_decoded_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = decoded_addr_decoded_decoded_andMatrixOutputs_123_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = decoded_addr_decoded_decoded_andMatrixOutputs_125_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = decoded_addr_decoded_decoded_andMatrixOutputs_144_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = decoded_addr_decoded_decoded_andMatrixOutputs_89_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = decoded_addr_decoded_decoded_andMatrixOutputs_8_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_152 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_153 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_154 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_155 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_156 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = decoded_addr_decoded_decoded_andMatrixOutputs_64_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = decoded_addr_decoded_decoded_andMatrixOutputs_86_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = decoded_addr_decoded_decoded_andMatrixOutputs_134_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = decoded_addr_decoded_decoded_andMatrixOutputs_17_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = decoded_addr_decoded_decoded_andMatrixOutputs_90_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = decoded_addr_decoded_decoded_andMatrixOutputs_138_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = decoded_addr_decoded_decoded_andMatrixOutputs_147_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = decoded_addr_decoded_decoded_andMatrixOutputs_22_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = decoded_addr_decoded_decoded_andMatrixOutputs_97_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = decoded_addr_decoded_decoded_andMatrixOutputs_68_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = decoded_addr_decoded_decoded_andMatrixOutputs_38_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = decoded_addr_decoded_decoded_andMatrixOutputs_35_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = decoded_addr_decoded_decoded_andMatrixOutputs_66_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = decoded_addr_decoded_decoded_andMatrixOutputs_41_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = decoded_addr_decoded_decoded_andMatrixOutputs_34_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = decoded_addr_decoded_decoded_andMatrixOutputs_149_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = decoded_addr_decoded_decoded_andMatrixOutputs_69_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = decoded_addr_decoded_decoded_andMatrixOutputs_110_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = decoded_addr_decoded_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = decoded_addr_decoded_decoded_andMatrixOutputs_127_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = decoded_addr_decoded_decoded_andMatrixOutputs_124_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = decoded_addr_decoded_decoded_andMatrixOutputs_70_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = decoded_addr_decoded_decoded_andMatrixOutputs_50_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = decoded_addr_decoded_decoded_andMatrixOutputs_10_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = decoded_addr_decoded_decoded_andMatrixOutputs_47_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = decoded_addr_decoded_decoded_andMatrixOutputs_18_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = decoded_addr_decoded_decoded_andMatrixOutputs_91_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = decoded_addr_decoded_decoded_andMatrixOutputs_60_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = decoded_addr_decoded_decoded_andMatrixOutputs_88_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = decoded_addr_decoded_decoded_andMatrixOutputs_103_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = decoded_addr_decoded_decoded_andMatrixOutputs_115_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = decoded_addr_decoded_decoded_andMatrixOutputs_96_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = decoded_addr_decoded_decoded_andMatrixOutputs_142_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = decoded_addr_decoded_decoded_andMatrixOutputs_75_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = decoded_addr_decoded_decoded_andMatrixOutputs_44_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_150_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = decoded_addr_decoded_decoded_andMatrixOutputs_150_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = decoded_addr_decoded_decoded_andMatrixOutputs_101_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = decoded_addr_decoded_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_156_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = decoded_addr_decoded_decoded_andMatrixOutputs_156_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_147 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_148 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_145 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_146 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_147 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_148 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_156 = decoded_addr_decoded_decoded_andMatrixOutputs_2_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_152_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_155 = decoded_addr_decoded_decoded_andMatrixOutputs_152_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_154 = decoded_addr_decoded_decoded_andMatrixOutputs_133_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_153 = decoded_addr_decoded_decoded_andMatrixOutputs_59_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = decoded_addr_decoded_decoded_andMatrixOutputs_3_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = decoded_addr_decoded_decoded_andMatrixOutputs_52_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = decoded_addr_decoded_decoded_andMatrixOutputs_23_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = decoded_addr_decoded_decoded_andMatrixOutputs_12_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_143 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_144 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_132 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_133 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_134 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_135 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = decoded_addr_decoded_decoded_andMatrixOutputs_79_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = decoded_addr_decoded_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = decoded_addr_decoded_decoded_andMatrixOutputs_98_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = decoded_addr_decoded_decoded_andMatrixOutputs_26_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = decoded_addr_decoded_decoded_andMatrixOutputs_129_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_153_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = decoded_addr_decoded_decoded_andMatrixOutputs_153_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = decoded_addr_decoded_decoded_andMatrixOutputs_80_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = decoded_addr_decoded_decoded_andMatrixOutputs_145_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = decoded_addr_decoded_decoded_andMatrixOutputs_46_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = decoded_addr_decoded_decoded_andMatrixOutputs_33_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = decoded_addr_decoded_decoded_andMatrixOutputs_65_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = decoded_addr_decoded_decoded_andMatrixOutputs_61_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = decoded_addr_decoded_decoded_andMatrixOutputs_137_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = decoded_addr_decoded_decoded_andMatrixOutputs_9_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = decoded_addr_decoded_decoded_andMatrixOutputs_119_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = decoded_addr_decoded_decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = decoded_addr_decoded_decoded_andMatrixOutputs_74_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = decoded_addr_decoded_decoded_andMatrixOutputs_135_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = decoded_addr_decoded_decoded_andMatrixOutputs_105_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = decoded_addr_decoded_decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = decoded_addr_decoded_decoded_andMatrixOutputs_31_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = decoded_addr_decoded_decoded_andMatrixOutputs_16_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = decoded_addr_decoded_decoded_andMatrixOutputs_148_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = decoded_addr_decoded_decoded_andMatrixOutputs_136_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = decoded_addr_decoded_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = decoded_addr_decoded_decoded_andMatrixOutputs_93_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = decoded_addr_decoded_decoded_andMatrixOutputs_100_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = decoded_addr_decoded_decoded_andMatrixOutputs_63_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = decoded_addr_decoded_decoded_andMatrixOutputs_99_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = decoded_addr_decoded_decoded_andMatrixOutputs_57_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = decoded_addr_decoded_decoded_andMatrixOutputs_131_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = decoded_addr_decoded_decoded_andMatrixOutputs_51_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = decoded_addr_decoded_decoded_andMatrixOutputs_54_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = decoded_addr_decoded_decoded_andMatrixOutputs_20_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = decoded_addr_decoded_decoded_andMatrixOutputs_111_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = decoded_addr_decoded_decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = decoded_addr_decoded_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = decoded_addr_decoded_decoded_andMatrixOutputs_32_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = decoded_addr_decoded_decoded_andMatrixOutputs_132_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = decoded_addr_decoded_decoded_andMatrixOutputs_37_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = decoded_addr_decoded_decoded_andMatrixOutputs_76_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = decoded_addr_decoded_decoded_andMatrixOutputs_56_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = decoded_addr_decoded_decoded_andMatrixOutputs_140_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = decoded_addr_decoded_decoded_andMatrixOutputs_39_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = decoded_addr_decoded_decoded_andMatrixOutputs_25_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = decoded_addr_decoded_decoded_andMatrixOutputs_67_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = decoded_addr_decoded_decoded_andMatrixOutputs_19_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = decoded_addr_decoded_decoded_andMatrixOutputs_116_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = decoded_addr_decoded_decoded_andMatrixOutputs_112_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_155_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = decoded_addr_decoded_decoded_andMatrixOutputs_155_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = decoded_addr_decoded_decoded_andMatrixOutputs_72_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = decoded_addr_decoded_decoded_andMatrixOutputs_106_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = decoded_addr_decoded_decoded_andMatrixOutputs_102_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = decoded_addr_decoded_decoded_andMatrixOutputs_130_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = decoded_addr_decoded_decoded_andMatrixOutputs_122_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = decoded_addr_decoded_decoded_andMatrixOutputs_48_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = decoded_addr_decoded_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = decoded_addr_decoded_decoded_andMatrixOutputs_53_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = decoded_addr_decoded_decoded_andMatrixOutputs_45_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = decoded_addr_decoded_decoded_andMatrixOutputs_73_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = decoded_addr_decoded_decoded_andMatrixOutputs_81_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = decoded_addr_decoded_decoded_andMatrixOutputs_114_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = decoded_addr_decoded_decoded_andMatrixOutputs_27_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_148}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_148}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_150}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_150}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = decoded_addr_decoded_decoded_andMatrixOutputs_121_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_143}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_149}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_151}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_154_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = decoded_addr_decoded_decoded_andMatrixOutputs_154_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_144}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_150}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_151}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_152}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = decoded_addr_decoded_decoded_andMatrixOutputs_104_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_145}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_132}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_151}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_152}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_153}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = decoded_addr_decoded_decoded_andMatrixOutputs_40_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_146}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_133}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_152}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_153}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_154}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = decoded_addr_decoded_decoded_andMatrixOutputs_13_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_147}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_134}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_153}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_155 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_154}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_155 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_155 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_155 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = decoded_addr_decoded_decoded_andMatrixOutputs_84_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_148}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_135}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_155 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_154}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_156 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_155}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_156 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_156}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_156 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_156, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_156 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_156, decoded_addr_decoded_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T = decoded_addr_decoded_decoded_andMatrixOutputs_78_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_13, _decoded_addr_decoded_decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_15, _decoded_addr_decoded_decoded_orMatrixOutputs_T_14}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_18, _decoded_addr_decoded_decoded_orMatrixOutputs_T_17}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_20, _decoded_addr_decoded_decoded_orMatrixOutputs_T_19}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_21}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_25, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_28, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_30, _decoded_addr_decoded_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_33, _decoded_addr_decoded_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_31}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_35, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_36}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [19:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [38:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_44, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_47, _decoded_addr_decoded_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_45}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_49, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_52, _decoded_addr_decoded_decoded_orMatrixOutputs_T_51}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_54, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_55}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_62, _decoded_addr_decoded_decoded_orMatrixOutputs_T_61}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_64, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_67, _decoded_addr_decoded_decoded_orMatrixOutputs_T_66}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_72, _decoded_addr_decoded_decoded_orMatrixOutputs_T_71}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_77, _decoded_addr_decoded_decoded_orMatrixOutputs_T_76}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [19:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [38:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36] wire [77:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_79, _decoded_addr_decoded_decoded_orMatrixOutputs_T_78}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_81, _decoded_addr_decoded_decoded_orMatrixOutputs_T_80}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_86, _decoded_addr_decoded_decoded_orMatrixOutputs_T_85}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_88, _decoded_addr_decoded_decoded_orMatrixOutputs_T_87}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_91, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_89}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_93, _decoded_addr_decoded_decoded_orMatrixOutputs_T_92}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_94}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_101, _decoded_addr_decoded_decoded_orMatrixOutputs_T_100}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_111, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_116, _decoded_addr_decoded_decoded_orMatrixOutputs_T_115}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [19:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [38:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_118, _decoded_addr_decoded_decoded_orMatrixOutputs_T_117}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_121, _decoded_addr_decoded_decoded_orMatrixOutputs_T_120}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_123, _decoded_addr_decoded_decoded_orMatrixOutputs_T_122}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_126, _decoded_addr_decoded_decoded_orMatrixOutputs_T_125}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_128, _decoded_addr_decoded_decoded_orMatrixOutputs_T_127}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_131, _decoded_addr_decoded_decoded_orMatrixOutputs_T_130}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_133, _decoded_addr_decoded_decoded_orMatrixOutputs_T_132}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_134}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [19:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_138, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_139}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_143, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_144}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_148, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_151, _decoded_addr_decoded_decoded_orMatrixOutputs_T_150}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_149}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_153, _decoded_addr_decoded_decoded_orMatrixOutputs_T_152}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_156, _decoded_addr_decoded_decoded_orMatrixOutputs_T_155}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_154}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [19:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [39:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:102:36] wire [78:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [156:0] decoded_addr_decoded_decoded_orMatrixOutputs = {decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T = decoded_addr_decoded_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = decoded_addr_decoded_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = decoded_addr_decoded_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = decoded_addr_decoded_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = decoded_addr_decoded_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = decoded_addr_decoded_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = decoded_addr_decoded_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = decoded_addr_decoded_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = decoded_addr_decoded_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = decoded_addr_decoded_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = decoded_addr_decoded_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = decoded_addr_decoded_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = decoded_addr_decoded_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = decoded_addr_decoded_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = decoded_addr_decoded_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = decoded_addr_decoded_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = decoded_addr_decoded_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = decoded_addr_decoded_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = decoded_addr_decoded_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = decoded_addr_decoded_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = decoded_addr_decoded_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = decoded_addr_decoded_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = decoded_addr_decoded_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = decoded_addr_decoded_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = decoded_addr_decoded_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = decoded_addr_decoded_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = decoded_addr_decoded_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = decoded_addr_decoded_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = decoded_addr_decoded_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = decoded_addr_decoded_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = decoded_addr_decoded_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = decoded_addr_decoded_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = decoded_addr_decoded_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = decoded_addr_decoded_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = decoded_addr_decoded_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = decoded_addr_decoded_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = decoded_addr_decoded_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = decoded_addr_decoded_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = decoded_addr_decoded_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = decoded_addr_decoded_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = decoded_addr_decoded_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = decoded_addr_decoded_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = decoded_addr_decoded_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = decoded_addr_decoded_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = decoded_addr_decoded_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = decoded_addr_decoded_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = decoded_addr_decoded_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = decoded_addr_decoded_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = decoded_addr_decoded_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = decoded_addr_decoded_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = decoded_addr_decoded_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = decoded_addr_decoded_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = decoded_addr_decoded_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = decoded_addr_decoded_decoded_orMatrixOutputs[53]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = decoded_addr_decoded_decoded_orMatrixOutputs[54]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = decoded_addr_decoded_decoded_orMatrixOutputs[55]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = decoded_addr_decoded_decoded_orMatrixOutputs[56]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = decoded_addr_decoded_decoded_orMatrixOutputs[57]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = decoded_addr_decoded_decoded_orMatrixOutputs[58]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = decoded_addr_decoded_decoded_orMatrixOutputs[59]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = decoded_addr_decoded_decoded_orMatrixOutputs[60]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = decoded_addr_decoded_decoded_orMatrixOutputs[61]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = decoded_addr_decoded_decoded_orMatrixOutputs[62]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = decoded_addr_decoded_decoded_orMatrixOutputs[63]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = decoded_addr_decoded_decoded_orMatrixOutputs[64]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = decoded_addr_decoded_decoded_orMatrixOutputs[65]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = decoded_addr_decoded_decoded_orMatrixOutputs[66]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = decoded_addr_decoded_decoded_orMatrixOutputs[67]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = decoded_addr_decoded_decoded_orMatrixOutputs[68]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = decoded_addr_decoded_decoded_orMatrixOutputs[69]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = decoded_addr_decoded_decoded_orMatrixOutputs[70]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = decoded_addr_decoded_decoded_orMatrixOutputs[71]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = decoded_addr_decoded_decoded_orMatrixOutputs[72]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = decoded_addr_decoded_decoded_orMatrixOutputs[73]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = decoded_addr_decoded_decoded_orMatrixOutputs[74]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = decoded_addr_decoded_decoded_orMatrixOutputs[75]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = decoded_addr_decoded_decoded_orMatrixOutputs[76]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = decoded_addr_decoded_decoded_orMatrixOutputs[77]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = decoded_addr_decoded_decoded_orMatrixOutputs[78]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = decoded_addr_decoded_decoded_orMatrixOutputs[79]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = decoded_addr_decoded_decoded_orMatrixOutputs[80]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = decoded_addr_decoded_decoded_orMatrixOutputs[81]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = decoded_addr_decoded_decoded_orMatrixOutputs[82]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = decoded_addr_decoded_decoded_orMatrixOutputs[83]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = decoded_addr_decoded_decoded_orMatrixOutputs[84]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = decoded_addr_decoded_decoded_orMatrixOutputs[85]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = decoded_addr_decoded_decoded_orMatrixOutputs[86]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = decoded_addr_decoded_decoded_orMatrixOutputs[87]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = decoded_addr_decoded_decoded_orMatrixOutputs[88]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = decoded_addr_decoded_decoded_orMatrixOutputs[89]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = decoded_addr_decoded_decoded_orMatrixOutputs[90]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = decoded_addr_decoded_decoded_orMatrixOutputs[91]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = decoded_addr_decoded_decoded_orMatrixOutputs[92]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = decoded_addr_decoded_decoded_orMatrixOutputs[93]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = decoded_addr_decoded_decoded_orMatrixOutputs[94]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = decoded_addr_decoded_decoded_orMatrixOutputs[95]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = decoded_addr_decoded_decoded_orMatrixOutputs[96]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = decoded_addr_decoded_decoded_orMatrixOutputs[97]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = decoded_addr_decoded_decoded_orMatrixOutputs[98]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = decoded_addr_decoded_decoded_orMatrixOutputs[99]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = decoded_addr_decoded_decoded_orMatrixOutputs[100]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = decoded_addr_decoded_decoded_orMatrixOutputs[101]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = decoded_addr_decoded_decoded_orMatrixOutputs[102]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = decoded_addr_decoded_decoded_orMatrixOutputs[103]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = decoded_addr_decoded_decoded_orMatrixOutputs[104]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = decoded_addr_decoded_decoded_orMatrixOutputs[105]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = decoded_addr_decoded_decoded_orMatrixOutputs[106]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = decoded_addr_decoded_decoded_orMatrixOutputs[107]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = decoded_addr_decoded_decoded_orMatrixOutputs[108]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = decoded_addr_decoded_decoded_orMatrixOutputs[109]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = decoded_addr_decoded_decoded_orMatrixOutputs[110]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = decoded_addr_decoded_decoded_orMatrixOutputs[111]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = decoded_addr_decoded_decoded_orMatrixOutputs[112]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = decoded_addr_decoded_decoded_orMatrixOutputs[113]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = decoded_addr_decoded_decoded_orMatrixOutputs[114]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = decoded_addr_decoded_decoded_orMatrixOutputs[115]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = decoded_addr_decoded_decoded_orMatrixOutputs[116]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = decoded_addr_decoded_decoded_orMatrixOutputs[117]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = decoded_addr_decoded_decoded_orMatrixOutputs[118]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = decoded_addr_decoded_decoded_orMatrixOutputs[119]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = decoded_addr_decoded_decoded_orMatrixOutputs[120]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = decoded_addr_decoded_decoded_orMatrixOutputs[121]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = decoded_addr_decoded_decoded_orMatrixOutputs[122]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = decoded_addr_decoded_decoded_orMatrixOutputs[123]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = decoded_addr_decoded_decoded_orMatrixOutputs[124]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = decoded_addr_decoded_decoded_orMatrixOutputs[125]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = decoded_addr_decoded_decoded_orMatrixOutputs[126]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = decoded_addr_decoded_decoded_orMatrixOutputs[127]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = decoded_addr_decoded_decoded_orMatrixOutputs[128]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = decoded_addr_decoded_decoded_orMatrixOutputs[129]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = decoded_addr_decoded_decoded_orMatrixOutputs[130]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = decoded_addr_decoded_decoded_orMatrixOutputs[131]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = decoded_addr_decoded_decoded_orMatrixOutputs[132]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = decoded_addr_decoded_decoded_orMatrixOutputs[133]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = decoded_addr_decoded_decoded_orMatrixOutputs[134]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = decoded_addr_decoded_decoded_orMatrixOutputs[135]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = decoded_addr_decoded_decoded_orMatrixOutputs[136]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = decoded_addr_decoded_decoded_orMatrixOutputs[137]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = decoded_addr_decoded_decoded_orMatrixOutputs[138]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = decoded_addr_decoded_decoded_orMatrixOutputs[139]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = decoded_addr_decoded_decoded_orMatrixOutputs[140]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = decoded_addr_decoded_decoded_orMatrixOutputs[141]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = decoded_addr_decoded_decoded_orMatrixOutputs[142]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = decoded_addr_decoded_decoded_orMatrixOutputs[143]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = decoded_addr_decoded_decoded_orMatrixOutputs[144]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = decoded_addr_decoded_decoded_orMatrixOutputs[145]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = decoded_addr_decoded_decoded_orMatrixOutputs[146]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = decoded_addr_decoded_decoded_orMatrixOutputs[147]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = decoded_addr_decoded_decoded_orMatrixOutputs[148]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = decoded_addr_decoded_decoded_orMatrixOutputs[149]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_150 = decoded_addr_decoded_decoded_orMatrixOutputs[150]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_151 = decoded_addr_decoded_decoded_orMatrixOutputs[151]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_152 = decoded_addr_decoded_decoded_orMatrixOutputs[152]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_153 = decoded_addr_decoded_decoded_orMatrixOutputs[153]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_154 = decoded_addr_decoded_decoded_orMatrixOutputs[154]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_155 = decoded_addr_decoded_decoded_orMatrixOutputs[155]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_156 = decoded_addr_decoded_decoded_orMatrixOutputs[156]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_13, _decoded_addr_decoded_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_15, _decoded_addr_decoded_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_18, _decoded_addr_decoded_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_20, _decoded_addr_decoded_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_25, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_28, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_30, _decoded_addr_decoded_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_33, _decoded_addr_decoded_decoded_invMatrixOutputs_T_32}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_35, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [19:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [38:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_44, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_47, _decoded_addr_decoded_decoded_invMatrixOutputs_T_46}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_45}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_49, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_52, _decoded_addr_decoded_decoded_invMatrixOutputs_T_51}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_50}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_54, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_55}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_62, _decoded_addr_decoded_decoded_invMatrixOutputs_T_61}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_64, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_67, _decoded_addr_decoded_decoded_invMatrixOutputs_T_66}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_72, _decoded_addr_decoded_decoded_invMatrixOutputs_T_71}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_77, _decoded_addr_decoded_decoded_invMatrixOutputs_T_76}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [19:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [38:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [77:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_79, _decoded_addr_decoded_decoded_invMatrixOutputs_T_78}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_81, _decoded_addr_decoded_decoded_invMatrixOutputs_T_80}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_86, _decoded_addr_decoded_decoded_invMatrixOutputs_T_85}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_88, _decoded_addr_decoded_decoded_invMatrixOutputs_T_87}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_91, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_89}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_93, _decoded_addr_decoded_decoded_invMatrixOutputs_T_92}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_94}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_101, _decoded_addr_decoded_decoded_invMatrixOutputs_T_100}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_111, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_116, _decoded_addr_decoded_decoded_invMatrixOutputs_T_115}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [19:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [38:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_118, _decoded_addr_decoded_decoded_invMatrixOutputs_T_117}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_121, _decoded_addr_decoded_decoded_invMatrixOutputs_T_120}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_123, _decoded_addr_decoded_decoded_invMatrixOutputs_T_122}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_126, _decoded_addr_decoded_decoded_invMatrixOutputs_T_125}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_128, _decoded_addr_decoded_decoded_invMatrixOutputs_T_127}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_131, _decoded_addr_decoded_decoded_invMatrixOutputs_T_130}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_133, _decoded_addr_decoded_decoded_invMatrixOutputs_T_132}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_134}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [19:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_138, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_139}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_143, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_144}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_148, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_151, _decoded_addr_decoded_decoded_invMatrixOutputs_T_150}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_149}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_153, _decoded_addr_decoded_decoded_invMatrixOutputs_T_152}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_156, _decoded_addr_decoded_decoded_invMatrixOutputs_T_155}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_154}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [19:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [39:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [78:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded_invMatrixOutputs = {decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded = decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoded_addr_decoded_decoded_plaInput = decoded_addr_addr[11:0]; // @[pla.scala:77:22] wire decoded_addr_decoded_0 = decoded_addr_decoded_decoded[156]; // @[pla.scala:81:23] wire decoded_addr_101_2 = decoded_addr_decoded_0; // @[Decode.scala:50:77] wire decoded_addr_decoded_1 = decoded_addr_decoded_decoded[155]; // @[pla.scala:81:23] wire decoded_addr_57_2 = decoded_addr_decoded_1; // @[Decode.scala:50:77] wire decoded_addr_decoded_2 = decoded_addr_decoded_decoded[154]; // @[pla.scala:81:23] wire decoded_addr_11_2 = decoded_addr_decoded_2; // @[Decode.scala:50:77] wire decoded_addr_decoded_3 = decoded_addr_decoded_decoded[153]; // @[pla.scala:81:23] wire decoded_addr_122_2 = decoded_addr_decoded_3; // @[Decode.scala:50:77] wire decoded_addr_decoded_4 = decoded_addr_decoded_decoded[152]; // @[pla.scala:81:23] wire decoded_addr_98_2 = decoded_addr_decoded_4; // @[Decode.scala:50:77] wire decoded_addr_decoded_5 = decoded_addr_decoded_decoded[151]; // @[pla.scala:81:23] wire decoded_addr_104_2 = decoded_addr_decoded_5; // @[Decode.scala:50:77] wire decoded_addr_decoded_6 = decoded_addr_decoded_decoded[150]; // @[pla.scala:81:23] wire decoded_addr_75_2 = decoded_addr_decoded_6; // @[Decode.scala:50:77] wire decoded_addr_decoded_7 = decoded_addr_decoded_decoded[149]; // @[pla.scala:81:23] wire decoded_addr_112_2 = decoded_addr_decoded_7; // @[Decode.scala:50:77] wire decoded_addr_decoded_8 = decoded_addr_decoded_decoded[148]; // @[pla.scala:81:23] wire decoded_addr_79_2 = decoded_addr_decoded_8; // @[Decode.scala:50:77] wire decoded_addr_decoded_9 = decoded_addr_decoded_decoded[147]; // @[pla.scala:81:23] wire decoded_addr_135_2 = decoded_addr_decoded_9; // @[Decode.scala:50:77] wire decoded_addr_decoded_10 = decoded_addr_decoded_decoded[146]; // @[pla.scala:81:23] wire decoded_addr_138_2 = decoded_addr_decoded_10; // @[Decode.scala:50:77] wire decoded_addr_decoded_11 = decoded_addr_decoded_decoded[145]; // @[pla.scala:81:23] wire decoded_addr_142_2 = decoded_addr_decoded_11; // @[Decode.scala:50:77] wire decoded_addr_decoded_12 = decoded_addr_decoded_decoded[144]; // @[pla.scala:81:23] wire decoded_addr_30_2 = decoded_addr_decoded_12; // @[Decode.scala:50:77] wire decoded_addr_decoded_13 = decoded_addr_decoded_decoded[143]; // @[pla.scala:81:23] wire decoded_addr_137_2 = decoded_addr_decoded_13; // @[Decode.scala:50:77] wire decoded_addr_decoded_14 = decoded_addr_decoded_decoded[142]; // @[pla.scala:81:23] wire decoded_addr_50_2 = decoded_addr_decoded_14; // @[Decode.scala:50:77] wire decoded_addr_decoded_15 = decoded_addr_decoded_decoded[141]; // @[pla.scala:81:23] wire decoded_addr_93_2 = decoded_addr_decoded_15; // @[Decode.scala:50:77] wire decoded_addr_decoded_16 = decoded_addr_decoded_decoded[140]; // @[pla.scala:81:23] wire decoded_addr_59_2 = decoded_addr_decoded_16; // @[Decode.scala:50:77] wire decoded_addr_decoded_17 = decoded_addr_decoded_decoded[139]; // @[pla.scala:81:23] wire decoded_addr_37_2 = decoded_addr_decoded_17; // @[Decode.scala:50:77] wire decoded_addr_decoded_18 = decoded_addr_decoded_decoded[138]; // @[pla.scala:81:23] wire decoded_addr_71_2 = decoded_addr_decoded_18; // @[Decode.scala:50:77] wire decoded_addr_decoded_19 = decoded_addr_decoded_decoded[137]; // @[pla.scala:81:23] wire decoded_addr_103_2 = decoded_addr_decoded_19; // @[Decode.scala:50:77] wire decoded_addr_decoded_20 = decoded_addr_decoded_decoded[136]; // @[pla.scala:81:23] wire decoded_addr_60_2 = decoded_addr_decoded_20; // @[Decode.scala:50:77] wire decoded_addr_decoded_21 = decoded_addr_decoded_decoded[135]; // @[pla.scala:81:23] wire decoded_addr_6_2 = decoded_addr_decoded_21; // @[Decode.scala:50:77] wire decoded_addr_decoded_22 = decoded_addr_decoded_decoded[134]; // @[pla.scala:81:23] wire decoded_addr_150_2 = decoded_addr_decoded_22; // @[Decode.scala:50:77] wire decoded_addr_decoded_23 = decoded_addr_decoded_decoded[133]; // @[pla.scala:81:23] wire decoded_addr_134_2 = decoded_addr_decoded_23; // @[Decode.scala:50:77] wire decoded_addr_decoded_24 = decoded_addr_decoded_decoded[132]; // @[pla.scala:81:23] wire decoded_addr_54_2 = decoded_addr_decoded_24; // @[Decode.scala:50:77] wire decoded_addr_decoded_25 = decoded_addr_decoded_decoded[131]; // @[pla.scala:81:23] wire decoded_addr_131_2 = decoded_addr_decoded_25; // @[Decode.scala:50:77] wire decoded_addr_decoded_26 = decoded_addr_decoded_decoded[130]; // @[pla.scala:81:23] wire decoded_addr_91_2 = decoded_addr_decoded_26; // @[Decode.scala:50:77] wire decoded_addr_decoded_27 = decoded_addr_decoded_decoded[129]; // @[pla.scala:81:23] wire decoded_addr_136_2 = decoded_addr_decoded_27; // @[Decode.scala:50:77] wire decoded_addr_decoded_28 = decoded_addr_decoded_decoded[128]; // @[pla.scala:81:23] wire decoded_addr_107_2 = decoded_addr_decoded_28; // @[Decode.scala:50:77] wire decoded_addr_decoded_29 = decoded_addr_decoded_decoded[127]; // @[pla.scala:81:23] wire decoded_addr_125_2 = decoded_addr_decoded_29; // @[Decode.scala:50:77] wire decoded_addr_decoded_30 = decoded_addr_decoded_decoded[126]; // @[pla.scala:81:23] wire decoded_addr_153_2 = decoded_addr_decoded_30; // @[Decode.scala:50:77] wire decoded_addr_decoded_31 = decoded_addr_decoded_decoded[125]; // @[pla.scala:81:23] wire decoded_addr_18_2 = decoded_addr_decoded_31; // @[Decode.scala:50:77] wire decoded_addr_decoded_32 = decoded_addr_decoded_decoded[124]; // @[pla.scala:81:23] wire decoded_addr_28_2 = decoded_addr_decoded_32; // @[Decode.scala:50:77] wire decoded_addr_decoded_33 = decoded_addr_decoded_decoded[123]; // @[pla.scala:81:23] wire decoded_addr_86_2 = decoded_addr_decoded_33; // @[Decode.scala:50:77] wire decoded_addr_decoded_34 = decoded_addr_decoded_decoded[122]; // @[pla.scala:81:23] wire decoded_addr_53_2 = decoded_addr_decoded_34; // @[Decode.scala:50:77] wire decoded_addr_decoded_35 = decoded_addr_decoded_decoded[121]; // @[pla.scala:81:23] wire decoded_addr_151_2 = decoded_addr_decoded_35; // @[Decode.scala:50:77] wire decoded_addr_decoded_36 = decoded_addr_decoded_decoded[120]; // @[pla.scala:81:23] wire decoded_addr_73_2 = decoded_addr_decoded_36; // @[Decode.scala:50:77] wire decoded_addr_decoded_37 = decoded_addr_decoded_decoded[119]; // @[pla.scala:81:23] wire decoded_addr_115_2 = decoded_addr_decoded_37; // @[Decode.scala:50:77] wire decoded_addr_decoded_38 = decoded_addr_decoded_decoded[118]; // @[pla.scala:81:23] wire decoded_addr_85_2 = decoded_addr_decoded_38; // @[Decode.scala:50:77] wire decoded_addr_decoded_39 = decoded_addr_decoded_decoded[117]; // @[pla.scala:81:23] wire decoded_addr_32_2 = decoded_addr_decoded_39; // @[Decode.scala:50:77] wire decoded_addr_decoded_40 = decoded_addr_decoded_decoded[116]; // @[pla.scala:81:23] wire decoded_addr_0_2 = decoded_addr_decoded_40; // @[Decode.scala:50:77] wire decoded_addr_decoded_41 = decoded_addr_decoded_decoded[115]; // @[pla.scala:81:23] wire decoded_addr_62_2 = decoded_addr_decoded_41; // @[Decode.scala:50:77] wire decoded_addr_decoded_42 = decoded_addr_decoded_decoded[114]; // @[pla.scala:81:23] wire decoded_addr_144_2 = decoded_addr_decoded_42; // @[Decode.scala:50:77] wire decoded_addr_decoded_43 = decoded_addr_decoded_decoded[113]; // @[pla.scala:81:23] wire decoded_addr_130_2 = decoded_addr_decoded_43; // @[Decode.scala:50:77] wire decoded_addr_decoded_44 = decoded_addr_decoded_decoded[112]; // @[pla.scala:81:23] wire decoded_addr_77_2 = decoded_addr_decoded_44; // @[Decode.scala:50:77] wire decoded_addr_decoded_45 = decoded_addr_decoded_decoded[111]; // @[pla.scala:81:23] wire decoded_addr_120_2 = decoded_addr_decoded_45; // @[Decode.scala:50:77] wire decoded_addr_decoded_46 = decoded_addr_decoded_decoded[110]; // @[pla.scala:81:23] wire decoded_addr_94_2 = decoded_addr_decoded_46; // @[Decode.scala:50:77] wire decoded_addr_decoded_47 = decoded_addr_decoded_decoded[109]; // @[pla.scala:81:23] wire decoded_addr_117_2 = decoded_addr_decoded_47; // @[Decode.scala:50:77] wire decoded_addr_decoded_48 = decoded_addr_decoded_decoded[108]; // @[pla.scala:81:23] wire decoded_addr_1_2 = decoded_addr_decoded_48; // @[Decode.scala:50:77] wire decoded_addr_decoded_49 = decoded_addr_decoded_decoded[107]; // @[pla.scala:81:23] wire decoded_addr_17_2 = decoded_addr_decoded_49; // @[Decode.scala:50:77] wire decoded_addr_decoded_50 = decoded_addr_decoded_decoded[106]; // @[pla.scala:81:23] wire decoded_addr_81_2 = decoded_addr_decoded_50; // @[Decode.scala:50:77] wire decoded_addr_decoded_51 = decoded_addr_decoded_decoded[105]; // @[pla.scala:81:23] wire decoded_addr_40_2 = decoded_addr_decoded_51; // @[Decode.scala:50:77] wire decoded_addr_decoded_52 = decoded_addr_decoded_decoded[104]; // @[pla.scala:81:23] wire decoded_addr_52_2 = decoded_addr_decoded_52; // @[Decode.scala:50:77] wire decoded_addr_decoded_53 = decoded_addr_decoded_decoded[103]; // @[pla.scala:81:23] wire decoded_addr_113_2 = decoded_addr_decoded_53; // @[Decode.scala:50:77] wire decoded_addr_decoded_54 = decoded_addr_decoded_decoded[102]; // @[pla.scala:81:23] wire decoded_addr_95_2 = decoded_addr_decoded_54; // @[Decode.scala:50:77] wire decoded_addr_decoded_55 = decoded_addr_decoded_decoded[101]; // @[pla.scala:81:23] wire decoded_addr_84_2 = decoded_addr_decoded_55; // @[Decode.scala:50:77] wire decoded_addr_decoded_56 = decoded_addr_decoded_decoded[100]; // @[pla.scala:81:23] wire decoded_addr_70_2 = decoded_addr_decoded_56; // @[Decode.scala:50:77] wire decoded_addr_decoded_57 = decoded_addr_decoded_decoded[99]; // @[pla.scala:81:23] wire decoded_addr_109_2 = decoded_addr_decoded_57; // @[Decode.scala:50:77] wire decoded_addr_decoded_58 = decoded_addr_decoded_decoded[98]; // @[pla.scala:81:23] wire decoded_addr_126_2 = decoded_addr_decoded_58; // @[Decode.scala:50:77] wire decoded_addr_decoded_59 = decoded_addr_decoded_decoded[97]; // @[pla.scala:81:23] wire decoded_addr_25_2 = decoded_addr_decoded_59; // @[Decode.scala:50:77] wire decoded_addr_decoded_60 = decoded_addr_decoded_decoded[96]; // @[pla.scala:81:23] wire decoded_addr_128_2 = decoded_addr_decoded_60; // @[Decode.scala:50:77] wire decoded_addr_decoded_61 = decoded_addr_decoded_decoded[95]; // @[pla.scala:81:23] wire decoded_addr_27_2 = decoded_addr_decoded_61; // @[Decode.scala:50:77] wire decoded_addr_decoded_62 = decoded_addr_decoded_decoded[94]; // @[pla.scala:81:23] wire decoded_addr_133_2 = decoded_addr_decoded_62; // @[Decode.scala:50:77] wire decoded_addr_decoded_63 = decoded_addr_decoded_decoded[93]; // @[pla.scala:81:23] wire decoded_addr_8_2 = decoded_addr_decoded_63; // @[Decode.scala:50:77] wire decoded_addr_decoded_64 = decoded_addr_decoded_decoded[92]; // @[pla.scala:81:23] wire decoded_addr_65_2 = decoded_addr_decoded_64; // @[Decode.scala:50:77] wire decoded_addr_decoded_65 = decoded_addr_decoded_decoded[91]; // @[pla.scala:81:23] wire decoded_addr_80_2 = decoded_addr_decoded_65; // @[Decode.scala:50:77] wire decoded_addr_decoded_66 = decoded_addr_decoded_decoded[90]; // @[pla.scala:81:23] wire decoded_addr_47_2 = decoded_addr_decoded_66; // @[Decode.scala:50:77] wire decoded_addr_decoded_67 = decoded_addr_decoded_decoded[89]; // @[pla.scala:81:23] wire decoded_addr_116_2 = decoded_addr_decoded_67; // @[Decode.scala:50:77] wire decoded_addr_decoded_68 = decoded_addr_decoded_decoded[88]; // @[pla.scala:81:23] wire decoded_addr_63_2 = decoded_addr_decoded_68; // @[Decode.scala:50:77] wire decoded_addr_decoded_69 = decoded_addr_decoded_decoded[87]; // @[pla.scala:81:23] wire decoded_addr_96_2 = decoded_addr_decoded_69; // @[Decode.scala:50:77] wire decoded_addr_decoded_70 = decoded_addr_decoded_decoded[86]; // @[pla.scala:81:23] wire decoded_addr_155_2 = decoded_addr_decoded_70; // @[Decode.scala:50:77] wire decoded_addr_decoded_71 = decoded_addr_decoded_decoded[85]; // @[pla.scala:81:23] wire decoded_addr_15_2 = decoded_addr_decoded_71; // @[Decode.scala:50:77] wire decoded_addr_decoded_72 = decoded_addr_decoded_decoded[84]; // @[pla.scala:81:23] wire decoded_addr_22_2 = decoded_addr_decoded_72; // @[Decode.scala:50:77] wire decoded_addr_decoded_73 = decoded_addr_decoded_decoded[83]; // @[pla.scala:81:23] wire decoded_addr_34_2 = decoded_addr_decoded_73; // @[Decode.scala:50:77] wire decoded_addr_decoded_74 = decoded_addr_decoded_decoded[82]; // @[pla.scala:81:23] wire decoded_addr_20_2 = decoded_addr_decoded_74; // @[Decode.scala:50:77] wire decoded_addr_decoded_75 = decoded_addr_decoded_decoded[81]; // @[pla.scala:81:23] wire decoded_addr_139_2 = decoded_addr_decoded_75; // @[Decode.scala:50:77] wire decoded_addr_decoded_76 = decoded_addr_decoded_decoded[80]; // @[pla.scala:81:23] wire decoded_addr_156_2 = decoded_addr_decoded_76; // @[Decode.scala:50:77] wire decoded_addr_decoded_77 = decoded_addr_decoded_decoded[79]; // @[pla.scala:81:23] wire decoded_addr_51_2 = decoded_addr_decoded_77; // @[Decode.scala:50:77] wire decoded_addr_decoded_78 = decoded_addr_decoded_decoded[78]; // @[pla.scala:81:23] wire decoded_addr_78_2 = decoded_addr_decoded_78; // @[Decode.scala:50:77] wire decoded_addr_decoded_79 = decoded_addr_decoded_decoded[77]; // @[pla.scala:81:23] wire decoded_addr_106_2 = decoded_addr_decoded_79; // @[Decode.scala:50:77] wire decoded_addr_decoded_80 = decoded_addr_decoded_decoded[76]; // @[pla.scala:81:23] wire decoded_addr_87_2 = decoded_addr_decoded_80; // @[Decode.scala:50:77] wire decoded_addr_decoded_81 = decoded_addr_decoded_decoded[75]; // @[pla.scala:81:23] wire decoded_addr_46_2 = decoded_addr_decoded_81; // @[Decode.scala:50:77] wire decoded_addr_decoded_82 = decoded_addr_decoded_decoded[74]; // @[pla.scala:81:23] wire decoded_addr_67_2 = decoded_addr_decoded_82; // @[Decode.scala:50:77] wire decoded_addr_decoded_83 = decoded_addr_decoded_decoded[73]; // @[pla.scala:81:23] wire decoded_addr_124_2 = decoded_addr_decoded_83; // @[Decode.scala:50:77] wire decoded_addr_decoded_84 = decoded_addr_decoded_decoded[72]; // @[pla.scala:81:23] wire decoded_addr_31_2 = decoded_addr_decoded_84; // @[Decode.scala:50:77] wire decoded_addr_decoded_85 = decoded_addr_decoded_decoded[71]; // @[pla.scala:81:23] wire decoded_addr_5_2 = decoded_addr_decoded_85; // @[Decode.scala:50:77] wire decoded_addr_decoded_86 = decoded_addr_decoded_decoded[70]; // @[pla.scala:81:23] wire decoded_addr_33_2 = decoded_addr_decoded_86; // @[Decode.scala:50:77] wire decoded_addr_decoded_87 = decoded_addr_decoded_decoded[69]; // @[pla.scala:81:23] wire decoded_addr_149_2 = decoded_addr_decoded_87; // @[Decode.scala:50:77] wire decoded_addr_decoded_88 = decoded_addr_decoded_decoded[68]; // @[pla.scala:81:23] wire decoded_addr_121_2 = decoded_addr_decoded_88; // @[Decode.scala:50:77] wire decoded_addr_decoded_89 = decoded_addr_decoded_decoded[67]; // @[pla.scala:81:23] wire decoded_addr_66_2 = decoded_addr_decoded_89; // @[Decode.scala:50:77] wire decoded_addr_decoded_90 = decoded_addr_decoded_decoded[66]; // @[pla.scala:81:23] wire decoded_addr_111_2 = decoded_addr_decoded_90; // @[Decode.scala:50:77] wire decoded_addr_decoded_91 = decoded_addr_decoded_decoded[65]; // @[pla.scala:81:23] wire decoded_addr_92_2 = decoded_addr_decoded_91; // @[Decode.scala:50:77] wire decoded_addr_decoded_92 = decoded_addr_decoded_decoded[64]; // @[pla.scala:81:23] wire decoded_addr_118_2 = decoded_addr_decoded_92; // @[Decode.scala:50:77] wire decoded_addr_decoded_93 = decoded_addr_decoded_decoded[63]; // @[pla.scala:81:23] wire decoded_addr_76_2 = decoded_addr_decoded_93; // @[Decode.scala:50:77] wire decoded_addr_decoded_94 = decoded_addr_decoded_decoded[62]; // @[pla.scala:81:23] wire decoded_addr_55_2 = decoded_addr_decoded_94; // @[Decode.scala:50:77] wire decoded_addr_decoded_95 = decoded_addr_decoded_decoded[61]; // @[pla.scala:81:23] wire decoded_addr_154_2 = decoded_addr_decoded_95; // @[Decode.scala:50:77] wire decoded_addr_decoded_96 = decoded_addr_decoded_decoded[60]; // @[pla.scala:81:23] wire decoded_addr_42_2 = decoded_addr_decoded_96; // @[Decode.scala:50:77] wire decoded_addr_decoded_97 = decoded_addr_decoded_decoded[59]; // @[pla.scala:81:23] wire decoded_addr_58_2 = decoded_addr_decoded_97; // @[Decode.scala:50:77] wire decoded_addr_decoded_98 = decoded_addr_decoded_decoded[58]; // @[pla.scala:81:23] wire decoded_addr_38_2 = decoded_addr_decoded_98; // @[Decode.scala:50:77] wire decoded_addr_decoded_99 = decoded_addr_decoded_decoded[57]; // @[pla.scala:81:23] wire decoded_addr_82_2 = decoded_addr_decoded_99; // @[Decode.scala:50:77] wire decoded_addr_decoded_100 = decoded_addr_decoded_decoded[56]; // @[pla.scala:81:23] wire decoded_addr_100_2 = decoded_addr_decoded_100; // @[Decode.scala:50:77] wire decoded_addr_decoded_101 = decoded_addr_decoded_decoded[55]; // @[pla.scala:81:23] wire decoded_addr_4_2 = decoded_addr_decoded_101; // @[Decode.scala:50:77] wire decoded_addr_decoded_102 = decoded_addr_decoded_decoded[54]; // @[pla.scala:81:23] wire decoded_addr_105_2 = decoded_addr_decoded_102; // @[Decode.scala:50:77] wire decoded_addr_decoded_103 = decoded_addr_decoded_decoded[53]; // @[pla.scala:81:23] wire decoded_addr_123_2 = decoded_addr_decoded_103; // @[Decode.scala:50:77] wire decoded_addr_decoded_104 = decoded_addr_decoded_decoded[52]; // @[pla.scala:81:23] wire decoded_addr_23_2 = decoded_addr_decoded_104; // @[Decode.scala:50:77] wire decoded_addr_decoded_105 = decoded_addr_decoded_decoded[51]; // @[pla.scala:81:23] wire decoded_addr_145_2 = decoded_addr_decoded_105; // @[Decode.scala:50:77] wire decoded_addr_decoded_106 = decoded_addr_decoded_decoded[50]; // @[pla.scala:81:23] wire decoded_addr_12_2 = decoded_addr_decoded_106; // @[Decode.scala:50:77] wire decoded_addr_decoded_107 = decoded_addr_decoded_decoded[49]; // @[pla.scala:81:23] wire decoded_addr_140_2 = decoded_addr_decoded_107; // @[Decode.scala:50:77] wire decoded_addr_decoded_108 = decoded_addr_decoded_decoded[48]; // @[pla.scala:81:23] wire decoded_addr_13_2 = decoded_addr_decoded_108; // @[Decode.scala:50:77] wire decoded_addr_decoded_109 = decoded_addr_decoded_decoded[47]; // @[pla.scala:81:23] wire decoded_addr_68_2 = decoded_addr_decoded_109; // @[Decode.scala:50:77] wire decoded_addr_decoded_110 = decoded_addr_decoded_decoded[46]; // @[pla.scala:81:23] wire decoded_addr_89_2 = decoded_addr_decoded_110; // @[Decode.scala:50:77] wire decoded_addr_decoded_111 = decoded_addr_decoded_decoded[45]; // @[pla.scala:81:23] wire decoded_addr_48_2 = decoded_addr_decoded_111; // @[Decode.scala:50:77] wire decoded_addr_decoded_112 = decoded_addr_decoded_decoded[44]; // @[pla.scala:81:23] wire decoded_addr_110_2 = decoded_addr_decoded_112; // @[Decode.scala:50:77] wire decoded_addr_decoded_113 = decoded_addr_decoded_decoded[43]; // @[pla.scala:81:23] wire decoded_addr_61_2 = decoded_addr_decoded_113; // @[Decode.scala:50:77] wire decoded_addr_decoded_114 = decoded_addr_decoded_decoded[42]; // @[pla.scala:81:23] wire decoded_addr_90_2 = decoded_addr_decoded_114; // @[Decode.scala:50:77] wire decoded_addr_decoded_115 = decoded_addr_decoded_decoded[41]; // @[pla.scala:81:23] wire decoded_addr_148_2 = decoded_addr_decoded_115; // @[Decode.scala:50:77] wire decoded_addr_decoded_116 = decoded_addr_decoded_decoded[40]; // @[pla.scala:81:23] wire decoded_addr_14_2 = decoded_addr_decoded_116; // @[Decode.scala:50:77] wire decoded_addr_decoded_117 = decoded_addr_decoded_decoded[39]; // @[pla.scala:81:23] wire decoded_addr_36_2 = decoded_addr_decoded_117; // @[Decode.scala:50:77] wire decoded_addr_decoded_118 = decoded_addr_decoded_decoded[38]; // @[pla.scala:81:23] wire decoded_addr_2_2 = decoded_addr_decoded_118; // @[Decode.scala:50:77] wire decoded_addr_decoded_119 = decoded_addr_decoded_decoded[37]; // @[pla.scala:81:23] wire decoded_addr_69_2 = decoded_addr_decoded_119; // @[Decode.scala:50:77] wire decoded_addr_decoded_120 = decoded_addr_decoded_decoded[36]; // @[pla.scala:81:23] wire decoded_addr_43_2 = decoded_addr_decoded_120; // @[Decode.scala:50:77] wire decoded_addr_decoded_121 = decoded_addr_decoded_decoded[35]; // @[pla.scala:81:23] wire decoded_addr_64_2 = decoded_addr_decoded_121; // @[Decode.scala:50:77] wire decoded_addr_decoded_122 = decoded_addr_decoded_decoded[34]; // @[pla.scala:81:23] wire decoded_addr_49_2 = decoded_addr_decoded_122; // @[Decode.scala:50:77] wire decoded_addr_decoded_123 = decoded_addr_decoded_decoded[33]; // @[pla.scala:81:23] wire decoded_addr_45_2 = decoded_addr_decoded_123; // @[Decode.scala:50:77] wire decoded_addr_decoded_124 = decoded_addr_decoded_decoded[32]; // @[pla.scala:81:23] wire decoded_addr_16_2 = decoded_addr_decoded_124; // @[Decode.scala:50:77] wire decoded_addr_decoded_125 = decoded_addr_decoded_decoded[31]; // @[pla.scala:81:23] wire decoded_addr_152_2 = decoded_addr_decoded_125; // @[Decode.scala:50:77] wire decoded_addr_decoded_126 = decoded_addr_decoded_decoded[30]; // @[pla.scala:81:23] wire decoded_addr_97_2 = decoded_addr_decoded_126; // @[Decode.scala:50:77] wire decoded_addr_decoded_127 = decoded_addr_decoded_decoded[29]; // @[pla.scala:81:23] wire decoded_addr_7_2 = decoded_addr_decoded_127; // @[Decode.scala:50:77] wire decoded_addr_decoded_128 = decoded_addr_decoded_decoded[28]; // @[pla.scala:81:23] wire decoded_addr_29_2 = decoded_addr_decoded_128; // @[Decode.scala:50:77] wire decoded_addr_decoded_129 = decoded_addr_decoded_decoded[27]; // @[pla.scala:81:23] wire decoded_addr_26_2 = decoded_addr_decoded_129; // @[Decode.scala:50:77] wire decoded_addr_decoded_130 = decoded_addr_decoded_decoded[26]; // @[pla.scala:81:23] wire decoded_addr_143_2 = decoded_addr_decoded_130; // @[Decode.scala:50:77] wire decoded_addr_decoded_131 = decoded_addr_decoded_decoded[25]; // @[pla.scala:81:23] wire decoded_addr_127_2 = decoded_addr_decoded_131; // @[Decode.scala:50:77] wire decoded_addr_decoded_132 = decoded_addr_decoded_decoded[24]; // @[pla.scala:81:23] wire decoded_addr_24_2 = decoded_addr_decoded_132; // @[Decode.scala:50:77] wire decoded_addr_decoded_133 = decoded_addr_decoded_decoded[23]; // @[pla.scala:81:23] wire decoded_addr_72_2 = decoded_addr_decoded_133; // @[Decode.scala:50:77] wire decoded_addr_decoded_134 = decoded_addr_decoded_decoded[22]; // @[pla.scala:81:23] wire decoded_addr_147_2 = decoded_addr_decoded_134; // @[Decode.scala:50:77] wire decoded_addr_decoded_135 = decoded_addr_decoded_decoded[21]; // @[pla.scala:81:23] wire decoded_addr_10_2 = decoded_addr_decoded_135; // @[Decode.scala:50:77] wire decoded_addr_decoded_136 = decoded_addr_decoded_decoded[20]; // @[pla.scala:81:23] wire decoded_addr_108_2 = decoded_addr_decoded_136; // @[Decode.scala:50:77] wire decoded_addr_decoded_137 = decoded_addr_decoded_decoded[19]; // @[pla.scala:81:23] wire decoded_addr_9_2 = decoded_addr_decoded_137; // @[Decode.scala:50:77] wire decoded_addr_decoded_138 = decoded_addr_decoded_decoded[18]; // @[pla.scala:81:23] wire decoded_addr_129_2 = decoded_addr_decoded_138; // @[Decode.scala:50:77] wire decoded_addr_decoded_139 = decoded_addr_decoded_decoded[17]; // @[pla.scala:81:23] wire decoded_addr_88_2 = decoded_addr_decoded_139; // @[Decode.scala:50:77] wire decoded_addr_decoded_140 = decoded_addr_decoded_decoded[16]; // @[pla.scala:81:23] wire decoded_addr_56_2 = decoded_addr_decoded_140; // @[Decode.scala:50:77] wire decoded_addr_decoded_141 = decoded_addr_decoded_decoded[15]; // @[pla.scala:81:23] wire decoded_addr_21_2 = decoded_addr_decoded_141; // @[Decode.scala:50:77] wire decoded_addr_decoded_142 = decoded_addr_decoded_decoded[14]; // @[pla.scala:81:23] wire decoded_addr_141_2 = decoded_addr_decoded_142; // @[Decode.scala:50:77] wire decoded_addr_decoded_143 = decoded_addr_decoded_decoded[13]; // @[pla.scala:81:23] wire decoded_addr_119_2 = decoded_addr_decoded_143; // @[Decode.scala:50:77] wire decoded_addr_decoded_144 = decoded_addr_decoded_decoded[12]; // @[pla.scala:81:23] wire decoded_addr_44_2 = decoded_addr_decoded_144; // @[Decode.scala:50:77] wire decoded_addr_decoded_145 = decoded_addr_decoded_decoded[11]; // @[pla.scala:81:23] wire decoded_addr_74_2 = decoded_addr_decoded_145; // @[Decode.scala:50:77] wire decoded_addr_decoded_146 = decoded_addr_decoded_decoded[10]; // @[pla.scala:81:23] wire decoded_addr_114_2 = decoded_addr_decoded_146; // @[Decode.scala:50:77] wire decoded_addr_decoded_147 = decoded_addr_decoded_decoded[9]; // @[pla.scala:81:23] wire decoded_addr_146_2 = decoded_addr_decoded_147; // @[Decode.scala:50:77] wire decoded_addr_decoded_148 = decoded_addr_decoded_decoded[8]; // @[pla.scala:81:23] wire decoded_addr_35_2 = decoded_addr_decoded_148; // @[Decode.scala:50:77] wire decoded_addr_decoded_149 = decoded_addr_decoded_decoded[7]; // @[pla.scala:81:23] wire decoded_addr_41_2 = decoded_addr_decoded_149; // @[Decode.scala:50:77] wire decoded_addr_decoded_150 = decoded_addr_decoded_decoded[6]; // @[pla.scala:81:23] wire decoded_addr_83_2 = decoded_addr_decoded_150; // @[Decode.scala:50:77] wire decoded_addr_decoded_151 = decoded_addr_decoded_decoded[5]; // @[pla.scala:81:23] wire decoded_addr_102_2 = decoded_addr_decoded_151; // @[Decode.scala:50:77] wire decoded_addr_decoded_152 = decoded_addr_decoded_decoded[4]; // @[pla.scala:81:23] wire decoded_addr_19_2 = decoded_addr_decoded_152; // @[Decode.scala:50:77] wire decoded_addr_decoded_153 = decoded_addr_decoded_decoded[3]; // @[pla.scala:81:23] wire decoded_addr_3_2 = decoded_addr_decoded_153; // @[Decode.scala:50:77] wire decoded_addr_decoded_154 = decoded_addr_decoded_decoded[2]; // @[pla.scala:81:23] wire decoded_addr_39_2 = decoded_addr_decoded_154; // @[Decode.scala:50:77] wire decoded_addr_decoded_155 = decoded_addr_decoded_decoded[1]; // @[pla.scala:81:23] wire decoded_addr_132_2 = decoded_addr_decoded_155; // @[Decode.scala:50:77] wire decoded_addr_decoded_156 = decoded_addr_decoded_decoded[0]; // @[pla.scala:81:23] wire decoded_addr_99_2 = decoded_addr_decoded_156; // @[Decode.scala:50:77] wire _wdata_T = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _new_mip_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _newBPC_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _newBPC_T_25 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire [63:0] _wdata_T_1 = _wdata_T ? io_rw_rdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{9,13}] wire [63:0] _wdata_T_2 = _wdata_T_1 | io_rw_wdata_0; // @[CSR.scala:377:7, :1643:{9,30}] wire [1:0] _wdata_T_3 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _new_mip_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _newBPC_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _newBPC_T_28 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire _wdata_T_4 = &_wdata_T_3; // @[CSR.scala:1643:{49,55}] wire [63:0] _wdata_T_5 = _wdata_T_4 ? io_rw_wdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{45,55}] wire [63:0] _wdata_T_6 = ~_wdata_T_5; // @[CSR.scala:1643:{41,45}] assign wdata = _wdata_T_2 & _wdata_T_6; // @[CSR.scala:1643:{30,39,41}] assign io_customCSRs_0_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_1_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_2_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_3_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] wire [63:0] _new_satp_WIRE = wdata; // @[CSR.scala:1355:40, :1643:39] wire [63:0] _new_envcfg_WIRE = wdata; // @[CSR.scala:137:36, :1643:39] wire [63:0] _new_envcfg_WIRE_1 = wdata; // @[CSR.scala:137:36, :1643:39] wire [63:0] _reg_bp_0_control_WIRE_1 = wdata; // @[CSR.scala:1471:41, :1643:39] wire [63:0] _reg_bp_1_control_WIRE_1 = wdata; // @[CSR.scala:1471:41, :1643:39] wire [63:0] _newCfg_T = wdata; // @[CSR.scala:1491:29, :1643:39] wire system_insn = io_rw_cmd_0 == 3'h4; // @[CSR.scala:377:7, :876:31] wire [31:0] _insn_T = {io_rw_addr_0, 20'h0}; // @[CSR.scala:377:7, :892:44] wire [31:0] insn = {_insn_T[31:7], _insn_T[6:0] | 7'h73}; // @[CSR.scala:892:{30,44}] wire [31:0] decoded_plaInput = insn; // @[pla.scala:77:22] wire [31:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [8:0] decoded; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo = {decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi = {decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo = {decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo = {decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi = {decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi = {decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_1 = {decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_1 = {decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_1 = {decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_1 = {decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_1 = {decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_1 = {decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_5 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_2 = {decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_2 = {decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_2 = {decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_2 = {decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_3 = {decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_3 = {decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_3 = {decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_3 = {decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_3 = {decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2 = &_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_1 = decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_4 = {decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_4 = {decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_4 = {decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_4 = {decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_4 = {decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_4 = {decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T = decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_5 = {decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_5 = {decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_5 = {decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_5 = {decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_5 = {decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_2 = decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_6 = {decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_3 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_4 = |_decoded_orMatrixOutputs_T_3; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi = {_decoded_orMatrixOutputs_T, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo = {decoded_orMatrixOutputs_lo_hi, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo = {_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi = {decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi = {decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_4 = decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_5 = decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_6 = decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_7 = decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_8 = decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo = {decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo = {_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi = {_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi = {decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi = {decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire insn_call = system_insn & decoded[8]; // @[pla.scala:81:23] wire insn_break = system_insn & decoded[7]; // @[pla.scala:81:23] wire insn_ret = system_insn & decoded[6]; // @[pla.scala:81:23] wire insn_cease = system_insn & decoded[5]; // @[pla.scala:81:23] wire insn_wfi = system_insn & decoded[4]; // @[pla.scala:81:23] wire [11:0] addr = io_decode_0_inst_0[31:20]; // @[CSR.scala:377:7, :897:27] wire [11:0] io_decode_0_fp_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_vector_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput_1 = addr; // @[pla.scala:77:22] wire [31:0] decoded_invInputs_1 = ~decoded_plaInput_1; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs_1; // @[pla.scala:120:37] wire [8:0] decoded_1; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12_1 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14_1 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15_1 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16_1 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_6 = {decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_6 = {decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_6 = {decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_6 = {decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_6 = {decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_6 = {decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_7 = {decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2_1 = &_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_13 = decoded_andMatrixOutputs_6_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_7 = {decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_7 = {decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_7 = {decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_7 = {decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_7 = {decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_7 = {decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_8 = {decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2_1 = &_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_12 = decoded_andMatrixOutputs_4_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13_1 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_8 = {decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_8 = {decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_8 = {decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_8 = {decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_9 = {decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2_1 = &_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_9 = {decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_9 = {decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_9 = {decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_9 = {decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_10 = {decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2_1 = &_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_8 = decoded_andMatrixOutputs_1_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_10 = {decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_10 = {decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_10 = {decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_10 = {decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_10 = {decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_11 = {decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2_1 = &_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_7 = decoded_andMatrixOutputs_0_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_11 = {decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_11 = {decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_11 = {decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_11 = {decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_12 = {decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2_1 = &_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_9 = decoded_andMatrixOutputs_5_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_13 = {decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2_1 = &_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_10 = {decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_11 = |_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi_1 = {_decoded_orMatrixOutputs_T_7, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo_1 = {decoded_orMatrixOutputs_lo_hi_1, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo_1 = {_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi_1 = {_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi_1 = {decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi_1 = {decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs_1 = {decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T_9 = decoded_orMatrixOutputs_1[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_10 = decoded_orMatrixOutputs_1[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_11 = decoded_orMatrixOutputs_1[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_12 = decoded_orMatrixOutputs_1[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_13 = decoded_orMatrixOutputs_1[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_14 = decoded_orMatrixOutputs_1[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_15 = decoded_orMatrixOutputs_1[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_16 = decoded_orMatrixOutputs_1[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_17 = decoded_orMatrixOutputs_1[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo_1 = {_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi_1 = {_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo_1 = {decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo_1 = {_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi_1 = {_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi_1 = {decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi_1 = {decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs_1 = {decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1}; // @[pla.scala:120:37] assign decoded_1 = decoded_invMatrixOutputs_1; // @[pla.scala:81:23, :120:37] wire is_break = decoded_1[7]; // @[pla.scala:81:23] wire is_ret = decoded_1[6]; // @[pla.scala:81:23] wire is_wfi = decoded_1[4]; // @[pla.scala:81:23] wire is_sfence = decoded_1[3]; // @[pla.scala:81:23] wire is_hfence_vvma = decoded_1[2]; // @[pla.scala:81:23] wire is_hfence_gvma = decoded_1[1]; // @[pla.scala:81:23] wire is_hlsv = decoded_1[0]; // @[pla.scala:81:23] wire _is_counter_T = addr > 12'hBFF; // @[package.scala:213:47] wire _is_counter_T_1 = addr < 12'hC20; // @[package.scala:213:60] wire _is_counter_T_2 = _is_counter_T & _is_counter_T_1; // @[package.scala:213:{47,55,60}] wire _is_counter_T_3 = addr > 12'hC7F; // @[package.scala:213:47] wire _is_counter_T_4 = addr < 12'hCA0; // @[package.scala:213:60] wire _is_counter_T_5 = _is_counter_T_3 & _is_counter_T_4; // @[package.scala:213:{47,55,60}] wire is_counter = _is_counter_T_2 | _is_counter_T_5; // @[package.scala:213:55] wire _allow_wfi_T_1 = _allow_wfi_T; // @[CSR.scala:906:{42,61}] wire _allow_wfi_T_2 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74] wire _allow_wfi_T_6 = _allow_wfi_T_2; // @[CSR.scala:906:{74,90}] wire _allow_wfi_T_3 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94] wire allow_wfi = _allow_wfi_T_1 | _allow_wfi_T_6; // @[CSR.scala:906:{42,71,90}] wire _allow_sfence_vma_T_1 = _allow_sfence_vma_T; // @[CSR.scala:907:{41,60}] wire _allow_sfence_vma_T_2 = ~reg_mstatus_v & reg_mstatus_tvm; // @[CSR.scala:395:28, :907:77] wire _allow_sfence_vma_T_3 = ~_allow_sfence_vma_T_2; // @[CSR.scala:907:{73,77}] wire allow_sfence_vma = _allow_sfence_vma_T_1 | _allow_sfence_vma_T_3; // @[CSR.scala:907:{41,70,73}] wire _allow_hfence_vvma_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :908:53] wire _allow_hfence_vvma_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88] wire _allow_hfence_vvma_T_2 = _allow_hfence_vvma_T & _allow_hfence_vvma_T_1; // @[CSR.scala:908:{53,68,88}] wire _allow_hlsv_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :909:46] wire _allow_hlsv_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :909:81] wire _allow_hlsv_T_2 = _allow_hlsv_T_1; // @[CSR.scala:909:{81,92}] wire _allow_hlsv_T_3 = _allow_hlsv_T & _allow_hlsv_T_2; // @[CSR.scala:909:{46,61,92}] wire _allow_sret_T_1 = _allow_sret_T; // @[CSR.scala:910:{43,62}] wire _allow_sret_T_2 = ~reg_mstatus_v & reg_mstatus_tsr; // @[CSR.scala:395:28, :907:77, :910:79] wire _allow_sret_T_3 = ~_allow_sret_T_2; // @[CSR.scala:910:{75,79}] wire allow_sret = _allow_sret_T_1 | _allow_sret_T_3; // @[CSR.scala:910:{43,72,75}] wire [4:0] counter_addr = addr[4:0]; // @[CSR.scala:897:27, :911:28] wire [31:0] _GEN_10 = {27'h0, counter_addr}; // @[CSR.scala:911:28, :912:70] wire [31:0] _GEN_11 = read_mcounteren >> _GEN_10; // @[CSR.scala:532:14, :912:70] wire [31:0] _allow_counter_T_1; // @[CSR.scala:912:70] assign _allow_counter_T_1 = _GEN_11; // @[CSR.scala:912:70] wire [31:0] _io_decode_0_virtual_access_illegal_T_3; // @[CSR.scala:945:36] assign _io_decode_0_virtual_access_illegal_T_3 = _GEN_11; // @[CSR.scala:912:70, :945:36] wire _allow_counter_T_2 = _allow_counter_T_1[0]; // @[CSR.scala:912:70] wire _allow_counter_T_3 = _allow_counter_T | _allow_counter_T_2; // @[CSR.scala:912:{42,52,70}] wire _allow_counter_T_5 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :913:46] wire _allow_counter_T_6 = _allow_counter_T_5; // @[CSR.scala:913:{27,46}] wire [31:0] _GEN_12 = read_scounteren >> _GEN_10; // @[CSR.scala:536:14, :912:70, :913:75] wire [31:0] _allow_counter_T_7; // @[CSR.scala:913:75] assign _allow_counter_T_7 = _GEN_12; // @[CSR.scala:913:75] wire [31:0] _io_decode_0_virtual_access_illegal_T_11; // @[CSR.scala:945:128] assign _io_decode_0_virtual_access_illegal_T_11 = _GEN_12; // @[CSR.scala:913:75, :945:128] wire _allow_counter_T_8 = _allow_counter_T_7[0]; // @[CSR.scala:913:75] wire _allow_counter_T_9 = _allow_counter_T_6 | _allow_counter_T_8; // @[CSR.scala:913:{27,57,75}] wire _allow_counter_T_10 = _allow_counter_T_3 & _allow_counter_T_9; // @[CSR.scala:912:{52,86}, :913:57] wire allow_counter = _allow_counter_T_10; // @[CSR.scala:912:86, :913:91] wire _allow_counter_T_12 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :914:30] wire [31:0] _GEN_13 = 32'h0 >> _GEN_10; // @[CSR.scala:912:70, :914:63] wire [31:0] _allow_counter_T_14; // @[CSR.scala:914:63] assign _allow_counter_T_14 = _GEN_13; // @[CSR.scala:914:63] wire [31:0] _io_decode_0_virtual_access_illegal_T_6; // @[CSR.scala:945:71] assign _io_decode_0_virtual_access_illegal_T_6 = _GEN_13; // @[CSR.scala:914:63, :945:71] wire _allow_counter_T_15 = _allow_counter_T_14[0]; // @[CSR.scala:914:63] wire _io_decode_0_fp_illegal_T = io_status_fs_0 == 2'h0; // @[CSR.scala:377:7, :915:39] wire _io_decode_0_fp_illegal_T_2 = reg_mstatus_v & _io_decode_0_fp_illegal_T_1; // @[CSR.scala:395:28, :915:{64,83}] wire _io_decode_0_fp_illegal_T_3 = _io_decode_0_fp_illegal_T | _io_decode_0_fp_illegal_T_2; // @[CSR.scala:915:{39,47,64}] wire _io_decode_0_fp_illegal_T_4 = reg_misa[5]; // @[CSR.scala:648:25, :915:103] wire _io_decode_0_fp_illegal_T_5 = ~_io_decode_0_fp_illegal_T_4; // @[CSR.scala:915:{94,103}] assign _io_decode_0_fp_illegal_T_6 = _io_decode_0_fp_illegal_T_3 | _io_decode_0_fp_illegal_T_5; // @[CSR.scala:915:{47,91,94}] assign io_decode_0_fp_illegal_0 = _io_decode_0_fp_illegal_T_6; // @[CSR.scala:377:7, :915:91] wire _io_decode_0_vector_illegal_T = io_status_vs_0 == 2'h0; // @[CSR.scala:377:7, :916:43] wire _io_decode_0_vector_illegal_T_3 = _io_decode_0_vector_illegal_T; // @[CSR.scala:916:{43,51}] wire _io_decode_0_vector_illegal_T_4 = reg_misa[21]; // @[CSR.scala:648:25, :916:107] wire _io_decode_0_vector_illegal_T_5 = ~_io_decode_0_vector_illegal_T_4; // @[CSR.scala:916:{98,107}] assign _io_decode_0_vector_illegal_T_6 = _io_decode_0_vector_illegal_T_3 | _io_decode_0_vector_illegal_T_5; // @[CSR.scala:916:{51,95,98}] assign io_decode_0_vector_illegal_0 = _io_decode_0_vector_illegal_T_6; // @[CSR.scala:377:7, :916:95] wire [11:0] io_decode_0_fp_csr_invInputs = ~io_decode_0_fp_csr_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23] assign _io_decode_0_fp_csr_T = io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = io_decode_0_fp_csr_invInputs[3]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = io_decode_0_fp_csr_invInputs[4]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = io_decode_0_fp_csr_invInputs[5]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = io_decode_0_fp_csr_invInputs[6]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_4 = io_decode_0_fp_csr_invInputs[7]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_5 = io_decode_0_fp_csr_invInputs[8]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_6 = io_decode_0_fp_csr_invInputs[9]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_7 = io_decode_0_fp_csr_invInputs[10]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_8 = io_decode_0_fp_csr_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_lo_lo = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_7, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_lo_hi = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_5, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [3:0] io_decode_0_fp_csr_andMatrixOutputs_lo = {io_decode_0_fp_csr_andMatrixOutputs_lo_hi, io_decode_0_fp_csr_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_hi_lo = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_hi_hi_hi = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] io_decode_0_fp_csr_andMatrixOutputs_hi_hi = {io_decode_0_fp_csr_andMatrixOutputs_hi_hi_hi, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [4:0] io_decode_0_fp_csr_andMatrixOutputs_hi = {io_decode_0_fp_csr_andMatrixOutputs_hi_hi, io_decode_0_fp_csr_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [8:0] _io_decode_0_fp_csr_andMatrixOutputs_T = {io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_fp_csr_andMatrixOutputs_0_2 = &_io_decode_0_fp_csr_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_fp_csr_orMatrixOutputs = io_decode_0_fp_csr_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_fp_csr_invMatrixOutputs = io_decode_0_fp_csr_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_fp_csr_plaOutput = io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:81:23, :124:31] assign io_decode_0_fp_csr_0 = _io_decode_0_fp_csr_T; // @[Decode.scala:55:116] wire [11:0] io_decode_0_vector_csr_invInputs = ~io_decode_0_vector_csr_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_vector_csr_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_vector_csr_plaOutput; // @[pla.scala:81:23] assign _io_decode_0_vector_csr_T = io_decode_0_vector_csr_plaOutput; // @[pla.scala:81:23] wire io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_0 = io_decode_0_vector_csr_plaInput[3]; // @[pla.scala:77:22, :90:45] wire io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_1 = io_decode_0_vector_csr_invInputs[4]; // @[pla.scala:78:21, :91:29] wire io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_2 = io_decode_0_vector_csr_invInputs[5]; // @[pla.scala:78:21, :91:29] wire io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_3 = io_decode_0_vector_csr_invInputs[6]; // @[pla.scala:78:21, :91:29] wire io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_1_1 = io_decode_0_vector_csr_invInputs[6]; // @[pla.scala:78:21, :91:29] wire io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_4 = io_decode_0_vector_csr_invInputs[7]; // @[pla.scala:78:21, :91:29] wire io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_2_1 = io_decode_0_vector_csr_invInputs[7]; // @[pla.scala:78:21, :91:29] wire io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_5 = io_decode_0_vector_csr_invInputs[8]; // @[pla.scala:78:21, :91:29] wire io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_3_1 = io_decode_0_vector_csr_invInputs[8]; // @[pla.scala:78:21, :91:29] wire io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_6 = io_decode_0_vector_csr_invInputs[9]; // @[pla.scala:78:21, :91:29] wire io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_4_1 = io_decode_0_vector_csr_invInputs[9]; // @[pla.scala:78:21, :91:29] wire io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_7 = io_decode_0_vector_csr_invInputs[10]; // @[pla.scala:78:21, :91:29] wire io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_8 = io_decode_0_vector_csr_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_vector_csr_andMatrixOutputs_lo_lo = {io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_7, io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_0_vector_csr_andMatrixOutputs_lo_hi = {io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_5, io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [3:0] io_decode_0_vector_csr_andMatrixOutputs_lo = {io_decode_0_vector_csr_andMatrixOutputs_lo_hi, io_decode_0_vector_csr_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] io_decode_0_vector_csr_andMatrixOutputs_hi_lo = {io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_3, io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_0_vector_csr_andMatrixOutputs_hi_hi_hi = {io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] io_decode_0_vector_csr_andMatrixOutputs_hi_hi = {io_decode_0_vector_csr_andMatrixOutputs_hi_hi_hi, io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [4:0] io_decode_0_vector_csr_andMatrixOutputs_hi = {io_decode_0_vector_csr_andMatrixOutputs_hi_hi, io_decode_0_vector_csr_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [8:0] _io_decode_0_vector_csr_andMatrixOutputs_T = {io_decode_0_vector_csr_andMatrixOutputs_hi, io_decode_0_vector_csr_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_vector_csr_andMatrixOutputs_0_2 = &_io_decode_0_vector_csr_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_0_1 = io_decode_0_vector_csr_plaInput[5]; // @[pla.scala:77:22, :90:45] wire io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_5_1 = io_decode_0_vector_csr_plaInput[10]; // @[pla.scala:77:22, :90:45] wire io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_6_1 = io_decode_0_vector_csr_plaInput[11]; // @[pla.scala:77:22, :90:45] wire [1:0] io_decode_0_vector_csr_andMatrixOutputs_lo_hi_1 = {io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_4_1, io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] io_decode_0_vector_csr_andMatrixOutputs_lo_1 = {io_decode_0_vector_csr_andMatrixOutputs_lo_hi_1, io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:90:45, :98:53] wire [1:0] io_decode_0_vector_csr_andMatrixOutputs_hi_lo_1 = {io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_2_1, io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_0_vector_csr_andMatrixOutputs_hi_hi_1 = {io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_0_1, io_decode_0_vector_csr_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] io_decode_0_vector_csr_andMatrixOutputs_hi_1 = {io_decode_0_vector_csr_andMatrixOutputs_hi_hi_1, io_decode_0_vector_csr_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] _io_decode_0_vector_csr_andMatrixOutputs_T_1 = {io_decode_0_vector_csr_andMatrixOutputs_hi_1, io_decode_0_vector_csr_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire io_decode_0_vector_csr_andMatrixOutputs_1_2 = &_io_decode_0_vector_csr_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire [1:0] _io_decode_0_vector_csr_orMatrixOutputs_T = {io_decode_0_vector_csr_andMatrixOutputs_0_2, io_decode_0_vector_csr_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire io_decode_0_vector_csr_orMatrixOutputs = |_io_decode_0_vector_csr_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] assign io_decode_0_vector_csr_invMatrixOutputs = io_decode_0_vector_csr_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_vector_csr_plaOutput = io_decode_0_vector_csr_invMatrixOutputs; // @[pla.scala:81:23, :124:31] assign io_decode_0_vector_csr_0 = _io_decode_0_vector_csr_T; // @[Decode.scala:55:116] wire _io_decode_0_rocc_illegal_T_4 = reg_misa[23]; // @[CSR.scala:648:25, :919:105] wire _io_decode_0_rocc_illegal_T_5 = ~_io_decode_0_rocc_illegal_T_4; // @[CSR.scala:919:{96,105}] wire [1:0] _csr_addr_legal_T = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _csr_addr_legal_T_6 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_1 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_18 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_system_illegal_T_9 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire _csr_addr_legal_T_1 = reg_mstatus_prv >= _csr_addr_legal_T; // @[CSR.scala:190:36, :395:28, :920:42] wire csr_addr_legal = _csr_addr_legal_T_1; // @[CSR.scala:920:{42,60}] wire _csr_addr_legal_T_2 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :921:28] wire _csr_addr_legal_T_7 = _csr_addr_legal_T_6 == 2'h2; // @[CSR.scala:190:36, :921:92] wire _csr_exists_T = addr == 12'h7A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_1 = addr == 12'h7A1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_2 = addr == 12'h7A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_3 = addr == 12'h7A3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_4 = addr == 12'h301; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_5 = addr == 12'h300; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_6 = addr == 12'h305; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_7 = addr == 12'h344; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_8 = addr == 12'h304; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_9 = addr == 12'h340; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_10 = addr == 12'h341; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_11 = addr == 12'h343; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_12 = addr == 12'h342; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_13 = addr == 12'hF14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_14 = addr == 12'h7B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_15 = addr == 12'h7B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_16 = addr == 12'h7B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_17 = addr == 12'h1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_18 = addr == 12'h2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_19 = addr == 12'h3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_20 = addr == 12'h9; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_21 = addr == 12'hA; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_22 = addr == 12'hF; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_23 = addr == 12'h8; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_24 = addr == 12'hC21; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_25 = addr == 12'hC20; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_26 = addr == 12'hC22; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_27 = addr == 12'h320; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_28 = addr == 12'hB00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_29 = addr == 12'hB02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_30 = addr == 12'h323; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_31 = addr == 12'hB03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_32 = addr == 12'hC03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_33 = addr == 12'h324; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_34 = addr == 12'hB04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_35 = addr == 12'hC04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_36 = addr == 12'h325; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_37 = addr == 12'hB05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_38 = addr == 12'hC05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_39 = addr == 12'h326; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_40 = addr == 12'hB06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_41 = addr == 12'hC06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_42 = addr == 12'h327; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_43 = addr == 12'hB07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_44 = addr == 12'hC07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_45 = addr == 12'h328; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_46 = addr == 12'hB08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_47 = addr == 12'hC08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_48 = addr == 12'h329; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_49 = addr == 12'hB09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_50 = addr == 12'hC09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_51 = addr == 12'h32A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_52 = addr == 12'hB0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_53 = addr == 12'hC0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_54 = addr == 12'h32B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_55 = addr == 12'hB0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_56 = addr == 12'hC0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_57 = addr == 12'h32C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_58 = addr == 12'hB0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_59 = addr == 12'hC0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_60 = addr == 12'h32D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_61 = addr == 12'hB0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_62 = addr == 12'hC0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_63 = addr == 12'h32E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_64 = addr == 12'hB0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_65 = addr == 12'hC0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_66 = addr == 12'h32F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_67 = addr == 12'hB0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_68 = addr == 12'hC0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_69 = addr == 12'h330; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_70 = addr == 12'hB10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_71 = addr == 12'hC10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_72 = addr == 12'h331; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_73 = addr == 12'hB11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_74 = addr == 12'hC11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_75 = addr == 12'h332; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_76 = addr == 12'hB12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_77 = addr == 12'hC12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_78 = addr == 12'h333; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_79 = addr == 12'hB13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_80 = addr == 12'hC13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_81 = addr == 12'h334; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_82 = addr == 12'hB14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_83 = addr == 12'hC14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_84 = addr == 12'h335; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_85 = addr == 12'hB15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_86 = addr == 12'hC15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_87 = addr == 12'h336; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_88 = addr == 12'hB16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_89 = addr == 12'hC16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_90 = addr == 12'h337; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_91 = addr == 12'hB17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_92 = addr == 12'hC17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_93 = addr == 12'h338; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_94 = addr == 12'hB18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_95 = addr == 12'hC18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_96 = addr == 12'h339; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_97 = addr == 12'hB19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_98 = addr == 12'hC19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_99 = addr == 12'h33A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_100 = addr == 12'hB1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_101 = addr == 12'hC1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_102 = addr == 12'h33B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_103 = addr == 12'hB1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_104 = addr == 12'hC1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_105 = addr == 12'h33C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_106 = addr == 12'hB1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_107 = addr == 12'hC1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_108 = addr == 12'h33D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_109 = addr == 12'hB1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_110 = addr == 12'hC1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_111 = addr == 12'h33E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_112 = addr == 12'hB1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_113 = addr == 12'hC1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_114 = addr == 12'h33F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_115 = addr == 12'hB1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_116 = addr == 12'hC1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_117 = addr == 12'h306; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_118 = addr == 12'hC00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_119 = addr == 12'hC02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_120 = addr == 12'h30A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_121 = addr == 12'h100; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_122 = addr == 12'h144; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_123 = addr == 12'h104; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_124 = addr == 12'h140; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_125 = addr == 12'h142; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_126 = addr == 12'h143; // @[CSR.scala:897:27, :899:93] wire _GEN_14 = addr == 12'h180; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_127; // @[CSR.scala:899:93] assign _csr_exists_T_127 = _GEN_14; // @[CSR.scala:899:93] wire _io_decode_0_read_illegal_T_3; // @[CSR.scala:925:14] assign _io_decode_0_read_illegal_T_3 = _GEN_14; // @[CSR.scala:899:93, :925:14] wire _io_decode_0_virtual_access_illegal_T_24; // @[CSR.scala:947:12] assign _io_decode_0_virtual_access_illegal_T_24 = _GEN_14; // @[CSR.scala:899:93, :947:12] wire _csr_exists_T_128 = addr == 12'h141; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_129 = addr == 12'h105; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_130 = addr == 12'h106; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_131 = addr == 12'h303; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_132 = addr == 12'h302; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_133 = addr == 12'h10A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_134 = addr == 12'h3A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_135 = addr == 12'h3A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_136 = addr == 12'h3B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_137 = addr == 12'h3B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_138 = addr == 12'h3B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_139 = addr == 12'h3B3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_140 = addr == 12'h3B4; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_141 = addr == 12'h3B5; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_142 = addr == 12'h3B6; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_143 = addr == 12'h3B7; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_144 = addr == 12'h3B8; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_145 = addr == 12'h3B9; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_146 = addr == 12'h3BA; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_147 = addr == 12'h3BB; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_148 = addr == 12'h3BC; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_149 = addr == 12'h3BD; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_150 = addr == 12'h3BE; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_151 = addr == 12'h3BF; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_152 = addr == 12'h7C1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_153 = addr == 12'hF12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_154 = addr == 12'hF11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_155 = addr == 12'hF13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_156 = addr == 12'hF15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_157 = _csr_exists_T | _csr_exists_T_1; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_158 = _csr_exists_T_157 | _csr_exists_T_2; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_159 = _csr_exists_T_158 | _csr_exists_T_3; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_160 = _csr_exists_T_159 | _csr_exists_T_4; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_161 = _csr_exists_T_160 | _csr_exists_T_5; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_162 = _csr_exists_T_161 | _csr_exists_T_6; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_163 = _csr_exists_T_162 | _csr_exists_T_7; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_164 = _csr_exists_T_163 | _csr_exists_T_8; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_165 = _csr_exists_T_164 | _csr_exists_T_9; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_166 = _csr_exists_T_165 | _csr_exists_T_10; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_167 = _csr_exists_T_166 | _csr_exists_T_11; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_168 = _csr_exists_T_167 | _csr_exists_T_12; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_169 = _csr_exists_T_168 | _csr_exists_T_13; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_170 = _csr_exists_T_169 | _csr_exists_T_14; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_171 = _csr_exists_T_170 | _csr_exists_T_15; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_172 = _csr_exists_T_171 | _csr_exists_T_16; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_173 = _csr_exists_T_172 | _csr_exists_T_17; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_174 = _csr_exists_T_173 | _csr_exists_T_18; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_175 = _csr_exists_T_174 | _csr_exists_T_19; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_176 = _csr_exists_T_175 | _csr_exists_T_20; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_177 = _csr_exists_T_176 | _csr_exists_T_21; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_178 = _csr_exists_T_177 | _csr_exists_T_22; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_179 = _csr_exists_T_178 | _csr_exists_T_23; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_180 = _csr_exists_T_179 | _csr_exists_T_24; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_181 = _csr_exists_T_180 | _csr_exists_T_25; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_182 = _csr_exists_T_181 | _csr_exists_T_26; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_183 = _csr_exists_T_182 | _csr_exists_T_27; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_184 = _csr_exists_T_183 | _csr_exists_T_28; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_185 = _csr_exists_T_184 | _csr_exists_T_29; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_186 = _csr_exists_T_185 | _csr_exists_T_30; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_187 = _csr_exists_T_186 | _csr_exists_T_31; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_188 = _csr_exists_T_187 | _csr_exists_T_32; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_189 = _csr_exists_T_188 | _csr_exists_T_33; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_190 = _csr_exists_T_189 | _csr_exists_T_34; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_191 = _csr_exists_T_190 | _csr_exists_T_35; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_192 = _csr_exists_T_191 | _csr_exists_T_36; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_193 = _csr_exists_T_192 | _csr_exists_T_37; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_194 = _csr_exists_T_193 | _csr_exists_T_38; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_195 = _csr_exists_T_194 | _csr_exists_T_39; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_196 = _csr_exists_T_195 | _csr_exists_T_40; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_197 = _csr_exists_T_196 | _csr_exists_T_41; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_198 = _csr_exists_T_197 | _csr_exists_T_42; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_199 = _csr_exists_T_198 | _csr_exists_T_43; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_200 = _csr_exists_T_199 | _csr_exists_T_44; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_201 = _csr_exists_T_200 | _csr_exists_T_45; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_202 = _csr_exists_T_201 | _csr_exists_T_46; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_203 = _csr_exists_T_202 | _csr_exists_T_47; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_204 = _csr_exists_T_203 | _csr_exists_T_48; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_205 = _csr_exists_T_204 | _csr_exists_T_49; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_206 = _csr_exists_T_205 | _csr_exists_T_50; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_207 = _csr_exists_T_206 | _csr_exists_T_51; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_208 = _csr_exists_T_207 | _csr_exists_T_52; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_209 = _csr_exists_T_208 | _csr_exists_T_53; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_210 = _csr_exists_T_209 | _csr_exists_T_54; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_211 = _csr_exists_T_210 | _csr_exists_T_55; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_212 = _csr_exists_T_211 | _csr_exists_T_56; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_213 = _csr_exists_T_212 | _csr_exists_T_57; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_214 = _csr_exists_T_213 | _csr_exists_T_58; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_215 = _csr_exists_T_214 | _csr_exists_T_59; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_216 = _csr_exists_T_215 | _csr_exists_T_60; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_217 = _csr_exists_T_216 | _csr_exists_T_61; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_218 = _csr_exists_T_217 | _csr_exists_T_62; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_219 = _csr_exists_T_218 | _csr_exists_T_63; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_220 = _csr_exists_T_219 | _csr_exists_T_64; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_221 = _csr_exists_T_220 | _csr_exists_T_65; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_222 = _csr_exists_T_221 | _csr_exists_T_66; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_223 = _csr_exists_T_222 | _csr_exists_T_67; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_224 = _csr_exists_T_223 | _csr_exists_T_68; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_225 = _csr_exists_T_224 | _csr_exists_T_69; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_226 = _csr_exists_T_225 | _csr_exists_T_70; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_227 = _csr_exists_T_226 | _csr_exists_T_71; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_228 = _csr_exists_T_227 | _csr_exists_T_72; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_229 = _csr_exists_T_228 | _csr_exists_T_73; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_230 = _csr_exists_T_229 | _csr_exists_T_74; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_231 = _csr_exists_T_230 | _csr_exists_T_75; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_232 = _csr_exists_T_231 | _csr_exists_T_76; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_233 = _csr_exists_T_232 | _csr_exists_T_77; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_234 = _csr_exists_T_233 | _csr_exists_T_78; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_235 = _csr_exists_T_234 | _csr_exists_T_79; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_236 = _csr_exists_T_235 | _csr_exists_T_80; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_237 = _csr_exists_T_236 | _csr_exists_T_81; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_238 = _csr_exists_T_237 | _csr_exists_T_82; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_239 = _csr_exists_T_238 | _csr_exists_T_83; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_240 = _csr_exists_T_239 | _csr_exists_T_84; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_241 = _csr_exists_T_240 | _csr_exists_T_85; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_242 = _csr_exists_T_241 | _csr_exists_T_86; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_243 = _csr_exists_T_242 | _csr_exists_T_87; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_244 = _csr_exists_T_243 | _csr_exists_T_88; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_245 = _csr_exists_T_244 | _csr_exists_T_89; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_246 = _csr_exists_T_245 | _csr_exists_T_90; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_247 = _csr_exists_T_246 | _csr_exists_T_91; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_248 = _csr_exists_T_247 | _csr_exists_T_92; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_249 = _csr_exists_T_248 | _csr_exists_T_93; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_250 = _csr_exists_T_249 | _csr_exists_T_94; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_251 = _csr_exists_T_250 | _csr_exists_T_95; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_252 = _csr_exists_T_251 | _csr_exists_T_96; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_253 = _csr_exists_T_252 | _csr_exists_T_97; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_254 = _csr_exists_T_253 | _csr_exists_T_98; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_255 = _csr_exists_T_254 | _csr_exists_T_99; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_256 = _csr_exists_T_255 | _csr_exists_T_100; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_257 = _csr_exists_T_256 | _csr_exists_T_101; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_258 = _csr_exists_T_257 | _csr_exists_T_102; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_259 = _csr_exists_T_258 | _csr_exists_T_103; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_260 = _csr_exists_T_259 | _csr_exists_T_104; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_261 = _csr_exists_T_260 | _csr_exists_T_105; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_262 = _csr_exists_T_261 | _csr_exists_T_106; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_263 = _csr_exists_T_262 | _csr_exists_T_107; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_264 = _csr_exists_T_263 | _csr_exists_T_108; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_265 = _csr_exists_T_264 | _csr_exists_T_109; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_266 = _csr_exists_T_265 | _csr_exists_T_110; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_267 = _csr_exists_T_266 | _csr_exists_T_111; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_268 = _csr_exists_T_267 | _csr_exists_T_112; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_269 = _csr_exists_T_268 | _csr_exists_T_113; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_270 = _csr_exists_T_269 | _csr_exists_T_114; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_271 = _csr_exists_T_270 | _csr_exists_T_115; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_272 = _csr_exists_T_271 | _csr_exists_T_116; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_273 = _csr_exists_T_272 | _csr_exists_T_117; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_274 = _csr_exists_T_273 | _csr_exists_T_118; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_275 = _csr_exists_T_274 | _csr_exists_T_119; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_276 = _csr_exists_T_275 | _csr_exists_T_120; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_277 = _csr_exists_T_276 | _csr_exists_T_121; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_278 = _csr_exists_T_277 | _csr_exists_T_122; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_279 = _csr_exists_T_278 | _csr_exists_T_123; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_280 = _csr_exists_T_279 | _csr_exists_T_124; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_281 = _csr_exists_T_280 | _csr_exists_T_125; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_282 = _csr_exists_T_281 | _csr_exists_T_126; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_283 = _csr_exists_T_282 | _csr_exists_T_127; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_284 = _csr_exists_T_283 | _csr_exists_T_128; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_285 = _csr_exists_T_284 | _csr_exists_T_129; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_286 = _csr_exists_T_285 | _csr_exists_T_130; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_287 = _csr_exists_T_286 | _csr_exists_T_131; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_288 = _csr_exists_T_287 | _csr_exists_T_132; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_289 = _csr_exists_T_288 | _csr_exists_T_133; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_290 = _csr_exists_T_289 | _csr_exists_T_134; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_291 = _csr_exists_T_290 | _csr_exists_T_135; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_292 = _csr_exists_T_291 | _csr_exists_T_136; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_293 = _csr_exists_T_292 | _csr_exists_T_137; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_294 = _csr_exists_T_293 | _csr_exists_T_138; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_295 = _csr_exists_T_294 | _csr_exists_T_139; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_296 = _csr_exists_T_295 | _csr_exists_T_140; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_297 = _csr_exists_T_296 | _csr_exists_T_141; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_298 = _csr_exists_T_297 | _csr_exists_T_142; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_299 = _csr_exists_T_298 | _csr_exists_T_143; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_300 = _csr_exists_T_299 | _csr_exists_T_144; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_301 = _csr_exists_T_300 | _csr_exists_T_145; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_302 = _csr_exists_T_301 | _csr_exists_T_146; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_303 = _csr_exists_T_302 | _csr_exists_T_147; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_304 = _csr_exists_T_303 | _csr_exists_T_148; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_305 = _csr_exists_T_304 | _csr_exists_T_149; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_306 = _csr_exists_T_305 | _csr_exists_T_150; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_307 = _csr_exists_T_306 | _csr_exists_T_151; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_308 = _csr_exists_T_307 | _csr_exists_T_152; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_309 = _csr_exists_T_308 | _csr_exists_T_153; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_310 = _csr_exists_T_309 | _csr_exists_T_154; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_311 = _csr_exists_T_310 | _csr_exists_T_155; // @[CSR.scala:899:{93,111}] wire csr_exists = _csr_exists_T_311 | _csr_exists_T_156; // @[CSR.scala:899:{93,111}] wire _io_decode_0_read_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28] wire _io_decode_0_read_illegal_T_1 = ~csr_exists; // @[CSR.scala:899:111, :924:7] wire _io_decode_0_read_illegal_T_2 = _io_decode_0_read_illegal_T | _io_decode_0_read_illegal_T_1; // @[CSR.scala:923:{28,44}, :924:7] wire _io_decode_0_read_illegal_T_4 = addr == 12'h680; // @[CSR.scala:897:27, :925:38] wire _io_decode_0_read_illegal_T_5 = _io_decode_0_read_illegal_T_3 | _io_decode_0_read_illegal_T_4; // @[CSR.scala:925:{14,30,38}] wire _io_decode_0_read_illegal_T_6 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59] wire _io_decode_0_read_illegal_T_7 = _io_decode_0_read_illegal_T_5 & _io_decode_0_read_illegal_T_6; // @[CSR.scala:925:{30,56,59}] wire _io_decode_0_read_illegal_T_8 = _io_decode_0_read_illegal_T_2 | _io_decode_0_read_illegal_T_7; // @[CSR.scala:923:44, :924:19, :925:56] wire _io_decode_0_read_illegal_T_9 = ~allow_counter; // @[CSR.scala:913:91, :926:21] wire _io_decode_0_read_illegal_T_10 = is_counter & _io_decode_0_read_illegal_T_9; // @[CSR.scala:904:81, :926:{18,21}] wire _io_decode_0_read_illegal_T_11 = _io_decode_0_read_illegal_T_8 | _io_decode_0_read_illegal_T_10; // @[CSR.scala:924:19, :925:78, :926:18] wire [11:0] io_decode_0_read_illegal_invInputs = ~io_decode_0_read_illegal_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_12 = io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = io_decode_0_read_illegal_plaInput[4]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = io_decode_0_read_illegal_plaInput[5]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = io_decode_0_read_illegal_invInputs[6]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = io_decode_0_read_illegal_plaInput[7]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = io_decode_0_read_illegal_plaInput[8]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = io_decode_0_read_illegal_plaInput[9]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = io_decode_0_read_illegal_plaInput[10]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = io_decode_0_read_illegal_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_lo = {io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_hi = {io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _io_decode_0_read_illegal_andMatrixOutputs_T = {io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_read_illegal_andMatrixOutputs_0_2 = &_io_decode_0_read_illegal_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_read_illegal_orMatrixOutputs = io_decode_0_read_illegal_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_read_illegal_invMatrixOutputs = io_decode_0_read_illegal_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_read_illegal_plaOutput = io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:81:23, :124:31] wire _io_decode_0_read_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45] wire _io_decode_0_read_illegal_T_14 = _io_decode_0_read_illegal_T_12 & _io_decode_0_read_illegal_T_13; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_15 = _io_decode_0_read_illegal_T_11 | _io_decode_0_read_illegal_T_14; // @[CSR.scala:925:78, :926:36, :927:42] wire [11:0] io_decode_0_read_illegal_invInputs_1 = ~io_decode_0_read_illegal_plaInput_1; // @[pla.scala:77:22, :78:21] wire io_decode_0_read_illegal_invMatrixOutputs_1; // @[pla.scala:124:31] wire io_decode_0_read_illegal_plaOutput_1; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_16 = io_decode_0_read_illegal_plaOutput_1; // @[pla.scala:81:23] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0_1 = io_decode_0_read_illegal_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1_1 = io_decode_0_read_illegal_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2_1 = io_decode_0_read_illegal_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3_1 = io_decode_0_read_illegal_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1_2 = io_decode_0_read_illegal_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4_1 = io_decode_0_read_illegal_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2_2 = io_decode_0_read_illegal_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5_1 = io_decode_0_read_illegal_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3_2 = io_decode_0_read_illegal_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6_1 = io_decode_0_read_illegal_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4_2 = io_decode_0_read_illegal_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7_1 = io_decode_0_read_illegal_invInputs_1[10]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_8 = io_decode_0_read_illegal_invInputs_1[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_lo_1 = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7_1, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_hi_1 = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5_1, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_lo_1 = {io_decode_0_read_illegal_andMatrixOutputs_lo_hi_1, io_decode_0_read_illegal_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_lo_1 = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3_1, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_hi_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0_1, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] io_decode_0_read_illegal_andMatrixOutputs_hi_hi_1 = {io_decode_0_read_illegal_andMatrixOutputs_hi_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [4:0] io_decode_0_read_illegal_andMatrixOutputs_hi_1 = {io_decode_0_read_illegal_andMatrixOutputs_hi_hi_1, io_decode_0_read_illegal_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [8:0] _io_decode_0_read_illegal_andMatrixOutputs_T_1 = {io_decode_0_read_illegal_andMatrixOutputs_hi_1, io_decode_0_read_illegal_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire io_decode_0_read_illegal_andMatrixOutputs_0_2_1 = &_io_decode_0_read_illegal_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0_2 = io_decode_0_read_illegal_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5_2 = io_decode_0_read_illegal_plaInput_1[10]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6_2 = io_decode_0_read_illegal_plaInput_1[11]; // @[pla.scala:77:22, :90:45] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_hi_2 = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] io_decode_0_read_illegal_andMatrixOutputs_lo_2 = {io_decode_0_read_illegal_andMatrixOutputs_lo_hi_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:90:45, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_lo_2 = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_hi_2 = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_hi_2 = {io_decode_0_read_illegal_andMatrixOutputs_hi_hi_2, io_decode_0_read_illegal_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] _io_decode_0_read_illegal_andMatrixOutputs_T_2 = {io_decode_0_read_illegal_andMatrixOutputs_hi_2, io_decode_0_read_illegal_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire io_decode_0_read_illegal_andMatrixOutputs_1_2 = &_io_decode_0_read_illegal_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire [1:0] _io_decode_0_read_illegal_orMatrixOutputs_T = {io_decode_0_read_illegal_andMatrixOutputs_0_2_1, io_decode_0_read_illegal_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire io_decode_0_read_illegal_orMatrixOutputs_1 = |_io_decode_0_read_illegal_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] assign io_decode_0_read_illegal_invMatrixOutputs_1 = io_decode_0_read_illegal_orMatrixOutputs_1; // @[pla.scala:114:36, :124:31] assign io_decode_0_read_illegal_plaOutput_1 = io_decode_0_read_illegal_invMatrixOutputs_1; // @[pla.scala:81:23, :124:31] wire _io_decode_0_read_illegal_T_17 = _io_decode_0_read_illegal_T_16 & io_decode_0_vector_illegal_0; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_18 = _io_decode_0_read_illegal_T_15 | _io_decode_0_read_illegal_T_17; // @[CSR.scala:926:36, :927:56, :928:43] wire _io_decode_0_read_illegal_T_19 = io_decode_0_fp_csr_0 & io_decode_0_fp_illegal_0; // @[CSR.scala:377:7, :929:21] assign _io_decode_0_read_illegal_T_20 = _io_decode_0_read_illegal_T_18 | _io_decode_0_read_illegal_T_19; // @[CSR.scala:927:56, :928:68, :929:21] assign io_decode_0_read_illegal_0 = _io_decode_0_read_illegal_T_20; // @[CSR.scala:377:7, :928:68] wire [1:0] _io_decode_0_write_illegal_T = addr[11:10]; // @[CSR.scala:897:27, :930:33] assign _io_decode_0_write_illegal_T_1 = &_io_decode_0_write_illegal_T; // @[CSR.scala:930:{33,41}] assign io_decode_0_write_illegal_0 = _io_decode_0_write_illegal_T_1; // @[CSR.scala:377:7, :930:41] wire [11:0] io_decode_0_write_flush_addr_m = {_io_decode_0_write_illegal_T, addr[9:0] | 10'h300}; // @[CSR.scala:897:27, :930:33, :932:25] wire _io_decode_0_write_flush_T = io_decode_0_write_flush_addr_m > 12'h33F; // @[CSR.scala:932:25, :933:16] wire _io_decode_0_write_flush_T_1 = io_decode_0_write_flush_addr_m < 12'h344; // @[CSR.scala:932:25, :933:45] wire _io_decode_0_write_flush_T_2 = _io_decode_0_write_flush_T & _io_decode_0_write_flush_T_1; // @[CSR.scala:933:{16,35,45}] assign _io_decode_0_write_flush_T_3 = ~_io_decode_0_write_flush_T_2; // @[CSR.scala:933:{7,35}] assign io_decode_0_write_flush_0 = _io_decode_0_write_flush_T_3; // @[CSR.scala:377:7, :933:7] wire _io_decode_0_system_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28, :935:30] wire _io_decode_0_system_illegal_T_1 = ~is_hlsv; // @[CSR.scala:903:82, :935:49] wire _io_decode_0_system_illegal_T_2 = _io_decode_0_system_illegal_T & _io_decode_0_system_illegal_T_1; // @[CSR.scala:935:{30,46,49}] wire _io_decode_0_system_illegal_T_3 = ~allow_wfi; // @[CSR.scala:906:71, :936:17] wire _io_decode_0_system_illegal_T_4 = is_wfi & _io_decode_0_system_illegal_T_3; // @[CSR.scala:903:82, :936:{14,17}] wire _io_decode_0_system_illegal_T_5 = _io_decode_0_system_illegal_T_2 | _io_decode_0_system_illegal_T_4; // @[CSR.scala:935:{46,58}, :936:14] wire _io_decode_0_system_illegal_T_6 = ~allow_sret; // @[CSR.scala:910:72, :937:17] wire _io_decode_0_system_illegal_T_7 = is_ret & _io_decode_0_system_illegal_T_6; // @[CSR.scala:903:82, :937:{14,17}] wire _io_decode_0_system_illegal_T_8 = _io_decode_0_system_illegal_T_5 | _io_decode_0_system_illegal_T_7; // @[CSR.scala:935:58, :936:28, :937:14] wire _io_decode_0_system_illegal_T_9 = addr[10]; // @[CSR.scala:897:27, :938:21] wire _io_decode_0_system_illegal_T_10 = is_ret & _io_decode_0_system_illegal_T_9; // @[CSR.scala:903:82, :938:{14,21}] wire _io_decode_0_system_illegal_T_11 = addr[7]; // @[CSR.scala:897:27, :938:33] wire _io_decode_0_system_illegal_T_12 = _io_decode_0_system_illegal_T_10 & _io_decode_0_system_illegal_T_11; // @[CSR.scala:938:{14,26,33}] wire _io_decode_0_system_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45, :938:40] wire _io_decode_0_system_illegal_T_14 = _io_decode_0_system_illegal_T_12 & _io_decode_0_system_illegal_T_13; // @[CSR.scala:938:{26,37,40}] wire _io_decode_0_system_illegal_T_15 = _io_decode_0_system_illegal_T_8 | _io_decode_0_system_illegal_T_14; // @[CSR.scala:936:28, :937:29, :938:37] wire _io_decode_0_system_illegal_T_16 = is_sfence | is_hfence_gvma; // @[CSR.scala:903:82, :939:18] wire _io_decode_0_system_illegal_T_17 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59, :939:40] wire _io_decode_0_system_illegal_T_18 = _io_decode_0_system_illegal_T_16 & _io_decode_0_system_illegal_T_17; // @[CSR.scala:939:{18,37,40}] wire _io_decode_0_system_illegal_T_19 = _io_decode_0_system_illegal_T_15 | _io_decode_0_system_illegal_T_18; // @[CSR.scala:937:29, :938:51, :939:37] wire _io_decode_0_system_illegal_T_22 = _io_decode_0_system_illegal_T_19; // @[CSR.scala:938:51, :939:58] assign _io_decode_0_system_illegal_T_25 = _io_decode_0_system_illegal_T_22; // @[CSR.scala:939:58, :940:44] assign io_decode_0_system_illegal_0 = _io_decode_0_system_illegal_T_25; // @[CSR.scala:377:7, :940:44] wire _io_decode_0_virtual_access_illegal_T = reg_mstatus_v & csr_exists; // @[CSR.scala:395:28, :899:111, :943:52] wire _io_decode_0_virtual_access_illegal_T_2 = _io_decode_0_virtual_access_illegal_T_1 == 2'h2; // @[CSR.scala:190:36, :944:22] wire _io_decode_0_virtual_access_illegal_T_4 = _io_decode_0_virtual_access_illegal_T_3[0]; // @[CSR.scala:945:36] wire _io_decode_0_virtual_access_illegal_T_5 = is_counter & _io_decode_0_virtual_access_illegal_T_4; // @[CSR.scala:904:81, :945:{18,36}] wire _io_decode_0_virtual_access_illegal_T_7 = _io_decode_0_virtual_access_illegal_T_6[0]; // @[CSR.scala:945:71] wire _io_decode_0_virtual_access_illegal_T_8 = ~_io_decode_0_virtual_access_illegal_T_7; // @[CSR.scala:945:{55,71}] wire _io_decode_0_virtual_access_illegal_T_9 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105] wire _io_decode_0_virtual_access_illegal_T_20 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :946:53] wire _io_decode_0_virtual_access_illegal_T_25 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :947:46] wire _io_decode_0_virtual_system_illegal_T_2 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :953:34] wire _io_decode_0_virtual_system_illegal_T_12 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :954:64] wire _io_decode_0_virtual_system_illegal_T_17 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :955:37] wire _cause_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :959:61] wire _reg_hstatus_spvp_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :1067:61] wire _io_decode_0_virtual_access_illegal_T_10 = ~_io_decode_0_virtual_access_illegal_T_9; // @[CSR.scala:945:{89,105}] wire _io_decode_0_virtual_access_illegal_T_12 = _io_decode_0_virtual_access_illegal_T_11[0]; // @[CSR.scala:945:128] wire _io_decode_0_virtual_access_illegal_T_13 = ~_io_decode_0_virtual_access_illegal_T_12; // @[CSR.scala:945:{112,128}] wire _io_decode_0_virtual_access_illegal_T_14 = _io_decode_0_virtual_access_illegal_T_10 & _io_decode_0_virtual_access_illegal_T_13; // @[CSR.scala:945:{89,109,112}] wire _io_decode_0_virtual_access_illegal_T_15 = _io_decode_0_virtual_access_illegal_T_8 | _io_decode_0_virtual_access_illegal_T_14; // @[CSR.scala:945:{55,86,109}] wire _io_decode_0_virtual_access_illegal_T_16 = _io_decode_0_virtual_access_illegal_T_5 & _io_decode_0_virtual_access_illegal_T_15; // @[CSR.scala:945:{18,51,86}] wire _io_decode_0_virtual_access_illegal_T_17 = _io_decode_0_virtual_access_illegal_T_2 | _io_decode_0_virtual_access_illegal_T_16; // @[CSR.scala:944:{22,34}, :945:51] wire _io_decode_0_virtual_access_illegal_T_19 = _io_decode_0_virtual_access_illegal_T_18 == 2'h1; // @[CSR.scala:190:36, :946:22] wire _io_decode_0_virtual_access_illegal_T_21 = ~_io_decode_0_virtual_access_illegal_T_20; // @[CSR.scala:946:{37,53}] wire _io_decode_0_virtual_access_illegal_T_22 = _io_decode_0_virtual_access_illegal_T_19 & _io_decode_0_virtual_access_illegal_T_21; // @[CSR.scala:946:{22,34,37}] wire _io_decode_0_virtual_access_illegal_T_23 = _io_decode_0_virtual_access_illegal_T_17 | _io_decode_0_virtual_access_illegal_T_22; // @[CSR.scala:944:34, :945:144, :946:34] wire _io_decode_0_virtual_access_illegal_T_28 = _io_decode_0_virtual_access_illegal_T_23; // @[CSR.scala:945:144, :946:57] wire _io_decode_0_virtual_access_illegal_T_26 = _io_decode_0_virtual_access_illegal_T_24 & _io_decode_0_virtual_access_illegal_T_25; // @[CSR.scala:947:{12,28,46}] assign _io_decode_0_virtual_access_illegal_T_29 = _io_decode_0_virtual_access_illegal_T & _io_decode_0_virtual_access_illegal_T_28; // @[CSR.scala:943:{52,66}, :946:57] assign io_decode_0_virtual_access_illegal_0 = _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:377:7, :943:66] wire _io_decode_0_virtual_system_illegal_T = is_hfence_vvma | is_hfence_gvma; // @[CSR.scala:903:82, :950:22] wire _io_decode_0_virtual_system_illegal_T_1 = _io_decode_0_virtual_system_illegal_T | is_hlsv; // @[CSR.scala:903:82, :950:22, :951:22] wire _io_decode_0_virtual_system_illegal_T_3 = ~_io_decode_0_virtual_system_illegal_T_2; // @[CSR.scala:953:{18,34}] wire _io_decode_0_virtual_system_illegal_T_6 = _io_decode_0_virtual_system_illegal_T_3; // @[CSR.scala:953:{18,38}] wire _io_decode_0_virtual_system_illegal_T_4 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74, :953:41] wire _io_decode_0_virtual_system_illegal_T_7 = is_wfi & _io_decode_0_virtual_system_illegal_T_6; // @[CSR.scala:903:82, :953:{14,38}] wire _io_decode_0_virtual_system_illegal_T_8 = _io_decode_0_virtual_system_illegal_T_1 | _io_decode_0_virtual_system_illegal_T_7; // @[CSR.scala:951:22, :952:15, :953:14] wire _io_decode_0_virtual_system_illegal_T_10 = _io_decode_0_virtual_system_illegal_T_9 == 2'h1; // @[CSR.scala:190:36, :954:32] wire _io_decode_0_virtual_system_illegal_T_11 = is_ret & _io_decode_0_virtual_system_illegal_T_10; // @[CSR.scala:903:82, :954:{14,32}] wire _io_decode_0_virtual_system_illegal_T_13 = ~_io_decode_0_virtual_system_illegal_T_12; // @[CSR.scala:954:{48,64}] wire _io_decode_0_virtual_system_illegal_T_14 = _io_decode_0_virtual_system_illegal_T_13; // @[CSR.scala:954:{48,68}] wire _io_decode_0_virtual_system_illegal_T_15 = _io_decode_0_virtual_system_illegal_T_11 & _io_decode_0_virtual_system_illegal_T_14; // @[CSR.scala:954:{14,44,68}] wire _io_decode_0_virtual_system_illegal_T_16 = _io_decode_0_virtual_system_illegal_T_8 | _io_decode_0_virtual_system_illegal_T_15; // @[CSR.scala:952:15, :953:77, :954:44] wire _io_decode_0_virtual_system_illegal_T_18 = ~_io_decode_0_virtual_system_illegal_T_17; // @[CSR.scala:955:{21,37}] wire _io_decode_0_virtual_system_illegal_T_19 = _io_decode_0_virtual_system_illegal_T_18; // @[CSR.scala:955:{21,41}] wire _io_decode_0_virtual_system_illegal_T_20 = is_sfence & _io_decode_0_virtual_system_illegal_T_19; // @[CSR.scala:903:82, :955:{17,41}] wire _io_decode_0_virtual_system_illegal_T_21 = _io_decode_0_virtual_system_illegal_T_16 | _io_decode_0_virtual_system_illegal_T_20; // @[CSR.scala:953:77, :954:89, :955:17] assign _io_decode_0_virtual_system_illegal_T_22 = reg_mstatus_v & _io_decode_0_virtual_system_illegal_T_21; // @[CSR.scala:395:28, :949:52, :954:89] assign io_decode_0_virtual_system_illegal_0 = _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:377:7, :949:52] wire _cause_T_1 = _cause_T & reg_mstatus_v; // @[CSR.scala:395:28, :959:{61,65}] wire [1:0] _cause_T_2 = _cause_T_1 ? 2'h2 : reg_mstatus_prv; // @[CSR.scala:395:28, :959:{45,65}] wire [4:0] _cause_T_3 = {3'h0, _cause_T_2} + 5'h8; // @[CSR.scala:959:{40,45}] wire [3:0] _cause_T_4 = _cause_T_3[3:0]; // @[CSR.scala:959:40] wire [63:0] _cause_T_5 = insn_break ? 64'h3 : io_cause_0; // @[CSR.scala:377:7, :893:83, :960:14] assign cause = insn_call ? {60'h0, _cause_T_4} : _cause_T_5; // @[CSR.scala:893:83, :959:{8,40}, :960:14] assign io_trace_0_cause_0 = cause; // @[CSR.scala:377:7, :959:8] wire [7:0] cause_lsbs = cause[7:0]; // @[CSR.scala:959:8, :961:25] wire [5:0] cause_deleg_lsbs = cause[5:0]; // @[CSR.scala:959:8, :962:31] wire [5:0] _notDebugTVec_interruptOffset_T = cause[5:0]; // @[CSR.scala:959:8, :962:31, :979:32] wire _causeIsDebugInt_T = cause[63]; // @[CSR.scala:959:8, :963:30] wire _causeIsDebugTrigger_T = cause[63]; // @[CSR.scala:959:8, :963:30, :964:35] wire _causeIsDebugBreak_T = cause[63]; // @[CSR.scala:959:8, :963:30, :965:33] wire _delegate_T_2 = cause[63]; // @[CSR.scala:959:8, :963:30, :970:78] wire _delegateVS_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :971:58] wire _notDebugTVec_doVector_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :981:36] wire _causeIsRnmiInt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :985:29] wire _causeIsRnmiBEU_T = cause[63]; // @[CSR.scala:959:8, :963:30, :986:29] wire _reg_vscause_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1060:31] assign _io_trace_0_interrupt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1626:25] wire _GEN_15 = cause_lsbs == 8'hE; // @[CSR.scala:961:25, :963:53] wire _causeIsDebugInt_T_1; // @[CSR.scala:963:53] assign _causeIsDebugInt_T_1 = _GEN_15; // @[CSR.scala:963:53] wire _causeIsDebugTrigger_T_2; // @[CSR.scala:964:58] assign _causeIsDebugTrigger_T_2 = _GEN_15; // @[CSR.scala:963:53, :964:58] wire causeIsDebugInt = _causeIsDebugInt_T & _causeIsDebugInt_T_1; // @[CSR.scala:963:{30,39,53}] wire _causeIsDebugTrigger_T_1 = ~_causeIsDebugTrigger_T; // @[CSR.scala:964:{29,35}] wire causeIsDebugTrigger = _causeIsDebugTrigger_T_1 & _causeIsDebugTrigger_T_2; // @[CSR.scala:964:{29,44,58}] wire _causeIsDebugBreak_T_1 = ~_causeIsDebugBreak_T; // @[CSR.scala:965:{27,33}] wire _causeIsDebugBreak_T_2 = _causeIsDebugBreak_T_1 & insn_break; // @[CSR.scala:893:83, :965:{27,42}] wire [1:0] causeIsDebugBreak_lo = {reg_dcsr_ebreaks, reg_dcsr_ebreaku}; // @[CSR.scala:403:25, :965:62] wire [1:0] causeIsDebugBreak_hi = {reg_dcsr_ebreakm, 1'h0}; // @[CSR.scala:403:25, :965:62] wire [3:0] _causeIsDebugBreak_T_3 = {causeIsDebugBreak_hi, causeIsDebugBreak_lo}; // @[CSR.scala:965:62] wire [3:0] _causeIsDebugBreak_T_4 = _causeIsDebugBreak_T_3 >> reg_mstatus_prv; // @[CSR.scala:395:28, :965:{62,134}] wire _causeIsDebugBreak_T_5 = _causeIsDebugBreak_T_4[0]; // @[CSR.scala:965:134] wire causeIsDebugBreak = _causeIsDebugBreak_T_2 & _causeIsDebugBreak_T_5; // @[CSR.scala:965:{42,56,134}] wire _trapToDebug_T = reg_singleStepped | causeIsDebugInt; // @[CSR.scala:486:30, :963:39, :966:56] wire _trapToDebug_T_1 = _trapToDebug_T | causeIsDebugTrigger; // @[CSR.scala:964:44, :966:{56,75}] wire _trapToDebug_T_2 = _trapToDebug_T_1 | causeIsDebugBreak; // @[CSR.scala:965:56, :966:{75,98}] wire _trapToDebug_T_3 = _trapToDebug_T_2 | reg_debug; // @[CSR.scala:482:26, :966:{98,119}] wire trapToDebug = _trapToDebug_T_3; // @[CSR.scala:966:{34,119}] wire [11:0] _debugTVec_T = {8'h80, ~insn_break, 3'h0}; // @[CSR.scala:893:83, :969:37] wire [11:0] debugTVec = reg_debug ? _debugTVec_T : 12'h800; // @[CSR.scala:482:26, :969:{22,37}] wire _delegate_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51, :970:55] wire _delegate_T_1 = _delegate_T; // @[CSR.scala:970:{36,55}] wire [63:0] _GEN_16 = {58'h0, cause_deleg_lsbs}; // @[CSR.scala:962:31, :970:100] wire [63:0] _delegate_T_3 = read_mideleg >> _GEN_16; // @[CSR.scala:498:14, :970:100] wire _delegate_T_4 = _delegate_T_3[0]; // @[CSR.scala:970:100] wire [63:0] _delegate_T_5 = read_medeleg >> _GEN_16; // @[CSR.scala:502:14, :970:{100,132}] wire _delegate_T_6 = _delegate_T_5[0]; // @[CSR.scala:970:132] wire _delegate_T_7 = _delegate_T_2 ? _delegate_T_4 : _delegate_T_6; // @[CSR.scala:970:{72,78,100,132}] wire delegate = _delegate_T_1 & _delegate_T_7; // @[CSR.scala:970:{36,66,72}] wire _delegateVS_T = reg_mstatus_v & delegate; // @[CSR.scala:395:28, :970:66, :971:34] wire [63:0] _GEN_17 = 64'h0 >> _GEN_16; // @[CSR.scala:970:100, :971:80] wire [63:0] _delegateVS_T_2; // @[CSR.scala:971:80] assign _delegateVS_T_2 = _GEN_17; // @[CSR.scala:971:80] wire [63:0] _delegateVS_T_4; // @[CSR.scala:971:112] assign _delegateVS_T_4 = _GEN_17; // @[CSR.scala:971:{80,112}] wire _delegateVS_T_3 = _delegateVS_T_2[0]; // @[CSR.scala:971:80] wire _delegateVS_T_5 = _delegateVS_T_4[0]; // @[CSR.scala:971:112] wire _delegateVS_T_6 = _delegateVS_T_1 ? _delegateVS_T_3 : _delegateVS_T_5; // @[CSR.scala:971:{52,58,80,112}] wire delegateVS = _delegateVS_T & _delegateVS_T_6; // @[CSR.scala:971:{34,46,52}] wire [63:0] _notDebugTVec_base_T = delegateVS ? read_vstvec : read_stvec; // @[package.scala:132:15] wire [63:0] notDebugTVec_base = delegate ? _notDebugTVec_base_T : read_mtvec; // @[package.scala:138:15] wire [7:0] notDebugTVec_interruptOffset = {_notDebugTVec_interruptOffset_T, 2'h0}; // @[CSR.scala:979:{32,59}] wire [55:0] _notDebugTVec_interruptVec_T = notDebugTVec_base[63:8]; // @[CSR.scala:978:19, :980:33] wire [63:0] notDebugTVec_interruptVec = {_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset}; // @[CSR.scala:979:59, :980:{27,33}] wire _notDebugTVec_doVector_T = notDebugTVec_base[0]; // @[CSR.scala:978:19, :981:24] wire _notDebugTVec_doVector_T_2 = _notDebugTVec_doVector_T & _notDebugTVec_doVector_T_1; // @[CSR.scala:981:{24,28,36}] wire [1:0] _notDebugTVec_doVector_T_3 = cause_lsbs[7:6]; // @[CSR.scala:961:25, :981:70] wire _notDebugTVec_doVector_T_4 = _notDebugTVec_doVector_T_3 == 2'h0; // @[CSR.scala:981:{70,94}] wire notDebugTVec_doVector = _notDebugTVec_doVector_T_2 & _notDebugTVec_doVector_T_4; // @[CSR.scala:981:{28,55,94}] wire [61:0] _notDebugTVec_T = notDebugTVec_base[63:2]; // @[CSR.scala:978:19, :982:38] wire [63:0] _notDebugTVec_T_1 = {_notDebugTVec_T, 2'h0}; // @[CSR.scala:982:{38,56}] wire [63:0] notDebugTVec = notDebugTVec_doVector ? notDebugTVec_interruptVec : _notDebugTVec_T_1; // @[CSR.scala:980:27, :981:55, :982:{8,56}] wire [63:0] _tvec_T = notDebugTVec; // @[CSR.scala:982:8, :995:45] wire _causeIsRnmiInt_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46] wire _causeIsRnmiBEU_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46, :986:46] wire _causeIsRnmiInt_T_2 = _causeIsRnmiInt_T & _causeIsRnmiInt_T_1; // @[CSR.scala:985:{29,38,46}] wire _causeIsRnmiInt_T_3 = cause_lsbs == 8'hD; // @[CSR.scala:961:25, :985:70] wire _GEN_18 = cause_lsbs == 8'hC; // @[CSR.scala:961:25, :985:107] wire _causeIsRnmiInt_T_4; // @[CSR.scala:985:107] assign _causeIsRnmiInt_T_4 = _GEN_18; // @[CSR.scala:985:107] wire _causeIsRnmiBEU_T_3; // @[CSR.scala:986:69] assign _causeIsRnmiBEU_T_3 = _GEN_18; // @[CSR.scala:985:107, :986:69] wire _causeIsRnmiInt_T_5 = _causeIsRnmiInt_T_3 | _causeIsRnmiInt_T_4; // @[CSR.scala:985:{70,93,107}] wire causeIsRnmiInt = _causeIsRnmiInt_T_2 & _causeIsRnmiInt_T_5; // @[CSR.scala:985:{38,55,93}] wire _causeIsRnmiBEU_T_2 = _causeIsRnmiBEU_T & _causeIsRnmiBEU_T_1; // @[CSR.scala:986:{29,38,46}] wire causeIsRnmiBEU = _causeIsRnmiBEU_T_2 & _causeIsRnmiBEU_T_3; // @[CSR.scala:986:{38,55,69}] wire [63:0] tvec = trapToDebug ? {52'h0, debugTVec} : _tvec_T; // @[CSR.scala:966:34, :969:22, :995:{17,45}] wire _GEN_19 = insn_call | insn_break; // @[CSR.scala:893:83, :1000:24] wire _io_eret_T; // @[CSR.scala:1000:24] assign _io_eret_T = _GEN_19; // @[CSR.scala:1000:24] wire _exception_T; // @[CSR.scala:1020:29] assign _exception_T = _GEN_19; // @[CSR.scala:1000:24, :1020:29] assign _io_eret_T_1 = _io_eret_T | insn_ret; // @[CSR.scala:893:83, :1000:{24,38}] assign io_eret_0 = _io_eret_T_1; // @[CSR.scala:377:7, :1000:38] wire _io_singleStep_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1001:37] assign _io_singleStep_T_1 = reg_dcsr_step & _io_singleStep_T; // @[CSR.scala:403:25, :1001:{34,37}] assign io_singleStep_0 = _io_singleStep_T_1; // @[CSR.scala:377:7, :1001:34] wire _io_status_sd_T = &io_status_fs_0; // @[CSR.scala:377:7, :1003:32] wire _io_status_sd_T_2 = _io_status_sd_T; // @[CSR.scala:1003:{32,37}] wire _io_status_sd_T_3 = &io_status_vs_0; // @[CSR.scala:377:7, :1003:74] assign _io_status_sd_T_4 = _io_status_sd_T_2 | _io_status_sd_T_3; // @[CSR.scala:1003:{37,58,74}] assign io_status_sd_0 = _io_status_sd_T_4; // @[CSR.scala:377:7, :1003:58] assign io_status_isa_0 = reg_misa[31:0]; // @[CSR.scala:377:7, :648:25, :1005:17] wire _io_status_dprv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1008:45] wire _io_status_dprv_T_1 = reg_mstatus_mprv & _io_status_dprv_T; // @[CSR.scala:395:28, :1008:{42,45}] assign _io_status_dprv_T_2 = _io_status_dprv_T_1 ? reg_mstatus_mpp : reg_mstatus_prv; // @[CSR.scala:395:28, :1008:{24,42}] assign io_status_dprv_0 = _io_status_dprv_T_2; // @[CSR.scala:377:7, :1008:24] wire _io_status_dv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1009:60] wire _io_status_dv_T_1 = reg_mstatus_mprv & _io_status_dv_T; // @[CSR.scala:395:28, :1009:{57,60}] wire _io_status_dv_T_2 = _io_status_dv_T_1 & reg_mstatus_mpv; // @[CSR.scala:395:28, :1009:{39,57}] assign _io_status_dv_T_3 = reg_mstatus_v | _io_status_dv_T_2; // @[CSR.scala:395:28, :1009:{33,39}] assign io_status_dv_0 = _io_status_dv_T_3; // @[CSR.scala:377:7, :1009:33] wire _io_gstatus_sd_T = &io_gstatus_fs_0; // @[CSR.scala:377:7, :1016:34] wire _io_gstatus_sd_T_2 = _io_gstatus_sd_T; // @[CSR.scala:1016:{34,39}] wire exception = _exception_T | io_exception_0; // @[CSR.scala:377:7, :1020:{29,43}] wire _en_T_8 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_20 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_32 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_44 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_56 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_68 = exception; // @[CSR.scala:1020:43, :1096:24] assign _io_trace_0_exception_T_1 = exception; // @[CSR.scala:1020:43, :1620:37] wire [39:0] _epc_T = ~io_pc_0; // @[CSR.scala:377:7, :1664:28] wire [39:0] _epc_T_1 = {_epc_T[39:1], 1'h1}; // @[CSR.scala:1664:{28,31}] wire [39:0] epc = ~_epc_T_1; // @[CSR.scala:1664:{26,31}] wire [39:0] tval = insn_break ? epc : io_tval_0; // @[CSR.scala:377:7, :893:83, :1033:17, :1664:26] wire [1:0] _reg_dcsr_cause_T = causeIsDebugTrigger ? 2'h2 : 2'h1; // @[CSR.scala:964:44, :1041:90] wire [1:0] _reg_dcsr_cause_T_1 = causeIsDebugInt ? 2'h3 : _reg_dcsr_cause_T; // @[CSR.scala:963:39, :1041:{58,90}] wire [2:0] _reg_dcsr_cause_T_2 = reg_singleStepped ? 3'h4 : {1'h0, _reg_dcsr_cause_T_1}; // @[CSR.scala:486:30, :1041:{30,58}] wire [1:0] _reg_mncause_T = {1'h1, causeIsRnmiBEU}; // @[CSR.scala:986:55, :1052:55] wire [63:0] _reg_mncause_T_1 = {62'h2000000000000000, _reg_mncause_T}; // @[CSR.scala:1052:{50,55}] wire [61:0] _reg_vscause_T_1 = cause[63:2]; // @[CSR.scala:959:8, :1060:50] wire [63:0] _reg_vscause_T_2 = {_reg_vscause_T_1, 2'h1}; // @[CSR.scala:1060:{44,50}] wire [63:0] _reg_vscause_T_3 = _reg_vscause_T ? _reg_vscause_T_2 : cause; // @[CSR.scala:959:8, :1060:{25,31,44}] wire _reg_hstatus_spvp_T_1 = reg_mstatus_v ? _reg_hstatus_spvp_T : reg_hstatus_spvp; // @[CSR.scala:395:28, :552:28, :1067:{30,61}] wire _GEN_20 = delegateVS | delegate; // @[CSR.scala:395:28, :970:66, :971:46, :1056:37, :1065:35, :1081:23] wire _en_T_5 = cause == 64'h8000000000000000; // @[CSR.scala:959:8, :1096:88] wire _en_T_11 = cause == 64'h8000000000000001; // @[CSR.scala:959:8, :1096:88] wire en_1 = _en_T_8 & _en_T_11; // @[CSR.scala:1096:{24,79,88}] wire _en_T_17 = cause == 64'h8000000000000002; // @[CSR.scala:959:8, :1096:88] wire _en_T_23 = cause == 64'h8000000000000003; // @[CSR.scala:959:8, :1096:88] wire en_3 = _en_T_20 & _en_T_23; // @[CSR.scala:1096:{24,79,88}] wire _en_T_29 = cause == 64'h8000000000000004; // @[CSR.scala:959:8, :1096:88] wire _en_T_35 = cause == 64'h8000000000000005; // @[CSR.scala:959:8, :1096:88] wire en_5 = _en_T_32 & _en_T_35; // @[CSR.scala:1096:{24,79,88}] wire _en_T_41 = cause == 64'h8000000000000006; // @[CSR.scala:959:8, :1096:88] wire _en_T_47 = cause == 64'h8000000000000007; // @[CSR.scala:959:8, :1096:88] wire en_7 = _en_T_44 & _en_T_47; // @[CSR.scala:1096:{24,79,88}] wire _en_T_53 = cause == 64'h8000000000000008; // @[CSR.scala:959:8, :1096:88] wire _en_T_59 = cause == 64'h8000000000000009; // @[CSR.scala:959:8, :1096:88] wire en_9 = _en_T_56 & _en_T_59; // @[CSR.scala:1096:{24,79,88}] wire _en_T_65 = cause == 64'h800000000000000A; // @[CSR.scala:959:8, :1096:88] wire _en_T_71 = cause == 64'h800000000000000B; // @[CSR.scala:959:8, :1096:88] wire en_11 = _en_T_68 & _en_T_71; // @[CSR.scala:1096:{24,79,88}] wire _en_T_77 = cause == 64'h800000000000000C; // @[CSR.scala:959:8, :1096:88] wire _en_T_83 = cause == 64'h800000000000000D; // @[CSR.scala:959:8, :1096:88] wire _en_T_89 = cause == 64'h800000000000000E; // @[CSR.scala:959:8, :1096:88] wire _en_T_95 = cause == 64'h800000000000000F; // @[CSR.scala:959:8, :1096:88] wire _en_T_96 = cause == 64'h0; // @[CSR.scala:959:8, :1108:35] wire en_16 = exception & _en_T_96; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_97 = cause == 64'h1; // @[CSR.scala:959:8, :1108:35] wire en_17 = exception & _en_T_97; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_98 = cause == 64'h2; // @[CSR.scala:959:8, :1108:35] wire en_18 = exception & _en_T_98; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_99 = cause == 64'h3; // @[CSR.scala:959:8, :1108:35] wire en_19 = exception & _en_T_99; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_100 = cause == 64'h4; // @[CSR.scala:959:8, :1108:35] wire en_20 = exception & _en_T_100; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_101 = cause == 64'h5; // @[CSR.scala:959:8, :1108:35] wire en_21 = exception & _en_T_101; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_102 = cause == 64'h6; // @[CSR.scala:959:8, :1108:35] wire en_22 = exception & _en_T_102; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_103 = cause == 64'h7; // @[CSR.scala:959:8, :1108:35] wire en_23 = exception & _en_T_103; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_104 = cause == 64'h8; // @[CSR.scala:959:8, :1108:35] wire en_24 = exception & _en_T_104; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_105 = cause == 64'h9; // @[CSR.scala:959:8, :1108:35] wire en_25 = exception & _en_T_105; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_106 = cause == 64'hB; // @[CSR.scala:959:8, :1108:35] wire en_26 = exception & _en_T_106; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_107 = cause == 64'hC; // @[CSR.scala:959:8, :1108:35] wire en_27 = exception & _en_T_107; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_108 = cause == 64'hD; // @[CSR.scala:959:8, :1108:35] wire en_28 = exception & _en_T_108; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_109 = cause == 64'hF; // @[CSR.scala:959:8, :1108:35] wire en_29 = exception & _en_T_109; // @[CSR.scala:1020:43, :1108:{26,35}] wire [1:0] ret_prv; // @[CSR.scala:1116:27] wire [1:0] _io_evec_T_2 = {~_io_evec_T_1, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [39:0] _io_evec_T_3 = {_io_evec_T[39:2], _io_evec_T[1:0] | _io_evec_T_2}; // @[CSR.scala:1665:{28,31,36}] wire [39:0] _io_evec_T_4 = ~_io_evec_T_3; // @[CSR.scala:1665:{26,31}] wire [39:0] _io_evec_T_5 = ~reg_vsepc; // @[CSR.scala:564:22, :1665:28] wire [1:0] _io_evec_T_7 = {~_io_evec_T_6, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [39:0] _io_evec_T_8 = {_io_evec_T_5[39:2], _io_evec_T_5[1:0] | _io_evec_T_7}; // @[CSR.scala:1665:{28,31,36}] wire [39:0] _io_evec_T_9 = ~_io_evec_T_8; // @[CSR.scala:1665:{26,31}] wire _T_248 = io_rw_addr_0[10] & io_rw_addr_0[7]; // @[CSR.scala:377:7, :1134:{43,48,61}] wire _reg_mstatus_v_T_2 = ~(reg_dcsr_prv[1]); // @[CSR.scala:403:25, :1136:72] wire [39:0] _io_evec_T_10 = ~reg_dpc; // @[CSR.scala:483:20, :1665:28] wire [1:0] _io_evec_T_12 = {~_io_evec_T_11, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [39:0] _io_evec_T_13 = {_io_evec_T_10[39:2], _io_evec_T_10[1:0] | _io_evec_T_12}; // @[CSR.scala:1665:{28,31,36}] wire [39:0] _io_evec_T_14 = ~_io_evec_T_13; // @[CSR.scala:1665:{26,31}] wire [1:0] _io_evec_T_17 = {~_io_evec_T_16, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [39:0] _io_evec_T_18 = {_io_evec_T_15[39:2], _io_evec_T_15[1:0] | _io_evec_T_17}; // @[CSR.scala:1665:{28,31,36}] wire [39:0] _io_evec_T_19 = ~_io_evec_T_18; // @[CSR.scala:1665:{26,31}] assign ret_prv = io_rw_addr_0[9] ? (_T_248 ? reg_dcsr_prv : reg_mstatus_mpp) : {1'h0, reg_mstatus_v ? reg_vsstatus_spp : reg_mstatus_spp}; // @[CSR.scala:377:7, :395:28, :403:25, :562:25, :1116:27, :1117:{43,48}, :1118:29, :1122:17, :1130:17, :1134:{48,66}, :1135:15, :1139:65] wire _reg_mstatus_v_T_8 = ~(reg_mstatus_mpp[1]); // @[CSR.scala:395:28, :1150:80] wire [39:0] _io_evec_T_20 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28] wire [1:0] _io_evec_T_22 = {~_io_evec_T_21, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [39:0] _io_evec_T_23 = {_io_evec_T_20[39:2], _io_evec_T_20[1:0] | _io_evec_T_22}; // @[CSR.scala:1665:{28,31,36}] wire [39:0] _io_evec_T_24 = ~_io_evec_T_23; // @[CSR.scala:1665:{26,31}] assign io_evec_0 = insn_ret ? (io_rw_addr_0[9] ? (_T_248 ? _io_evec_T_14 : _io_evec_T_24) : reg_mstatus_v ? _io_evec_T_9 : _io_evec_T_4) : tvec[39:0]; // @[CSR.scala:377:7, :395:28, :893:83, :995:17, :996:11, :1115:19, :1117:{43,48}, :1118:29, :1124:17, :1132:17, :1134:{48,66}, :1138:15, :1139:65, :1665:26] assign new_prv = insn_ret ? ret_prv : exception ? (trapToDebug ? (reg_debug ? reg_mstatus_prv : 2'h3) : {~_GEN_20, 1'h1}) : reg_mstatus_prv; // @[CSR.scala:395:28, :397:28, :482:26, :893:83, :966:34, :1020:43, :1035:20, :1036:24, :1037:25, :1044:17, :1046:31, :1056:37, :1064:15, :1065:35, :1078:15, :1081:23, :1091:15, :1115:19, :1116:27, :1154:13] assign _io_csr_stall_T = reg_wfi | io_status_cease_0; // @[CSR.scala:377:7, :575:54, :1161:27] assign io_csr_stall_0 = _io_csr_stall_T; // @[CSR.scala:377:7, :1161:27] reg io_status_cease_r; // @[CSR.scala:1162:31] assign io_status_cease_0 = io_status_cease_r; // @[CSR.scala:377:7, :1162:31] wire [63:0] _io_rw_rdata_T_1 = decoded_addr_57_2 ? read_mapping_1_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_157 = _io_rw_rdata_T_1; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_2 = decoded_addr_11_2 ? read_mapping_2_2 : 64'h0; // @[Mux.scala:30:73] wire [50:0] _io_rw_rdata_T_3 = decoded_addr_122_2 ? read_mapping_3_2 : 51'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_4 = decoded_addr_98_2 ? reg_misa : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_5 = decoded_addr_104_2 ? read_mstatus : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_6 = decoded_addr_75_2 ? read_mtvec : 64'h0; // @[Mux.scala:30:73] wire [15:0] _io_rw_rdata_T_7 = decoded_addr_112_2 ? read_mip : 16'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_8 = decoded_addr_79_2 ? reg_mie : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_9 = decoded_addr_135_2 ? reg_mscratch : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_10 = decoded_addr_138_2 ? read_mapping_10_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_11 = decoded_addr_142_2 ? read_mapping_11_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_12 = decoded_addr_30_2 ? reg_mcause : 64'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_13 = decoded_addr_137_2 & io_hartid_0; // @[Mux.scala:30:73] wire [31:0] _io_rw_rdata_T_14 = decoded_addr_50_2 ? debug_csrs_0_2 : 32'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_15 = decoded_addr_93_2 ? debug_csrs_1_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_16 = decoded_addr_59_2 ? reg_dscratch0 : 64'h0; // @[Mux.scala:30:73] wire [4:0] _io_rw_rdata_T_17 = decoded_addr_37_2 ? reg_fflags : 5'h0; // @[Mux.scala:30:73] wire [2:0] _io_rw_rdata_T_18 = decoded_addr_71_2 ? reg_frm : 3'h0; // @[Mux.scala:30:73] wire [7:0] _io_rw_rdata_T_19 = decoded_addr_103_2 ? read_fcsr : 8'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_20 = decoded_addr_60_2 & reg_vxsat; // @[Mux.scala:30:73] wire [1:0] _io_rw_rdata_T_21 = decoded_addr_6_2 ? reg_vxrm : 2'h0; // @[Mux.scala:30:73] wire [2:0] _io_rw_rdata_T_22 = decoded_addr_150_2 ? read_vcsr : 3'h0; // @[Mux.scala:30:73] wire [11:0] _io_rw_rdata_T_23 = decoded_addr_134_2 ? reg_vstart : 12'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_24 = decoded_addr_54_2 ? vector_csrs_4_2 : 64'h0; // @[Mux.scala:30:73] wire [12:0] _io_rw_rdata_T_25 = decoded_addr_131_2 ? reg_vconfig_vl : 13'h0; // @[Mux.scala:30:73] wire [9:0] _io_rw_rdata_T_26 = {decoded_addr_91_2, 9'h0}; // @[Mux.scala:30:73] wire [2:0] _io_rw_rdata_T_27 = decoded_addr_136_2 ? reg_mcountinhibit : 3'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_28 = decoded_addr_107_2 ? value_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_29 = decoded_addr_125_2 ? value : 64'h0; // @[Mux.scala:30:73] wire [31:0] _io_rw_rdata_T_117 = decoded_addr_36_2 ? read_mcounteren : 32'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_118 = decoded_addr_2_2 ? value_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_119 = decoded_addr_69_2 ? value : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_120 = decoded_addr_43_2 ? {57'h0, lo_4} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_121 = decoded_addr_64_2 ? {hi_7[41:0], lo_5} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_122 = decoded_addr_49_2 ? read_sip : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_123 = decoded_addr_45_2 ? read_sie : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_124 = decoded_addr_16_2 ? reg_sscratch : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_125 = decoded_addr_152_2 ? reg_scause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_126 = decoded_addr_97_2 ? {{24{reg_stval[39]}}, reg_stval} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_127 = decoded_addr_7_2 ? {hi_8, reg_satp_ppn} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_128 = decoded_addr_29_2 ? {{24{_T_30[39]}}, _T_30} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_129 = decoded_addr_26_2 ? read_stvec : 64'h0; // @[Mux.scala:30:73] wire [31:0] _io_rw_rdata_T_130 = decoded_addr_143_2 ? read_scounteren : 32'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_131 = decoded_addr_127_2 ? read_mideleg : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_132 = decoded_addr_24_2 ? read_medeleg : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_133 = decoded_addr_72_2 ? {57'h0, lo_6} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_134 = decoded_addr_147_2 ? {hi_18, lo_15} : 64'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_136 = decoded_addr_108_2 ? reg_pmp_0_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_137 = decoded_addr_9_2 ? reg_pmp_1_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_138 = decoded_addr_129_2 ? reg_pmp_2_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_139 = decoded_addr_88_2 ? reg_pmp_3_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_140 = decoded_addr_56_2 ? reg_pmp_4_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_141 = decoded_addr_21_2 ? reg_pmp_5_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_142 = decoded_addr_141_2 ? reg_pmp_6_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_143 = decoded_addr_119_2 ? reg_pmp_7_addr : 30'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_152 = decoded_addr_19_2 ? reg_custom_0 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_153 = decoded_addr_3_2 ? reg_custom_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_154 = decoded_addr_39_2 ? reg_custom_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_155 = decoded_addr_132_2 ? reg_custom_3 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_158 = _io_rw_rdata_T_157 | _io_rw_rdata_T_2; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_159 = {_io_rw_rdata_T_158[63:51], _io_rw_rdata_T_158[50:0] | _io_rw_rdata_T_3}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_160 = _io_rw_rdata_T_159 | _io_rw_rdata_T_4; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_161 = _io_rw_rdata_T_160 | _io_rw_rdata_T_5; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_162 = _io_rw_rdata_T_161 | _io_rw_rdata_T_6; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_163 = {_io_rw_rdata_T_162[63:16], _io_rw_rdata_T_162[15:0] | _io_rw_rdata_T_7}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_164 = _io_rw_rdata_T_163 | _io_rw_rdata_T_8; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_165 = _io_rw_rdata_T_164 | _io_rw_rdata_T_9; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_166 = _io_rw_rdata_T_165 | _io_rw_rdata_T_10; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_167 = _io_rw_rdata_T_166 | _io_rw_rdata_T_11; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_168 = _io_rw_rdata_T_167 | _io_rw_rdata_T_12; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_169 = {_io_rw_rdata_T_168[63:1], _io_rw_rdata_T_168[0] | _io_rw_rdata_T_13}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_170 = {_io_rw_rdata_T_169[63:32], _io_rw_rdata_T_169[31:0] | _io_rw_rdata_T_14}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_171 = _io_rw_rdata_T_170 | _io_rw_rdata_T_15; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_172 = _io_rw_rdata_T_171 | _io_rw_rdata_T_16; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_173 = {_io_rw_rdata_T_172[63:5], _io_rw_rdata_T_172[4:0] | _io_rw_rdata_T_17}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_174 = {_io_rw_rdata_T_173[63:3], _io_rw_rdata_T_173[2:0] | _io_rw_rdata_T_18}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_175 = {_io_rw_rdata_T_174[63:8], _io_rw_rdata_T_174[7:0] | _io_rw_rdata_T_19}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_176 = {_io_rw_rdata_T_175[63:1], _io_rw_rdata_T_175[0] | _io_rw_rdata_T_20}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_177 = {_io_rw_rdata_T_176[63:2], _io_rw_rdata_T_176[1:0] | _io_rw_rdata_T_21}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_178 = {_io_rw_rdata_T_177[63:3], _io_rw_rdata_T_177[2:0] | _io_rw_rdata_T_22}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_179 = {_io_rw_rdata_T_178[63:12], _io_rw_rdata_T_178[11:0] | _io_rw_rdata_T_23}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_180 = _io_rw_rdata_T_179 | _io_rw_rdata_T_24; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_181 = {_io_rw_rdata_T_180[63:13], _io_rw_rdata_T_180[12:0] | _io_rw_rdata_T_25}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_182 = {_io_rw_rdata_T_181[63:10], _io_rw_rdata_T_181[9:0] | _io_rw_rdata_T_26}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_183 = {_io_rw_rdata_T_182[63:3], _io_rw_rdata_T_182[2:0] | _io_rw_rdata_T_27}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_184 = _io_rw_rdata_T_183 | _io_rw_rdata_T_28; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_185 = _io_rw_rdata_T_184 | _io_rw_rdata_T_29; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_186 = _io_rw_rdata_T_185; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_187 = _io_rw_rdata_T_186; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_188 = _io_rw_rdata_T_187; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_189 = _io_rw_rdata_T_188; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_190 = _io_rw_rdata_T_189; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_191 = _io_rw_rdata_T_190; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_192 = _io_rw_rdata_T_191; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_193 = _io_rw_rdata_T_192; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_194 = _io_rw_rdata_T_193; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_195 = _io_rw_rdata_T_194; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_196 = _io_rw_rdata_T_195; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_197 = _io_rw_rdata_T_196; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_198 = _io_rw_rdata_T_197; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_199 = _io_rw_rdata_T_198; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_200 = _io_rw_rdata_T_199; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_201 = _io_rw_rdata_T_200; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_202 = _io_rw_rdata_T_201; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_203 = _io_rw_rdata_T_202; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_204 = _io_rw_rdata_T_203; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_205 = _io_rw_rdata_T_204; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_206 = _io_rw_rdata_T_205; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_207 = _io_rw_rdata_T_206; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_208 = _io_rw_rdata_T_207; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_209 = _io_rw_rdata_T_208; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_210 = _io_rw_rdata_T_209; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_211 = _io_rw_rdata_T_210; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_212 = _io_rw_rdata_T_211; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_213 = _io_rw_rdata_T_212; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_214 = _io_rw_rdata_T_213; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_215 = _io_rw_rdata_T_214; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_216 = _io_rw_rdata_T_215; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_217 = _io_rw_rdata_T_216; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_218 = _io_rw_rdata_T_217; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_219 = _io_rw_rdata_T_218; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_220 = _io_rw_rdata_T_219; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_221 = _io_rw_rdata_T_220; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_222 = _io_rw_rdata_T_221; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_223 = _io_rw_rdata_T_222; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_224 = _io_rw_rdata_T_223; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_225 = _io_rw_rdata_T_224; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_226 = _io_rw_rdata_T_225; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_227 = _io_rw_rdata_T_226; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_228 = _io_rw_rdata_T_227; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_229 = _io_rw_rdata_T_228; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_230 = _io_rw_rdata_T_229; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_231 = _io_rw_rdata_T_230; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_232 = _io_rw_rdata_T_231; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_233 = _io_rw_rdata_T_232; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_234 = _io_rw_rdata_T_233; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_235 = _io_rw_rdata_T_234; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_236 = _io_rw_rdata_T_235; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_237 = _io_rw_rdata_T_236; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_238 = _io_rw_rdata_T_237; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_239 = _io_rw_rdata_T_238; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_240 = _io_rw_rdata_T_239; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_241 = _io_rw_rdata_T_240; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_242 = _io_rw_rdata_T_241; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_243 = _io_rw_rdata_T_242; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_244 = _io_rw_rdata_T_243; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_245 = _io_rw_rdata_T_244; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_246 = _io_rw_rdata_T_245; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_247 = _io_rw_rdata_T_246; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_248 = _io_rw_rdata_T_247; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_249 = _io_rw_rdata_T_248; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_250 = _io_rw_rdata_T_249; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_251 = _io_rw_rdata_T_250; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_252 = _io_rw_rdata_T_251; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_253 = _io_rw_rdata_T_252; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_254 = _io_rw_rdata_T_253; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_255 = _io_rw_rdata_T_254; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_256 = _io_rw_rdata_T_255; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_257 = _io_rw_rdata_T_256; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_258 = _io_rw_rdata_T_257; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_259 = _io_rw_rdata_T_258; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_260 = _io_rw_rdata_T_259; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_261 = _io_rw_rdata_T_260; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_262 = _io_rw_rdata_T_261; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_263 = _io_rw_rdata_T_262; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_264 = _io_rw_rdata_T_263; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_265 = _io_rw_rdata_T_264; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_266 = _io_rw_rdata_T_265; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_267 = _io_rw_rdata_T_266; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_268 = _io_rw_rdata_T_267; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_269 = _io_rw_rdata_T_268; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_270 = _io_rw_rdata_T_269; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_271 = _io_rw_rdata_T_270; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_272 = _io_rw_rdata_T_271; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_273 = {_io_rw_rdata_T_272[63:32], _io_rw_rdata_T_272[31:0] | _io_rw_rdata_T_117}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_274 = _io_rw_rdata_T_273 | _io_rw_rdata_T_118; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_275 = _io_rw_rdata_T_274 | _io_rw_rdata_T_119; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_276 = _io_rw_rdata_T_275 | _io_rw_rdata_T_120; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_277 = _io_rw_rdata_T_276 | _io_rw_rdata_T_121; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_278 = _io_rw_rdata_T_277 | _io_rw_rdata_T_122; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_279 = _io_rw_rdata_T_278 | _io_rw_rdata_T_123; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_280 = _io_rw_rdata_T_279 | _io_rw_rdata_T_124; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_281 = _io_rw_rdata_T_280 | _io_rw_rdata_T_125; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_282 = _io_rw_rdata_T_281 | _io_rw_rdata_T_126; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_283 = _io_rw_rdata_T_282 | _io_rw_rdata_T_127; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_284 = _io_rw_rdata_T_283 | _io_rw_rdata_T_128; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_285 = _io_rw_rdata_T_284 | _io_rw_rdata_T_129; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_286 = {_io_rw_rdata_T_285[63:32], _io_rw_rdata_T_285[31:0] | _io_rw_rdata_T_130}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_287 = _io_rw_rdata_T_286 | _io_rw_rdata_T_131; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_288 = _io_rw_rdata_T_287 | _io_rw_rdata_T_132; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_289 = _io_rw_rdata_T_288 | _io_rw_rdata_T_133; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_290 = _io_rw_rdata_T_289 | _io_rw_rdata_T_134; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_291 = _io_rw_rdata_T_290; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_292 = {_io_rw_rdata_T_291[63:30], _io_rw_rdata_T_291[29:0] | _io_rw_rdata_T_136}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_293 = {_io_rw_rdata_T_292[63:30], _io_rw_rdata_T_292[29:0] | _io_rw_rdata_T_137}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_294 = {_io_rw_rdata_T_293[63:30], _io_rw_rdata_T_293[29:0] | _io_rw_rdata_T_138}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_295 = {_io_rw_rdata_T_294[63:30], _io_rw_rdata_T_294[29:0] | _io_rw_rdata_T_139}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_296 = {_io_rw_rdata_T_295[63:30], _io_rw_rdata_T_295[29:0] | _io_rw_rdata_T_140}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_297 = {_io_rw_rdata_T_296[63:30], _io_rw_rdata_T_296[29:0] | _io_rw_rdata_T_141}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_298 = {_io_rw_rdata_T_297[63:30], _io_rw_rdata_T_297[29:0] | _io_rw_rdata_T_142}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_299 = {_io_rw_rdata_T_298[63:30], _io_rw_rdata_T_298[29:0] | _io_rw_rdata_T_143}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_300 = _io_rw_rdata_T_299; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_301 = _io_rw_rdata_T_300; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_302 = _io_rw_rdata_T_301; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_303 = _io_rw_rdata_T_302; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_304 = _io_rw_rdata_T_303; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_305 = _io_rw_rdata_T_304; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_306 = _io_rw_rdata_T_305; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_307 = _io_rw_rdata_T_306; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_308 = _io_rw_rdata_T_307 | _io_rw_rdata_T_152; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_309 = _io_rw_rdata_T_308 | _io_rw_rdata_T_153; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_310 = _io_rw_rdata_T_309 | _io_rw_rdata_T_154; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_311 = _io_rw_rdata_T_310 | _io_rw_rdata_T_155; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_312 = _io_rw_rdata_T_311; // @[Mux.scala:30:73] assign _io_rw_rdata_WIRE = _io_rw_rdata_T_312; // @[Mux.scala:30:73] assign io_rw_rdata_0 = _io_rw_rdata_WIRE; // @[Mux.scala:30:73] wire set_vs_dirty; // @[CSR.scala:1191:33] wire set_fs_dirty; // @[CSR.scala:1200:33] wire [4:0] _reg_fflags_T = reg_fflags | io_fcsr_flags_bits_0; // @[CSR.scala:377:7, :577:23, :1211:30] wire _csr_wen_T = io_rw_cmd_0 == 3'h6; // @[package.scala:16:47] wire _csr_wen_T_1 = &io_rw_cmd_0; // @[package.scala:16:47] wire _csr_wen_T_2 = io_rw_cmd_0 == 3'h5; // @[package.scala:16:47] wire _csr_wen_T_3 = _csr_wen_T | _csr_wen_T_1; // @[package.scala:16:47, :81:59] wire _csr_wen_T_4 = _csr_wen_T_3 | _csr_wen_T_2; // @[package.scala:16:47, :81:59] wire csr_wen = _csr_wen_T_4; // @[package.scala:81:59] wire _io_csrw_counter_T = csr_wen; // @[CSR.scala:1222:56, :1223:57] wire _io_csrw_counter_T_1 = io_rw_addr_0 > 12'hAFF; // @[package.scala:213:47] wire _io_csrw_counter_T_2 = io_rw_addr_0 < 12'hB20; // @[package.scala:213:60] wire _io_csrw_counter_T_3 = _io_csrw_counter_T_1 & _io_csrw_counter_T_2; // @[package.scala:213:{47,55,60}] wire _io_csrw_counter_T_4 = io_rw_addr_0 > 12'hB7F; // @[package.scala:213:47] wire _io_csrw_counter_T_5 = io_rw_addr_0 < 12'hBA0; // @[package.scala:213:60] wire _io_csrw_counter_T_6 = _io_csrw_counter_T_4 & _io_csrw_counter_T_5; // @[package.scala:213:{47,55,60}] wire _io_csrw_counter_T_7 = _io_csrw_counter_T_3 | _io_csrw_counter_T_6; // @[package.scala:213:55] wire _io_csrw_counter_T_8 = _io_csrw_counter_T & _io_csrw_counter_T_7; // @[CSR.scala:1223:{57,68,134}] wire [4:0] _io_csrw_counter_T_9 = io_rw_addr_0[4:0]; // @[CSR.scala:377:7, :1223:222] wire [31:0] _io_csrw_counter_T_10 = 32'h1 << _io_csrw_counter_T_9; // @[OneHot.scala:58:35] assign _io_csrw_counter_T_11 = _io_csrw_counter_T_8 ? _io_csrw_counter_T_10 : 32'h0; // @[OneHot.scala:58:35] assign io_csrw_counter = _io_csrw_counter_T_11; // @[CSR.scala:377:7, :1223:25] wire _new_mstatus_T_36; // @[CSR.scala:1229:39] wire _new_mstatus_T_35; // @[CSR.scala:1229:39] wire _new_mstatus_T_34; // @[CSR.scala:1229:39] wire [31:0] _new_mstatus_T_33; // @[CSR.scala:1229:39] wire [1:0] _new_mstatus_T_32; // @[CSR.scala:1229:39] wire _new_mstatus_T_31; // @[CSR.scala:1229:39] wire [1:0] _new_mstatus_T_30; // @[CSR.scala:1229:39] wire _new_mstatus_T_29; // @[CSR.scala:1229:39] wire _new_mstatus_T_28; // @[CSR.scala:1229:39] wire [22:0] _new_mstatus_T_27; // @[CSR.scala:1229:39] wire _new_mstatus_T_26; // @[CSR.scala:1229:39] wire _new_mstatus_T_25; // @[CSR.scala:1229:39] wire _new_mstatus_T_24; // @[CSR.scala:1229:39] wire _new_mstatus_T_23; // @[CSR.scala:1229:39] wire [1:0] _new_mstatus_T_22; // @[CSR.scala:1229:39] wire [1:0] _new_mstatus_T_21; // @[CSR.scala:1229:39] wire _new_mstatus_T_20; // @[CSR.scala:1229:39] wire [7:0] _new_mstatus_T_19; // @[CSR.scala:1229:39] wire _new_mstatus_T_18; // @[CSR.scala:1229:39] wire _new_mstatus_T_17; // @[CSR.scala:1229:39] wire _new_mstatus_T_16; // @[CSR.scala:1229:39] wire _new_mstatus_T_15; // @[CSR.scala:1229:39] wire _new_mstatus_T_14; // @[CSR.scala:1229:39] wire _new_mstatus_T_13; // @[CSR.scala:1229:39] wire [1:0] _new_mstatus_T_12; // @[CSR.scala:1229:39] wire [1:0] _new_mstatus_T_11; // @[CSR.scala:1229:39] wire [1:0] _new_mstatus_T_10; // @[CSR.scala:1229:39] wire [1:0] _new_mstatus_T_9; // @[CSR.scala:1229:39] wire _new_mstatus_T_8; // @[CSR.scala:1229:39] wire _new_mstatus_T_7; // @[CSR.scala:1229:39] wire _new_mstatus_T_6; // @[CSR.scala:1229:39] wire _new_mstatus_T_5; // @[CSR.scala:1229:39] wire _new_mstatus_T_4; // @[CSR.scala:1229:39] wire _new_mstatus_T_3; // @[CSR.scala:1229:39] wire _new_mstatus_T_2; // @[CSR.scala:1229:39] wire _new_mstatus_T_1; // @[CSR.scala:1229:39] wire _new_mstatus_T; // @[CSR.scala:1229:39] wire new_mstatus_debug; // @[CSR.scala:1229:39] wire new_mstatus_cease; // @[CSR.scala:1229:39] wire new_mstatus_wfi; // @[CSR.scala:1229:39] wire [31:0] new_mstatus_isa; // @[CSR.scala:1229:39] wire [1:0] new_mstatus_dprv; // @[CSR.scala:1229:39] wire new_mstatus_dv; // @[CSR.scala:1229:39] wire [1:0] new_mstatus_prv; // @[CSR.scala:1229:39] wire new_mstatus_v; // @[CSR.scala:1229:39] wire new_mstatus_sd; // @[CSR.scala:1229:39] wire [22:0] new_mstatus_zero2; // @[CSR.scala:1229:39] wire new_mstatus_mpv; // @[CSR.scala:1229:39] wire new_mstatus_gva; // @[CSR.scala:1229:39] wire new_mstatus_mbe; // @[CSR.scala:1229:39] wire new_mstatus_sbe; // @[CSR.scala:1229:39] wire [1:0] new_mstatus_sxl; // @[CSR.scala:1229:39] wire [1:0] new_mstatus_uxl; // @[CSR.scala:1229:39] wire new_mstatus_sd_rv32; // @[CSR.scala:1229:39] wire [7:0] new_mstatus_zero1; // @[CSR.scala:1229:39] wire new_mstatus_tsr; // @[CSR.scala:1229:39] wire new_mstatus_tw; // @[CSR.scala:1229:39] wire new_mstatus_tvm; // @[CSR.scala:1229:39] wire new_mstatus_mxr; // @[CSR.scala:1229:39] wire new_mstatus_sum; // @[CSR.scala:1229:39] wire new_mstatus_mprv; // @[CSR.scala:1229:39] wire [1:0] new_mstatus_xs; // @[CSR.scala:1229:39] wire [1:0] new_mstatus_fs; // @[CSR.scala:1229:39] wire [1:0] new_mstatus_mpp; // @[CSR.scala:1229:39] wire [1:0] new_mstatus_vs; // @[CSR.scala:1229:39] wire new_mstatus_spp; // @[CSR.scala:1229:39] wire new_mstatus_mpie; // @[CSR.scala:1229:39] wire new_mstatus_ube; // @[CSR.scala:1229:39] wire new_mstatus_spie; // @[CSR.scala:1229:39] wire new_mstatus_upie; // @[CSR.scala:1229:39] wire new_mstatus_mie; // @[CSR.scala:1229:39] wire new_mstatus_hie; // @[CSR.scala:1229:39] wire new_mstatus_sie; // @[CSR.scala:1229:39] wire new_mstatus_uie; // @[CSR.scala:1229:39] wire [104:0] _GEN_21 = {41'h0, wdata}; // @[CSR.scala:1229:39, :1643:39] wire [104:0] _new_mstatus_WIRE; // @[CSR.scala:1229:39] assign _new_mstatus_WIRE = _GEN_21; // @[CSR.scala:1229:39] wire [104:0] _new_sstatus_WIRE; // @[CSR.scala:1338:41] assign _new_sstatus_WIRE = _GEN_21; // @[CSR.scala:1229:39, :1338:41] assign _new_mstatus_T = _new_mstatus_WIRE[0]; // @[CSR.scala:1229:39] assign new_mstatus_uie = _new_mstatus_T; // @[CSR.scala:1229:39] assign _new_mstatus_T_1 = _new_mstatus_WIRE[1]; // @[CSR.scala:1229:39] assign new_mstatus_sie = _new_mstatus_T_1; // @[CSR.scala:1229:39] assign _new_mstatus_T_2 = _new_mstatus_WIRE[2]; // @[CSR.scala:1229:39] assign new_mstatus_hie = _new_mstatus_T_2; // @[CSR.scala:1229:39] assign _new_mstatus_T_3 = _new_mstatus_WIRE[3]; // @[CSR.scala:1229:39] assign new_mstatus_mie = _new_mstatus_T_3; // @[CSR.scala:1229:39] assign _new_mstatus_T_4 = _new_mstatus_WIRE[4]; // @[CSR.scala:1229:39] assign new_mstatus_upie = _new_mstatus_T_4; // @[CSR.scala:1229:39] assign _new_mstatus_T_5 = _new_mstatus_WIRE[5]; // @[CSR.scala:1229:39] assign new_mstatus_spie = _new_mstatus_T_5; // @[CSR.scala:1229:39] assign _new_mstatus_T_6 = _new_mstatus_WIRE[6]; // @[CSR.scala:1229:39] assign new_mstatus_ube = _new_mstatus_T_6; // @[CSR.scala:1229:39] assign _new_mstatus_T_7 = _new_mstatus_WIRE[7]; // @[CSR.scala:1229:39] assign new_mstatus_mpie = _new_mstatus_T_7; // @[CSR.scala:1229:39] assign _new_mstatus_T_8 = _new_mstatus_WIRE[8]; // @[CSR.scala:1229:39] assign new_mstatus_spp = _new_mstatus_T_8; // @[CSR.scala:1229:39] assign _new_mstatus_T_9 = _new_mstatus_WIRE[10:9]; // @[CSR.scala:1229:39] assign new_mstatus_vs = _new_mstatus_T_9; // @[CSR.scala:1229:39] assign _new_mstatus_T_10 = _new_mstatus_WIRE[12:11]; // @[CSR.scala:1229:39] assign new_mstatus_mpp = _new_mstatus_T_10; // @[CSR.scala:1229:39] assign _new_mstatus_T_11 = _new_mstatus_WIRE[14:13]; // @[CSR.scala:1229:39] assign new_mstatus_fs = _new_mstatus_T_11; // @[CSR.scala:1229:39] assign _new_mstatus_T_12 = _new_mstatus_WIRE[16:15]; // @[CSR.scala:1229:39] assign new_mstatus_xs = _new_mstatus_T_12; // @[CSR.scala:1229:39] assign _new_mstatus_T_13 = _new_mstatus_WIRE[17]; // @[CSR.scala:1229:39] assign new_mstatus_mprv = _new_mstatus_T_13; // @[CSR.scala:1229:39] assign _new_mstatus_T_14 = _new_mstatus_WIRE[18]; // @[CSR.scala:1229:39] assign new_mstatus_sum = _new_mstatus_T_14; // @[CSR.scala:1229:39] assign _new_mstatus_T_15 = _new_mstatus_WIRE[19]; // @[CSR.scala:1229:39] assign new_mstatus_mxr = _new_mstatus_T_15; // @[CSR.scala:1229:39] assign _new_mstatus_T_16 = _new_mstatus_WIRE[20]; // @[CSR.scala:1229:39] assign new_mstatus_tvm = _new_mstatus_T_16; // @[CSR.scala:1229:39] assign _new_mstatus_T_17 = _new_mstatus_WIRE[21]; // @[CSR.scala:1229:39] assign new_mstatus_tw = _new_mstatus_T_17; // @[CSR.scala:1229:39] assign _new_mstatus_T_18 = _new_mstatus_WIRE[22]; // @[CSR.scala:1229:39] assign new_mstatus_tsr = _new_mstatus_T_18; // @[CSR.scala:1229:39] assign _new_mstatus_T_19 = _new_mstatus_WIRE[30:23]; // @[CSR.scala:1229:39] assign new_mstatus_zero1 = _new_mstatus_T_19; // @[CSR.scala:1229:39] assign _new_mstatus_T_20 = _new_mstatus_WIRE[31]; // @[CSR.scala:1229:39] assign new_mstatus_sd_rv32 = _new_mstatus_T_20; // @[CSR.scala:1229:39] assign _new_mstatus_T_21 = _new_mstatus_WIRE[33:32]; // @[CSR.scala:1229:39] assign new_mstatus_uxl = _new_mstatus_T_21; // @[CSR.scala:1229:39] assign _new_mstatus_T_22 = _new_mstatus_WIRE[35:34]; // @[CSR.scala:1229:39] assign new_mstatus_sxl = _new_mstatus_T_22; // @[CSR.scala:1229:39] assign _new_mstatus_T_23 = _new_mstatus_WIRE[36]; // @[CSR.scala:1229:39] assign new_mstatus_sbe = _new_mstatus_T_23; // @[CSR.scala:1229:39] assign _new_mstatus_T_24 = _new_mstatus_WIRE[37]; // @[CSR.scala:1229:39] assign new_mstatus_mbe = _new_mstatus_T_24; // @[CSR.scala:1229:39] assign _new_mstatus_T_25 = _new_mstatus_WIRE[38]; // @[CSR.scala:1229:39] assign new_mstatus_gva = _new_mstatus_T_25; // @[CSR.scala:1229:39] assign _new_mstatus_T_26 = _new_mstatus_WIRE[39]; // @[CSR.scala:1229:39] assign new_mstatus_mpv = _new_mstatus_T_26; // @[CSR.scala:1229:39] assign _new_mstatus_T_27 = _new_mstatus_WIRE[62:40]; // @[CSR.scala:1229:39] assign new_mstatus_zero2 = _new_mstatus_T_27; // @[CSR.scala:1229:39] assign _new_mstatus_T_28 = _new_mstatus_WIRE[63]; // @[CSR.scala:1229:39] assign new_mstatus_sd = _new_mstatus_T_28; // @[CSR.scala:1229:39] assign _new_mstatus_T_29 = _new_mstatus_WIRE[64]; // @[CSR.scala:1229:39] assign new_mstatus_v = _new_mstatus_T_29; // @[CSR.scala:1229:39] assign _new_mstatus_T_30 = _new_mstatus_WIRE[66:65]; // @[CSR.scala:1229:39] assign new_mstatus_prv = _new_mstatus_T_30; // @[CSR.scala:1229:39] assign _new_mstatus_T_31 = _new_mstatus_WIRE[67]; // @[CSR.scala:1229:39] assign new_mstatus_dv = _new_mstatus_T_31; // @[CSR.scala:1229:39] assign _new_mstatus_T_32 = _new_mstatus_WIRE[69:68]; // @[CSR.scala:1229:39] assign new_mstatus_dprv = _new_mstatus_T_32; // @[CSR.scala:1229:39] assign _new_mstatus_T_33 = _new_mstatus_WIRE[101:70]; // @[CSR.scala:1229:39] assign new_mstatus_isa = _new_mstatus_T_33; // @[CSR.scala:1229:39] assign _new_mstatus_T_34 = _new_mstatus_WIRE[102]; // @[CSR.scala:1229:39] assign new_mstatus_wfi = _new_mstatus_T_34; // @[CSR.scala:1229:39] assign _new_mstatus_T_35 = _new_mstatus_WIRE[103]; // @[CSR.scala:1229:39] assign new_mstatus_cease = _new_mstatus_T_35; // @[CSR.scala:1229:39] assign _new_mstatus_T_36 = _new_mstatus_WIRE[104]; // @[CSR.scala:1229:39] assign new_mstatus_debug = _new_mstatus_T_36; // @[CSR.scala:1229:39] wire _reg_mstatus_mpp_T_2 = new_mstatus_mpp == 2'h2; // @[CSR.scala:1229:39, :1647:35] wire [1:0] _reg_mstatus_mpp_T_3 = _reg_mstatus_mpp_T_2 ? 2'h0 : new_mstatus_mpp; // @[CSR.scala:1229:39, :1647:{29,35}] wire _reg_mstatus_fs_T = |new_mstatus_fs; // @[CSR.scala:1229:39, :1668:73] wire [1:0] _reg_mstatus_fs_T_1 = {2{_reg_mstatus_fs_T}}; // @[CSR.scala:1668:{66,73}] wire f = wdata[5]; // @[CSR.scala:1259:20, :1643:39] wire [63:0] _reg_misa_T = ~wdata; // @[CSR.scala:1263:25, :1643:39] wire _reg_misa_T_1 = ~f; // @[CSR.scala:1259:20, :1263:35] wire [3:0] _reg_misa_T_2 = {_reg_misa_T_1, 3'h0}; // @[CSR.scala:1263:{35,38}] wire [63:0] _reg_misa_T_3 = {_reg_misa_T[63:4], _reg_misa_T[3:0] | _reg_misa_T_2}; // @[CSR.scala:1263:{25,32,38}] wire [63:0] _reg_misa_T_4 = ~_reg_misa_T_3; // @[CSR.scala:1263:{23,32}] wire [63:0] _reg_misa_T_5 = _reg_misa_T_4 & 64'h20102D; // @[CSR.scala:1263:{23,55}] wire [63:0] _reg_misa_T_7 = reg_misa & 64'hFFFFFFFFFFDFEFD2; // @[CSR.scala:648:25, :1263:73] wire [63:0] _reg_misa_T_8 = _reg_misa_T_5 | _reg_misa_T_7; // @[CSR.scala:1263:{55,62,73}] wire [3:0] new_mip_lo_lo = {new_mip_lo_lo_hi, new_mip_lo_lo_lo}; // @[CSR.scala:1271:59] wire [3:0] new_mip_lo_hi = {new_mip_lo_hi_hi, new_mip_lo_hi_lo}; // @[CSR.scala:1271:59] wire [7:0] new_mip_lo = {new_mip_lo_hi, new_mip_lo_lo}; // @[CSR.scala:1271:59] wire [3:0] new_mip_hi_lo = {new_mip_hi_lo_hi, new_mip_hi_lo_lo}; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_hi_hi = {new_mip_hi_hi_hi_hi, 1'h0}; // @[CSR.scala:1271:59] wire [3:0] new_mip_hi_hi = {new_mip_hi_hi_hi, new_mip_hi_hi_lo}; // @[CSR.scala:1271:59] wire [7:0] new_mip_hi = {new_mip_hi_hi, new_mip_hi_lo}; // @[CSR.scala:1271:59] wire [15:0] _new_mip_T = {new_mip_hi, new_mip_lo}; // @[CSR.scala:1271:59] wire [15:0] _new_mip_T_2 = _new_mip_T_1 ? _new_mip_T : 16'h0; // @[CSR.scala:1271:59, :1643:{9,13}] wire [63:0] _new_mip_T_3 = {48'h0, _new_mip_T_2} | io_rw_wdata_0; // @[CSR.scala:377:7, :1643:{9,30}] wire _new_mip_T_5 = &_new_mip_T_4; // @[CSR.scala:1643:{49,55}] wire [63:0] _new_mip_T_6 = _new_mip_T_5 ? io_rw_wdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{45,55}] wire [63:0] _new_mip_T_7 = ~_new_mip_T_6; // @[CSR.scala:1643:{41,45}] wire [63:0] _new_mip_T_8 = _new_mip_T_3 & _new_mip_T_7; // @[CSR.scala:1643:{30,39,41}] wire _new_mip_T_24; // @[CSR.scala:1271:88] wire _new_mip_T_23; // @[CSR.scala:1271:88] wire _new_mip_T_22; // @[CSR.scala:1271:88] wire _new_mip_T_21; // @[CSR.scala:1271:88] wire _new_mip_T_20; // @[CSR.scala:1271:88] wire _new_mip_T_19; // @[CSR.scala:1271:88] wire _new_mip_T_18; // @[CSR.scala:1271:88] wire _new_mip_T_17; // @[CSR.scala:1271:88] wire _new_mip_T_16; // @[CSR.scala:1271:88] wire _new_mip_T_15; // @[CSR.scala:1271:88] wire _new_mip_T_14; // @[CSR.scala:1271:88] wire _new_mip_T_13; // @[CSR.scala:1271:88] wire _new_mip_T_12; // @[CSR.scala:1271:88] wire _new_mip_T_11; // @[CSR.scala:1271:88] wire _new_mip_T_10; // @[CSR.scala:1271:88] wire _new_mip_T_9; // @[CSR.scala:1271:88] wire new_mip_zero1; // @[CSR.scala:1271:88] wire new_mip_debug; // @[CSR.scala:1271:88] wire new_mip_rocc; // @[CSR.scala:1271:88] wire new_mip_sgeip; // @[CSR.scala:1271:88] wire new_mip_meip; // @[CSR.scala:1271:88] wire new_mip_vseip; // @[CSR.scala:1271:88] wire new_mip_seip; // @[CSR.scala:1271:88] wire new_mip_ueip; // @[CSR.scala:1271:88] wire new_mip_mtip; // @[CSR.scala:1271:88] wire new_mip_vstip; // @[CSR.scala:1271:88] wire new_mip_stip; // @[CSR.scala:1271:88] wire new_mip_utip; // @[CSR.scala:1271:88] wire new_mip_msip; // @[CSR.scala:1271:88] wire new_mip_vssip; // @[CSR.scala:1271:88] wire new_mip_ssip; // @[CSR.scala:1271:88] wire new_mip_usip; // @[CSR.scala:1271:88] wire [15:0] _new_mip_WIRE = _new_mip_T_8[15:0]; // @[CSR.scala:1271:88, :1643:39] assign _new_mip_T_9 = _new_mip_WIRE[0]; // @[CSR.scala:1271:88] assign new_mip_usip = _new_mip_T_9; // @[CSR.scala:1271:88] assign _new_mip_T_10 = _new_mip_WIRE[1]; // @[CSR.scala:1271:88] assign new_mip_ssip = _new_mip_T_10; // @[CSR.scala:1271:88] assign _new_mip_T_11 = _new_mip_WIRE[2]; // @[CSR.scala:1271:88] assign new_mip_vssip = _new_mip_T_11; // @[CSR.scala:1271:88] assign _new_mip_T_12 = _new_mip_WIRE[3]; // @[CSR.scala:1271:88] assign new_mip_msip = _new_mip_T_12; // @[CSR.scala:1271:88] assign _new_mip_T_13 = _new_mip_WIRE[4]; // @[CSR.scala:1271:88] assign new_mip_utip = _new_mip_T_13; // @[CSR.scala:1271:88] assign _new_mip_T_14 = _new_mip_WIRE[5]; // @[CSR.scala:1271:88] assign new_mip_stip = _new_mip_T_14; // @[CSR.scala:1271:88] assign _new_mip_T_15 = _new_mip_WIRE[6]; // @[CSR.scala:1271:88] assign new_mip_vstip = _new_mip_T_15; // @[CSR.scala:1271:88] assign _new_mip_T_16 = _new_mip_WIRE[7]; // @[CSR.scala:1271:88] assign new_mip_mtip = _new_mip_T_16; // @[CSR.scala:1271:88] assign _new_mip_T_17 = _new_mip_WIRE[8]; // @[CSR.scala:1271:88] assign new_mip_ueip = _new_mip_T_17; // @[CSR.scala:1271:88] assign _new_mip_T_18 = _new_mip_WIRE[9]; // @[CSR.scala:1271:88] assign new_mip_seip = _new_mip_T_18; // @[CSR.scala:1271:88] assign _new_mip_T_19 = _new_mip_WIRE[10]; // @[CSR.scala:1271:88] assign new_mip_vseip = _new_mip_T_19; // @[CSR.scala:1271:88] assign _new_mip_T_20 = _new_mip_WIRE[11]; // @[CSR.scala:1271:88] assign new_mip_meip = _new_mip_T_20; // @[CSR.scala:1271:88] assign _new_mip_T_21 = _new_mip_WIRE[12]; // @[CSR.scala:1271:88] assign new_mip_sgeip = _new_mip_T_21; // @[CSR.scala:1271:88] assign _new_mip_T_22 = _new_mip_WIRE[13]; // @[CSR.scala:1271:88] assign new_mip_rocc = _new_mip_T_22; // @[CSR.scala:1271:88] assign _new_mip_T_23 = _new_mip_WIRE[14]; // @[CSR.scala:1271:88] assign new_mip_debug = _new_mip_T_23; // @[CSR.scala:1271:88] assign _new_mip_T_24 = _new_mip_WIRE[15]; // @[CSR.scala:1271:88] assign new_mip_zero1 = _new_mip_T_24; // @[CSR.scala:1271:88] wire [63:0] _reg_mie_T = {52'h0, wdata[11:1] & 11'h555, 1'h0}; // @[CSR.scala:1281:59, :1643:39] wire [63:0] _reg_mepc_T = ~wdata; // @[CSR.scala:1263:25, :1643:39, :1664:28] wire [63:0] _reg_mepc_T_1 = {_reg_mepc_T[63:1], 1'h1}; // @[CSR.scala:1664:{28,31}] wire [63:0] _reg_mepc_T_2 = ~_reg_mepc_T_1; // @[CSR.scala:1664:{26,31}] wire [31:0] _new_dcsr_WIRE = wdata[31:0]; // @[CSR.scala:1285:52, :1322:38, :1643:39] wire [63:0] _reg_mcause_T = wdata & 64'h800000000000000F; // @[CSR.scala:1286:62, :1643:39] wire [63:0] _reg_mcountinhibit_T_1 = wdata & 64'hFFFFFFFFFFFFFFFD; // @[CSR.scala:1306:76, :1643:39] wire [57:0] _large_T_6 = wdata[63:6]; // @[Counters.scala:68:28] wire [57:0] _large_T_7 = wdata[63:6]; // @[Counters.scala:68:28] assign set_fs_dirty = csr_wen & (decoded_addr_103_2 | decoded_addr_71_2 | decoded_addr_37_2) | io_fcsr_flags_valid_0; // @[CSR.scala:377:7, :855:93, :1200:33, :1210:30, :1222:56, :1224:18, :1312:{40,55}, :1313:{40,55}, :1314:38, :1315:22] wire [58:0] _reg_frm_T = wdata[63:5]; // @[CSR.scala:1317:26, :1643:39] wire [1:0] _new_dcsr_T_14; // @[CSR.scala:1322:38] wire [1:0] _new_dcsr_T_13; // @[CSR.scala:1322:38] wire [11:0] _new_dcsr_T_12; // @[CSR.scala:1322:38] wire _new_dcsr_T_11; // @[CSR.scala:1322:38] wire _new_dcsr_T_10; // @[CSR.scala:1322:38] wire _new_dcsr_T_9; // @[CSR.scala:1322:38] wire _new_dcsr_T_8; // @[CSR.scala:1322:38] wire _new_dcsr_T_7; // @[CSR.scala:1322:38] wire _new_dcsr_T_6; // @[CSR.scala:1322:38] wire _new_dcsr_T_5; // @[CSR.scala:1322:38] wire [2:0] _new_dcsr_T_4; // @[CSR.scala:1322:38] wire _new_dcsr_T_3; // @[CSR.scala:1322:38] wire [1:0] _new_dcsr_T_2; // @[CSR.scala:1322:38] wire _new_dcsr_T_1; // @[CSR.scala:1322:38] wire [1:0] _new_dcsr_T; // @[CSR.scala:1322:38] wire [1:0] new_dcsr_xdebugver; // @[CSR.scala:1322:38] wire [1:0] new_dcsr_zero4; // @[CSR.scala:1322:38] wire [11:0] new_dcsr_zero3; // @[CSR.scala:1322:38] wire new_dcsr_ebreakm; // @[CSR.scala:1322:38] wire new_dcsr_ebreakh; // @[CSR.scala:1322:38] wire new_dcsr_ebreaks; // @[CSR.scala:1322:38] wire new_dcsr_ebreaku; // @[CSR.scala:1322:38] wire new_dcsr_zero2; // @[CSR.scala:1322:38] wire new_dcsr_stopcycle; // @[CSR.scala:1322:38] wire new_dcsr_stoptime; // @[CSR.scala:1322:38] wire [2:0] new_dcsr_cause; // @[CSR.scala:1322:38] wire new_dcsr_v; // @[CSR.scala:1322:38] wire [1:0] new_dcsr_zero1; // @[CSR.scala:1322:38] wire new_dcsr_step; // @[CSR.scala:1322:38] wire [1:0] new_dcsr_prv; // @[CSR.scala:1322:38] assign _new_dcsr_T = _new_dcsr_WIRE[1:0]; // @[CSR.scala:1322:38] assign new_dcsr_prv = _new_dcsr_T; // @[CSR.scala:1322:38] assign _new_dcsr_T_1 = _new_dcsr_WIRE[2]; // @[CSR.scala:1322:38] assign new_dcsr_step = _new_dcsr_T_1; // @[CSR.scala:1322:38] assign _new_dcsr_T_2 = _new_dcsr_WIRE[4:3]; // @[CSR.scala:1322:38] assign new_dcsr_zero1 = _new_dcsr_T_2; // @[CSR.scala:1322:38] assign _new_dcsr_T_3 = _new_dcsr_WIRE[5]; // @[CSR.scala:1322:38] assign new_dcsr_v = _new_dcsr_T_3; // @[CSR.scala:1322:38] assign _new_dcsr_T_4 = _new_dcsr_WIRE[8:6]; // @[CSR.scala:1322:38] assign new_dcsr_cause = _new_dcsr_T_4; // @[CSR.scala:1322:38] assign _new_dcsr_T_5 = _new_dcsr_WIRE[9]; // @[CSR.scala:1322:38] assign new_dcsr_stoptime = _new_dcsr_T_5; // @[CSR.scala:1322:38] assign _new_dcsr_T_6 = _new_dcsr_WIRE[10]; // @[CSR.scala:1322:38] assign new_dcsr_stopcycle = _new_dcsr_T_6; // @[CSR.scala:1322:38] assign _new_dcsr_T_7 = _new_dcsr_WIRE[11]; // @[CSR.scala:1322:38] assign new_dcsr_zero2 = _new_dcsr_T_7; // @[CSR.scala:1322:38] assign _new_dcsr_T_8 = _new_dcsr_WIRE[12]; // @[CSR.scala:1322:38] assign new_dcsr_ebreaku = _new_dcsr_T_8; // @[CSR.scala:1322:38] assign _new_dcsr_T_9 = _new_dcsr_WIRE[13]; // @[CSR.scala:1322:38] assign new_dcsr_ebreaks = _new_dcsr_T_9; // @[CSR.scala:1322:38] assign _new_dcsr_T_10 = _new_dcsr_WIRE[14]; // @[CSR.scala:1322:38] assign new_dcsr_ebreakh = _new_dcsr_T_10; // @[CSR.scala:1322:38] assign _new_dcsr_T_11 = _new_dcsr_WIRE[15]; // @[CSR.scala:1322:38] assign new_dcsr_ebreakm = _new_dcsr_T_11; // @[CSR.scala:1322:38] assign _new_dcsr_T_12 = _new_dcsr_WIRE[27:16]; // @[CSR.scala:1322:38] assign new_dcsr_zero3 = _new_dcsr_T_12; // @[CSR.scala:1322:38] assign _new_dcsr_T_13 = _new_dcsr_WIRE[29:28]; // @[CSR.scala:1322:38] assign new_dcsr_zero4 = _new_dcsr_T_13; // @[CSR.scala:1322:38] assign _new_dcsr_T_14 = _new_dcsr_WIRE[31:30]; // @[CSR.scala:1322:38] assign new_dcsr_xdebugver = _new_dcsr_T_14; // @[CSR.scala:1322:38] wire _reg_dcsr_prv_T = new_dcsr_prv == 2'h2; // @[CSR.scala:1322:38, :1647:35] wire [1:0] _reg_dcsr_prv_T_1 = _reg_dcsr_prv_T ? 2'h0 : new_dcsr_prv; // @[CSR.scala:1322:38, :1647:{29,35}] wire [63:0] _reg_dpc_T = ~wdata; // @[CSR.scala:1263:25, :1643:39, :1664:28] wire [63:0] _reg_dpc_T_1 = {_reg_dpc_T[63:1], 1'h1}; // @[CSR.scala:1664:{28,31}] wire [63:0] _reg_dpc_T_2 = ~_reg_dpc_T_1; // @[CSR.scala:1664:{26,31}] wire _new_sstatus_T_36; // @[CSR.scala:1338:41] wire _new_sstatus_T_35; // @[CSR.scala:1338:41] wire _new_sstatus_T_34; // @[CSR.scala:1338:41] wire [31:0] _new_sstatus_T_33; // @[CSR.scala:1338:41] wire [1:0] _new_sstatus_T_32; // @[CSR.scala:1338:41] wire _new_sstatus_T_31; // @[CSR.scala:1338:41] wire [1:0] _new_sstatus_T_30; // @[CSR.scala:1338:41] wire _new_sstatus_T_29; // @[CSR.scala:1338:41] wire _new_sstatus_T_28; // @[CSR.scala:1338:41] wire [22:0] _new_sstatus_T_27; // @[CSR.scala:1338:41] wire _new_sstatus_T_26; // @[CSR.scala:1338:41] wire _new_sstatus_T_25; // @[CSR.scala:1338:41] wire _new_sstatus_T_24; // @[CSR.scala:1338:41] wire _new_sstatus_T_23; // @[CSR.scala:1338:41] wire [1:0] _new_sstatus_T_22; // @[CSR.scala:1338:41] wire [1:0] _new_sstatus_T_21; // @[CSR.scala:1338:41] wire _new_sstatus_T_20; // @[CSR.scala:1338:41] wire [7:0] _new_sstatus_T_19; // @[CSR.scala:1338:41] wire _new_sstatus_T_18; // @[CSR.scala:1338:41] wire _new_sstatus_T_17; // @[CSR.scala:1338:41] wire _new_sstatus_T_16; // @[CSR.scala:1338:41] wire _new_sstatus_T_15; // @[CSR.scala:1338:41] wire _new_sstatus_T_14; // @[CSR.scala:1338:41] wire _new_sstatus_T_13; // @[CSR.scala:1338:41] wire [1:0] _new_sstatus_T_12; // @[CSR.scala:1338:41] wire [1:0] _new_sstatus_T_11; // @[CSR.scala:1338:41] wire [1:0] _new_sstatus_T_10; // @[CSR.scala:1338:41] wire [1:0] _new_sstatus_T_9; // @[CSR.scala:1338:41] wire _new_sstatus_T_8; // @[CSR.scala:1338:41] wire _new_sstatus_T_7; // @[CSR.scala:1338:41] wire _new_sstatus_T_6; // @[CSR.scala:1338:41] wire _new_sstatus_T_5; // @[CSR.scala:1338:41] wire _new_sstatus_T_4; // @[CSR.scala:1338:41] wire _new_sstatus_T_3; // @[CSR.scala:1338:41] wire _new_sstatus_T_2; // @[CSR.scala:1338:41] wire _new_sstatus_T_1; // @[CSR.scala:1338:41] wire _new_sstatus_T; // @[CSR.scala:1338:41] wire new_sstatus_debug; // @[CSR.scala:1338:41] wire new_sstatus_cease; // @[CSR.scala:1338:41] wire new_sstatus_wfi; // @[CSR.scala:1338:41] wire [31:0] new_sstatus_isa; // @[CSR.scala:1338:41] wire [1:0] new_sstatus_dprv; // @[CSR.scala:1338:41] wire new_sstatus_dv; // @[CSR.scala:1338:41] wire [1:0] new_sstatus_prv; // @[CSR.scala:1338:41] wire new_sstatus_v; // @[CSR.scala:1338:41] wire new_sstatus_sd; // @[CSR.scala:1338:41] wire [22:0] new_sstatus_zero2; // @[CSR.scala:1338:41] wire new_sstatus_mpv; // @[CSR.scala:1338:41] wire new_sstatus_gva; // @[CSR.scala:1338:41] wire new_sstatus_mbe; // @[CSR.scala:1338:41] wire new_sstatus_sbe; // @[CSR.scala:1338:41] wire [1:0] new_sstatus_sxl; // @[CSR.scala:1338:41] wire [1:0] new_sstatus_uxl; // @[CSR.scala:1338:41] wire new_sstatus_sd_rv32; // @[CSR.scala:1338:41] wire [7:0] new_sstatus_zero1; // @[CSR.scala:1338:41] wire new_sstatus_tsr; // @[CSR.scala:1338:41] wire new_sstatus_tw; // @[CSR.scala:1338:41] wire new_sstatus_tvm; // @[CSR.scala:1338:41] wire new_sstatus_mxr; // @[CSR.scala:1338:41] wire new_sstatus_sum; // @[CSR.scala:1338:41] wire new_sstatus_mprv; // @[CSR.scala:1338:41] wire [1:0] new_sstatus_xs; // @[CSR.scala:1338:41] wire [1:0] new_sstatus_fs; // @[CSR.scala:1338:41] wire [1:0] new_sstatus_mpp; // @[CSR.scala:1338:41] wire [1:0] new_sstatus_vs; // @[CSR.scala:1338:41] wire new_sstatus_spp; // @[CSR.scala:1338:41] wire new_sstatus_mpie; // @[CSR.scala:1338:41] wire new_sstatus_ube; // @[CSR.scala:1338:41] wire new_sstatus_spie; // @[CSR.scala:1338:41] wire new_sstatus_upie; // @[CSR.scala:1338:41] wire new_sstatus_mie; // @[CSR.scala:1338:41] wire new_sstatus_hie; // @[CSR.scala:1338:41] wire new_sstatus_sie; // @[CSR.scala:1338:41] wire new_sstatus_uie; // @[CSR.scala:1338:41] assign _new_sstatus_T = _new_sstatus_WIRE[0]; // @[CSR.scala:1338:41] assign new_sstatus_uie = _new_sstatus_T; // @[CSR.scala:1338:41] assign _new_sstatus_T_1 = _new_sstatus_WIRE[1]; // @[CSR.scala:1338:41] assign new_sstatus_sie = _new_sstatus_T_1; // @[CSR.scala:1338:41] assign _new_sstatus_T_2 = _new_sstatus_WIRE[2]; // @[CSR.scala:1338:41] assign new_sstatus_hie = _new_sstatus_T_2; // @[CSR.scala:1338:41] assign _new_sstatus_T_3 = _new_sstatus_WIRE[3]; // @[CSR.scala:1338:41] assign new_sstatus_mie = _new_sstatus_T_3; // @[CSR.scala:1338:41] assign _new_sstatus_T_4 = _new_sstatus_WIRE[4]; // @[CSR.scala:1338:41] assign new_sstatus_upie = _new_sstatus_T_4; // @[CSR.scala:1338:41] assign _new_sstatus_T_5 = _new_sstatus_WIRE[5]; // @[CSR.scala:1338:41] assign new_sstatus_spie = _new_sstatus_T_5; // @[CSR.scala:1338:41] assign _new_sstatus_T_6 = _new_sstatus_WIRE[6]; // @[CSR.scala:1338:41] assign new_sstatus_ube = _new_sstatus_T_6; // @[CSR.scala:1338:41] assign _new_sstatus_T_7 = _new_sstatus_WIRE[7]; // @[CSR.scala:1338:41] assign new_sstatus_mpie = _new_sstatus_T_7; // @[CSR.scala:1338:41] assign _new_sstatus_T_8 = _new_sstatus_WIRE[8]; // @[CSR.scala:1338:41] assign new_sstatus_spp = _new_sstatus_T_8; // @[CSR.scala:1338:41] assign _new_sstatus_T_9 = _new_sstatus_WIRE[10:9]; // @[CSR.scala:1338:41] assign new_sstatus_vs = _new_sstatus_T_9; // @[CSR.scala:1338:41] assign _new_sstatus_T_10 = _new_sstatus_WIRE[12:11]; // @[CSR.scala:1338:41] assign new_sstatus_mpp = _new_sstatus_T_10; // @[CSR.scala:1338:41] assign _new_sstatus_T_11 = _new_sstatus_WIRE[14:13]; // @[CSR.scala:1338:41] assign new_sstatus_fs = _new_sstatus_T_11; // @[CSR.scala:1338:41] assign _new_sstatus_T_12 = _new_sstatus_WIRE[16:15]; // @[CSR.scala:1338:41] assign new_sstatus_xs = _new_sstatus_T_12; // @[CSR.scala:1338:41] assign _new_sstatus_T_13 = _new_sstatus_WIRE[17]; // @[CSR.scala:1338:41] assign new_sstatus_mprv = _new_sstatus_T_13; // @[CSR.scala:1338:41] assign _new_sstatus_T_14 = _new_sstatus_WIRE[18]; // @[CSR.scala:1338:41] assign new_sstatus_sum = _new_sstatus_T_14; // @[CSR.scala:1338:41] assign _new_sstatus_T_15 = _new_sstatus_WIRE[19]; // @[CSR.scala:1338:41] assign new_sstatus_mxr = _new_sstatus_T_15; // @[CSR.scala:1338:41] assign _new_sstatus_T_16 = _new_sstatus_WIRE[20]; // @[CSR.scala:1338:41] assign new_sstatus_tvm = _new_sstatus_T_16; // @[CSR.scala:1338:41] assign _new_sstatus_T_17 = _new_sstatus_WIRE[21]; // @[CSR.scala:1338:41] assign new_sstatus_tw = _new_sstatus_T_17; // @[CSR.scala:1338:41] assign _new_sstatus_T_18 = _new_sstatus_WIRE[22]; // @[CSR.scala:1338:41] assign new_sstatus_tsr = _new_sstatus_T_18; // @[CSR.scala:1338:41] assign _new_sstatus_T_19 = _new_sstatus_WIRE[30:23]; // @[CSR.scala:1338:41] assign new_sstatus_zero1 = _new_sstatus_T_19; // @[CSR.scala:1338:41] assign _new_sstatus_T_20 = _new_sstatus_WIRE[31]; // @[CSR.scala:1338:41] assign new_sstatus_sd_rv32 = _new_sstatus_T_20; // @[CSR.scala:1338:41] assign _new_sstatus_T_21 = _new_sstatus_WIRE[33:32]; // @[CSR.scala:1338:41] assign new_sstatus_uxl = _new_sstatus_T_21; // @[CSR.scala:1338:41] assign _new_sstatus_T_22 = _new_sstatus_WIRE[35:34]; // @[CSR.scala:1338:41] assign new_sstatus_sxl = _new_sstatus_T_22; // @[CSR.scala:1338:41] assign _new_sstatus_T_23 = _new_sstatus_WIRE[36]; // @[CSR.scala:1338:41] assign new_sstatus_sbe = _new_sstatus_T_23; // @[CSR.scala:1338:41] assign _new_sstatus_T_24 = _new_sstatus_WIRE[37]; // @[CSR.scala:1338:41] assign new_sstatus_mbe = _new_sstatus_T_24; // @[CSR.scala:1338:41] assign _new_sstatus_T_25 = _new_sstatus_WIRE[38]; // @[CSR.scala:1338:41] assign new_sstatus_gva = _new_sstatus_T_25; // @[CSR.scala:1338:41] assign _new_sstatus_T_26 = _new_sstatus_WIRE[39]; // @[CSR.scala:1338:41] assign new_sstatus_mpv = _new_sstatus_T_26; // @[CSR.scala:1338:41] assign _new_sstatus_T_27 = _new_sstatus_WIRE[62:40]; // @[CSR.scala:1338:41] assign new_sstatus_zero2 = _new_sstatus_T_27; // @[CSR.scala:1338:41] assign _new_sstatus_T_28 = _new_sstatus_WIRE[63]; // @[CSR.scala:1338:41] assign new_sstatus_sd = _new_sstatus_T_28; // @[CSR.scala:1338:41] assign _new_sstatus_T_29 = _new_sstatus_WIRE[64]; // @[CSR.scala:1338:41] assign new_sstatus_v = _new_sstatus_T_29; // @[CSR.scala:1338:41] assign _new_sstatus_T_30 = _new_sstatus_WIRE[66:65]; // @[CSR.scala:1338:41] assign new_sstatus_prv = _new_sstatus_T_30; // @[CSR.scala:1338:41] assign _new_sstatus_T_31 = _new_sstatus_WIRE[67]; // @[CSR.scala:1338:41] assign new_sstatus_dv = _new_sstatus_T_31; // @[CSR.scala:1338:41] assign _new_sstatus_T_32 = _new_sstatus_WIRE[69:68]; // @[CSR.scala:1338:41] assign new_sstatus_dprv = _new_sstatus_T_32; // @[CSR.scala:1338:41] assign _new_sstatus_T_33 = _new_sstatus_WIRE[101:70]; // @[CSR.scala:1338:41] assign new_sstatus_isa = _new_sstatus_T_33; // @[CSR.scala:1338:41] assign _new_sstatus_T_34 = _new_sstatus_WIRE[102]; // @[CSR.scala:1338:41] assign new_sstatus_wfi = _new_sstatus_T_34; // @[CSR.scala:1338:41] assign _new_sstatus_T_35 = _new_sstatus_WIRE[103]; // @[CSR.scala:1338:41] assign new_sstatus_cease = _new_sstatus_T_35; // @[CSR.scala:1338:41] assign _new_sstatus_T_36 = _new_sstatus_WIRE[104]; // @[CSR.scala:1338:41] assign new_sstatus_debug = _new_sstatus_T_36; // @[CSR.scala:1338:41] wire _reg_mstatus_fs_T_2 = |new_sstatus_fs; // @[CSR.scala:1338:41, :1668:73] wire [1:0] _reg_mstatus_fs_T_3 = {2{_reg_mstatus_fs_T_2}}; // @[CSR.scala:1668:{66,73}] wire [63:0] _new_sip_T = ~read_mideleg; // @[CSR.scala:498:14, :1350:36] wire [63:0] _new_sip_T_1 = {48'h0, _new_sip_T[15:0] & read_mip}; // @[CSR.scala:610:29, :1350:{34,36}] wire [63:0] _new_sip_T_2 = wdata & read_mideleg; // @[CSR.scala:498:14, :1350:60, :1643:39] wire [63:0] _new_sip_T_3 = _new_sip_T_1 | _new_sip_T_2; // @[CSR.scala:1350:{34,51,60}] wire _new_sip_T_19; // @[CSR.scala:1350:85] wire _new_sip_T_18; // @[CSR.scala:1350:85] wire _new_sip_T_17; // @[CSR.scala:1350:85] wire _new_sip_T_16; // @[CSR.scala:1350:85] wire _new_sip_T_15; // @[CSR.scala:1350:85] wire _new_sip_T_14; // @[CSR.scala:1350:85] wire _new_sip_T_13; // @[CSR.scala:1350:85] wire _new_sip_T_12; // @[CSR.scala:1350:85] wire _new_sip_T_11; // @[CSR.scala:1350:85] wire _new_sip_T_10; // @[CSR.scala:1350:85] wire _new_sip_T_9; // @[CSR.scala:1350:85] wire _new_sip_T_8; // @[CSR.scala:1350:85] wire _new_sip_T_7; // @[CSR.scala:1350:85] wire _new_sip_T_6; // @[CSR.scala:1350:85] wire _new_sip_T_5; // @[CSR.scala:1350:85] wire _new_sip_T_4; // @[CSR.scala:1350:85] wire new_sip_zero1; // @[CSR.scala:1350:85] wire new_sip_debug; // @[CSR.scala:1350:85] wire new_sip_rocc; // @[CSR.scala:1350:85] wire new_sip_sgeip; // @[CSR.scala:1350:85] wire new_sip_meip; // @[CSR.scala:1350:85] wire new_sip_vseip; // @[CSR.scala:1350:85] wire new_sip_seip; // @[CSR.scala:1350:85] wire new_sip_ueip; // @[CSR.scala:1350:85] wire new_sip_mtip; // @[CSR.scala:1350:85] wire new_sip_vstip; // @[CSR.scala:1350:85] wire new_sip_stip; // @[CSR.scala:1350:85] wire new_sip_utip; // @[CSR.scala:1350:85] wire new_sip_msip; // @[CSR.scala:1350:85] wire new_sip_vssip; // @[CSR.scala:1350:85] wire new_sip_ssip; // @[CSR.scala:1350:85] wire new_sip_usip; // @[CSR.scala:1350:85] wire [15:0] _new_sip_WIRE = _new_sip_T_3[15:0]; // @[CSR.scala:1350:{51,85}] assign _new_sip_T_4 = _new_sip_WIRE[0]; // @[CSR.scala:1350:85] assign new_sip_usip = _new_sip_T_4; // @[CSR.scala:1350:85] assign _new_sip_T_5 = _new_sip_WIRE[1]; // @[CSR.scala:1350:85] assign new_sip_ssip = _new_sip_T_5; // @[CSR.scala:1350:85] assign _new_sip_T_6 = _new_sip_WIRE[2]; // @[CSR.scala:1350:85] assign new_sip_vssip = _new_sip_T_6; // @[CSR.scala:1350:85] assign _new_sip_T_7 = _new_sip_WIRE[3]; // @[CSR.scala:1350:85] assign new_sip_msip = _new_sip_T_7; // @[CSR.scala:1350:85] assign _new_sip_T_8 = _new_sip_WIRE[4]; // @[CSR.scala:1350:85] assign new_sip_utip = _new_sip_T_8; // @[CSR.scala:1350:85] assign _new_sip_T_9 = _new_sip_WIRE[5]; // @[CSR.scala:1350:85] assign new_sip_stip = _new_sip_T_9; // @[CSR.scala:1350:85] assign _new_sip_T_10 = _new_sip_WIRE[6]; // @[CSR.scala:1350:85] assign new_sip_vstip = _new_sip_T_10; // @[CSR.scala:1350:85] assign _new_sip_T_11 = _new_sip_WIRE[7]; // @[CSR.scala:1350:85] assign new_sip_mtip = _new_sip_T_11; // @[CSR.scala:1350:85] assign _new_sip_T_12 = _new_sip_WIRE[8]; // @[CSR.scala:1350:85] assign new_sip_ueip = _new_sip_T_12; // @[CSR.scala:1350:85] assign _new_sip_T_13 = _new_sip_WIRE[9]; // @[CSR.scala:1350:85] assign new_sip_seip = _new_sip_T_13; // @[CSR.scala:1350:85] assign _new_sip_T_14 = _new_sip_WIRE[10]; // @[CSR.scala:1350:85] assign new_sip_vseip = _new_sip_T_14; // @[CSR.scala:1350:85] assign _new_sip_T_15 = _new_sip_WIRE[11]; // @[CSR.scala:1350:85] assign new_sip_meip = _new_sip_T_15; // @[CSR.scala:1350:85] assign _new_sip_T_16 = _new_sip_WIRE[12]; // @[CSR.scala:1350:85] assign new_sip_sgeip = _new_sip_T_16; // @[CSR.scala:1350:85] assign _new_sip_T_17 = _new_sip_WIRE[13]; // @[CSR.scala:1350:85] assign new_sip_rocc = _new_sip_T_17; // @[CSR.scala:1350:85] assign _new_sip_T_18 = _new_sip_WIRE[14]; // @[CSR.scala:1350:85] assign new_sip_debug = _new_sip_T_18; // @[CSR.scala:1350:85] assign _new_sip_T_19 = _new_sip_WIRE[15]; // @[CSR.scala:1350:85] assign new_sip_zero1 = _new_sip_T_19; // @[CSR.scala:1350:85] wire [3:0] _new_satp_T_2; // @[CSR.scala:1355:40] wire [15:0] _new_satp_T_1; // @[CSR.scala:1355:40] wire [43:0] _new_satp_T; // @[CSR.scala:1355:40] wire [3:0] new_satp_mode; // @[CSR.scala:1355:40] wire [15:0] new_satp_asid; // @[CSR.scala:1355:40] wire [43:0] new_satp_ppn; // @[CSR.scala:1355:40] assign _new_satp_T = _new_satp_WIRE[43:0]; // @[CSR.scala:1355:40] assign new_satp_ppn = _new_satp_T; // @[CSR.scala:1355:40] assign _new_satp_T_1 = _new_satp_WIRE[59:44]; // @[CSR.scala:1355:40] assign new_satp_asid = _new_satp_T_1; // @[CSR.scala:1355:40] assign _new_satp_T_2 = _new_satp_WIRE[63:60]; // @[CSR.scala:1355:40] assign new_satp_mode = _new_satp_T_2; // @[CSR.scala:1355:40] wire [3:0] _reg_satp_mode_T = new_satp_mode & 4'h8; // @[CSR.scala:1355:40, :1357:44] wire [19:0] _reg_satp_ppn_T = new_satp_ppn[19:0]; // @[CSR.scala:1355:40, :1358:41] wire [63:0] _reg_mie_T_1 = ~sie_mask; // @[CSR.scala:750:18, :1363:66] wire [63:0] _reg_mie_T_2 = reg_mie & _reg_mie_T_1; // @[CSR.scala:495:20, :1363:{64,66}] wire [63:0] _reg_mie_T_3 = wdata & sie_mask; // @[CSR.scala:750:18, :1363:86, :1643:39] wire [63:0] _reg_mie_T_4 = _reg_mie_T_2 | _reg_mie_T_3; // @[CSR.scala:1363:{64,77,86}] wire [63:0] _reg_sepc_T = ~wdata; // @[CSR.scala:1263:25, :1643:39, :1664:28] wire [63:0] _reg_sepc_T_1 = {_reg_sepc_T[63:1], 1'h1}; // @[CSR.scala:1664:{28,31}] wire [63:0] _reg_sepc_T_2 = ~_reg_sepc_T_1; // @[CSR.scala:1664:{26,31}] wire [63:0] _reg_scause_T = wdata & 64'h800000000000001F; // @[CSR.scala:1367:64, :1643:39] wire _new_envcfg_T_7; // @[CSR.scala:137:36] wire _new_envcfg_T_6; // @[CSR.scala:137:36] wire [53:0] _new_envcfg_T_5; // @[CSR.scala:137:36] wire _new_envcfg_T_4; // @[CSR.scala:137:36] wire _new_envcfg_T_3; // @[CSR.scala:137:36] wire [1:0] _new_envcfg_T_2; // @[CSR.scala:137:36] wire [2:0] _new_envcfg_T_1; // @[CSR.scala:137:36] wire _new_envcfg_T; // @[CSR.scala:137:36] wire new_envcfg_stce; // @[CSR.scala:137:36] wire new_envcfg_pbmte; // @[CSR.scala:137:36] wire [53:0] new_envcfg_zero54; // @[CSR.scala:137:36] wire new_envcfg_cbze; // @[CSR.scala:137:36] wire new_envcfg_cbcfe; // @[CSR.scala:137:36] wire [1:0] new_envcfg_cbie; // @[CSR.scala:137:36] wire [2:0] new_envcfg_zero3; // @[CSR.scala:137:36] wire new_envcfg_fiom; // @[CSR.scala:137:36] assign _new_envcfg_T = _new_envcfg_WIRE[0]; // @[CSR.scala:137:36] assign new_envcfg_fiom = _new_envcfg_T; // @[CSR.scala:137:36] assign _new_envcfg_T_1 = _new_envcfg_WIRE[3:1]; // @[CSR.scala:137:36] assign new_envcfg_zero3 = _new_envcfg_T_1; // @[CSR.scala:137:36] assign _new_envcfg_T_2 = _new_envcfg_WIRE[5:4]; // @[CSR.scala:137:36] assign new_envcfg_cbie = _new_envcfg_T_2; // @[CSR.scala:137:36] assign _new_envcfg_T_3 = _new_envcfg_WIRE[6]; // @[CSR.scala:137:36] assign new_envcfg_cbcfe = _new_envcfg_T_3; // @[CSR.scala:137:36] assign _new_envcfg_T_4 = _new_envcfg_WIRE[7]; // @[CSR.scala:137:36] assign new_envcfg_cbze = _new_envcfg_T_4; // @[CSR.scala:137:36] assign _new_envcfg_T_5 = _new_envcfg_WIRE[61:8]; // @[CSR.scala:137:36] assign new_envcfg_zero54 = _new_envcfg_T_5; // @[CSR.scala:137:36] assign _new_envcfg_T_6 = _new_envcfg_WIRE[62]; // @[CSR.scala:137:36] assign new_envcfg_pbmte = _new_envcfg_T_6; // @[CSR.scala:137:36] assign _new_envcfg_T_7 = _new_envcfg_WIRE[63]; // @[CSR.scala:137:36] assign new_envcfg_stce = _new_envcfg_T_7; // @[CSR.scala:137:36] wire _new_envcfg_T_15; // @[CSR.scala:137:36] wire _new_envcfg_T_14; // @[CSR.scala:137:36] wire [53:0] _new_envcfg_T_13; // @[CSR.scala:137:36] wire _new_envcfg_T_12; // @[CSR.scala:137:36] wire _new_envcfg_T_11; // @[CSR.scala:137:36] wire [1:0] _new_envcfg_T_10; // @[CSR.scala:137:36] wire [2:0] _new_envcfg_T_9; // @[CSR.scala:137:36] wire _new_envcfg_T_8; // @[CSR.scala:137:36] wire new_envcfg_1_stce; // @[CSR.scala:137:36] wire new_envcfg_1_pbmte; // @[CSR.scala:137:36] wire [53:0] new_envcfg_1_zero54; // @[CSR.scala:137:36] wire new_envcfg_1_cbze; // @[CSR.scala:137:36] wire new_envcfg_1_cbcfe; // @[CSR.scala:137:36] wire [1:0] new_envcfg_1_cbie; // @[CSR.scala:137:36] wire [2:0] new_envcfg_1_zero3; // @[CSR.scala:137:36] wire new_envcfg_1_fiom; // @[CSR.scala:137:36] assign _new_envcfg_T_8 = _new_envcfg_WIRE_1[0]; // @[CSR.scala:137:36] assign new_envcfg_1_fiom = _new_envcfg_T_8; // @[CSR.scala:137:36] assign _new_envcfg_T_9 = _new_envcfg_WIRE_1[3:1]; // @[CSR.scala:137:36] assign new_envcfg_1_zero3 = _new_envcfg_T_9; // @[CSR.scala:137:36] assign _new_envcfg_T_10 = _new_envcfg_WIRE_1[5:4]; // @[CSR.scala:137:36] assign new_envcfg_1_cbie = _new_envcfg_T_10; // @[CSR.scala:137:36] assign _new_envcfg_T_11 = _new_envcfg_WIRE_1[6]; // @[CSR.scala:137:36] assign new_envcfg_1_cbcfe = _new_envcfg_T_11; // @[CSR.scala:137:36] assign _new_envcfg_T_12 = _new_envcfg_WIRE_1[7]; // @[CSR.scala:137:36] assign new_envcfg_1_cbze = _new_envcfg_T_12; // @[CSR.scala:137:36] assign _new_envcfg_T_13 = _new_envcfg_WIRE_1[61:8]; // @[CSR.scala:137:36] assign new_envcfg_1_zero54 = _new_envcfg_T_13; // @[CSR.scala:137:36] assign _new_envcfg_T_14 = _new_envcfg_WIRE_1[62]; // @[CSR.scala:137:36] assign new_envcfg_1_pbmte = _new_envcfg_T_14; // @[CSR.scala:137:36] assign _new_envcfg_T_15 = _new_envcfg_WIRE_1[63]; // @[CSR.scala:137:36] assign new_envcfg_1_stce = _new_envcfg_T_15; // @[CSR.scala:137:36] wire [3:0] _reg_bp_0_control_T_14; // @[CSR.scala:1471:41] wire _reg_bp_0_control_T_13; // @[CSR.scala:1471:41] wire [5:0] _reg_bp_0_control_T_12; // @[CSR.scala:1471:41] wire [39:0] _reg_bp_0_control_T_11; // @[CSR.scala:1471:41] wire _reg_bp_0_control_T_10; // @[CSR.scala:1471:41] wire _reg_bp_0_control_T_9; // @[CSR.scala:1471:41] wire [1:0] _reg_bp_0_control_T_8; // @[CSR.scala:1471:41] wire [1:0] _reg_bp_0_control_T_7; // @[CSR.scala:1471:41] wire _reg_bp_0_control_T_6; // @[CSR.scala:1471:41] wire _reg_bp_0_control_T_5; // @[CSR.scala:1471:41] wire _reg_bp_0_control_T_4; // @[CSR.scala:1471:41] wire _reg_bp_0_control_T_3; // @[CSR.scala:1471:41] wire _reg_bp_0_control_T_2; // @[CSR.scala:1471:41] wire _reg_bp_0_control_T_1; // @[CSR.scala:1471:41] wire _reg_bp_0_control_T; // @[CSR.scala:1471:41] assign _reg_bp_0_control_T = _reg_bp_0_control_WIRE_1[0]; // @[CSR.scala:1471:41] wire _reg_bp_0_control_WIRE_r = _reg_bp_0_control_T; // @[CSR.scala:1471:41] assign _reg_bp_0_control_T_1 = _reg_bp_0_control_WIRE_1[1]; // @[CSR.scala:1471:41] wire _reg_bp_0_control_WIRE_w = _reg_bp_0_control_T_1; // @[CSR.scala:1471:41] assign _reg_bp_0_control_T_2 = _reg_bp_0_control_WIRE_1[2]; // @[CSR.scala:1471:41] wire _reg_bp_0_control_WIRE_x = _reg_bp_0_control_T_2; // @[CSR.scala:1471:41] assign _reg_bp_0_control_T_3 = _reg_bp_0_control_WIRE_1[3]; // @[CSR.scala:1471:41] wire _reg_bp_0_control_WIRE_u = _reg_bp_0_control_T_3; // @[CSR.scala:1471:41] assign _reg_bp_0_control_T_4 = _reg_bp_0_control_WIRE_1[4]; // @[CSR.scala:1471:41] wire _reg_bp_0_control_WIRE_s = _reg_bp_0_control_T_4; // @[CSR.scala:1471:41] assign _reg_bp_0_control_T_5 = _reg_bp_0_control_WIRE_1[5]; // @[CSR.scala:1471:41] wire _reg_bp_0_control_WIRE_h = _reg_bp_0_control_T_5; // @[CSR.scala:1471:41] assign _reg_bp_0_control_T_6 = _reg_bp_0_control_WIRE_1[6]; // @[CSR.scala:1471:41] wire _reg_bp_0_control_WIRE_m = _reg_bp_0_control_T_6; // @[CSR.scala:1471:41] assign _reg_bp_0_control_T_7 = _reg_bp_0_control_WIRE_1[8:7]; // @[CSR.scala:1471:41] wire [1:0] _reg_bp_0_control_WIRE_tmatch = _reg_bp_0_control_T_7; // @[CSR.scala:1471:41] assign _reg_bp_0_control_T_8 = _reg_bp_0_control_WIRE_1[10:9]; // @[CSR.scala:1471:41] wire [1:0] _reg_bp_0_control_WIRE_zero = _reg_bp_0_control_T_8; // @[CSR.scala:1471:41] assign _reg_bp_0_control_T_9 = _reg_bp_0_control_WIRE_1[11]; // @[CSR.scala:1471:41] wire _reg_bp_0_control_WIRE_chain = _reg_bp_0_control_T_9; // @[CSR.scala:1471:41] assign _reg_bp_0_control_T_10 = _reg_bp_0_control_WIRE_1[12]; // @[CSR.scala:1471:41] wire _reg_bp_0_control_WIRE_action = _reg_bp_0_control_T_10; // @[CSR.scala:1471:41] assign _reg_bp_0_control_T_11 = _reg_bp_0_control_WIRE_1[52:13]; // @[CSR.scala:1471:41] wire [39:0] _reg_bp_0_control_WIRE_reserved = _reg_bp_0_control_T_11; // @[CSR.scala:1471:41] assign _reg_bp_0_control_T_12 = _reg_bp_0_control_WIRE_1[58:53]; // @[CSR.scala:1471:41] wire [5:0] _reg_bp_0_control_WIRE_maskmax = _reg_bp_0_control_T_12; // @[CSR.scala:1471:41] assign _reg_bp_0_control_T_13 = _reg_bp_0_control_WIRE_1[59]; // @[CSR.scala:1471:41] wire _reg_bp_0_control_WIRE_dmode = _reg_bp_0_control_T_13; // @[CSR.scala:1471:41] assign _reg_bp_0_control_T_14 = _reg_bp_0_control_WIRE_1[63:60]; // @[CSR.scala:1471:41] wire [3:0] _reg_bp_0_control_WIRE_ttype = _reg_bp_0_control_T_14; // @[CSR.scala:1471:41] wire [2:0] newBPC_lo_lo = {newBPC_lo_lo_hi, reg_bp_0_control_r}; // @[CSR.scala:492:19, :1477:67] wire [3:0] newBPC_lo_hi = {newBPC_lo_hi_hi, newBPC_lo_hi_lo}; // @[CSR.scala:1477:67] wire [6:0] newBPC_lo = {newBPC_lo_hi, newBPC_lo_lo}; // @[CSR.scala:1477:67] wire [5:0] newBPC_hi_lo = {newBPC_hi_lo_hi, newBPC_hi_lo_lo}; // @[CSR.scala:1477:67] wire [50:0] newBPC_hi_hi = {newBPC_hi_hi_hi, 46'h40000000000}; // @[CSR.scala:1477:67] wire [56:0] newBPC_hi = {newBPC_hi_hi, newBPC_hi_lo}; // @[CSR.scala:1477:67] wire [63:0] _newBPC_T = {newBPC_hi, newBPC_lo}; // @[CSR.scala:1477:67] wire [63:0] _newBPC_T_2 = _newBPC_T_1 ? _newBPC_T : 64'h0; // @[CSR.scala:1477:67, :1643:{9,13}] wire [63:0] _newBPC_T_3 = _newBPC_T_2 | io_rw_wdata_0; // @[CSR.scala:377:7, :1643:{9,30}] wire _newBPC_T_5 = &_newBPC_T_4; // @[CSR.scala:1643:{49,55}] wire [63:0] _newBPC_T_6 = _newBPC_T_5 ? io_rw_wdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{45,55}] wire [63:0] _newBPC_T_7 = ~_newBPC_T_6; // @[CSR.scala:1643:{41,45}] wire [63:0] _newBPC_T_8 = _newBPC_T_3 & _newBPC_T_7; // @[CSR.scala:1643:{30,39,41}] wire [63:0] _newBPC_WIRE = _newBPC_T_8; // @[CSR.scala:1477:96, :1643:39] wire [3:0] _newBPC_T_23; // @[CSR.scala:1477:96] wire _newBPC_T_22; // @[CSR.scala:1477:96] wire [5:0] _newBPC_T_21; // @[CSR.scala:1477:96] wire [39:0] _newBPC_T_20; // @[CSR.scala:1477:96] wire _newBPC_T_19; // @[CSR.scala:1477:96] wire _newBPC_T_18; // @[CSR.scala:1477:96] wire [1:0] _newBPC_T_17; // @[CSR.scala:1477:96] wire [1:0] _newBPC_T_16; // @[CSR.scala:1477:96] wire _newBPC_T_15; // @[CSR.scala:1477:96] wire _newBPC_T_14; // @[CSR.scala:1477:96] wire _newBPC_T_13; // @[CSR.scala:1477:96] wire _newBPC_T_12; // @[CSR.scala:1477:96] wire _newBPC_T_11; // @[CSR.scala:1477:96] wire _newBPC_T_10; // @[CSR.scala:1477:96] wire _newBPC_T_9; // @[CSR.scala:1477:96] wire [3:0] newBPC_ttype; // @[CSR.scala:1477:96] wire newBPC_dmode; // @[CSR.scala:1477:96] wire [5:0] newBPC_maskmax; // @[CSR.scala:1477:96] wire [39:0] newBPC_reserved; // @[CSR.scala:1477:96] wire newBPC_action; // @[CSR.scala:1477:96] wire newBPC_chain; // @[CSR.scala:1477:96] wire [1:0] newBPC_zero; // @[CSR.scala:1477:96] wire [1:0] newBPC_tmatch; // @[CSR.scala:1477:96] wire newBPC_m; // @[CSR.scala:1477:96] wire newBPC_h; // @[CSR.scala:1477:96] wire newBPC_s; // @[CSR.scala:1477:96] wire newBPC_u; // @[CSR.scala:1477:96] wire newBPC_x; // @[CSR.scala:1477:96] wire newBPC_w; // @[CSR.scala:1477:96] wire newBPC_r; // @[CSR.scala:1477:96] assign _newBPC_T_9 = _newBPC_WIRE[0]; // @[CSR.scala:1477:96] assign newBPC_r = _newBPC_T_9; // @[CSR.scala:1477:96] assign _newBPC_T_10 = _newBPC_WIRE[1]; // @[CSR.scala:1477:96] assign newBPC_w = _newBPC_T_10; // @[CSR.scala:1477:96] assign _newBPC_T_11 = _newBPC_WIRE[2]; // @[CSR.scala:1477:96] assign newBPC_x = _newBPC_T_11; // @[CSR.scala:1477:96] assign _newBPC_T_12 = _newBPC_WIRE[3]; // @[CSR.scala:1477:96] assign newBPC_u = _newBPC_T_12; // @[CSR.scala:1477:96] assign _newBPC_T_13 = _newBPC_WIRE[4]; // @[CSR.scala:1477:96] assign newBPC_s = _newBPC_T_13; // @[CSR.scala:1477:96] assign _newBPC_T_14 = _newBPC_WIRE[5]; // @[CSR.scala:1477:96] assign newBPC_h = _newBPC_T_14; // @[CSR.scala:1477:96] assign _newBPC_T_15 = _newBPC_WIRE[6]; // @[CSR.scala:1477:96] assign newBPC_m = _newBPC_T_15; // @[CSR.scala:1477:96] assign _newBPC_T_16 = _newBPC_WIRE[8:7]; // @[CSR.scala:1477:96] assign newBPC_tmatch = _newBPC_T_16; // @[CSR.scala:1477:96] assign _newBPC_T_17 = _newBPC_WIRE[10:9]; // @[CSR.scala:1477:96] assign newBPC_zero = _newBPC_T_17; // @[CSR.scala:1477:96] assign _newBPC_T_18 = _newBPC_WIRE[11]; // @[CSR.scala:1477:96] assign newBPC_chain = _newBPC_T_18; // @[CSR.scala:1477:96] assign _newBPC_T_19 = _newBPC_WIRE[12]; // @[CSR.scala:1477:96] assign newBPC_action = _newBPC_T_19; // @[CSR.scala:1477:96] assign _newBPC_T_20 = _newBPC_WIRE[52:13]; // @[CSR.scala:1477:96] assign newBPC_reserved = _newBPC_T_20; // @[CSR.scala:1477:96] assign _newBPC_T_21 = _newBPC_WIRE[58:53]; // @[CSR.scala:1477:96] assign newBPC_maskmax = _newBPC_T_21; // @[CSR.scala:1477:96] assign _newBPC_T_22 = _newBPC_WIRE[59]; // @[CSR.scala:1477:96] assign newBPC_dmode = _newBPC_T_22; // @[CSR.scala:1477:96] assign _newBPC_T_23 = _newBPC_WIRE[63:60]; // @[CSR.scala:1477:96] assign newBPC_ttype = _newBPC_T_23; // @[CSR.scala:1477:96] wire _dMode_T = newBPC_dmode & reg_debug; // @[CSR.scala:482:26, :1477:96, :1478:38] wire dMode = _dMode_T; // @[CSR.scala:1478:{38,51}] wire _reg_bp_0_control_chain_T_4 = dMode; // @[CSR.scala:1478:51, :1481:85] wire [3:0] _reg_bp_1_control_T_14; // @[CSR.scala:1471:41] wire _reg_bp_1_control_T_13; // @[CSR.scala:1471:41] wire [5:0] _reg_bp_1_control_T_12; // @[CSR.scala:1471:41] wire [39:0] _reg_bp_1_control_T_11; // @[CSR.scala:1471:41] wire _reg_bp_1_control_T_10; // @[CSR.scala:1471:41] wire _reg_bp_1_control_T_9; // @[CSR.scala:1471:41] wire [1:0] _reg_bp_1_control_T_8; // @[CSR.scala:1471:41] wire [1:0] _reg_bp_1_control_T_7; // @[CSR.scala:1471:41] wire _reg_bp_1_control_T_6; // @[CSR.scala:1471:41] wire _reg_bp_1_control_T_5; // @[CSR.scala:1471:41] wire _reg_bp_1_control_T_4; // @[CSR.scala:1471:41] wire _reg_bp_1_control_T_3; // @[CSR.scala:1471:41] wire _reg_bp_1_control_T_2; // @[CSR.scala:1471:41] wire _reg_bp_1_control_T_1; // @[CSR.scala:1471:41] wire _reg_bp_1_control_T; // @[CSR.scala:1471:41] assign _reg_bp_1_control_T = _reg_bp_1_control_WIRE_1[0]; // @[CSR.scala:1471:41] wire _reg_bp_1_control_WIRE_r = _reg_bp_1_control_T; // @[CSR.scala:1471:41] assign _reg_bp_1_control_T_1 = _reg_bp_1_control_WIRE_1[1]; // @[CSR.scala:1471:41] wire _reg_bp_1_control_WIRE_w = _reg_bp_1_control_T_1; // @[CSR.scala:1471:41] assign _reg_bp_1_control_T_2 = _reg_bp_1_control_WIRE_1[2]; // @[CSR.scala:1471:41] wire _reg_bp_1_control_WIRE_x = _reg_bp_1_control_T_2; // @[CSR.scala:1471:41] assign _reg_bp_1_control_T_3 = _reg_bp_1_control_WIRE_1[3]; // @[CSR.scala:1471:41] wire _reg_bp_1_control_WIRE_u = _reg_bp_1_control_T_3; // @[CSR.scala:1471:41] assign _reg_bp_1_control_T_4 = _reg_bp_1_control_WIRE_1[4]; // @[CSR.scala:1471:41] wire _reg_bp_1_control_WIRE_s = _reg_bp_1_control_T_4; // @[CSR.scala:1471:41] assign _reg_bp_1_control_T_5 = _reg_bp_1_control_WIRE_1[5]; // @[CSR.scala:1471:41] wire _reg_bp_1_control_WIRE_h = _reg_bp_1_control_T_5; // @[CSR.scala:1471:41] assign _reg_bp_1_control_T_6 = _reg_bp_1_control_WIRE_1[6]; // @[CSR.scala:1471:41] wire _reg_bp_1_control_WIRE_m = _reg_bp_1_control_T_6; // @[CSR.scala:1471:41] assign _reg_bp_1_control_T_7 = _reg_bp_1_control_WIRE_1[8:7]; // @[CSR.scala:1471:41] wire [1:0] _reg_bp_1_control_WIRE_tmatch = _reg_bp_1_control_T_7; // @[CSR.scala:1471:41] assign _reg_bp_1_control_T_8 = _reg_bp_1_control_WIRE_1[10:9]; // @[CSR.scala:1471:41] wire [1:0] _reg_bp_1_control_WIRE_zero = _reg_bp_1_control_T_8; // @[CSR.scala:1471:41] assign _reg_bp_1_control_T_9 = _reg_bp_1_control_WIRE_1[11]; // @[CSR.scala:1471:41] wire _reg_bp_1_control_WIRE_chain = _reg_bp_1_control_T_9; // @[CSR.scala:1471:41] assign _reg_bp_1_control_T_10 = _reg_bp_1_control_WIRE_1[12]; // @[CSR.scala:1471:41] wire _reg_bp_1_control_WIRE_action = _reg_bp_1_control_T_10; // @[CSR.scala:1471:41] assign _reg_bp_1_control_T_11 = _reg_bp_1_control_WIRE_1[52:13]; // @[CSR.scala:1471:41] wire [39:0] _reg_bp_1_control_WIRE_reserved = _reg_bp_1_control_T_11; // @[CSR.scala:1471:41] assign _reg_bp_1_control_T_12 = _reg_bp_1_control_WIRE_1[58:53]; // @[CSR.scala:1471:41] wire [5:0] _reg_bp_1_control_WIRE_maskmax = _reg_bp_1_control_T_12; // @[CSR.scala:1471:41] assign _reg_bp_1_control_T_13 = _reg_bp_1_control_WIRE_1[59]; // @[CSR.scala:1471:41] wire _reg_bp_1_control_WIRE_dmode = _reg_bp_1_control_T_13; // @[CSR.scala:1471:41] assign _reg_bp_1_control_T_14 = _reg_bp_1_control_WIRE_1[63:60]; // @[CSR.scala:1471:41] wire [3:0] _reg_bp_1_control_WIRE_ttype = _reg_bp_1_control_T_14; // @[CSR.scala:1471:41] wire _newBPC_T_29 = &_newBPC_T_28; // @[CSR.scala:1643:{49,55}] wire [63:0] _newBPC_T_30 = _newBPC_T_29 ? io_rw_wdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{45,55}] wire [63:0] _newBPC_T_31 = ~_newBPC_T_30; // @[CSR.scala:1643:{41,45}] wire [63:0] _newBPC_T_32 = _newBPC_T_27 & _newBPC_T_31; // @[CSR.scala:1643:{30,39,41}] wire [63:0] _newBPC_WIRE_1 = _newBPC_T_32; // @[CSR.scala:1477:96, :1643:39] wire [3:0] _newBPC_T_47; // @[CSR.scala:1477:96] wire _newBPC_T_46; // @[CSR.scala:1477:96] wire [5:0] _newBPC_T_45; // @[CSR.scala:1477:96] wire [39:0] _newBPC_T_44; // @[CSR.scala:1477:96] wire _newBPC_T_43; // @[CSR.scala:1477:96] wire _newBPC_T_42; // @[CSR.scala:1477:96] wire [1:0] _newBPC_T_41; // @[CSR.scala:1477:96] wire [1:0] _newBPC_T_40; // @[CSR.scala:1477:96] wire _newBPC_T_39; // @[CSR.scala:1477:96] wire _newBPC_T_38; // @[CSR.scala:1477:96] wire _newBPC_T_37; // @[CSR.scala:1477:96] wire _newBPC_T_36; // @[CSR.scala:1477:96] wire _newBPC_T_35; // @[CSR.scala:1477:96] wire _newBPC_T_34; // @[CSR.scala:1477:96] wire _newBPC_T_33; // @[CSR.scala:1477:96] wire [3:0] newBPC_1_ttype; // @[CSR.scala:1477:96] wire newBPC_1_dmode; // @[CSR.scala:1477:96] wire [5:0] newBPC_1_maskmax; // @[CSR.scala:1477:96] wire [39:0] newBPC_1_reserved; // @[CSR.scala:1477:96] wire newBPC_1_action; // @[CSR.scala:1477:96] wire newBPC_1_chain; // @[CSR.scala:1477:96] wire [1:0] newBPC_1_zero; // @[CSR.scala:1477:96] wire [1:0] newBPC_1_tmatch; // @[CSR.scala:1477:96] wire newBPC_1_m; // @[CSR.scala:1477:96] wire newBPC_1_h; // @[CSR.scala:1477:96] wire newBPC_1_s; // @[CSR.scala:1477:96] wire newBPC_1_u; // @[CSR.scala:1477:96] wire newBPC_1_x; // @[CSR.scala:1477:96] wire newBPC_1_w; // @[CSR.scala:1477:96] wire newBPC_1_r; // @[CSR.scala:1477:96] assign _newBPC_T_33 = _newBPC_WIRE_1[0]; // @[CSR.scala:1477:96] assign newBPC_1_r = _newBPC_T_33; // @[CSR.scala:1477:96] assign _newBPC_T_34 = _newBPC_WIRE_1[1]; // @[CSR.scala:1477:96] assign newBPC_1_w = _newBPC_T_34; // @[CSR.scala:1477:96] assign _newBPC_T_35 = _newBPC_WIRE_1[2]; // @[CSR.scala:1477:96] assign newBPC_1_x = _newBPC_T_35; // @[CSR.scala:1477:96] assign _newBPC_T_36 = _newBPC_WIRE_1[3]; // @[CSR.scala:1477:96] assign newBPC_1_u = _newBPC_T_36; // @[CSR.scala:1477:96] assign _newBPC_T_37 = _newBPC_WIRE_1[4]; // @[CSR.scala:1477:96] assign newBPC_1_s = _newBPC_T_37; // @[CSR.scala:1477:96] assign _newBPC_T_38 = _newBPC_WIRE_1[5]; // @[CSR.scala:1477:96] assign newBPC_1_h = _newBPC_T_38; // @[CSR.scala:1477:96] assign _newBPC_T_39 = _newBPC_WIRE_1[6]; // @[CSR.scala:1477:96] assign newBPC_1_m = _newBPC_T_39; // @[CSR.scala:1477:96] assign _newBPC_T_40 = _newBPC_WIRE_1[8:7]; // @[CSR.scala:1477:96] assign newBPC_1_tmatch = _newBPC_T_40; // @[CSR.scala:1477:96] assign _newBPC_T_41 = _newBPC_WIRE_1[10:9]; // @[CSR.scala:1477:96] assign newBPC_1_zero = _newBPC_T_41; // @[CSR.scala:1477:96] assign _newBPC_T_42 = _newBPC_WIRE_1[11]; // @[CSR.scala:1477:96] assign newBPC_1_chain = _newBPC_T_42; // @[CSR.scala:1477:96] assign _newBPC_T_43 = _newBPC_WIRE_1[12]; // @[CSR.scala:1477:96] assign newBPC_1_action = _newBPC_T_43; // @[CSR.scala:1477:96] assign _newBPC_T_44 = _newBPC_WIRE_1[52:13]; // @[CSR.scala:1477:96] assign newBPC_1_reserved = _newBPC_T_44; // @[CSR.scala:1477:96] assign _newBPC_T_45 = _newBPC_WIRE_1[58:53]; // @[CSR.scala:1477:96] assign newBPC_1_maskmax = _newBPC_T_45; // @[CSR.scala:1477:96] assign _newBPC_T_46 = _newBPC_WIRE_1[59]; // @[CSR.scala:1477:96] assign newBPC_1_dmode = _newBPC_T_46; // @[CSR.scala:1477:96] assign _newBPC_T_47 = _newBPC_WIRE_1[63:60]; // @[CSR.scala:1477:96] assign newBPC_1_ttype = _newBPC_T_47; // @[CSR.scala:1477:96] wire _dMode_T_3 = newBPC_1_dmode & reg_debug; // @[CSR.scala:482:26, :1477:96, :1478:38] wire dMode_1 = _dMode_T_3; // @[CSR.scala:1478:{38,51}] wire _reg_bp_1_control_chain_T_4 = dMode_1; // @[CSR.scala:1478:51, :1481:85] wire _newCfg_T_6; // @[CSR.scala:1491:73] wire [1:0] _newCfg_T_5; // @[CSR.scala:1491:73] wire [1:0] _newCfg_T_4; // @[CSR.scala:1491:73] wire _newCfg_T_3; // @[CSR.scala:1491:73] wire _newCfg_T_2; // @[CSR.scala:1491:73] wire _newCfg_T_1; // @[CSR.scala:1491:73] wire newCfg_l; // @[CSR.scala:1491:73] wire [1:0] newCfg_res; // @[CSR.scala:1491:73] wire [1:0] newCfg_a; // @[CSR.scala:1491:73] wire newCfg_x; // @[CSR.scala:1491:73] wire newCfg_w; // @[CSR.scala:1491:73] wire newCfg_r; // @[CSR.scala:1491:73] wire [7:0] _newCfg_WIRE = _newCfg_T[7:0]; // @[CSR.scala:1491:{29,73}] assign _newCfg_T_1 = _newCfg_WIRE[0]; // @[CSR.scala:1491:73] assign newCfg_r = _newCfg_T_1; // @[CSR.scala:1491:73] assign _newCfg_T_2 = _newCfg_WIRE[1]; // @[CSR.scala:1491:73] assign newCfg_w = _newCfg_T_2; // @[CSR.scala:1491:73] assign _newCfg_T_3 = _newCfg_WIRE[2]; // @[CSR.scala:1491:73] assign newCfg_x = _newCfg_T_3; // @[CSR.scala:1491:73] assign _newCfg_T_4 = _newCfg_WIRE[4:3]; // @[CSR.scala:1491:73] assign newCfg_a = _newCfg_T_4; // @[CSR.scala:1491:73] assign _newCfg_T_5 = _newCfg_WIRE[6:5]; // @[CSR.scala:1491:73] assign newCfg_res = _newCfg_T_5; // @[CSR.scala:1491:73] assign _newCfg_T_6 = _newCfg_WIRE[7]; // @[CSR.scala:1491:73] assign newCfg_l = _newCfg_T_6; // @[CSR.scala:1491:73] wire _reg_pmp_0_cfg_w_T = newCfg_w & newCfg_r; // @[CSR.scala:1491:73, :1494:31] wire [55:0] _newCfg_T_7 = wdata[63:8]; // @[CSR.scala:1491:29, :1643:39] wire _newCfg_T_13; // @[CSR.scala:1491:73] wire [1:0] _newCfg_T_12; // @[CSR.scala:1491:73] wire [1:0] _newCfg_T_11; // @[CSR.scala:1491:73] wire _newCfg_T_10; // @[CSR.scala:1491:73] wire _newCfg_T_9; // @[CSR.scala:1491:73] wire _newCfg_T_8; // @[CSR.scala:1491:73] wire newCfg_1_l; // @[CSR.scala:1491:73] wire [1:0] newCfg_1_res; // @[CSR.scala:1491:73] wire [1:0] newCfg_1_a; // @[CSR.scala:1491:73] wire newCfg_1_x; // @[CSR.scala:1491:73] wire newCfg_1_w; // @[CSR.scala:1491:73] wire newCfg_1_r; // @[CSR.scala:1491:73] wire [7:0] _newCfg_WIRE_1 = _newCfg_T_7[7:0]; // @[CSR.scala:1491:{29,73}] assign _newCfg_T_8 = _newCfg_WIRE_1[0]; // @[CSR.scala:1491:73] assign newCfg_1_r = _newCfg_T_8; // @[CSR.scala:1491:73] assign _newCfg_T_9 = _newCfg_WIRE_1[1]; // @[CSR.scala:1491:73] assign newCfg_1_w = _newCfg_T_9; // @[CSR.scala:1491:73] assign _newCfg_T_10 = _newCfg_WIRE_1[2]; // @[CSR.scala:1491:73] assign newCfg_1_x = _newCfg_T_10; // @[CSR.scala:1491:73] assign _newCfg_T_11 = _newCfg_WIRE_1[4:3]; // @[CSR.scala:1491:73] assign newCfg_1_a = _newCfg_T_11; // @[CSR.scala:1491:73] assign _newCfg_T_12 = _newCfg_WIRE_1[6:5]; // @[CSR.scala:1491:73] assign newCfg_1_res = _newCfg_T_12; // @[CSR.scala:1491:73] assign _newCfg_T_13 = _newCfg_WIRE_1[7]; // @[CSR.scala:1491:73] assign newCfg_1_l = _newCfg_T_13; // @[CSR.scala:1491:73] wire _reg_pmp_1_cfg_w_T = newCfg_1_w & newCfg_1_r; // @[CSR.scala:1491:73, :1494:31] wire [47:0] _newCfg_T_14 = wdata[63:16]; // @[CSR.scala:1491:29, :1643:39] wire _newCfg_T_20; // @[CSR.scala:1491:73] wire [1:0] _newCfg_T_19; // @[CSR.scala:1491:73] wire [1:0] _newCfg_T_18; // @[CSR.scala:1491:73] wire _newCfg_T_17; // @[CSR.scala:1491:73] wire _newCfg_T_16; // @[CSR.scala:1491:73] wire _newCfg_T_15; // @[CSR.scala:1491:73] wire newCfg_2_l; // @[CSR.scala:1491:73] wire [1:0] newCfg_2_res; // @[CSR.scala:1491:73] wire [1:0] newCfg_2_a; // @[CSR.scala:1491:73] wire newCfg_2_x; // @[CSR.scala:1491:73] wire newCfg_2_w; // @[CSR.scala:1491:73] wire newCfg_2_r; // @[CSR.scala:1491:73] wire [7:0] _newCfg_WIRE_2 = _newCfg_T_14[7:0]; // @[CSR.scala:1491:{29,73}] assign _newCfg_T_15 = _newCfg_WIRE_2[0]; // @[CSR.scala:1491:73] assign newCfg_2_r = _newCfg_T_15; // @[CSR.scala:1491:73] assign _newCfg_T_16 = _newCfg_WIRE_2[1]; // @[CSR.scala:1491:73] assign newCfg_2_w = _newCfg_T_16; // @[CSR.scala:1491:73] assign _newCfg_T_17 = _newCfg_WIRE_2[2]; // @[CSR.scala:1491:73] assign newCfg_2_x = _newCfg_T_17; // @[CSR.scala:1491:73] assign _newCfg_T_18 = _newCfg_WIRE_2[4:3]; // @[CSR.scala:1491:73] assign newCfg_2_a = _newCfg_T_18; // @[CSR.scala:1491:73] assign _newCfg_T_19 = _newCfg_WIRE_2[6:5]; // @[CSR.scala:1491:73] assign newCfg_2_res = _newCfg_T_19; // @[CSR.scala:1491:73] assign _newCfg_T_20 = _newCfg_WIRE_2[7]; // @[CSR.scala:1491:73] assign newCfg_2_l = _newCfg_T_20; // @[CSR.scala:1491:73] wire _reg_pmp_2_cfg_w_T = newCfg_2_w & newCfg_2_r; // @[CSR.scala:1491:73, :1494:31] wire [39:0] _newCfg_T_21 = wdata[63:24]; // @[CSR.scala:1491:29, :1643:39] wire _newCfg_T_27; // @[CSR.scala:1491:73] wire [1:0] _newCfg_T_26; // @[CSR.scala:1491:73] wire [1:0] _newCfg_T_25; // @[CSR.scala:1491:73] wire _newCfg_T_24; // @[CSR.scala:1491:73] wire _newCfg_T_23; // @[CSR.scala:1491:73] wire _newCfg_T_22; // @[CSR.scala:1491:73] wire newCfg_3_l; // @[CSR.scala:1491:73] wire [1:0] newCfg_3_res; // @[CSR.scala:1491:73] wire [1:0] newCfg_3_a; // @[CSR.scala:1491:73] wire newCfg_3_x; // @[CSR.scala:1491:73] wire newCfg_3_w; // @[CSR.scala:1491:73] wire newCfg_3_r; // @[CSR.scala:1491:73] wire [7:0] _newCfg_WIRE_3 = _newCfg_T_21[7:0]; // @[CSR.scala:1491:{29,73}] assign _newCfg_T_22 = _newCfg_WIRE_3[0]; // @[CSR.scala:1491:73] assign newCfg_3_r = _newCfg_T_22; // @[CSR.scala:1491:73] assign _newCfg_T_23 = _newCfg_WIRE_3[1]; // @[CSR.scala:1491:73] assign newCfg_3_w = _newCfg_T_23; // @[CSR.scala:1491:73] assign _newCfg_T_24 = _newCfg_WIRE_3[2]; // @[CSR.scala:1491:73] assign newCfg_3_x = _newCfg_T_24; // @[CSR.scala:1491:73] assign _newCfg_T_25 = _newCfg_WIRE_3[4:3]; // @[CSR.scala:1491:73] assign newCfg_3_a = _newCfg_T_25; // @[CSR.scala:1491:73] assign _newCfg_T_26 = _newCfg_WIRE_3[6:5]; // @[CSR.scala:1491:73] assign newCfg_3_res = _newCfg_T_26; // @[CSR.scala:1491:73] assign _newCfg_T_27 = _newCfg_WIRE_3[7]; // @[CSR.scala:1491:73] assign newCfg_3_l = _newCfg_T_27; // @[CSR.scala:1491:73] wire _reg_pmp_3_cfg_w_T = newCfg_3_w & newCfg_3_r; // @[CSR.scala:1491:73, :1494:31] wire [31:0] _newCfg_T_28 = wdata[63:32]; // @[CSR.scala:1491:29, :1643:39] wire _newCfg_T_34; // @[CSR.scala:1491:73] wire [1:0] _newCfg_T_33; // @[CSR.scala:1491:73] wire [1:0] _newCfg_T_32; // @[CSR.scala:1491:73] wire _newCfg_T_31; // @[CSR.scala:1491:73] wire _newCfg_T_30; // @[CSR.scala:1491:73] wire _newCfg_T_29; // @[CSR.scala:1491:73] wire newCfg_4_l; // @[CSR.scala:1491:73] wire [1:0] newCfg_4_res; // @[CSR.scala:1491:73] wire [1:0] newCfg_4_a; // @[CSR.scala:1491:73] wire newCfg_4_x; // @[CSR.scala:1491:73] wire newCfg_4_w; // @[CSR.scala:1491:73] wire newCfg_4_r; // @[CSR.scala:1491:73] wire [7:0] _newCfg_WIRE_4 = _newCfg_T_28[7:0]; // @[CSR.scala:1491:{29,73}] assign _newCfg_T_29 = _newCfg_WIRE_4[0]; // @[CSR.scala:1491:73] assign newCfg_4_r = _newCfg_T_29; // @[CSR.scala:1491:73] assign _newCfg_T_30 = _newCfg_WIRE_4[1]; // @[CSR.scala:1491:73] assign newCfg_4_w = _newCfg_T_30; // @[CSR.scala:1491:73] assign _newCfg_T_31 = _newCfg_WIRE_4[2]; // @[CSR.scala:1491:73] assign newCfg_4_x = _newCfg_T_31; // @[CSR.scala:1491:73] assign _newCfg_T_32 = _newCfg_WIRE_4[4:3]; // @[CSR.scala:1491:73] assign newCfg_4_a = _newCfg_T_32; // @[CSR.scala:1491:73] assign _newCfg_T_33 = _newCfg_WIRE_4[6:5]; // @[CSR.scala:1491:73] assign newCfg_4_res = _newCfg_T_33; // @[CSR.scala:1491:73] assign _newCfg_T_34 = _newCfg_WIRE_4[7]; // @[CSR.scala:1491:73] assign newCfg_4_l = _newCfg_T_34; // @[CSR.scala:1491:73] wire _reg_pmp_4_cfg_w_T = newCfg_4_w & newCfg_4_r; // @[CSR.scala:1491:73, :1494:31] wire [23:0] _newCfg_T_35 = wdata[63:40]; // @[CSR.scala:1491:29, :1643:39] wire _newCfg_T_41; // @[CSR.scala:1491:73] wire [1:0] _newCfg_T_40; // @[CSR.scala:1491:73] wire [1:0] _newCfg_T_39; // @[CSR.scala:1491:73] wire _newCfg_T_38; // @[CSR.scala:1491:73] wire _newCfg_T_37; // @[CSR.scala:1491:73] wire _newCfg_T_36; // @[CSR.scala:1491:73] wire newCfg_5_l; // @[CSR.scala:1491:73] wire [1:0] newCfg_5_res; // @[CSR.scala:1491:73] wire [1:0] newCfg_5_a; // @[CSR.scala:1491:73] wire newCfg_5_x; // @[CSR.scala:1491:73] wire newCfg_5_w; // @[CSR.scala:1491:73] wire newCfg_5_r; // @[CSR.scala:1491:73] wire [7:0] _newCfg_WIRE_5 = _newCfg_T_35[7:0]; // @[CSR.scala:1491:{29,73}] assign _newCfg_T_36 = _newCfg_WIRE_5[0]; // @[CSR.scala:1491:73] assign newCfg_5_r = _newCfg_T_36; // @[CSR.scala:1491:73] assign _newCfg_T_37 = _newCfg_WIRE_5[1]; // @[CSR.scala:1491:73] assign newCfg_5_w = _newCfg_T_37; // @[CSR.scala:1491:73] assign _newCfg_T_38 = _newCfg_WIRE_5[2]; // @[CSR.scala:1491:73] assign newCfg_5_x = _newCfg_T_38; // @[CSR.scala:1491:73] assign _newCfg_T_39 = _newCfg_WIRE_5[4:3]; // @[CSR.scala:1491:73] assign newCfg_5_a = _newCfg_T_39; // @[CSR.scala:1491:73] assign _newCfg_T_40 = _newCfg_WIRE_5[6:5]; // @[CSR.scala:1491:73] assign newCfg_5_res = _newCfg_T_40; // @[CSR.scala:1491:73] assign _newCfg_T_41 = _newCfg_WIRE_5[7]; // @[CSR.scala:1491:73] assign newCfg_5_l = _newCfg_T_41; // @[CSR.scala:1491:73] wire _reg_pmp_5_cfg_w_T = newCfg_5_w & newCfg_5_r; // @[CSR.scala:1491:73, :1494:31] wire [15:0] _newCfg_T_42 = wdata[63:48]; // @[CSR.scala:1491:29, :1643:39] wire _newCfg_T_48; // @[CSR.scala:1491:73] wire [1:0] _newCfg_T_47; // @[CSR.scala:1491:73] wire [1:0] _newCfg_T_46; // @[CSR.scala:1491:73] wire _newCfg_T_45; // @[CSR.scala:1491:73] wire _newCfg_T_44; // @[CSR.scala:1491:73] wire _newCfg_T_43; // @[CSR.scala:1491:73] wire newCfg_6_l; // @[CSR.scala:1491:73] wire [1:0] newCfg_6_res; // @[CSR.scala:1491:73] wire [1:0] newCfg_6_a; // @[CSR.scala:1491:73] wire newCfg_6_x; // @[CSR.scala:1491:73] wire newCfg_6_w; // @[CSR.scala:1491:73] wire newCfg_6_r; // @[CSR.scala:1491:73] wire [7:0] _newCfg_WIRE_6 = _newCfg_T_42[7:0]; // @[CSR.scala:1491:{29,73}] assign _newCfg_T_43 = _newCfg_WIRE_6[0]; // @[CSR.scala:1491:73] assign newCfg_6_r = _newCfg_T_43; // @[CSR.scala:1491:73] assign _newCfg_T_44 = _newCfg_WIRE_6[1]; // @[CSR.scala:1491:73] assign newCfg_6_w = _newCfg_T_44; // @[CSR.scala:1491:73] assign _newCfg_T_45 = _newCfg_WIRE_6[2]; // @[CSR.scala:1491:73] assign newCfg_6_x = _newCfg_T_45; // @[CSR.scala:1491:73] assign _newCfg_T_46 = _newCfg_WIRE_6[4:3]; // @[CSR.scala:1491:73] assign newCfg_6_a = _newCfg_T_46; // @[CSR.scala:1491:73] assign _newCfg_T_47 = _newCfg_WIRE_6[6:5]; // @[CSR.scala:1491:73] assign newCfg_6_res = _newCfg_T_47; // @[CSR.scala:1491:73] assign _newCfg_T_48 = _newCfg_WIRE_6[7]; // @[CSR.scala:1491:73] assign newCfg_6_l = _newCfg_T_48; // @[CSR.scala:1491:73] wire _reg_pmp_6_cfg_w_T = newCfg_6_w & newCfg_6_r; // @[CSR.scala:1491:73, :1494:31] wire [7:0] _newCfg_T_49 = wdata[63:56]; // @[CSR.scala:1491:29, :1643:39] wire [7:0] _newCfg_WIRE_7 = _newCfg_T_49; // @[CSR.scala:1491:{29,73}] wire _newCfg_T_55; // @[CSR.scala:1491:73] wire [1:0] _newCfg_T_54; // @[CSR.scala:1491:73] wire [1:0] _newCfg_T_53; // @[CSR.scala:1491:73] wire _newCfg_T_52; // @[CSR.scala:1491:73] wire _newCfg_T_51; // @[CSR.scala:1491:73] wire _newCfg_T_50; // @[CSR.scala:1491:73] wire newCfg_7_l; // @[CSR.scala:1491:73] wire [1:0] newCfg_7_res; // @[CSR.scala:1491:73] wire [1:0] newCfg_7_a; // @[CSR.scala:1491:73] wire newCfg_7_x; // @[CSR.scala:1491:73] wire newCfg_7_w; // @[CSR.scala:1491:73] wire newCfg_7_r; // @[CSR.scala:1491:73] assign _newCfg_T_50 = _newCfg_WIRE_7[0]; // @[CSR.scala:1491:73] assign newCfg_7_r = _newCfg_T_50; // @[CSR.scala:1491:73] assign _newCfg_T_51 = _newCfg_WIRE_7[1]; // @[CSR.scala:1491:73] assign newCfg_7_w = _newCfg_T_51; // @[CSR.scala:1491:73] assign _newCfg_T_52 = _newCfg_WIRE_7[2]; // @[CSR.scala:1491:73] assign newCfg_7_x = _newCfg_T_52; // @[CSR.scala:1491:73] assign _newCfg_T_53 = _newCfg_WIRE_7[4:3]; // @[CSR.scala:1491:73] assign newCfg_7_a = _newCfg_T_53; // @[CSR.scala:1491:73] assign _newCfg_T_54 = _newCfg_WIRE_7[6:5]; // @[CSR.scala:1491:73] assign newCfg_7_res = _newCfg_T_54; // @[CSR.scala:1491:73] assign _newCfg_T_55 = _newCfg_WIRE_7[7]; // @[CSR.scala:1491:73] assign newCfg_7_l = _newCfg_T_55; // @[CSR.scala:1491:73] wire _reg_pmp_7_cfg_w_T = newCfg_7_w & newCfg_7_r; // @[CSR.scala:1491:73, :1494:31] wire [63:0] _reg_custom_0_T = wdata & 64'h208; // @[CSR.scala:1506:23, :1643:39] wire [63:0] _GEN_22 = reg_custom_0 & 64'hFFFFFFFFFFFFFDF7; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_0_T_2; // @[CSR.scala:1506:38] assign _reg_custom_0_T_2 = _GEN_22; // @[CSR.scala:1506:38] wire [63:0] _reg_custom_0_T_6; // @[CSR.scala:1531:39] assign _reg_custom_0_T_6 = _GEN_22; // @[CSR.scala:1506:38, :1531:39] wire [63:0] _reg_custom_0_T_3 = _reg_custom_0_T | _reg_custom_0_T_2; // @[CSR.scala:1506:{23,31,38}] assign io_customCSRs_0_wen_0 = csr_wen & decoded_addr_19_2; // @[CSR.scala:377:7, :855:93, :1166:12, :1222:56, :1224:18, :1505:35] wire [63:0] _reg_custom_1_T_3 = _reg_custom_1_T_2; // @[CSR.scala:1506:{31,38}] assign io_customCSRs_1_wen_0 = csr_wen & decoded_addr_3_2; // @[CSR.scala:377:7, :855:93, :1166:12, :1222:56, :1224:18, :1505:35] wire [63:0] _reg_custom_2_T_3 = _reg_custom_2_T_2; // @[CSR.scala:1506:{31,38}] assign io_customCSRs_2_wen_0 = csr_wen & decoded_addr_39_2; // @[CSR.scala:377:7, :855:93, :1166:12, :1222:56, :1224:18, :1505:35] wire [63:0] _reg_custom_3_T_3 = _reg_custom_3_T_2; // @[CSR.scala:1506:{31,38}] assign io_customCSRs_3_wen_0 = csr_wen & decoded_addr_132_2; // @[CSR.scala:377:7, :855:93, :1166:12, :1222:56, :1224:18, :1505:35] wire [62:0] _reg_vxrm_T = wdata[63:1]; // @[CSR.scala:1523:31, :1643:39] wire [63:0] _reg_custom_0_T_7 = _reg_custom_0_T_6; // @[CSR.scala:1531:{32,39}] wire [63:0] _reg_custom_1_T_7 = _reg_custom_1_T_6; // @[CSR.scala:1531:{32,39}] wire [63:0] _reg_custom_2_T_7 = _reg_custom_2_T_6; // @[CSR.scala:1531:{32,39}] wire [63:0] _reg_custom_3_T_7 = _reg_custom_3_T_6; // @[CSR.scala:1531:{32,39}]
Generate the Verilog code corresponding to the following Chisel files. File fetch-target-queue.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Fetch Target Queue (FTQ) //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // Each entry in the FTQ holds the fetch address and branch prediction snapshot state. // // TODO: // * reduce port counts. package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util.{Str} import boom.v3.common._ import boom.v3.exu._ import boom.v3.util._ /** * FTQ Parameters used in configurations * * @param nEntries # of entries in the FTQ */ case class FtqParameters( nEntries: Int = 16 ) /** * Bundle to add to the FTQ RAM and to be used as the pass in IO */ class FTQBundle(implicit p: Parameters) extends BoomBundle with HasBoomFrontendParameters { // // TODO compress out high-order bits // val fetch_pc = UInt(vaddrBitsExtended.W) // IDX of instruction that was predicted taken, if any val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W)) // Was the CFI in this bundle found to be taken? or not val cfi_taken = Bool() // Was this CFI mispredicted by the branch prediction pipeline? val cfi_mispredicted = Bool() // What type of CFI was taken out of this bundle val cfi_type = UInt(CFI_SZ.W) // mask of branches which were visible in this fetch bundle val br_mask = UInt(fetchWidth.W) // This CFI is likely a CALL val cfi_is_call = Bool() // This CFI is likely a RET val cfi_is_ret = Bool() // Is the NPC after the CFI +4 or +2 val cfi_npc_plus4 = Bool() // What was the top of the RAS that this bundle saw? val ras_top = UInt(vaddrBitsExtended.W) val ras_idx = UInt(log2Ceil(nRasEntries).W) // Which bank did this start from? val start_bank = UInt(1.W) // // Metadata for the branch predictor // val bpd_meta = Vec(nBanks, UInt(bpdMaxMetaLength.W)) } /** * IO to provide a port for a FunctionalUnit to get the PC of an instruction. * And for JALRs, the PC of the next instruction. */ class GetPCFromFtqIO(implicit p: Parameters) extends BoomBundle { val ftq_idx = Input(UInt(log2Ceil(ftqSz).W)) val entry = Output(new FTQBundle) val ghist = Output(new GlobalHistory) val pc = Output(UInt(vaddrBitsExtended.W)) val com_pc = Output(UInt(vaddrBitsExtended.W)) // the next_pc may not be valid (stalled or still being fetched) val next_val = Output(Bool()) val next_pc = Output(UInt(vaddrBitsExtended.W)) } /** * Queue to store the fetch PC and other relevant branch predictor signals that are inflight in the * processor. * * @param num_entries # of entries in the FTQ */ class FetchTargetQueue(implicit p: Parameters) extends BoomModule with HasBoomCoreParameters with HasBoomFrontendParameters { val num_entries = ftqSz private val idx_sz = log2Ceil(num_entries) val io = IO(new BoomBundle { // Enqueue one entry for every fetch cycle. val enq = Flipped(Decoupled(new FetchBundle())) // Pass to FetchBuffer (newly fetched instructions). val enq_idx = Output(UInt(idx_sz.W)) // ROB tells us the youngest committed ftq_idx to remove from FTQ. val deq = Flipped(Valid(UInt(idx_sz.W))) // Give PC info to BranchUnit. val get_ftq_pc = Vec(2, new GetPCFromFtqIO()) // Used to regenerate PC for trace port stuff in FireSim // Don't tape this out, this blows up the FTQ val debug_ftq_idx = Input(Vec(coreWidth, UInt(log2Ceil(ftqSz).W))) val debug_fetch_pc = Output(Vec(coreWidth, UInt(vaddrBitsExtended.W))) val redirect = Input(Valid(UInt(idx_sz.W))) val brupdate = Input(new BrUpdateInfo) val bpdupdate = Output(Valid(new BranchPredictionUpdate)) val ras_update = Output(Bool()) val ras_update_idx = Output(UInt(log2Ceil(nRasEntries).W)) val ras_update_pc = Output(UInt(vaddrBitsExtended.W)) }) val bpd_ptr = RegInit(0.U(idx_sz.W)) val deq_ptr = RegInit(0.U(idx_sz.W)) val enq_ptr = RegInit(1.U(idx_sz.W)) val full = ((WrapInc(WrapInc(enq_ptr, num_entries), num_entries) === bpd_ptr) || (WrapInc(enq_ptr, num_entries) === bpd_ptr)) val pcs = Reg(Vec(num_entries, UInt(vaddrBitsExtended.W))) val meta = SyncReadMem(num_entries, Vec(nBanks, UInt(bpdMaxMetaLength.W))) val ram = Reg(Vec(num_entries, new FTQBundle)) val ghist = Seq.fill(2) { SyncReadMem(num_entries, new GlobalHistory) } val lhist = if (useLHist) { Some(SyncReadMem(num_entries, Vec(nBanks, UInt(localHistoryLength.W)))) } else { None } val do_enq = io.enq.fire // This register lets us initialize the ghist to 0 val prev_ghist = RegInit((0.U).asTypeOf(new GlobalHistory)) val prev_entry = RegInit((0.U).asTypeOf(new FTQBundle)) val prev_pc = RegInit(0.U(vaddrBitsExtended.W)) when (do_enq) { pcs(enq_ptr) := io.enq.bits.pc val new_entry = Wire(new FTQBundle) new_entry.cfi_idx := io.enq.bits.cfi_idx // Initially, if we see a CFI, it is assumed to be taken. // Branch resolutions may change this new_entry.cfi_taken := io.enq.bits.cfi_idx.valid new_entry.cfi_mispredicted := false.B new_entry.cfi_type := io.enq.bits.cfi_type new_entry.cfi_is_call := io.enq.bits.cfi_is_call new_entry.cfi_is_ret := io.enq.bits.cfi_is_ret new_entry.cfi_npc_plus4 := io.enq.bits.cfi_npc_plus4 new_entry.ras_top := io.enq.bits.ras_top new_entry.ras_idx := io.enq.bits.ghist.ras_idx new_entry.br_mask := io.enq.bits.br_mask & io.enq.bits.mask new_entry.start_bank := bank(io.enq.bits.pc) val new_ghist = Mux(io.enq.bits.ghist.current_saw_branch_not_taken, io.enq.bits.ghist, prev_ghist.update( prev_entry.br_mask, prev_entry.cfi_taken, prev_entry.br_mask(prev_entry.cfi_idx.bits), prev_entry.cfi_idx.bits, prev_entry.cfi_idx.valid, prev_pc, prev_entry.cfi_is_call, prev_entry.cfi_is_ret ) ) lhist.map( l => l.write(enq_ptr, io.enq.bits.lhist)) ghist.map( g => g.write(enq_ptr, new_ghist)) meta.write(enq_ptr, io.enq.bits.bpd_meta) ram(enq_ptr) := new_entry prev_pc := io.enq.bits.pc prev_entry := new_entry prev_ghist := new_ghist enq_ptr := WrapInc(enq_ptr, num_entries) } io.enq_idx := enq_ptr io.bpdupdate.valid := false.B io.bpdupdate.bits := DontCare when (io.deq.valid) { deq_ptr := io.deq.bits } // This register avoids a spurious bpd update on the first fetch packet val first_empty = RegInit(true.B) // We can update the branch predictors when we know the target of the // CFI in this fetch bundle val ras_update = WireInit(false.B) val ras_update_pc = WireInit(0.U(vaddrBitsExtended.W)) val ras_update_idx = WireInit(0.U(log2Ceil(nRasEntries).W)) io.ras_update := RegNext(ras_update) io.ras_update_pc := RegNext(ras_update_pc) io.ras_update_idx := RegNext(ras_update_idx) val bpd_update_mispredict = RegInit(false.B) val bpd_update_repair = RegInit(false.B) val bpd_repair_idx = Reg(UInt(log2Ceil(ftqSz).W)) val bpd_end_idx = Reg(UInt(log2Ceil(ftqSz).W)) val bpd_repair_pc = Reg(UInt(vaddrBitsExtended.W)) val bpd_idx = Mux(io.redirect.valid, io.redirect.bits, Mux(bpd_update_repair || bpd_update_mispredict, bpd_repair_idx, bpd_ptr)) val bpd_entry = RegNext(ram(bpd_idx)) val bpd_ghist = ghist(0).read(bpd_idx, true.B) val bpd_lhist = if (useLHist) { lhist.get.read(bpd_idx, true.B) } else { VecInit(Seq.fill(nBanks) { 0.U }) } val bpd_meta = meta.read(bpd_idx, true.B) // TODO fix these SRAMs val bpd_pc = RegNext(pcs(bpd_idx)) val bpd_target = RegNext(pcs(WrapInc(bpd_idx, num_entries))) when (io.redirect.valid) { bpd_update_mispredict := false.B bpd_update_repair := false.B } .elsewhen (RegNext(io.brupdate.b2.mispredict)) { bpd_update_mispredict := true.B bpd_repair_idx := RegNext(io.brupdate.b2.uop.ftq_idx) bpd_end_idx := RegNext(enq_ptr) } .elsewhen (bpd_update_mispredict) { bpd_update_mispredict := false.B bpd_update_repair := true.B bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries) } .elsewhen (bpd_update_repair && RegNext(bpd_update_mispredict)) { bpd_repair_pc := bpd_pc bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries) } .elsewhen (bpd_update_repair) { bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries) when (WrapInc(bpd_repair_idx, num_entries) === bpd_end_idx || bpd_pc === bpd_repair_pc) { bpd_update_repair := false.B } } val do_commit_update = (!bpd_update_mispredict && !bpd_update_repair && bpd_ptr =/= deq_ptr && enq_ptr =/= WrapInc(bpd_ptr, num_entries) && !io.brupdate.b2.mispredict && !io.redirect.valid && !RegNext(io.redirect.valid)) val do_mispredict_update = bpd_update_mispredict val do_repair_update = bpd_update_repair when (RegNext(do_commit_update || do_repair_update || do_mispredict_update)) { val cfi_idx = bpd_entry.cfi_idx.bits val valid_repair = bpd_pc =/= bpd_repair_pc io.bpdupdate.valid := (!first_empty && (bpd_entry.cfi_idx.valid || bpd_entry.br_mask =/= 0.U) && !(RegNext(do_repair_update) && !valid_repair)) io.bpdupdate.bits.is_mispredict_update := RegNext(do_mispredict_update) io.bpdupdate.bits.is_repair_update := RegNext(do_repair_update) io.bpdupdate.bits.pc := bpd_pc io.bpdupdate.bits.btb_mispredicts := 0.U io.bpdupdate.bits.br_mask := Mux(bpd_entry.cfi_idx.valid, MaskLower(UIntToOH(cfi_idx)) & bpd_entry.br_mask, bpd_entry.br_mask) io.bpdupdate.bits.cfi_idx := bpd_entry.cfi_idx io.bpdupdate.bits.cfi_mispredicted := bpd_entry.cfi_mispredicted io.bpdupdate.bits.cfi_taken := bpd_entry.cfi_taken io.bpdupdate.bits.target := bpd_target io.bpdupdate.bits.cfi_is_br := bpd_entry.br_mask(cfi_idx) io.bpdupdate.bits.cfi_is_jal := bpd_entry.cfi_type === CFI_JAL || bpd_entry.cfi_type === CFI_JALR io.bpdupdate.bits.ghist := bpd_ghist io.bpdupdate.bits.lhist := bpd_lhist io.bpdupdate.bits.meta := bpd_meta first_empty := false.B } when (do_commit_update) { bpd_ptr := WrapInc(bpd_ptr, num_entries) } io.enq.ready := RegNext(!full || do_commit_update) val redirect_idx = io.redirect.bits val redirect_entry = ram(redirect_idx) val redirect_new_entry = WireInit(redirect_entry) when (io.redirect.valid) { enq_ptr := WrapInc(io.redirect.bits, num_entries) when (io.brupdate.b2.mispredict) { val new_cfi_idx = (io.brupdate.b2.uop.pc_lob ^ Mux(redirect_entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U))(log2Ceil(fetchWidth), 1) redirect_new_entry.cfi_idx.valid := true.B redirect_new_entry.cfi_idx.bits := new_cfi_idx redirect_new_entry.cfi_mispredicted := true.B redirect_new_entry.cfi_taken := io.brupdate.b2.taken redirect_new_entry.cfi_is_call := redirect_entry.cfi_is_call && redirect_entry.cfi_idx.bits === new_cfi_idx redirect_new_entry.cfi_is_ret := redirect_entry.cfi_is_ret && redirect_entry.cfi_idx.bits === new_cfi_idx } ras_update := true.B ras_update_pc := redirect_entry.ras_top ras_update_idx := redirect_entry.ras_idx } .elsewhen (RegNext(io.redirect.valid)) { prev_entry := RegNext(redirect_new_entry) prev_ghist := bpd_ghist prev_pc := bpd_pc ram(RegNext(io.redirect.bits)) := RegNext(redirect_new_entry) } //------------------------------------------------------------- // **** Core Read PCs **** //------------------------------------------------------------- for (i <- 0 until 2) { val idx = io.get_ftq_pc(i).ftq_idx val next_idx = WrapInc(idx, num_entries) val next_is_enq = (next_idx === enq_ptr) && io.enq.fire val next_pc = Mux(next_is_enq, io.enq.bits.pc, pcs(next_idx)) val get_entry = ram(idx) val next_entry = ram(next_idx) io.get_ftq_pc(i).entry := RegNext(get_entry) if (i == 1) io.get_ftq_pc(i).ghist := ghist(1).read(idx, true.B) else io.get_ftq_pc(i).ghist := DontCare io.get_ftq_pc(i).pc := RegNext(pcs(idx)) io.get_ftq_pc(i).next_pc := RegNext(next_pc) io.get_ftq_pc(i).next_val := RegNext(next_idx =/= enq_ptr || next_is_enq) io.get_ftq_pc(i).com_pc := RegNext(pcs(Mux(io.deq.valid, io.deq.bits, deq_ptr))) } for (w <- 0 until coreWidth) { io.debug_fetch_pc(w) := RegNext(pcs(io.debug_ftq_idx(w))) } }
module ghist_1( // @[fetch-target-queue.scala:144:43] input [4:0] R0_addr, input R0_clk, output [71:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [71:0] W0_data ); ghist_0_ext ghist_0_ext ( // @[fetch-target-queue.scala:144:43] .R0_addr (R0_addr), .R0_en (1'h1), // @[fetch-target-queue.scala:144:43] .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[fetch-target-queue.scala:144:43] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_157( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_174 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File FunctionalUnit.scala: package saturn.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ import saturn.insns.{VectorInstruction} abstract class FunctionalUnitIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val iss = new Bundle { val valid = Input(Bool()) val op = Input(new ExecuteMicroOp) val ready = Output(Bool()) } val scalar_write = Decoupled(new ScalarWrite) val set_vxsat = Output(Bool()) val set_fflags = Output(Valid(UInt(5.W))) } class PipelinedFunctionalUnitIO(depth: Int)(implicit p: Parameters) extends FunctionalUnitIO { val write = Valid(new VectorWrite(dLen)) val pipe = Input(Vec(depth, Valid(new ExecuteMicroOp))) val pipe0_stall = Output(Bool()) } class IterativeFunctionalUnitIO(implicit p: Parameters) extends FunctionalUnitIO { val write = Decoupled(new VectorWrite(dLen)) val hazard = Output(Valid(new PipeHazard(10))) val acc = Output(Bool()) val tail = Output(Bool()) val busy = Output(Bool()) } trait FunctionalUnitFactory { def insns: Seq[VectorInstruction] def generate(implicit p: Parameters): FunctionalUnit } abstract class FunctionalUnit(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io: FunctionalUnitIO } abstract class PipelinedFunctionalUnit(val depth: Int)(implicit p: Parameters) extends FunctionalUnit()(p) { val io = IO(new PipelinedFunctionalUnitIO(depth)) require (depth > 0) def narrow2_expand(bits: Seq[UInt], eew: UInt, upper: Bool, sext: Bool): Vec[UInt] = { val narrow_eew = (0 until 3).map { eew => Wire(Vec(dLenB >> (eew + 1), UInt((16 << eew).W))) } for (eew <- 0 until 3) { val in_vec = bits.grouped(1 << eew).map(g => VecInit(g).asUInt).toSeq for (i <- 0 until dLenB >> (eew + 1)) { val lo = Mux(upper, in_vec(i + (dLenB >> (eew + 1))), in_vec(i)) val hi = Fill(16 << eew, lo((8 << eew)-1) && sext) narrow_eew(eew)(i) := Cat(hi, lo) } } VecInit(narrow_eew.map(_.asUInt))(eew).asTypeOf(Vec(dLenB, UInt(8.W))) } } abstract class IterativeFunctionalUnit(implicit p: Parameters) extends FunctionalUnit()(p) { val io = IO(new IterativeFunctionalUnitIO) val valid = RegInit(false.B) val op = Reg(new ExecuteMicroOp) val last = Wire(Bool()) io.busy := valid io.hazard.bits.latency := DontCare when (io.iss.valid && io.iss.ready) { valid := true.B op := io.iss.op } .elsewhen (last) { valid := false.B } } File MaskUnit.scala: package saturn.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ import saturn.insns._ case object MaskUnitFactory extends FunctionalUnitFactory { def insns = Seq(MV_S_X, MV_X_S, POPC, FIRST, FMV_S_F, FMV_F_S, MSBF, MSOF, MSIF, IOTA, ID) def generate(implicit p: Parameters) = new MaskUnit()(p) } class MaskUnit(implicit p: Parameters) extends PipelinedFunctionalUnit(1)(p) { val supported_insns = MaskUnitFactory.insns val scalar_wb_busy = RegInit(false.B) val scalar_wb_data = Reg(UInt(64.W)) val scalar_wb_rd = Reg(UInt(5.W)) val scalar_wb_fp = Reg(Bool()) val scalar_wb_size = Reg(UInt(2.W)) val found_first = Reg(Bool()) def accepts(op: ExecuteMicroOp): Bool = (op.opff6.isOneOf(OPFFunct6.wrfunary0) || op.opmf6.isOneOf(OPMFunct6.wrxunary0, OPMFunct6.munary0)) && !scalar_wb_busy io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, io.iss.op.rs1, io.iss.op.rs2, supported_insns, Nil).matched && !scalar_wb_busy && !io.pipe(0).bits.tail io.set_vxsat := false.B io.set_fflags.valid := false.B io.set_fflags.bits := DontCare val op = io.pipe(0).bits val opmvv = op.funct3 === OPMVV val opmvx = op.funct3 === OPMVX val opfvv = op.funct3 === OPFVV val opfvf = op.funct3 === OPFVF val wxunary0 = opmvv && !op.funct6(2) val rxunary0 = opmvx val wfunary0 = opfvv val rfunary0 = opfvf val munary0 = opmvv && op.funct6(2) val set_before = op.rs1.isOneOf(1.U, 3.U) val set_first = op.rs1.isOneOf(2.U, 3.U) val elems = (op.rvs2_data & op.rvm_data & op.full_tail_mask) val popc = PopCount(elems) val ff = PriorityEncoder(elems) val ff_oh = PriorityEncoderOH(elems) val bf = ~((0 until dLen).map { i => (elems << i)(dLen-1,0) }.reduce(_|_)) val nonzero = elems =/= 0.U val first_here = (!found_first || op.head) && nonzero val before = Mux(found_first && !op.head, 0.U, Mux(nonzero, bf, ~(0.U(dLen.W)))) val first = Mux(first_here, ff_oh, 0.U) val set = Mux(set_before, before, 0.U) | Mux(set_first, first, 0.U) val sign = VecInit.tabulate(4)({sew => op.rvs2_data((8 << sew)-1)})(op.rvs2_eew) val eew_mask = eewBitMask(op.rvs2_eew).pad(64) val elem = (op.rvs2_data & eew_mask) | (Fill(64, sign && op.isOpm) & ~eew_mask) val scalar_wb_rdata = Mux(op.head, 0.U, scalar_wb_data) val iota_dlenb = VecInit.tabulate(4)({sew => val grouped = Mux(op.rs1(0), ~(0.U(dLen.W)), elems).asTypeOf(Vec(8 << sew, UInt((dLenB >> sew).W))) grouped(op.eidx(log2Ceil(dLen)-1,log2Ceil(dLenB) - sew)) })(op.rvd_eew) val iota_sums = (0 until dLenB).map { i => (PopCount(iota_dlenb & ((1<<i)-1).U) +& scalar_wb_rdata)(log2Ceil(maxVLMax),0) } val iota_out = VecInit.tabulate(4)({sew => val out = Wire(Vec(dLenB >> sew, UInt((8<<sew).W))) out := iota_sums.take(dLenB >> sew) out.asUInt })(op.vd_eew) when (io.pipe(0).valid) { scalar_wb_rd := io.pipe(0).bits.rd scalar_wb_size := io.pipe(0).bits.rvs2_eew when (op.head) { found_first := false.B scalar_wb_data := 0.U } when (first_here) { found_first := true.B } when (wxunary0) { when (op.rs1 === 16.U) { // popc scalar_wb_data := (scalar_wb_rdata + popc)(log2Ceil(maxVLMax),0) } .elsewhen (op.rs1 === 17.U) { // first when (first_here) { scalar_wb_data := op.eidx + ff } .elsewhen (!found_first || op.head) { scalar_wb_data := ~(0.U(64.W)) } } .otherwise { // mv scalar_wb_data := elem } } when (wfunary0) { // fmv scalar_wb_data := elem } when (munary0) { val mask = VecInit.tabulate(4)({sew => ~(0.U((dLenB >> sew).W))})(op.vd_eew) val incr = PopCount(iota_dlenb & mask) scalar_wb_data := (scalar_wb_rdata + incr)(log2Ceil(maxVLMax),0) } when (op.tail) { scalar_wb_busy := wxunary0 || wfunary0 scalar_wb_fp := wfunary0 } } io.scalar_write.valid := scalar_wb_busy io.scalar_write.bits.data := scalar_wb_data io.scalar_write.bits.rd := scalar_wb_rd io.scalar_write.bits.fp := scalar_wb_fp io.scalar_write.bits.size := scalar_wb_size io.pipe0_stall := false.B io.write.valid := io.pipe(0).valid && (rxunary0 || rfunary0 || munary0) io.write.bits.eg := op.wvd_eg io.write.bits.mask := Mux1H(Seq( (rxunary0 || rfunary0 , eewBitMask(op.vd_eew)), (munary0 && op.rs1(4) , FillInterleaved(8, op.wmask)), (munary0 && !op.rs1(4), op.full_tail_mask & op.rvm_data) )) io.write.bits.data := Mux1H(Seq( (rxunary0 || rfunary0 , op.rvs1_data(63,0)), (munary0 && op.rs1(4) , iota_out), (munary0 && !op.rs1(4), set) )) when (io.scalar_write.fire) { scalar_wb_busy := false.B } }
module MaskUnit( // @[MaskUnit.scala:17:7] input clock, // @[MaskUnit.scala:17:7] input reset, // @[MaskUnit.scala:17:7] input [2:0] io_iss_op_funct3, // @[FunctionalUnit.scala:49:14] input [5:0] io_iss_op_funct6, // @[FunctionalUnit.scala:49:14] input [4:0] io_iss_op_rs1, // @[FunctionalUnit.scala:49:14] input [4:0] io_iss_op_rs2, // @[FunctionalUnit.scala:49:14] output io_iss_ready, // @[FunctionalUnit.scala:49:14] input io_scalar_write_ready, // @[FunctionalUnit.scala:49:14] output io_scalar_write_valid, // @[FunctionalUnit.scala:49:14] output [63:0] io_scalar_write_bits_data, // @[FunctionalUnit.scala:49:14] output io_scalar_write_bits_fp, // @[FunctionalUnit.scala:49:14] output [1:0] io_scalar_write_bits_size, // @[FunctionalUnit.scala:49:14] output [4:0] io_scalar_write_bits_rd, // @[FunctionalUnit.scala:49:14] output io_write_valid, // @[FunctionalUnit.scala:49:14] output [6:0] io_write_bits_eg, // @[FunctionalUnit.scala:49:14] output [63:0] io_write_bits_data, // @[FunctionalUnit.scala:49:14] output [63:0] io_write_bits_mask, // @[FunctionalUnit.scala:49:14] input io_pipe_0_valid, // @[FunctionalUnit.scala:49:14] input [7:0] io_pipe_0_bits_eidx, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_rvs1_data, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_rvs2_data, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_rvm_data, // @[FunctionalUnit.scala:49:14] input [1:0] io_pipe_0_bits_rvs2_eew, // @[FunctionalUnit.scala:49:14] input [1:0] io_pipe_0_bits_rvd_eew, // @[FunctionalUnit.scala:49:14] input [1:0] io_pipe_0_bits_vd_eew, // @[FunctionalUnit.scala:49:14] input [7:0] io_pipe_0_bits_wmask, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_full_tail_mask, // @[FunctionalUnit.scala:49:14] input [6:0] io_pipe_0_bits_wvd_eg, // @[FunctionalUnit.scala:49:14] input [2:0] io_pipe_0_bits_funct3, // @[FunctionalUnit.scala:49:14] input [5:0] io_pipe_0_bits_funct6, // @[FunctionalUnit.scala:49:14] input [4:0] io_pipe_0_bits_rs1, // @[FunctionalUnit.scala:49:14] input [4:0] io_pipe_0_bits_rd, // @[FunctionalUnit.scala:49:14] input io_pipe_0_bits_head, // @[FunctionalUnit.scala:49:14] input io_pipe_0_bits_tail // @[FunctionalUnit.scala:49:14] ); reg scalar_wb_busy; // @[MaskUnit.scala:20:31] reg [63:0] scalar_wb_data; // @[MaskUnit.scala:21:27] reg [4:0] scalar_wb_rd; // @[MaskUnit.scala:22:25] reg scalar_wb_fp; // @[MaskUnit.scala:23:25] reg [1:0] scalar_wb_size; // @[MaskUnit.scala:24:27] reg found_first; // @[MaskUnit.scala:25:24] wire [18:0] io_iss_ready_decode_invInputs = ~{io_iss_op_rs1, io_iss_op_rs2, io_iss_op_funct3, io_iss_op_funct6}; // @[pla.scala:78:21] wire opmvv = io_pipe_0_bits_funct3 == 3'h2; // @[MaskUnit.scala:36:25] wire opmvx = io_pipe_0_bits_funct3 == 3'h6; // @[MaskUnit.scala:37:25] wire munary0 = opmvv & io_pipe_0_bits_funct6[2]; // @[MaskUnit.scala:36:25, :41:37, :45:24] wire _set_first_T_1 = io_pipe_0_bits_rs1 == 5'h3; // @[package.scala:16:47] wire [63:0] elems = io_pipe_0_bits_rvs2_data & io_pipe_0_bits_rvm_data & io_pipe_0_bits_full_tail_mask; // @[MaskUnit.scala:50:{29,43}] wire _ff_oh_T = io_pipe_0_bits_rvs2_data[0] & io_pipe_0_bits_rvm_data[0] & io_pipe_0_bits_full_tail_mask[0]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_1 = io_pipe_0_bits_rvs2_data[1] & io_pipe_0_bits_rvm_data[1] & io_pipe_0_bits_full_tail_mask[1]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_2 = io_pipe_0_bits_rvs2_data[2] & io_pipe_0_bits_rvm_data[2] & io_pipe_0_bits_full_tail_mask[2]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_3 = io_pipe_0_bits_rvs2_data[3] & io_pipe_0_bits_rvm_data[3] & io_pipe_0_bits_full_tail_mask[3]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_4 = io_pipe_0_bits_rvs2_data[4] & io_pipe_0_bits_rvm_data[4] & io_pipe_0_bits_full_tail_mask[4]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_5 = io_pipe_0_bits_rvs2_data[5] & io_pipe_0_bits_rvm_data[5] & io_pipe_0_bits_full_tail_mask[5]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_6 = io_pipe_0_bits_rvs2_data[6] & io_pipe_0_bits_rvm_data[6] & io_pipe_0_bits_full_tail_mask[6]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_7 = io_pipe_0_bits_rvs2_data[7] & io_pipe_0_bits_rvm_data[7] & io_pipe_0_bits_full_tail_mask[7]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_8 = io_pipe_0_bits_rvs2_data[8] & io_pipe_0_bits_rvm_data[8] & io_pipe_0_bits_full_tail_mask[8]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_9 = io_pipe_0_bits_rvs2_data[9] & io_pipe_0_bits_rvm_data[9] & io_pipe_0_bits_full_tail_mask[9]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_10 = io_pipe_0_bits_rvs2_data[10] & io_pipe_0_bits_rvm_data[10] & io_pipe_0_bits_full_tail_mask[10]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_11 = io_pipe_0_bits_rvs2_data[11] & io_pipe_0_bits_rvm_data[11] & io_pipe_0_bits_full_tail_mask[11]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_12 = io_pipe_0_bits_rvs2_data[12] & io_pipe_0_bits_rvm_data[12] & io_pipe_0_bits_full_tail_mask[12]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_13 = io_pipe_0_bits_rvs2_data[13] & io_pipe_0_bits_rvm_data[13] & io_pipe_0_bits_full_tail_mask[13]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_14 = io_pipe_0_bits_rvs2_data[14] & io_pipe_0_bits_rvm_data[14] & io_pipe_0_bits_full_tail_mask[14]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_15 = io_pipe_0_bits_rvs2_data[15] & io_pipe_0_bits_rvm_data[15] & io_pipe_0_bits_full_tail_mask[15]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_16 = io_pipe_0_bits_rvs2_data[16] & io_pipe_0_bits_rvm_data[16] & io_pipe_0_bits_full_tail_mask[16]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_17 = io_pipe_0_bits_rvs2_data[17] & io_pipe_0_bits_rvm_data[17] & io_pipe_0_bits_full_tail_mask[17]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_18 = io_pipe_0_bits_rvs2_data[18] & io_pipe_0_bits_rvm_data[18] & io_pipe_0_bits_full_tail_mask[18]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_19 = io_pipe_0_bits_rvs2_data[19] & io_pipe_0_bits_rvm_data[19] & io_pipe_0_bits_full_tail_mask[19]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_20 = io_pipe_0_bits_rvs2_data[20] & io_pipe_0_bits_rvm_data[20] & io_pipe_0_bits_full_tail_mask[20]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_21 = io_pipe_0_bits_rvs2_data[21] & io_pipe_0_bits_rvm_data[21] & io_pipe_0_bits_full_tail_mask[21]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_22 = io_pipe_0_bits_rvs2_data[22] & io_pipe_0_bits_rvm_data[22] & io_pipe_0_bits_full_tail_mask[22]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_23 = io_pipe_0_bits_rvs2_data[23] & io_pipe_0_bits_rvm_data[23] & io_pipe_0_bits_full_tail_mask[23]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_24 = io_pipe_0_bits_rvs2_data[24] & io_pipe_0_bits_rvm_data[24] & io_pipe_0_bits_full_tail_mask[24]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_25 = io_pipe_0_bits_rvs2_data[25] & io_pipe_0_bits_rvm_data[25] & io_pipe_0_bits_full_tail_mask[25]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_26 = io_pipe_0_bits_rvs2_data[26] & io_pipe_0_bits_rvm_data[26] & io_pipe_0_bits_full_tail_mask[26]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_27 = io_pipe_0_bits_rvs2_data[27] & io_pipe_0_bits_rvm_data[27] & io_pipe_0_bits_full_tail_mask[27]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_28 = io_pipe_0_bits_rvs2_data[28] & io_pipe_0_bits_rvm_data[28] & io_pipe_0_bits_full_tail_mask[28]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_29 = io_pipe_0_bits_rvs2_data[29] & io_pipe_0_bits_rvm_data[29] & io_pipe_0_bits_full_tail_mask[29]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_30 = io_pipe_0_bits_rvs2_data[30] & io_pipe_0_bits_rvm_data[30] & io_pipe_0_bits_full_tail_mask[30]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_31 = io_pipe_0_bits_rvs2_data[31] & io_pipe_0_bits_rvm_data[31] & io_pipe_0_bits_full_tail_mask[31]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_32 = io_pipe_0_bits_rvs2_data[32] & io_pipe_0_bits_rvm_data[32] & io_pipe_0_bits_full_tail_mask[32]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_33 = io_pipe_0_bits_rvs2_data[33] & io_pipe_0_bits_rvm_data[33] & io_pipe_0_bits_full_tail_mask[33]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_34 = io_pipe_0_bits_rvs2_data[34] & io_pipe_0_bits_rvm_data[34] & io_pipe_0_bits_full_tail_mask[34]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_35 = io_pipe_0_bits_rvs2_data[35] & io_pipe_0_bits_rvm_data[35] & io_pipe_0_bits_full_tail_mask[35]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_36 = io_pipe_0_bits_rvs2_data[36] & io_pipe_0_bits_rvm_data[36] & io_pipe_0_bits_full_tail_mask[36]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_37 = io_pipe_0_bits_rvs2_data[37] & io_pipe_0_bits_rvm_data[37] & io_pipe_0_bits_full_tail_mask[37]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_38 = io_pipe_0_bits_rvs2_data[38] & io_pipe_0_bits_rvm_data[38] & io_pipe_0_bits_full_tail_mask[38]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_39 = io_pipe_0_bits_rvs2_data[39] & io_pipe_0_bits_rvm_data[39] & io_pipe_0_bits_full_tail_mask[39]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_40 = io_pipe_0_bits_rvs2_data[40] & io_pipe_0_bits_rvm_data[40] & io_pipe_0_bits_full_tail_mask[40]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_41 = io_pipe_0_bits_rvs2_data[41] & io_pipe_0_bits_rvm_data[41] & io_pipe_0_bits_full_tail_mask[41]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_42 = io_pipe_0_bits_rvs2_data[42] & io_pipe_0_bits_rvm_data[42] & io_pipe_0_bits_full_tail_mask[42]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_43 = io_pipe_0_bits_rvs2_data[43] & io_pipe_0_bits_rvm_data[43] & io_pipe_0_bits_full_tail_mask[43]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_44 = io_pipe_0_bits_rvs2_data[44] & io_pipe_0_bits_rvm_data[44] & io_pipe_0_bits_full_tail_mask[44]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_45 = io_pipe_0_bits_rvs2_data[45] & io_pipe_0_bits_rvm_data[45] & io_pipe_0_bits_full_tail_mask[45]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_46 = io_pipe_0_bits_rvs2_data[46] & io_pipe_0_bits_rvm_data[46] & io_pipe_0_bits_full_tail_mask[46]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_47 = io_pipe_0_bits_rvs2_data[47] & io_pipe_0_bits_rvm_data[47] & io_pipe_0_bits_full_tail_mask[47]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_48 = io_pipe_0_bits_rvs2_data[48] & io_pipe_0_bits_rvm_data[48] & io_pipe_0_bits_full_tail_mask[48]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_49 = io_pipe_0_bits_rvs2_data[49] & io_pipe_0_bits_rvm_data[49] & io_pipe_0_bits_full_tail_mask[49]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_50 = io_pipe_0_bits_rvs2_data[50] & io_pipe_0_bits_rvm_data[50] & io_pipe_0_bits_full_tail_mask[50]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_51 = io_pipe_0_bits_rvs2_data[51] & io_pipe_0_bits_rvm_data[51] & io_pipe_0_bits_full_tail_mask[51]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_52 = io_pipe_0_bits_rvs2_data[52] & io_pipe_0_bits_rvm_data[52] & io_pipe_0_bits_full_tail_mask[52]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_53 = io_pipe_0_bits_rvs2_data[53] & io_pipe_0_bits_rvm_data[53] & io_pipe_0_bits_full_tail_mask[53]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_54 = io_pipe_0_bits_rvs2_data[54] & io_pipe_0_bits_rvm_data[54] & io_pipe_0_bits_full_tail_mask[54]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_55 = io_pipe_0_bits_rvs2_data[55] & io_pipe_0_bits_rvm_data[55] & io_pipe_0_bits_full_tail_mask[55]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_56 = io_pipe_0_bits_rvs2_data[56] & io_pipe_0_bits_rvm_data[56] & io_pipe_0_bits_full_tail_mask[56]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_57 = io_pipe_0_bits_rvs2_data[57] & io_pipe_0_bits_rvm_data[57] & io_pipe_0_bits_full_tail_mask[57]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_58 = io_pipe_0_bits_rvs2_data[58] & io_pipe_0_bits_rvm_data[58] & io_pipe_0_bits_full_tail_mask[58]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_59 = io_pipe_0_bits_rvs2_data[59] & io_pipe_0_bits_rvm_data[59] & io_pipe_0_bits_full_tail_mask[59]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_60 = io_pipe_0_bits_rvs2_data[60] & io_pipe_0_bits_rvm_data[60] & io_pipe_0_bits_full_tail_mask[60]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_61 = io_pipe_0_bits_rvs2_data[61] & io_pipe_0_bits_rvm_data[61] & io_pipe_0_bits_full_tail_mask[61]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_62 = io_pipe_0_bits_rvs2_data[62] & io_pipe_0_bits_rvm_data[62] & io_pipe_0_bits_full_tail_mask[62]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire _ff_oh_T_63 = io_pipe_0_bits_rvs2_data[63] & io_pipe_0_bits_rvm_data[63] & io_pipe_0_bits_full_tail_mask[63]; // @[MaskUnit.scala:50:{29,43}, :51:22] wire [61:0] _GEN = elems[62:1] | elems[61:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [59:0] _GEN_0 = elems[60:1] | elems[59:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [55:0] _GEN_1 = elems[56:1] | elems[55:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [51:0] _GEN_2 = elems[52:1] | elems[51:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [47:0] _GEN_3 = elems[48:1] | elems[47:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [43:0] _GEN_4 = elems[44:1] | elems[43:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [39:0] _GEN_5 = elems[40:1] | elems[39:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [35:0] _GEN_6 = elems[36:1] | elems[35:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [31:0] _GEN_7 = elems[32:1] | elems[31:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [27:0] _GEN_8 = elems[28:1] | elems[27:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [23:0] _GEN_9 = elems[24:1] | elems[23:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [19:0] _GEN_10 = elems[20:1] | elems[19:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [15:0] _GEN_11 = elems[16:1] | elems[15:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [11:0] _GEN_12 = elems[12:1] | elems[11:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [7:0] _GEN_13 = elems[8:1] | elems[7:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [3:0] _GEN_14 = elems[4:1] | elems[3:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [57:0] _GEN_15 = _GEN_0[59:2] | elems[58:1] | elems[57:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [53:0] _GEN_16 = _GEN_1[55:2] | elems[54:1] | elems[53:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [45:0] _GEN_17 = _GEN_3[47:2] | elems[46:1] | elems[45:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [37:0] _GEN_18 = _GEN_5[39:2] | elems[38:1] | elems[37:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [29:0] _GEN_19 = _GEN_7[31:2] | elems[30:1] | elems[29:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [21:0] _GEN_20 = _GEN_9[23:2] | elems[22:1] | elems[21:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [13:0] _GEN_21 = _GEN_11[15:2] | elems[14:1] | elems[13:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [5:0] _GEN_22 = _GEN_13[7:2] | elems[6:1] | elems[5:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [56:0] _GEN_23 = _GEN[60:4] | _GEN_15[56:0]; // @[MaskUnit.scala:54:73] wire [49:0] _GEN_24 = _GEN_16[53:4] | _GEN_2[51:2] | elems[50:1] | elems[49:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [41:0] _GEN_25 = _GEN_17[45:4] | _GEN_4[43:2] | elems[42:1] | elems[41:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [25:0] _GEN_26 = _GEN_19[29:4] | _GEN_8[27:2] | elems[26:1] | elems[25:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [9:0] _GEN_27 = _GEN_21[13:4] | _GEN_12[11:2] | elems[10:1] | elems[9:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [48:0] _GEN_28 = _GEN_23[56:8] | _GEN_24[48:0]; // @[MaskUnit.scala:54:73] wire [33:0] _GEN_29 = _GEN_25[41:8] | _GEN_18[37:4] | _GEN_6[35:2] | elems[34:1] | elems[33:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [17:0] _GEN_30 = _GEN_26[25:8] | _GEN_20[21:4] | _GEN_10[19:2] | elems[18:1] | elems[17:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire [32:0] _GEN_31 = _GEN_28[48:16] | _GEN_29[32:0]; // @[MaskUnit.scala:54:73] wire [1:0] _GEN_32 = _GEN_30[17:16] | _GEN_27[9:8] | _GEN_22[5:4] | _GEN_14[3:2] | elems[2:1] | elems[1:0]; // @[MaskUnit.scala:50:{29,43}, :54:{52,73}] wire first_here = (~found_first | io_pipe_0_bits_head) & (|elems); // @[MaskUnit.scala:25:24, :50:{29,43}, :55:23, :56:{21,34,46}] wire [63:0] set = (~(io_pipe_0_bits_rs1 == 5'h1 | _set_first_T_1) | found_first & ~io_pipe_0_bits_head ? 64'h0 : ~({64{|elems}} & (elems | {elems[0] | _GEN[61] | _GEN_15[57] | _GEN_24[49] | _GEN_29[33] | _GEN_32[1], _GEN_31[32] | _GEN_32[0], _GEN_31[31] | _GEN_30[15] | _GEN_27[7] | _GEN_22[3] | _GEN_14[1] | elems[0], _GEN_31[30] | _GEN_30[14] | _GEN_27[6] | _GEN_22[2] | _GEN_14[0], _GEN_31[29] | _GEN_30[13] | _GEN_27[5] | _GEN_22[1] | elems[0], _GEN_31[28] | _GEN_30[12] | _GEN_27[4] | _GEN_22[0], _GEN_31[27] | _GEN_30[11] | _GEN_27[3] | _GEN_13[1] | elems[0], _GEN_31[26] | _GEN_30[10] | _GEN_27[2] | _GEN_13[0], _GEN_31[25] | _GEN_30[9] | _GEN_27[1] | elems[0], _GEN_31[24] | _GEN_30[8] | _GEN_27[0], _GEN_31[23] | _GEN_30[7] | _GEN_21[3] | _GEN_12[1] | elems[0], _GEN_31[22] | _GEN_30[6] | _GEN_21[2] | _GEN_12[0], _GEN_31[21] | _GEN_30[5] | _GEN_21[1] | elems[0], _GEN_31[20] | _GEN_30[4] | _GEN_21[0], _GEN_31[19] | _GEN_30[3] | _GEN_11[1] | elems[0], _GEN_31[18] | _GEN_30[2] | _GEN_11[0], _GEN_31[17] | _GEN_30[1] | elems[0], _GEN_31[16] | _GEN_30[0], _GEN_31[15] | _GEN_26[7] | _GEN_20[3] | _GEN_10[1] | elems[0], _GEN_31[14] | _GEN_26[6] | _GEN_20[2] | _GEN_10[0], _GEN_31[13] | _GEN_26[5] | _GEN_20[1] | elems[0], _GEN_31[12] | _GEN_26[4] | _GEN_20[0], _GEN_31[11] | _GEN_26[3] | _GEN_9[1] | elems[0], _GEN_31[10] | _GEN_26[2] | _GEN_9[0], _GEN_31[9] | _GEN_26[1] | elems[0], _GEN_31[8] | _GEN_26[0], _GEN_31[7] | _GEN_19[3] | _GEN_8[1] | elems[0], _GEN_31[6] | _GEN_19[2] | _GEN_8[0], _GEN_31[5] | _GEN_19[1] | elems[0], _GEN_31[4] | _GEN_19[0], _GEN_31[3] | _GEN_7[1] | elems[0], _GEN_31[2] | _GEN_7[0], _GEN_31[1] | elems[0], _GEN_31[0], _GEN_28[15] | _GEN_25[7] | _GEN_18[3] | _GEN_6[1] | elems[0], _GEN_28[14] | _GEN_25[6] | _GEN_18[2] | _GEN_6[0], _GEN_28[13] | _GEN_25[5] | _GEN_18[1] | elems[0], _GEN_28[12] | _GEN_25[4] | _GEN_18[0], _GEN_28[11] | _GEN_25[3] | _GEN_5[1] | elems[0], _GEN_28[10] | _GEN_25[2] | _GEN_5[0], _GEN_28[9] | _GEN_25[1] | elems[0], _GEN_28[8] | _GEN_25[0], _GEN_28[7] | _GEN_17[3] | _GEN_4[1] | elems[0], _GEN_28[6] | _GEN_17[2] | _GEN_4[0], _GEN_28[5] | _GEN_17[1] | elems[0], _GEN_28[4] | _GEN_17[0], _GEN_28[3] | _GEN_3[1] | elems[0], _GEN_28[2] | _GEN_3[0], _GEN_28[1] | elems[0], _GEN_28[0], _GEN_23[7] | _GEN_16[3] | _GEN_2[1] | elems[0], _GEN_23[6] | _GEN_16[2] | _GEN_2[0], _GEN_23[5] | _GEN_16[1] | elems[0], _GEN_23[4] | _GEN_16[0], _GEN_23[3] | _GEN_1[1] | elems[0], _GEN_23[2] | _GEN_1[0], _GEN_23[1] | elems[0], _GEN_23[0], _GEN[3] | _GEN_0[1] | elems[0], _GEN[2] | _GEN_0[0], _GEN[1] | elems[0], _GEN[0], elems[0], 1'h0}))) | ((io_pipe_0_bits_rs1 == 5'h2 | _set_first_T_1) & first_here ? (_ff_oh_T ? 64'h1 : _ff_oh_T_1 ? 64'h2 : _ff_oh_T_2 ? 64'h4 : _ff_oh_T_3 ? 64'h8 : _ff_oh_T_4 ? 64'h10 : _ff_oh_T_5 ? 64'h20 : _ff_oh_T_6 ? 64'h40 : _ff_oh_T_7 ? 64'h80 : _ff_oh_T_8 ? 64'h100 : _ff_oh_T_9 ? 64'h200 : _ff_oh_T_10 ? 64'h400 : _ff_oh_T_11 ? 64'h800 : _ff_oh_T_12 ? 64'h1000 : _ff_oh_T_13 ? 64'h2000 : _ff_oh_T_14 ? 64'h4000 : _ff_oh_T_15 ? 64'h8000 : _ff_oh_T_16 ? 64'h10000 : _ff_oh_T_17 ? 64'h20000 : _ff_oh_T_18 ? 64'h40000 : _ff_oh_T_19 ? 64'h80000 : _ff_oh_T_20 ? 64'h100000 : _ff_oh_T_21 ? 64'h200000 : _ff_oh_T_22 ? 64'h400000 : _ff_oh_T_23 ? 64'h800000 : _ff_oh_T_24 ? 64'h1000000 : _ff_oh_T_25 ? 64'h2000000 : _ff_oh_T_26 ? 64'h4000000 : _ff_oh_T_27 ? 64'h8000000 : _ff_oh_T_28 ? 64'h10000000 : _ff_oh_T_29 ? 64'h20000000 : _ff_oh_T_30 ? 64'h40000000 : _ff_oh_T_31 ? 64'h80000000 : _ff_oh_T_32 ? 64'h100000000 : _ff_oh_T_33 ? 64'h200000000 : _ff_oh_T_34 ? 64'h400000000 : _ff_oh_T_35 ? 64'h800000000 : _ff_oh_T_36 ? 64'h1000000000 : _ff_oh_T_37 ? 64'h2000000000 : _ff_oh_T_38 ? 64'h4000000000 : _ff_oh_T_39 ? 64'h8000000000 : _ff_oh_T_40 ? 64'h10000000000 : _ff_oh_T_41 ? 64'h20000000000 : _ff_oh_T_42 ? 64'h40000000000 : _ff_oh_T_43 ? 64'h80000000000 : _ff_oh_T_44 ? 64'h100000000000 : _ff_oh_T_45 ? 64'h200000000000 : _ff_oh_T_46 ? 64'h400000000000 : _ff_oh_T_47 ? 64'h800000000000 : _ff_oh_T_48 ? 64'h1000000000000 : _ff_oh_T_49 ? 64'h2000000000000 : _ff_oh_T_50 ? 64'h4000000000000 : _ff_oh_T_51 ? 64'h8000000000000 : _ff_oh_T_52 ? 64'h10000000000000 : _ff_oh_T_53 ? 64'h20000000000000 : _ff_oh_T_54 ? 64'h40000000000000 : _ff_oh_T_55 ? 64'h80000000000000 : _ff_oh_T_56 ? 64'h100000000000000 : _ff_oh_T_57 ? 64'h200000000000000 : _ff_oh_T_58 ? 64'h400000000000000 : _ff_oh_T_59 ? 64'h800000000000000 : _ff_oh_T_60 ? 64'h1000000000000000 : _ff_oh_T_61 ? 64'h2000000000000000 : _ff_oh_T_62 ? 64'h4000000000000000 : {_ff_oh_T_63, 63'h0}) : 64'h0); // @[Mux.scala:50:70] wire [8:0] scalar_wb_rdata = io_pipe_0_bits_head ? 9'h0 : scalar_wb_data[8:0]; // @[MaskUnit.scala:21:27, :63:28] wire [63:0] _iota_dlenb_grouped_T_2 = io_pipe_0_bits_rs1[0] ? 64'hFFFFFFFFFFFFFFFF : elems; // @[MaskUnit.scala:50:{29,43}, :66:{22,29}] wire [63:0] _iota_dlenb_grouped_T_13 = io_pipe_0_bits_rs1[0] ? 64'hFFFFFFFFFFFFFFFF : elems; // @[MaskUnit.scala:50:{29,43}, :66:{22,29}] wire [63:0] _iota_dlenb_grouped_T_32 = io_pipe_0_bits_rs1[0] ? 64'hFFFFFFFFFFFFFFFF : elems; // @[MaskUnit.scala:50:{29,43}, :66:{22,29}] wire [63:0] _iota_dlenb_grouped_T_67 = io_pipe_0_bits_rs1[0] ? 64'hFFFFFFFFFFFFFFFF : elems; // @[MaskUnit.scala:50:{29,43}, :66:{22,29}] wire [7:0][7:0] _GEN_33 = {{_iota_dlenb_grouped_T_2[63:56]}, {_iota_dlenb_grouped_T_2[55:48]}, {_iota_dlenb_grouped_T_2[47:40]}, {_iota_dlenb_grouped_T_2[39:32]}, {_iota_dlenb_grouped_T_2[31:24]}, {_iota_dlenb_grouped_T_2[23:16]}, {_iota_dlenb_grouped_T_2[15:8]}, {_iota_dlenb_grouped_T_2[7:0]}}; // @[MaskUnit.scala:65:39, :66:{22,65}] wire [15:0][3:0] _GEN_34 = {{_iota_dlenb_grouped_T_13[63:60]}, {_iota_dlenb_grouped_T_13[59:56]}, {_iota_dlenb_grouped_T_13[55:52]}, {_iota_dlenb_grouped_T_13[51:48]}, {_iota_dlenb_grouped_T_13[47:44]}, {_iota_dlenb_grouped_T_13[43:40]}, {_iota_dlenb_grouped_T_13[39:36]}, {_iota_dlenb_grouped_T_13[35:32]}, {_iota_dlenb_grouped_T_13[31:28]}, {_iota_dlenb_grouped_T_13[27:24]}, {_iota_dlenb_grouped_T_13[23:20]}, {_iota_dlenb_grouped_T_13[19:16]}, {_iota_dlenb_grouped_T_13[15:12]}, {_iota_dlenb_grouped_T_13[11:8]}, {_iota_dlenb_grouped_T_13[7:4]}, {_iota_dlenb_grouped_T_13[3:0]}}; // @[MaskUnit.scala:65:39, :66:{22,65}] wire [31:0][1:0] _GEN_35 = {{_iota_dlenb_grouped_T_32[63:62]}, {_iota_dlenb_grouped_T_32[61:60]}, {_iota_dlenb_grouped_T_32[59:58]}, {_iota_dlenb_grouped_T_32[57:56]}, {_iota_dlenb_grouped_T_32[55:54]}, {_iota_dlenb_grouped_T_32[53:52]}, {_iota_dlenb_grouped_T_32[51:50]}, {_iota_dlenb_grouped_T_32[49:48]}, {_iota_dlenb_grouped_T_32[47:46]}, {_iota_dlenb_grouped_T_32[45:44]}, {_iota_dlenb_grouped_T_32[43:42]}, {_iota_dlenb_grouped_T_32[41:40]}, {_iota_dlenb_grouped_T_32[39:38]}, {_iota_dlenb_grouped_T_32[37:36]}, {_iota_dlenb_grouped_T_32[35:34]}, {_iota_dlenb_grouped_T_32[33:32]}, {_iota_dlenb_grouped_T_32[31:30]}, {_iota_dlenb_grouped_T_32[29:28]}, {_iota_dlenb_grouped_T_32[27:26]}, {_iota_dlenb_grouped_T_32[25:24]}, {_iota_dlenb_grouped_T_32[23:22]}, {_iota_dlenb_grouped_T_32[21:20]}, {_iota_dlenb_grouped_T_32[19:18]}, {_iota_dlenb_grouped_T_32[17:16]}, {_iota_dlenb_grouped_T_32[15:14]}, {_iota_dlenb_grouped_T_32[13:12]}, {_iota_dlenb_grouped_T_32[11:10]}, {_iota_dlenb_grouped_T_32[9:8]}, {_iota_dlenb_grouped_T_32[7:6]}, {_iota_dlenb_grouped_T_32[5:4]}, {_iota_dlenb_grouped_T_32[3:2]}, {_iota_dlenb_grouped_T_32[1:0]}}; // @[MaskUnit.scala:65:39, :66:{22,65}] wire [63:0] _GEN_36 = {{_iota_dlenb_grouped_T_67[63]}, {_iota_dlenb_grouped_T_67[62]}, {_iota_dlenb_grouped_T_67[61]}, {_iota_dlenb_grouped_T_67[60]}, {_iota_dlenb_grouped_T_67[59]}, {_iota_dlenb_grouped_T_67[58]}, {_iota_dlenb_grouped_T_67[57]}, {_iota_dlenb_grouped_T_67[56]}, {_iota_dlenb_grouped_T_67[55]}, {_iota_dlenb_grouped_T_67[54]}, {_iota_dlenb_grouped_T_67[53]}, {_iota_dlenb_grouped_T_67[52]}, {_iota_dlenb_grouped_T_67[51]}, {_iota_dlenb_grouped_T_67[50]}, {_iota_dlenb_grouped_T_67[49]}, {_iota_dlenb_grouped_T_67[48]}, {_iota_dlenb_grouped_T_67[47]}, {_iota_dlenb_grouped_T_67[46]}, {_iota_dlenb_grouped_T_67[45]}, {_iota_dlenb_grouped_T_67[44]}, {_iota_dlenb_grouped_T_67[43]}, {_iota_dlenb_grouped_T_67[42]}, {_iota_dlenb_grouped_T_67[41]}, {_iota_dlenb_grouped_T_67[40]}, {_iota_dlenb_grouped_T_67[39]}, {_iota_dlenb_grouped_T_67[38]}, {_iota_dlenb_grouped_T_67[37]}, {_iota_dlenb_grouped_T_67[36]}, {_iota_dlenb_grouped_T_67[35]}, {_iota_dlenb_grouped_T_67[34]}, {_iota_dlenb_grouped_T_67[33]}, {_iota_dlenb_grouped_T_67[32]}, {_iota_dlenb_grouped_T_67[31]}, {_iota_dlenb_grouped_T_67[30]}, {_iota_dlenb_grouped_T_67[29]}, {_iota_dlenb_grouped_T_67[28]}, {_iota_dlenb_grouped_T_67[27]}, {_iota_dlenb_grouped_T_67[26]}, {_iota_dlenb_grouped_T_67[25]}, {_iota_dlenb_grouped_T_67[24]}, {_iota_dlenb_grouped_T_67[23]}, {_iota_dlenb_grouped_T_67[22]}, {_iota_dlenb_grouped_T_67[21]}, {_iota_dlenb_grouped_T_67[20]}, {_iota_dlenb_grouped_T_67[19]}, {_iota_dlenb_grouped_T_67[18]}, {_iota_dlenb_grouped_T_67[17]}, {_iota_dlenb_grouped_T_67[16]}, {_iota_dlenb_grouped_T_67[15]}, {_iota_dlenb_grouped_T_67[14]}, {_iota_dlenb_grouped_T_67[13]}, {_iota_dlenb_grouped_T_67[12]}, {_iota_dlenb_grouped_T_67[11]}, {_iota_dlenb_grouped_T_67[10]}, {_iota_dlenb_grouped_T_67[9]}, {_iota_dlenb_grouped_T_67[8]}, {_iota_dlenb_grouped_T_67[7]}, {_iota_dlenb_grouped_T_67[6]}, {_iota_dlenb_grouped_T_67[5]}, {_iota_dlenb_grouped_T_67[4]}, {_iota_dlenb_grouped_T_67[3]}, {_iota_dlenb_grouped_T_67[2]}, {_iota_dlenb_grouped_T_67[1]}, {_iota_dlenb_grouped_T_67[0]}}; // @[MaskUnit.scala:65:39, :66:{22,65}] wire [3:0][7:0] _GEN_37 = {{{7'h0, _GEN_36[io_pipe_0_bits_eidx[5:0]]}}, {{6'h0, _GEN_35[io_pipe_0_bits_eidx[5:1]]}}, {{4'h0, _GEN_34[io_pipe_0_bits_eidx[5:2]]}}, {_GEN_33[io_pipe_0_bits_eidx[5:3]]}}; // @[MaskUnit.scala:65:39, :67:20, :70:26] wire [8:0] _iota_sums_T_47 = {8'h0, _GEN_37[io_pipe_0_bits_rvd_eew][0]} + scalar_wb_rdata; // @[MaskUnit.scala:63:28, :70:{26,42}] wire [8:0] _iota_sums_T_71 = {7'h0, {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][0]} + {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][1]}} + scalar_wb_rdata; // @[MaskUnit.scala:63:28, :70:{14,26,42}] wire [8:0] _iota_sums_T_95 = {6'h0, {1'h0, {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][0]} + {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][1]}} + {2'h0, _GEN_37[io_pipe_0_bits_rvd_eew][2]}} + scalar_wb_rdata; // @[MaskUnit.scala:17:7, :63:28, :70:{14,26,42}] wire _io_write_bits_data_T = opmvx | io_pipe_0_bits_funct3 == 3'h5; // @[MaskUnit.scala:37:25, :39:25, :120:55] wire [7:0] _io_write_bits_mask_T_12 = {4'h0, {2'h0, {1'h0, io_pipe_0_bits_vd_eew == 2'h0} | {2{io_pipe_0_bits_vd_eew == 2'h1}}} | {4{io_pipe_0_bits_vd_eew == 2'h2}}} | {8{&io_pipe_0_bits_vd_eew}}; // @[MaskUnit.scala:17:7] wire [3:0][63:0] _GEN_38 = {{{55'h0, scalar_wb_rdata}}, {{23'h0, _iota_sums_T_47, 23'h0, scalar_wb_rdata}}, {{7'h0, _iota_sums_T_95, 7'h0, _iota_sums_T_71, 7'h0, _iota_sums_T_47, 7'h0, scalar_wb_rdata}}, {{{4'h0, {1'h0, {1'h0, {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][0]} + {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][1]}} + {1'h0, {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][2]} + {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][3]}}} + {1'h0, {1'h0, {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][4]} + {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][5]}} + {2'h0, _GEN_37[io_pipe_0_bits_rvd_eew][6]}}} + scalar_wb_rdata[7:0], {4'h0, {1'h0, {1'h0, {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][0]} + {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][1]}} + {1'h0, {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][2]} + {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][3]}}} + {2'h0, {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][4]} + {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][5]}}} + scalar_wb_rdata[7:0], {4'h0, {1'h0, {1'h0, {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][0]} + {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][1]}} + {1'h0, {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][2]} + {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][3]}}} + {3'h0, _GEN_37[io_pipe_0_bits_rvd_eew][4]}} + scalar_wb_rdata[7:0], {5'h0, {1'h0, {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][0]} + {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][1]}} + {1'h0, {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][2]} + {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][3]}}} + scalar_wb_rdata[7:0], _iota_sums_T_95[7:0], _iota_sums_T_71[7:0], _iota_sums_T_47[7:0], scalar_wb_rdata[7:0]}}}; // @[Mux.scala:30:73] wire [3:0][7:0] _GEN_39 = '{8'h1, 8'h3, 8'hF, 8'hFF}; wire [7:0] _eew_mask_T_11 = {4'h0, {2'h0, {1'h0, io_pipe_0_bits_rvs2_eew == 2'h0} | {2{io_pipe_0_bits_rvs2_eew == 2'h1}}} | {4{io_pipe_0_bits_rvs2_eew == 2'h2}}} | {8{&io_pipe_0_bits_rvs2_eew}}; // @[MaskUnit.scala:17:7] wire [63:0] eew_mask = {{8{_eew_mask_T_11[7]}}, {8{_eew_mask_T_11[6]}}, {8{_eew_mask_T_11[5]}}, {8{_eew_mask_T_11[4]}}, {8{_eew_mask_T_11[3]}}, {8{_eew_mask_T_11[2]}}, {8{_eew_mask_T_11[1]}}, {8{_eew_mask_T_11[0]}}}; // @[Parameters.scala:352:13, :353:46] wire [3:0] _GEN_40 = {{io_pipe_0_bits_rvs2_data[63]}, {io_pipe_0_bits_rvs2_data[31]}, {io_pipe_0_bits_rvs2_data[15]}, {io_pipe_0_bits_rvs2_data[7]}}; // @[MaskUnit.scala:60:54, :62:57] wire [63:0] elem = io_pipe_0_bits_rvs2_data & eew_mask | {64{_GEN_40[io_pipe_0_bits_rvs2_eew] & (opmvv | opmvx)}} & ~eew_mask; // @[MaskUnit.scala:36:25, :37:25, :62:{28,40,47,57,70,72}] wire opfvv = io_pipe_0_bits_funct3 == 3'h1; // @[MaskUnit.scala:38:25] wire wxunary0 = opmvv & ~(io_pipe_0_bits_funct6[2]); // @[MaskUnit.scala:36:25, :41:{24,27,37}] wire _GEN_41 = io_pipe_0_valid & io_pipe_0_bits_tail; // @[MaskUnit.scala:20:31, :78:27, :107:20, :108:22] always @(posedge clock) begin // @[MaskUnit.scala:17:7] if (reset) // @[MaskUnit.scala:17:7] scalar_wb_busy <= 1'h0; // @[MaskUnit.scala:20:31] else // @[MaskUnit.scala:17:7] scalar_wb_busy <= ~(io_scalar_write_ready & scalar_wb_busy) & (_GEN_41 ? wxunary0 | opfvv : scalar_wb_busy); // @[Decoupled.scala:51:35] if (io_pipe_0_valid) begin // @[FunctionalUnit.scala:49:14] if (munary0) // @[MaskUnit.scala:45:24] scalar_wb_data <= {55'h0, scalar_wb_rdata + {5'h0, {1'h0, {1'h0, {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][0] & _GEN_39[io_pipe_0_bits_vd_eew][0]} + {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][1] & _GEN_39[io_pipe_0_bits_vd_eew][1]}} + {1'h0, {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][2] & _GEN_39[io_pipe_0_bits_vd_eew][2]} + {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][3] & _GEN_39[io_pipe_0_bits_vd_eew][3]}}} + {1'h0, {1'h0, {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][4] & _GEN_39[io_pipe_0_bits_vd_eew][4]} + {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][5] & _GEN_39[io_pipe_0_bits_vd_eew][5]}} + {1'h0, {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][6] & _GEN_39[io_pipe_0_bits_vd_eew][6]} + {1'h0, _GEN_37[io_pipe_0_bits_rvd_eew][7] & _GEN_39[io_pipe_0_bits_vd_eew][7]}}}}}; // @[MaskUnit.scala:21:27, :54:47, :63:28, :70:26, :104:{26,38}, :105:{22,42}] else if (opfvv) // @[MaskUnit.scala:38:25] scalar_wb_data <= elem; // @[MaskUnit.scala:21:27, :62:40] else if (wxunary0) begin // @[MaskUnit.scala:41:24] if (io_pipe_0_bits_rs1 == 5'h10) // @[MaskUnit.scala:87:20] scalar_wb_data <= {55'h0, scalar_wb_rdata + {2'h0, {1'h0, {1'h0, {1'h0, {1'h0, {1'h0, {1'h0, _ff_oh_T} + {1'h0, _ff_oh_T_1}} + {1'h0, {1'h0, _ff_oh_T_2} + {1'h0, _ff_oh_T_3}}} + {1'h0, {1'h0, {1'h0, _ff_oh_T_4} + {1'h0, _ff_oh_T_5}} + {1'h0, {1'h0, _ff_oh_T_6} + {1'h0, _ff_oh_T_7}}}} + {1'h0, {1'h0, {1'h0, {1'h0, _ff_oh_T_8} + {1'h0, _ff_oh_T_9}} + {1'h0, {1'h0, _ff_oh_T_10} + {1'h0, _ff_oh_T_11}}} + {1'h0, {1'h0, {1'h0, _ff_oh_T_12} + {1'h0, _ff_oh_T_13}} + {1'h0, {1'h0, _ff_oh_T_14} + {1'h0, _ff_oh_T_15}}}}} + {1'h0, {1'h0, {1'h0, {1'h0, {1'h0, _ff_oh_T_16} + {1'h0, _ff_oh_T_17}} + {1'h0, {1'h0, _ff_oh_T_18} + {1'h0, _ff_oh_T_19}}} + {1'h0, {1'h0, {1'h0, _ff_oh_T_20} + {1'h0, _ff_oh_T_21}} + {1'h0, {1'h0, _ff_oh_T_22} + {1'h0, _ff_oh_T_23}}}} + {1'h0, {1'h0, {1'h0, {1'h0, _ff_oh_T_24} + {1'h0, _ff_oh_T_25}} + {1'h0, {1'h0, _ff_oh_T_26} + {1'h0, _ff_oh_T_27}}} + {1'h0, {1'h0, {1'h0, _ff_oh_T_28} + {1'h0, _ff_oh_T_29}} + {1'h0, {1'h0, _ff_oh_T_30} + {1'h0, _ff_oh_T_31}}}}}} + {1'h0, {1'h0, {1'h0, {1'h0, {1'h0, {1'h0, _ff_oh_T_32} + {1'h0, _ff_oh_T_33}} + {1'h0, {1'h0, _ff_oh_T_34} + {1'h0, _ff_oh_T_35}}} + {1'h0, {1'h0, {1'h0, _ff_oh_T_36} + {1'h0, _ff_oh_T_37}} + {1'h0, {1'h0, _ff_oh_T_38} + {1'h0, _ff_oh_T_39}}}} + {1'h0, {1'h0, {1'h0, {1'h0, _ff_oh_T_40} + {1'h0, _ff_oh_T_41}} + {1'h0, {1'h0, _ff_oh_T_42} + {1'h0, _ff_oh_T_43}}} + {1'h0, {1'h0, {1'h0, _ff_oh_T_44} + {1'h0, _ff_oh_T_45}} + {1'h0, {1'h0, _ff_oh_T_46} + {1'h0, _ff_oh_T_47}}}}} + {1'h0, {1'h0, {1'h0, {1'h0, {1'h0, _ff_oh_T_48} + {1'h0, _ff_oh_T_49}} + {1'h0, {1'h0, _ff_oh_T_50} + {1'h0, _ff_oh_T_51}}} + {1'h0, {1'h0, {1'h0, _ff_oh_T_52} + {1'h0, _ff_oh_T_53}} + {1'h0, {1'h0, _ff_oh_T_54} + {1'h0, _ff_oh_T_55}}}} + {1'h0, {1'h0, {1'h0, {1'h0, _ff_oh_T_56} + {1'h0, _ff_oh_T_57}} + {1'h0, {1'h0, _ff_oh_T_58} + {1'h0, _ff_oh_T_59}}} + {1'h0, {1'h0, {1'h0, _ff_oh_T_60} + {1'h0, _ff_oh_T_61}} + {1'h0, {1'h0, _ff_oh_T_62} + {1'h0, _ff_oh_T_63}}}}}}}}; // @[MaskUnit.scala:17:7, :21:27, :50:{29,43}, :51:22, :54:47, :63:28, :88:{24,44}] else if (io_pipe_0_bits_rs1 == 5'h11) begin // @[MaskUnit.scala:89:27] if (first_here) // @[MaskUnit.scala:56:46] scalar_wb_data <= {56'h0, io_pipe_0_bits_eidx + {2'h0, _ff_oh_T ? 6'h0 : _ff_oh_T_1 ? 6'h1 : _ff_oh_T_2 ? 6'h2 : _ff_oh_T_3 ? 6'h3 : _ff_oh_T_4 ? 6'h4 : _ff_oh_T_5 ? 6'h5 : _ff_oh_T_6 ? 6'h6 : _ff_oh_T_7 ? 6'h7 : _ff_oh_T_8 ? 6'h8 : _ff_oh_T_9 ? 6'h9 : _ff_oh_T_10 ? 6'hA : _ff_oh_T_11 ? 6'hB : _ff_oh_T_12 ? 6'hC : _ff_oh_T_13 ? 6'hD : _ff_oh_T_14 ? 6'hE : _ff_oh_T_15 ? 6'hF : _ff_oh_T_16 ? 6'h10 : _ff_oh_T_17 ? 6'h11 : _ff_oh_T_18 ? 6'h12 : _ff_oh_T_19 ? 6'h13 : _ff_oh_T_20 ? 6'h14 : _ff_oh_T_21 ? 6'h15 : _ff_oh_T_22 ? 6'h16 : _ff_oh_T_23 ? 6'h17 : _ff_oh_T_24 ? 6'h18 : _ff_oh_T_25 ? 6'h19 : _ff_oh_T_26 ? 6'h1A : _ff_oh_T_27 ? 6'h1B : _ff_oh_T_28 ? 6'h1C : _ff_oh_T_29 ? 6'h1D : _ff_oh_T_30 ? 6'h1E : _ff_oh_T_31 ? 6'h1F : _ff_oh_T_32 ? 6'h20 : _ff_oh_T_33 ? 6'h21 : _ff_oh_T_34 ? 6'h22 : _ff_oh_T_35 ? 6'h23 : _ff_oh_T_36 ? 6'h24 : _ff_oh_T_37 ? 6'h25 : _ff_oh_T_38 ? 6'h26 : _ff_oh_T_39 ? 6'h27 : _ff_oh_T_40 ? 6'h28 : _ff_oh_T_41 ? 6'h29 : _ff_oh_T_42 ? 6'h2A : _ff_oh_T_43 ? 6'h2B : _ff_oh_T_44 ? 6'h2C : _ff_oh_T_45 ? 6'h2D : _ff_oh_T_46 ? 6'h2E : _ff_oh_T_47 ? 6'h2F : _ff_oh_T_48 ? 6'h30 : _ff_oh_T_49 ? 6'h31 : _ff_oh_T_50 ? 6'h32 : _ff_oh_T_51 ? 6'h33 : _ff_oh_T_52 ? 6'h34 : _ff_oh_T_53 ? 6'h35 : _ff_oh_T_54 ? 6'h36 : _ff_oh_T_55 ? 6'h37 : _ff_oh_T_56 ? 6'h38 : _ff_oh_T_57 ? 6'h39 : _ff_oh_T_58 ? 6'h3A : _ff_oh_T_59 ? 6'h3B : _ff_oh_T_60 ? 6'h3C : _ff_oh_T_61 ? 6'h3D : {5'h1F, ~_ff_oh_T_62}}}; // @[Mux.scala:50:70] else if (~found_first | io_pipe_0_bits_head) // @[MaskUnit.scala:25:24, :56:21, :92:35] scalar_wb_data <= 64'hFFFFFFFFFFFFFFFF; // @[MaskUnit.scala:21:27] else if (io_pipe_0_bits_head) // @[FunctionalUnit.scala:49:14] scalar_wb_data <= 64'h0; // @[MaskUnit.scala:21:27] end else // @[MaskUnit.scala:89:27] scalar_wb_data <= elem; // @[MaskUnit.scala:21:27, :62:40] end else if (io_pipe_0_bits_head) // @[FunctionalUnit.scala:49:14] scalar_wb_data <= 64'h0; // @[MaskUnit.scala:21:27] scalar_wb_rd <= io_pipe_0_bits_rd; // @[MaskUnit.scala:22:25] scalar_wb_size <= io_pipe_0_bits_rvs2_eew; // @[MaskUnit.scala:24:27] found_first <= first_here | ~io_pipe_0_bits_head & found_first; // @[MaskUnit.scala:25:24, :56:46, :81:20, :82:19, :85:{23,37}] end if (_GEN_41) // @[MaskUnit.scala:20:31, :78:27, :107:20, :108:22] scalar_wb_fp <= opfvv; // @[MaskUnit.scala:23:25, :38:25] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Pipeline.scala: package gemmini import chisel3._ import chisel3.util._ class Pipeline[T <: Data] (gen: T, latency: Int)(comb: Seq[T => T] = Seq.fill(latency+1)((x: T) => x)) extends Module { val io = IO(new Bundle { val in = Flipped(Decoupled(gen)) val out = Decoupled(gen) val busy = Output(Bool()) }) require(comb.size == latency+1, "length of combinational is incorrect") if (latency == 0) { io.in.ready := io.out.ready io.out.valid := io.in.valid io.out.bits := comb.head(io.in.bits) io.busy := io.in.valid } else { val stages = Reg(Vec(latency, gen)) val valids = RegInit(VecInit(Seq.fill(latency)(false.B))) val stalling = VecInit(Seq.fill(latency)(false.B)) io.busy := io.in.valid || valids.reduce(_||_) // Stall signals io.in.ready := !stalling.head stalling.last := valids.last && !io.out.ready (stalling.init, stalling.tail, valids.init).zipped.foreach { case (s1, s2, v1) => s1 := v1 && s2 } // Valid signals // When the pipeline stage ahead of you isn't stalling, then make yourself invalid io.out.valid := valids.last when(io.out.ready) { valids.last := false.B } (valids.init, stalling.tail).zipped.foreach { case (v1, s2) => when(!s2) { v1 := false.B } } // When the pipeline stage behind you is valid then become true when(io.in.fire) { valids.head := true.B } (valids.tail, valids.init).zipped.foreach { case (v2, v1) => when(v1) { v2 := true.B } } // Stages when(io.in.fire) { stages.head := comb.head(io.in.bits) } io.out.bits := comb.last(stages.last) ((stages.tail zip stages.init) zip (stalling.tail zip comb.tail.init)).foreach { case ((st2, st1), (s2, c1)) => when(!s2) { st2 := c1(st1) } } } } object Pipeline { def apply[T <: Data](in: ReadyValidIO[T], latency: Int, comb: Seq[T => T]): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)(comb)) p.io.in <> in p.io.out } def apply[T <: Data](in: ReadyValidIO[T], latency: Int): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)()) p.io.in <> in p.io.out } }
module Pipeline_12( // @[Pipeline.scala:6:7] input clock, // @[Pipeline.scala:6:7] input reset, // @[Pipeline.scala:6:7] output io_in_ready, // @[Pipeline.scala:7:14] input io_in_valid, // @[Pipeline.scala:7:14] input [6:0] io_in_bits_cmd_inst_funct, // @[Pipeline.scala:7:14] input [63:0] io_in_bits_cmd_rs1, // @[Pipeline.scala:7:14] input [63:0] io_in_bits_cmd_rs2, // @[Pipeline.scala:7:14] input [67:0] io_in_bits_dram_addr, // @[Pipeline.scala:7:14] input [63:0] io_in_bits_spad_addr, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_K, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_J, // @[Pipeline.scala:7:14] input io_out_ready, // @[Pipeline.scala:7:14] output io_out_valid, // @[Pipeline.scala:7:14] output [6:0] io_out_bits_cmd_inst_funct, // @[Pipeline.scala:7:14] output [4:0] io_out_bits_cmd_inst_rs2, // @[Pipeline.scala:7:14] output [4:0] io_out_bits_cmd_inst_rs1, // @[Pipeline.scala:7:14] output io_out_bits_cmd_inst_xd, // @[Pipeline.scala:7:14] output io_out_bits_cmd_inst_xs1, // @[Pipeline.scala:7:14] output io_out_bits_cmd_inst_xs2, // @[Pipeline.scala:7:14] output [4:0] io_out_bits_cmd_inst_rd, // @[Pipeline.scala:7:14] output [6:0] io_out_bits_cmd_inst_opcode, // @[Pipeline.scala:7:14] output [63:0] io_out_bits_cmd_rs1, // @[Pipeline.scala:7:14] output [63:0] io_out_bits_cmd_rs2, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_debug, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_cease, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_wfi, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_cmd_status_isa, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_dprv, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_dv, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_prv, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_v, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sd, // @[Pipeline.scala:7:14] output [22:0] io_out_bits_cmd_status_zero2, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mpv, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_gva, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mbe, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sbe, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_sxl, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_uxl, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sd_rv32, // @[Pipeline.scala:7:14] output [7:0] io_out_bits_cmd_status_zero1, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_tsr, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_tw, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_tvm, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mxr, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sum, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mprv, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_xs, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_fs, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_mpp, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_vs, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_spp, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mpie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_ube, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_spie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_upie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_hie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_uie, // @[Pipeline.scala:7:14] output [67:0] io_out_bits_dram_addr, // @[Pipeline.scala:7:14] output [63:0] io_out_bits_spad_addr, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_K, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_J, // @[Pipeline.scala:7:14] output io_busy // @[Pipeline.scala:7:14] ); wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7] wire [6:0] io_in_bits_cmd_inst_funct_0 = io_in_bits_cmd_inst_funct; // @[Pipeline.scala:6:7] wire [63:0] io_in_bits_cmd_rs1_0 = io_in_bits_cmd_rs1; // @[Pipeline.scala:6:7] wire [63:0] io_in_bits_cmd_rs2_0 = io_in_bits_cmd_rs2; // @[Pipeline.scala:6:7] wire [67:0] io_in_bits_dram_addr_0 = io_in_bits_dram_addr; // @[Pipeline.scala:6:7] wire [63:0] io_in_bits_spad_addr_0 = io_in_bits_spad_addr; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_K_0 = io_in_bits_K; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_J_0 = io_in_bits_J; // @[Pipeline.scala:6:7] wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7] wire [4:0] io_in_bits_cmd_inst_rs2 = 5'h0; // @[Pipeline.scala:6:7, :7:14] wire [4:0] io_in_bits_cmd_inst_rs1 = 5'h0; // @[Pipeline.scala:6:7, :7:14] wire [4:0] io_in_bits_cmd_inst_rd = 5'h0; // @[Pipeline.scala:6:7, :7:14] wire [6:0] io_in_bits_cmd_inst_opcode = 7'h0; // @[Pipeline.scala:6:7, :7:14] wire [31:0] io_in_bits_cmd_status_isa = 32'h0; // @[Pipeline.scala:6:7, :7:14] wire [22:0] io_in_bits_cmd_status_zero2 = 23'h0; // @[Pipeline.scala:6:7, :7:14] wire [7:0] io_in_bits_cmd_status_zero1 = 8'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_dprv = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_prv = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_sxl = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_uxl = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_xs = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_fs = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_mpp = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_vs = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire io_in_bits_cmd_inst_xd = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_inst_xs1 = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_inst_xs2 = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_debug = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_cease = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_wfi = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_dv = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_v = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sd = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mpv = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_gva = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mbe = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sbe = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sd_rv32 = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_tsr = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_tw = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_tvm = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mxr = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sum = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mprv = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_spp = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mpie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_ube = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_spie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_upie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_hie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_uie = 1'h0; // @[Pipeline.scala:6:7] wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_1 = 1'h0; // @[Pipeline.scala:22:33] wire _io_in_ready_T; // @[Pipeline.scala:27:20] wire _io_busy_T_1; // @[Pipeline.scala:24:28] wire io_in_ready_0; // @[Pipeline.scala:6:7] wire [6:0] io_out_bits_cmd_inst_funct_0; // @[Pipeline.scala:6:7] wire [4:0] io_out_bits_cmd_inst_rs2_0; // @[Pipeline.scala:6:7] wire [4:0] io_out_bits_cmd_inst_rs1_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_inst_xd_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_inst_xs1_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_inst_xs2_0; // @[Pipeline.scala:6:7] wire [4:0] io_out_bits_cmd_inst_rd_0; // @[Pipeline.scala:6:7] wire [6:0] io_out_bits_cmd_inst_opcode_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_debug_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_cease_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_wfi_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_cmd_status_isa_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_dprv_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_dv_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_prv_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_v_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sd_0; // @[Pipeline.scala:6:7] wire [22:0] io_out_bits_cmd_status_zero2_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mpv_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_gva_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mbe_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sbe_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_sxl_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_uxl_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sd_rv32_0; // @[Pipeline.scala:6:7] wire [7:0] io_out_bits_cmd_status_zero1_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_tsr_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_tw_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_tvm_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mxr_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sum_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mprv_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_xs_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_fs_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_mpp_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_vs_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_spp_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mpie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_ube_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_spie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_upie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_hie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_uie_0; // @[Pipeline.scala:6:7] wire [63:0] io_out_bits_cmd_rs1_0; // @[Pipeline.scala:6:7] wire [63:0] io_out_bits_cmd_rs2_0; // @[Pipeline.scala:6:7] wire [67:0] io_out_bits_dram_addr_0; // @[Pipeline.scala:6:7] wire [63:0] io_out_bits_spad_addr_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_K_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_J_0; // @[Pipeline.scala:6:7] wire io_out_valid_0; // @[Pipeline.scala:6:7] wire io_busy_0; // @[Pipeline.scala:6:7] reg [6:0] stages_0_cmd_inst_funct; // @[Pipeline.scala:21:21] reg [63:0] stages_0_cmd_rs1; // @[Pipeline.scala:21:21] reg [63:0] stages_0_cmd_rs2; // @[Pipeline.scala:21:21] reg [67:0] stages_0_dram_addr; // @[Pipeline.scala:21:21] reg [63:0] stages_0_spad_addr; // @[Pipeline.scala:21:21] reg [15:0] stages_0_K; // @[Pipeline.scala:21:21] reg [15:0] stages_0_J; // @[Pipeline.scala:21:21] reg [6:0] stages_1_cmd_inst_funct; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_funct_0 = stages_1_cmd_inst_funct; // @[Pipeline.scala:6:7, :21:21] reg [4:0] stages_1_cmd_inst_rs2; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_rs2_0 = stages_1_cmd_inst_rs2; // @[Pipeline.scala:6:7, :21:21] reg [4:0] stages_1_cmd_inst_rs1; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_rs1_0 = stages_1_cmd_inst_rs1; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_inst_xd; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_xd_0 = stages_1_cmd_inst_xd; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_inst_xs1; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_xs1_0 = stages_1_cmd_inst_xs1; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_inst_xs2; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_xs2_0 = stages_1_cmd_inst_xs2; // @[Pipeline.scala:6:7, :21:21] reg [4:0] stages_1_cmd_inst_rd; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_rd_0 = stages_1_cmd_inst_rd; // @[Pipeline.scala:6:7, :21:21] reg [6:0] stages_1_cmd_inst_opcode; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_opcode_0 = stages_1_cmd_inst_opcode; // @[Pipeline.scala:6:7, :21:21] reg [63:0] stages_1_cmd_rs1; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_rs1_0 = stages_1_cmd_rs1; // @[Pipeline.scala:6:7, :21:21] reg [63:0] stages_1_cmd_rs2; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_rs2_0 = stages_1_cmd_rs2; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_debug; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_debug_0 = stages_1_cmd_status_debug; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_cease; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_cease_0 = stages_1_cmd_status_cease; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_wfi; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_wfi_0 = stages_1_cmd_status_wfi; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_1_cmd_status_isa; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_isa_0 = stages_1_cmd_status_isa; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_dprv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_dprv_0 = stages_1_cmd_status_dprv; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_dv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_dv_0 = stages_1_cmd_status_dv; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_prv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_prv_0 = stages_1_cmd_status_prv; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_v; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_v_0 = stages_1_cmd_status_v; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sd; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sd_0 = stages_1_cmd_status_sd; // @[Pipeline.scala:6:7, :21:21] reg [22:0] stages_1_cmd_status_zero2; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_zero2_0 = stages_1_cmd_status_zero2; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mpv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mpv_0 = stages_1_cmd_status_mpv; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_gva; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_gva_0 = stages_1_cmd_status_gva; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mbe; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mbe_0 = stages_1_cmd_status_mbe; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sbe; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sbe_0 = stages_1_cmd_status_sbe; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_sxl; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sxl_0 = stages_1_cmd_status_sxl; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_uxl; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_uxl_0 = stages_1_cmd_status_uxl; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sd_rv32; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sd_rv32_0 = stages_1_cmd_status_sd_rv32; // @[Pipeline.scala:6:7, :21:21] reg [7:0] stages_1_cmd_status_zero1; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_zero1_0 = stages_1_cmd_status_zero1; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_tsr; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_tsr_0 = stages_1_cmd_status_tsr; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_tw; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_tw_0 = stages_1_cmd_status_tw; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_tvm; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_tvm_0 = stages_1_cmd_status_tvm; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mxr; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mxr_0 = stages_1_cmd_status_mxr; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sum; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sum_0 = stages_1_cmd_status_sum; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mprv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mprv_0 = stages_1_cmd_status_mprv; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_xs; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_xs_0 = stages_1_cmd_status_xs; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_fs; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_fs_0 = stages_1_cmd_status_fs; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_mpp; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mpp_0 = stages_1_cmd_status_mpp; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_vs; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_vs_0 = stages_1_cmd_status_vs; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_spp; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_spp_0 = stages_1_cmd_status_spp; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mpie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mpie_0 = stages_1_cmd_status_mpie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_ube; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_ube_0 = stages_1_cmd_status_ube; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_spie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_spie_0 = stages_1_cmd_status_spie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_upie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_upie_0 = stages_1_cmd_status_upie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mie_0 = stages_1_cmd_status_mie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_hie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_hie_0 = stages_1_cmd_status_hie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sie_0 = stages_1_cmd_status_sie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_uie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_uie_0 = stages_1_cmd_status_uie; // @[Pipeline.scala:6:7, :21:21] reg [67:0] stages_1_dram_addr; // @[Pipeline.scala:21:21] assign io_out_bits_dram_addr_0 = stages_1_dram_addr; // @[Pipeline.scala:6:7, :21:21] reg [63:0] stages_1_spad_addr; // @[Pipeline.scala:21:21] assign io_out_bits_spad_addr_0 = stages_1_spad_addr; // @[Pipeline.scala:6:7, :21:21] reg [15:0] stages_1_K; // @[Pipeline.scala:21:21] assign io_out_bits_K_0 = stages_1_K; // @[Pipeline.scala:6:7, :21:21] reg [15:0] stages_1_J; // @[Pipeline.scala:21:21] assign io_out_bits_J_0 = stages_1_J; // @[Pipeline.scala:6:7, :21:21] reg valids_0; // @[Pipeline.scala:22:25] reg valids_1; // @[Pipeline.scala:22:25] assign io_out_valid_0 = valids_1; // @[Pipeline.scala:6:7, :22:25] wire _stalling_0_T; // @[Pipeline.scala:30:16] wire _stalling_1_T_1; // @[Pipeline.scala:28:34] wire stalling_0; // @[Pipeline.scala:23:27] wire stalling_1; // @[Pipeline.scala:23:27] wire _io_busy_T = valids_0 | valids_1; // @[Pipeline.scala:22:25, :24:46] assign _io_busy_T_1 = io_in_valid_0 | _io_busy_T; // @[Pipeline.scala:6:7, :24:{28,46}] assign io_busy_0 = _io_busy_T_1; // @[Pipeline.scala:6:7, :24:28] assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20] assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20] wire _stalling_1_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37] assign _stalling_1_T_1 = valids_1 & _stalling_1_T; // @[Pipeline.scala:22:25, :28:{34,37}] assign stalling_1 = _stalling_1_T_1; // @[Pipeline.scala:23:27, :28:34] assign _stalling_0_T = valids_0 & stalling_1; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_0 = _stalling_0_T; // @[Pipeline.scala:23:27, :30:16] wire _T_2 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Pipeline.scala:6:7] if (_T_2) begin // @[Decoupled.scala:51:35] stages_0_cmd_inst_funct <= io_in_bits_cmd_inst_funct_0; // @[Pipeline.scala:6:7, :21:21] stages_0_cmd_rs1 <= io_in_bits_cmd_rs1_0; // @[Pipeline.scala:6:7, :21:21] stages_0_cmd_rs2 <= io_in_bits_cmd_rs2_0; // @[Pipeline.scala:6:7, :21:21] stages_0_dram_addr <= io_in_bits_dram_addr_0; // @[Pipeline.scala:6:7, :21:21] stages_0_spad_addr <= io_in_bits_spad_addr_0; // @[Pipeline.scala:6:7, :21:21] stages_0_K <= io_in_bits_K_0; // @[Pipeline.scala:6:7, :21:21] stages_0_J <= io_in_bits_J_0; // @[Pipeline.scala:6:7, :21:21] end if (stalling_1) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_1_cmd_inst_funct <= stages_0_cmd_inst_funct; // @[Pipeline.scala:21:21] stages_1_cmd_inst_rs2 <= 5'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_inst_rs1 <= 5'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_inst_rd <= 5'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_inst_opcode <= 7'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_rs1 <= stages_0_cmd_rs1; // @[Pipeline.scala:21:21] stages_1_cmd_rs2 <= stages_0_cmd_rs2; // @[Pipeline.scala:21:21] stages_1_cmd_status_isa <= 32'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_dprv <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_prv <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_zero2 <= 23'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_sxl <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_uxl <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_zero1 <= 8'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_xs <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_fs <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_mpp <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_vs <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_dram_addr <= stages_0_dram_addr; // @[Pipeline.scala:21:21] stages_1_spad_addr <= stages_0_spad_addr; // @[Pipeline.scala:21:21] stages_1_K <= stages_0_K; // @[Pipeline.scala:21:21] stages_1_J <= stages_0_J; // @[Pipeline.scala:21:21] end stages_1_cmd_inst_xd <= stalling_1 & stages_1_cmd_inst_xd; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_inst_xs1 <= stalling_1 & stages_1_cmd_inst_xs1; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_inst_xs2 <= stalling_1 & stages_1_cmd_inst_xs2; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_debug <= stalling_1 & stages_1_cmd_status_debug; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_cease <= stalling_1 & stages_1_cmd_status_cease; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_wfi <= stalling_1 & stages_1_cmd_status_wfi; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_dv <= stalling_1 & stages_1_cmd_status_dv; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_v <= stalling_1 & stages_1_cmd_status_v; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sd <= stalling_1 & stages_1_cmd_status_sd; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mpv <= stalling_1 & stages_1_cmd_status_mpv; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_gva <= stalling_1 & stages_1_cmd_status_gva; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mbe <= stalling_1 & stages_1_cmd_status_mbe; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sbe <= stalling_1 & stages_1_cmd_status_sbe; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sd_rv32 <= stalling_1 & stages_1_cmd_status_sd_rv32; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_tsr <= stalling_1 & stages_1_cmd_status_tsr; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_tw <= stalling_1 & stages_1_cmd_status_tw; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_tvm <= stalling_1 & stages_1_cmd_status_tvm; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mxr <= stalling_1 & stages_1_cmd_status_mxr; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sum <= stalling_1 & stages_1_cmd_status_sum; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mprv <= stalling_1 & stages_1_cmd_status_mprv; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_spp <= stalling_1 & stages_1_cmd_status_spp; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mpie <= stalling_1 & stages_1_cmd_status_mpie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_ube <= stalling_1 & stages_1_cmd_status_ube; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_spie <= stalling_1 & stages_1_cmd_status_spie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_upie <= stalling_1 & stages_1_cmd_status_upie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mie <= stalling_1 & stages_1_cmd_status_mie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_hie <= stalling_1 & stages_1_cmd_status_hie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sie <= stalling_1 & stages_1_cmd_status_sie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_uie <= stalling_1 & stages_1_cmd_status_uie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] if (reset) begin // @[Pipeline.scala:6:7] valids_0 <= 1'h0; // @[Pipeline.scala:22:25] valids_1 <= 1'h0; // @[Pipeline.scala:22:25] end else begin // @[Pipeline.scala:6:7] valids_0 <= _T_2 | stalling_1 & valids_0; // @[Decoupled.scala:51:35] valids_1 <= valids_0 | ~io_out_ready_0 & valids_1; // @[Pipeline.scala:6:7, :22:25, :36:24, :37:19, :49:16, :50:12] end always @(posedge) assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7] assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_funct = io_out_bits_cmd_inst_funct_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_rs2 = io_out_bits_cmd_inst_rs2_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_rs1 = io_out_bits_cmd_inst_rs1_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_xd = io_out_bits_cmd_inst_xd_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_xs1 = io_out_bits_cmd_inst_xs1_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_xs2 = io_out_bits_cmd_inst_xs2_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_rd = io_out_bits_cmd_inst_rd_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_opcode = io_out_bits_cmd_inst_opcode_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_rs1 = io_out_bits_cmd_rs1_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_rs2 = io_out_bits_cmd_rs2_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_debug = io_out_bits_cmd_status_debug_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_cease = io_out_bits_cmd_status_cease_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_wfi = io_out_bits_cmd_status_wfi_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_isa = io_out_bits_cmd_status_isa_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_dprv = io_out_bits_cmd_status_dprv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_dv = io_out_bits_cmd_status_dv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_prv = io_out_bits_cmd_status_prv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_v = io_out_bits_cmd_status_v_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sd = io_out_bits_cmd_status_sd_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_zero2 = io_out_bits_cmd_status_zero2_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mpv = io_out_bits_cmd_status_mpv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_gva = io_out_bits_cmd_status_gva_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mbe = io_out_bits_cmd_status_mbe_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sbe = io_out_bits_cmd_status_sbe_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sxl = io_out_bits_cmd_status_sxl_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_uxl = io_out_bits_cmd_status_uxl_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sd_rv32 = io_out_bits_cmd_status_sd_rv32_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_zero1 = io_out_bits_cmd_status_zero1_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_tsr = io_out_bits_cmd_status_tsr_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_tw = io_out_bits_cmd_status_tw_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_tvm = io_out_bits_cmd_status_tvm_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mxr = io_out_bits_cmd_status_mxr_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sum = io_out_bits_cmd_status_sum_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mprv = io_out_bits_cmd_status_mprv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_xs = io_out_bits_cmd_status_xs_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_fs = io_out_bits_cmd_status_fs_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mpp = io_out_bits_cmd_status_mpp_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_vs = io_out_bits_cmd_status_vs_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_spp = io_out_bits_cmd_status_spp_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mpie = io_out_bits_cmd_status_mpie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_ube = io_out_bits_cmd_status_ube_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_spie = io_out_bits_cmd_status_spie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_upie = io_out_bits_cmd_status_upie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mie = io_out_bits_cmd_status_mie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_hie = io_out_bits_cmd_status_hie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sie = io_out_bits_cmd_status_sie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_uie = io_out_bits_cmd_status_uie_0; // @[Pipeline.scala:6:7] assign io_out_bits_dram_addr = io_out_bits_dram_addr_0; // @[Pipeline.scala:6:7] assign io_out_bits_spad_addr = io_out_bits_spad_addr_0; // @[Pipeline.scala:6:7] assign io_out_bits_K = io_out_bits_K_0; // @[Pipeline.scala:6:7] assign io_out_bits_J = io_out_bits_J_0; // @[Pipeline.scala:6:7] assign io_busy = io_busy_0; // @[Pipeline.scala:6:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_379( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_123 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_141( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File UserYanker.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.amba.axi4 import chisel3._ import chisel3.util.{Queue, QueueIO, UIntToOH} import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp} import freechips.rocketchip.util.BundleMap /** This adapter prunes all user bit fields of the echo type from request messages, * storing them in queues and echoing them back when matching response messages are received. * * It also optionally rate limits the number of transactions that can be in flight simultaneously * per FIFO domain / A[W|R]ID. * * @param capMaxFlight is an optional maximum number of transactions that can be in flight per A[W|R]ID. */ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) extends LazyModule { val node = AXI4AdapterNode( masterFn = { mp => mp.copy( masters = mp.masters.map { m => m.copy( maxFlight = (m.maxFlight, capMaxFlight) match { case (Some(x), Some(y)) => Some(x min y) case (Some(x), None) => Some(x) case (None, Some(y)) => Some(y) case (None, None) => None })}, echoFields = Nil)}, slaveFn = { sp => sp }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // Which fields are we stripping? val echoFields = edgeIn.master.echoFields val need_bypass = edgeOut.slave.minLatency < 1 edgeOut.master.masters.foreach { m => require (m.maxFlight.isDefined, "UserYanker needs a flight cap on each ID") } def queue(id: Int) = { val depth = edgeOut.master.masters.find(_.id.contains(id)).flatMap(_.maxFlight).getOrElse(0) if (depth == 0) { Wire(new QueueIO(BundleMap(echoFields), 1)) // unused ID => undefined value } else { Module(new Queue(BundleMap(echoFields), depth, flow=need_bypass)).io } } val rqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) } val wqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) } val arid = in.ar.bits.id val ar_ready = VecInit(rqueues.map(_.enq.ready))(arid) in .ar.ready := out.ar.ready && ar_ready out.ar.valid := in .ar.valid && ar_ready Connectable.waiveUnmatched(out.ar.bits, in.ar.bits) match { case (lhs, rhs) => lhs :<= rhs } val rid = out.r.bits.id val r_valid = VecInit(rqueues.map(_.deq.valid))(rid) val r_bits = VecInit(rqueues.map(_.deq.bits))(rid) assert (!out.r.valid || r_valid) // Q must be ready faster than the response Connectable.waiveUnmatched(in.r, out.r) match { case (lhs, rhs) => lhs :<>= rhs } in.r.bits.echo :<= r_bits val arsel = UIntToOH(arid, edgeIn.master.endId).asBools val rsel = UIntToOH(rid, edgeIn.master.endId).asBools (rqueues zip (arsel zip rsel)) foreach { case (q, (ar, r)) => q.deq.ready := out.r .valid && in .r .ready && r && out.r.bits.last q.deq.valid := DontCare q.deq.bits := DontCare q.enq.valid := in .ar.valid && out.ar.ready && ar q.enq.ready := DontCare q.enq.bits :<>= in.ar.bits.echo q.count := DontCare } val awid = in.aw.bits.id val aw_ready = VecInit(wqueues.map(_.enq.ready))(awid) in .aw.ready := out.aw.ready && aw_ready out.aw.valid := in .aw.valid && aw_ready Connectable.waiveUnmatched(out.aw.bits, in.aw.bits) match { case (lhs, rhs) => lhs :<>= rhs } val bid = out.b.bits.id val b_valid = VecInit(wqueues.map(_.deq.valid))(bid) val b_bits = VecInit(wqueues.map(_.deq.bits))(bid) assert (!out.b.valid || b_valid) // Q must be ready faster than the response Connectable.waiveUnmatched(in.b, out.b) match { case (lhs, rhs) => lhs :<>= rhs } in.b.bits.echo :<>= b_bits val awsel = UIntToOH(awid, edgeIn.master.endId).asBools val bsel = UIntToOH(bid, edgeIn.master.endId).asBools (wqueues zip (awsel zip bsel)) foreach { case (q, (aw, b)) => q.deq.ready := out.b .valid && in .b .ready && b q.deq.valid := DontCare q.deq.bits := DontCare q.enq.valid := in .aw.valid && out.aw.ready && aw q.enq.ready := DontCare q.enq.bits :<>= in.aw.bits.echo q.count := DontCare } out.w :<>= in.w } } } object AXI4UserYanker { def apply(capMaxFlight: Option[Int] = None)(implicit p: Parameters): AXI4Node = { val axi4yank = LazyModule(new AXI4UserYanker(capMaxFlight)) axi4yank.node } }
module AXI4UserYanker( // @[UserYanker.scala:36:9] input clock, // @[UserYanker.scala:36:9] input reset, // @[UserYanker.scala:36:9] output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25] input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_w_ready, // @[LazyModuleImp.scala:107:25] input auto_in_w_valid, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25] input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25] input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] input auto_in_r_ready, // @[LazyModuleImp.scala:107:25] output auto_in_r_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); wire auto_in_aw_valid_0 = auto_in_aw_valid; // @[UserYanker.scala:36:9] wire [3:0] auto_in_aw_bits_id_0 = auto_in_aw_bits_id; // @[UserYanker.scala:36:9] wire [31:0] auto_in_aw_bits_addr_0 = auto_in_aw_bits_addr; // @[UserYanker.scala:36:9] wire [7:0] auto_in_aw_bits_len_0 = auto_in_aw_bits_len; // @[UserYanker.scala:36:9] wire [2:0] auto_in_aw_bits_size_0 = auto_in_aw_bits_size; // @[UserYanker.scala:36:9] wire [1:0] auto_in_aw_bits_burst_0 = auto_in_aw_bits_burst; // @[UserYanker.scala:36:9] wire auto_in_aw_bits_lock_0 = auto_in_aw_bits_lock; // @[UserYanker.scala:36:9] wire [3:0] auto_in_aw_bits_cache_0 = auto_in_aw_bits_cache; // @[UserYanker.scala:36:9] wire [2:0] auto_in_aw_bits_prot_0 = auto_in_aw_bits_prot; // @[UserYanker.scala:36:9] wire [3:0] auto_in_aw_bits_qos_0 = auto_in_aw_bits_qos; // @[UserYanker.scala:36:9] wire [3:0] auto_in_aw_bits_echo_tl_state_size_0 = auto_in_aw_bits_echo_tl_state_size; // @[UserYanker.scala:36:9] wire [4:0] auto_in_aw_bits_echo_tl_state_source_0 = auto_in_aw_bits_echo_tl_state_source; // @[UserYanker.scala:36:9] wire auto_in_aw_bits_echo_extra_id_0 = auto_in_aw_bits_echo_extra_id; // @[UserYanker.scala:36:9] wire auto_in_w_valid_0 = auto_in_w_valid; // @[UserYanker.scala:36:9] wire [63:0] auto_in_w_bits_data_0 = auto_in_w_bits_data; // @[UserYanker.scala:36:9] wire [7:0] auto_in_w_bits_strb_0 = auto_in_w_bits_strb; // @[UserYanker.scala:36:9] wire auto_in_w_bits_last_0 = auto_in_w_bits_last; // @[UserYanker.scala:36:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[UserYanker.scala:36:9] wire auto_in_ar_valid_0 = auto_in_ar_valid; // @[UserYanker.scala:36:9] wire [3:0] auto_in_ar_bits_id_0 = auto_in_ar_bits_id; // @[UserYanker.scala:36:9] wire [31:0] auto_in_ar_bits_addr_0 = auto_in_ar_bits_addr; // @[UserYanker.scala:36:9] wire [7:0] auto_in_ar_bits_len_0 = auto_in_ar_bits_len; // @[UserYanker.scala:36:9] wire [2:0] auto_in_ar_bits_size_0 = auto_in_ar_bits_size; // @[UserYanker.scala:36:9] wire [1:0] auto_in_ar_bits_burst_0 = auto_in_ar_bits_burst; // @[UserYanker.scala:36:9] wire auto_in_ar_bits_lock_0 = auto_in_ar_bits_lock; // @[UserYanker.scala:36:9] wire [3:0] auto_in_ar_bits_cache_0 = auto_in_ar_bits_cache; // @[UserYanker.scala:36:9] wire [2:0] auto_in_ar_bits_prot_0 = auto_in_ar_bits_prot; // @[UserYanker.scala:36:9] wire [3:0] auto_in_ar_bits_qos_0 = auto_in_ar_bits_qos; // @[UserYanker.scala:36:9] wire [3:0] auto_in_ar_bits_echo_tl_state_size_0 = auto_in_ar_bits_echo_tl_state_size; // @[UserYanker.scala:36:9] wire [4:0] auto_in_ar_bits_echo_tl_state_source_0 = auto_in_ar_bits_echo_tl_state_source; // @[UserYanker.scala:36:9] wire auto_in_ar_bits_echo_extra_id_0 = auto_in_ar_bits_echo_extra_id; // @[UserYanker.scala:36:9] wire auto_in_r_ready_0 = auto_in_r_ready; // @[UserYanker.scala:36:9] wire auto_out_aw_ready_0 = auto_out_aw_ready; // @[UserYanker.scala:36:9] wire auto_out_w_ready_0 = auto_out_w_ready; // @[UserYanker.scala:36:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[UserYanker.scala:36:9] wire [3:0] auto_out_b_bits_id_0 = auto_out_b_bits_id; // @[UserYanker.scala:36:9] wire [1:0] auto_out_b_bits_resp_0 = auto_out_b_bits_resp; // @[UserYanker.scala:36:9] wire auto_out_ar_ready_0 = auto_out_ar_ready; // @[UserYanker.scala:36:9] wire auto_out_r_valid_0 = auto_out_r_valid; // @[UserYanker.scala:36:9] wire [3:0] auto_out_r_bits_id_0 = auto_out_r_bits_id; // @[UserYanker.scala:36:9] wire [63:0] auto_out_r_bits_data_0 = auto_out_r_bits_data; // @[UserYanker.scala:36:9] wire [1:0] auto_out_r_bits_resp_0 = auto_out_r_bits_resp; // @[UserYanker.scala:36:9] wire auto_out_r_bits_last_0 = auto_out_r_bits_last; // @[UserYanker.scala:36:9] wire nodeIn_aw_ready; // @[MixedNode.scala:551:17] wire nodeIn_aw_valid = auto_in_aw_valid_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_aw_bits_id = auto_in_aw_bits_id_0; // @[UserYanker.scala:36:9] wire [31:0] nodeIn_aw_bits_addr = auto_in_aw_bits_addr_0; // @[UserYanker.scala:36:9] wire [7:0] nodeIn_aw_bits_len = auto_in_aw_bits_len_0; // @[UserYanker.scala:36:9] wire [2:0] nodeIn_aw_bits_size = auto_in_aw_bits_size_0; // @[UserYanker.scala:36:9] wire [1:0] nodeIn_aw_bits_burst = auto_in_aw_bits_burst_0; // @[UserYanker.scala:36:9] wire nodeIn_aw_bits_lock = auto_in_aw_bits_lock_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_aw_bits_cache = auto_in_aw_bits_cache_0; // @[UserYanker.scala:36:9] wire [2:0] nodeIn_aw_bits_prot = auto_in_aw_bits_prot_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_aw_bits_qos = auto_in_aw_bits_qos_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_aw_bits_echo_tl_state_size = auto_in_aw_bits_echo_tl_state_size_0; // @[UserYanker.scala:36:9] wire [4:0] nodeIn_aw_bits_echo_tl_state_source = auto_in_aw_bits_echo_tl_state_source_0; // @[UserYanker.scala:36:9] wire nodeIn_aw_bits_echo_extra_id = auto_in_aw_bits_echo_extra_id_0; // @[UserYanker.scala:36:9] wire nodeIn_w_ready; // @[MixedNode.scala:551:17] wire nodeIn_w_valid = auto_in_w_valid_0; // @[UserYanker.scala:36:9] wire [63:0] nodeIn_w_bits_data = auto_in_w_bits_data_0; // @[UserYanker.scala:36:9] wire [7:0] nodeIn_w_bits_strb = auto_in_w_bits_strb_0; // @[UserYanker.scala:36:9] wire nodeIn_w_bits_last = auto_in_w_bits_last_0; // @[UserYanker.scala:36:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[UserYanker.scala:36:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_id; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_resp; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_echo_tl_state_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_b_bits_echo_tl_state_source; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_echo_extra_id; // @[MixedNode.scala:551:17] wire nodeIn_ar_ready; // @[MixedNode.scala:551:17] wire nodeIn_ar_valid = auto_in_ar_valid_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_ar_bits_id = auto_in_ar_bits_id_0; // @[UserYanker.scala:36:9] wire [31:0] nodeIn_ar_bits_addr = auto_in_ar_bits_addr_0; // @[UserYanker.scala:36:9] wire [7:0] nodeIn_ar_bits_len = auto_in_ar_bits_len_0; // @[UserYanker.scala:36:9] wire [2:0] nodeIn_ar_bits_size = auto_in_ar_bits_size_0; // @[UserYanker.scala:36:9] wire [1:0] nodeIn_ar_bits_burst = auto_in_ar_bits_burst_0; // @[UserYanker.scala:36:9] wire nodeIn_ar_bits_lock = auto_in_ar_bits_lock_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_ar_bits_cache = auto_in_ar_bits_cache_0; // @[UserYanker.scala:36:9] wire [2:0] nodeIn_ar_bits_prot = auto_in_ar_bits_prot_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_ar_bits_qos = auto_in_ar_bits_qos_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_ar_bits_echo_tl_state_size = auto_in_ar_bits_echo_tl_state_size_0; // @[UserYanker.scala:36:9] wire [4:0] nodeIn_ar_bits_echo_tl_state_source = auto_in_ar_bits_echo_tl_state_source_0; // @[UserYanker.scala:36:9] wire nodeIn_ar_bits_echo_extra_id = auto_in_ar_bits_echo_extra_id_0; // @[UserYanker.scala:36:9] wire nodeIn_r_ready = auto_in_r_ready_0; // @[UserYanker.scala:36:9] wire nodeIn_r_valid; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_r_bits_id; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_r_bits_data; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_r_bits_resp; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_r_bits_echo_tl_state_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_r_bits_echo_tl_state_source; // @[MixedNode.scala:551:17] wire nodeIn_r_bits_echo_extra_id; // @[MixedNode.scala:551:17] wire nodeIn_r_bits_last; // @[MixedNode.scala:551:17] wire nodeOut_aw_ready = auto_out_aw_ready_0; // @[UserYanker.scala:36:9] wire nodeOut_aw_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_aw_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_aw_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_aw_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_aw_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_qos; // @[MixedNode.scala:542:17] wire nodeOut_w_ready = auto_out_w_ready_0; // @[UserYanker.scala:36:9] wire nodeOut_w_valid; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_w_bits_data; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_w_bits_strb; // @[MixedNode.scala:542:17] wire nodeOut_w_bits_last; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[UserYanker.scala:36:9] wire [3:0] nodeOut_b_bits_id = auto_out_b_bits_id_0; // @[UserYanker.scala:36:9] wire [1:0] nodeOut_b_bits_resp = auto_out_b_bits_resp_0; // @[UserYanker.scala:36:9] wire nodeOut_ar_ready = auto_out_ar_ready_0; // @[UserYanker.scala:36:9] wire nodeOut_ar_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_ar_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_ar_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_ar_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_ar_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_qos; // @[MixedNode.scala:542:17] wire nodeOut_r_ready; // @[MixedNode.scala:542:17] wire nodeOut_r_valid = auto_out_r_valid_0; // @[UserYanker.scala:36:9] wire [3:0] nodeOut_r_bits_id = auto_out_r_bits_id_0; // @[UserYanker.scala:36:9] wire [63:0] nodeOut_r_bits_data = auto_out_r_bits_data_0; // @[UserYanker.scala:36:9] wire [1:0] nodeOut_r_bits_resp = auto_out_r_bits_resp_0; // @[UserYanker.scala:36:9] wire nodeOut_r_bits_last = auto_out_r_bits_last_0; // @[UserYanker.scala:36:9] wire auto_in_aw_ready_0; // @[UserYanker.scala:36:9] wire auto_in_w_ready_0; // @[UserYanker.scala:36:9] wire [3:0] auto_in_b_bits_echo_tl_state_size_0; // @[UserYanker.scala:36:9] wire [4:0] auto_in_b_bits_echo_tl_state_source_0; // @[UserYanker.scala:36:9] wire auto_in_b_bits_echo_extra_id_0; // @[UserYanker.scala:36:9] wire [3:0] auto_in_b_bits_id_0; // @[UserYanker.scala:36:9] wire [1:0] auto_in_b_bits_resp_0; // @[UserYanker.scala:36:9] wire auto_in_b_valid_0; // @[UserYanker.scala:36:9] wire auto_in_ar_ready_0; // @[UserYanker.scala:36:9] wire [3:0] auto_in_r_bits_echo_tl_state_size_0; // @[UserYanker.scala:36:9] wire [4:0] auto_in_r_bits_echo_tl_state_source_0; // @[UserYanker.scala:36:9] wire auto_in_r_bits_echo_extra_id_0; // @[UserYanker.scala:36:9] wire [3:0] auto_in_r_bits_id_0; // @[UserYanker.scala:36:9] wire [63:0] auto_in_r_bits_data_0; // @[UserYanker.scala:36:9] wire [1:0] auto_in_r_bits_resp_0; // @[UserYanker.scala:36:9] wire auto_in_r_bits_last_0; // @[UserYanker.scala:36:9] wire auto_in_r_valid_0; // @[UserYanker.scala:36:9] wire [3:0] auto_out_aw_bits_id_0; // @[UserYanker.scala:36:9] wire [31:0] auto_out_aw_bits_addr_0; // @[UserYanker.scala:36:9] wire [7:0] auto_out_aw_bits_len_0; // @[UserYanker.scala:36:9] wire [2:0] auto_out_aw_bits_size_0; // @[UserYanker.scala:36:9] wire [1:0] auto_out_aw_bits_burst_0; // @[UserYanker.scala:36:9] wire auto_out_aw_bits_lock_0; // @[UserYanker.scala:36:9] wire [3:0] auto_out_aw_bits_cache_0; // @[UserYanker.scala:36:9] wire [2:0] auto_out_aw_bits_prot_0; // @[UserYanker.scala:36:9] wire [3:0] auto_out_aw_bits_qos_0; // @[UserYanker.scala:36:9] wire auto_out_aw_valid_0; // @[UserYanker.scala:36:9] wire [63:0] auto_out_w_bits_data_0; // @[UserYanker.scala:36:9] wire [7:0] auto_out_w_bits_strb_0; // @[UserYanker.scala:36:9] wire auto_out_w_bits_last_0; // @[UserYanker.scala:36:9] wire auto_out_w_valid_0; // @[UserYanker.scala:36:9] wire auto_out_b_ready_0; // @[UserYanker.scala:36:9] wire [3:0] auto_out_ar_bits_id_0; // @[UserYanker.scala:36:9] wire [31:0] auto_out_ar_bits_addr_0; // @[UserYanker.scala:36:9] wire [7:0] auto_out_ar_bits_len_0; // @[UserYanker.scala:36:9] wire [2:0] auto_out_ar_bits_size_0; // @[UserYanker.scala:36:9] wire [1:0] auto_out_ar_bits_burst_0; // @[UserYanker.scala:36:9] wire auto_out_ar_bits_lock_0; // @[UserYanker.scala:36:9] wire [3:0] auto_out_ar_bits_cache_0; // @[UserYanker.scala:36:9] wire [2:0] auto_out_ar_bits_prot_0; // @[UserYanker.scala:36:9] wire [3:0] auto_out_ar_bits_qos_0; // @[UserYanker.scala:36:9] wire auto_out_ar_valid_0; // @[UserYanker.scala:36:9] wire auto_out_r_ready_0; // @[UserYanker.scala:36:9] wire _nodeIn_aw_ready_T; // @[UserYanker.scala:89:36] assign auto_in_aw_ready_0 = nodeIn_aw_ready; // @[UserYanker.scala:36:9] assign nodeOut_aw_bits_id = nodeIn_aw_bits_id; // @[MixedNode.scala:542:17, :551:17] wire [3:0] awsel_shiftAmount = nodeIn_aw_bits_id; // @[OneHot.scala:64:49] assign nodeOut_aw_bits_addr = nodeIn_aw_bits_addr; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_len = nodeIn_aw_bits_len; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_size = nodeIn_aw_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_burst = nodeIn_aw_bits_burst; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_lock = nodeIn_aw_bits_lock; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_cache = nodeIn_aw_bits_cache; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_prot = nodeIn_aw_bits_prot; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_qos = nodeIn_aw_bits_qos; // @[MixedNode.scala:542:17, :551:17] assign auto_in_w_ready_0 = nodeIn_w_ready; // @[UserYanker.scala:36:9] assign nodeOut_w_valid = nodeIn_w_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_data = nodeIn_w_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_strb = nodeIn_w_bits_strb; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_last = nodeIn_w_bits_last; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[UserYanker.scala:36:9] assign auto_in_b_bits_id_0 = nodeIn_b_bits_id; // @[UserYanker.scala:36:9] assign auto_in_b_bits_resp_0 = nodeIn_b_bits_resp; // @[UserYanker.scala:36:9] assign auto_in_b_bits_echo_tl_state_size_0 = nodeIn_b_bits_echo_tl_state_size; // @[UserYanker.scala:36:9] assign auto_in_b_bits_echo_tl_state_source_0 = nodeIn_b_bits_echo_tl_state_source; // @[UserYanker.scala:36:9] assign auto_in_b_bits_echo_extra_id_0 = nodeIn_b_bits_echo_extra_id; // @[UserYanker.scala:36:9] wire _nodeIn_ar_ready_T; // @[UserYanker.scala:60:36] assign auto_in_ar_ready_0 = nodeIn_ar_ready; // @[UserYanker.scala:36:9] assign nodeOut_ar_bits_id = nodeIn_ar_bits_id; // @[MixedNode.scala:542:17, :551:17] wire [3:0] arsel_shiftAmount = nodeIn_ar_bits_id; // @[OneHot.scala:64:49] assign nodeOut_ar_bits_addr = nodeIn_ar_bits_addr; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_len = nodeIn_ar_bits_len; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_size = nodeIn_ar_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_burst = nodeIn_ar_bits_burst; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_lock = nodeIn_ar_bits_lock; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_cache = nodeIn_ar_bits_cache; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_prot = nodeIn_ar_bits_prot; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_qos = nodeIn_ar_bits_qos; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_r_ready = nodeIn_r_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_r_valid_0 = nodeIn_r_valid; // @[UserYanker.scala:36:9] assign auto_in_r_bits_id_0 = nodeIn_r_bits_id; // @[UserYanker.scala:36:9] assign auto_in_r_bits_data_0 = nodeIn_r_bits_data; // @[UserYanker.scala:36:9] assign auto_in_r_bits_resp_0 = nodeIn_r_bits_resp; // @[UserYanker.scala:36:9] assign auto_in_r_bits_echo_tl_state_size_0 = nodeIn_r_bits_echo_tl_state_size; // @[UserYanker.scala:36:9] assign auto_in_r_bits_echo_tl_state_source_0 = nodeIn_r_bits_echo_tl_state_source; // @[UserYanker.scala:36:9] assign auto_in_r_bits_echo_extra_id_0 = nodeIn_r_bits_echo_extra_id; // @[UserYanker.scala:36:9] assign auto_in_r_bits_last_0 = nodeIn_r_bits_last; // @[UserYanker.scala:36:9] wire _nodeOut_aw_valid_T; // @[UserYanker.scala:90:36] assign auto_out_aw_valid_0 = nodeOut_aw_valid; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_id_0 = nodeOut_aw_bits_id; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_addr_0 = nodeOut_aw_bits_addr; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_len_0 = nodeOut_aw_bits_len; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_size_0 = nodeOut_aw_bits_size; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_burst_0 = nodeOut_aw_bits_burst; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_lock_0 = nodeOut_aw_bits_lock; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_cache_0 = nodeOut_aw_bits_cache; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_prot_0 = nodeOut_aw_bits_prot; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_qos_0 = nodeOut_aw_bits_qos; // @[UserYanker.scala:36:9] assign nodeIn_w_ready = nodeOut_w_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_w_valid_0 = nodeOut_w_valid; // @[UserYanker.scala:36:9] assign auto_out_w_bits_data_0 = nodeOut_w_bits_data; // @[UserYanker.scala:36:9] assign auto_out_w_bits_strb_0 = nodeOut_w_bits_strb; // @[UserYanker.scala:36:9] assign auto_out_w_bits_last_0 = nodeOut_w_bits_last; // @[UserYanker.scala:36:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[UserYanker.scala:36:9] assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_id = nodeOut_b_bits_id; // @[MixedNode.scala:542:17, :551:17] wire [3:0] bsel_shiftAmount = nodeOut_b_bits_id; // @[OneHot.scala:64:49] assign nodeIn_b_bits_resp = nodeOut_b_bits_resp; // @[MixedNode.scala:542:17, :551:17] wire _nodeOut_ar_valid_T; // @[UserYanker.scala:61:36] assign auto_out_ar_valid_0 = nodeOut_ar_valid; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_id_0 = nodeOut_ar_bits_id; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_addr_0 = nodeOut_ar_bits_addr; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_len_0 = nodeOut_ar_bits_len; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_size_0 = nodeOut_ar_bits_size; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_burst_0 = nodeOut_ar_bits_burst; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_lock_0 = nodeOut_ar_bits_lock; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_cache_0 = nodeOut_ar_bits_cache; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_prot_0 = nodeOut_ar_bits_prot; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_qos_0 = nodeOut_ar_bits_qos; // @[UserYanker.scala:36:9] assign auto_out_r_ready_0 = nodeOut_r_ready; // @[UserYanker.scala:36:9] assign nodeIn_r_valid = nodeOut_r_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_id = nodeOut_r_bits_id; // @[MixedNode.scala:542:17, :551:17] wire [3:0] rsel_shiftAmount = nodeOut_r_bits_id; // @[OneHot.scala:64:49] assign nodeIn_r_bits_data = nodeOut_r_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_resp = nodeOut_r_bits_resp; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_last = nodeOut_r_bits_last; // @[MixedNode.scala:542:17, :551:17] wire _ar_ready_WIRE_0; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_1; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_2; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_3; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_4; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_5; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_6; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_7; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_8; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_9; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_10; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_11; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_12; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_13; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_14; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_15; // @[UserYanker.scala:59:29] wire [15:0] _GEN = {{_ar_ready_WIRE_15}, {_ar_ready_WIRE_14}, {_ar_ready_WIRE_13}, {_ar_ready_WIRE_12}, {_ar_ready_WIRE_11}, {_ar_ready_WIRE_10}, {_ar_ready_WIRE_9}, {_ar_ready_WIRE_8}, {_ar_ready_WIRE_7}, {_ar_ready_WIRE_6}, {_ar_ready_WIRE_5}, {_ar_ready_WIRE_4}, {_ar_ready_WIRE_3}, {_ar_ready_WIRE_2}, {_ar_ready_WIRE_1}, {_ar_ready_WIRE_0}}; // @[UserYanker.scala:59:29, :60:36] assign _nodeIn_ar_ready_T = nodeOut_ar_ready & _GEN[nodeIn_ar_bits_id]; // @[UserYanker.scala:60:36] assign nodeIn_ar_ready = _nodeIn_ar_ready_T; // @[UserYanker.scala:60:36] assign _nodeOut_ar_valid_T = nodeIn_ar_valid & _GEN[nodeIn_ar_bits_id]; // @[UserYanker.scala:60:36, :61:36] assign nodeOut_ar_valid = _nodeOut_ar_valid_T; // @[UserYanker.scala:61:36] wire [3:0] _r_bits_WIRE_0_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_1_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_2_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_3_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_4_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_5_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_6_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_7_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_8_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_9_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_10_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_11_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_12_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_13_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_14_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_15_tl_state_size; // @[UserYanker.scala:68:27] wire [15:0][3:0] _GEN_0 = {{_r_bits_WIRE_15_tl_state_size}, {_r_bits_WIRE_14_tl_state_size}, {_r_bits_WIRE_13_tl_state_size}, {_r_bits_WIRE_12_tl_state_size}, {_r_bits_WIRE_11_tl_state_size}, {_r_bits_WIRE_10_tl_state_size}, {_r_bits_WIRE_9_tl_state_size}, {_r_bits_WIRE_8_tl_state_size}, {_r_bits_WIRE_7_tl_state_size}, {_r_bits_WIRE_6_tl_state_size}, {_r_bits_WIRE_5_tl_state_size}, {_r_bits_WIRE_4_tl_state_size}, {_r_bits_WIRE_3_tl_state_size}, {_r_bits_WIRE_2_tl_state_size}, {_r_bits_WIRE_1_tl_state_size}, {_r_bits_WIRE_0_tl_state_size}}; // @[UserYanker.scala:68:27, :73:22] assign nodeIn_r_bits_echo_tl_state_size = _GEN_0[nodeOut_r_bits_id]; // @[UserYanker.scala:73:22] wire [4:0] _r_bits_WIRE_0_tl_state_source; // @[UserYanker.scala:68:27] wire [4:0] _r_bits_WIRE_1_tl_state_source; // @[UserYanker.scala:68:27] wire [4:0] _r_bits_WIRE_2_tl_state_source; // @[UserYanker.scala:68:27] wire [4:0] _r_bits_WIRE_3_tl_state_source; // @[UserYanker.scala:68:27] wire [4:0] _r_bits_WIRE_4_tl_state_source; // @[UserYanker.scala:68:27] wire [4:0] _r_bits_WIRE_5_tl_state_source; // @[UserYanker.scala:68:27] wire [4:0] _r_bits_WIRE_6_tl_state_source; // @[UserYanker.scala:68:27] wire [4:0] _r_bits_WIRE_7_tl_state_source; // @[UserYanker.scala:68:27] wire [4:0] _r_bits_WIRE_8_tl_state_source; // @[UserYanker.scala:68:27] wire [4:0] _r_bits_WIRE_9_tl_state_source; // @[UserYanker.scala:68:27] wire [4:0] _r_bits_WIRE_10_tl_state_source; // @[UserYanker.scala:68:27] wire [4:0] _r_bits_WIRE_11_tl_state_source; // @[UserYanker.scala:68:27] wire [4:0] _r_bits_WIRE_12_tl_state_source; // @[UserYanker.scala:68:27] wire [4:0] _r_bits_WIRE_13_tl_state_source; // @[UserYanker.scala:68:27] wire [4:0] _r_bits_WIRE_14_tl_state_source; // @[UserYanker.scala:68:27] wire [4:0] _r_bits_WIRE_15_tl_state_source; // @[UserYanker.scala:68:27] wire [15:0][4:0] _GEN_1 = {{_r_bits_WIRE_15_tl_state_source}, {_r_bits_WIRE_14_tl_state_source}, {_r_bits_WIRE_13_tl_state_source}, {_r_bits_WIRE_12_tl_state_source}, {_r_bits_WIRE_11_tl_state_source}, {_r_bits_WIRE_10_tl_state_source}, {_r_bits_WIRE_9_tl_state_source}, {_r_bits_WIRE_8_tl_state_source}, {_r_bits_WIRE_7_tl_state_source}, {_r_bits_WIRE_6_tl_state_source}, {_r_bits_WIRE_5_tl_state_source}, {_r_bits_WIRE_4_tl_state_source}, {_r_bits_WIRE_3_tl_state_source}, {_r_bits_WIRE_2_tl_state_source}, {_r_bits_WIRE_1_tl_state_source}, {_r_bits_WIRE_0_tl_state_source}}; // @[UserYanker.scala:68:27, :73:22] assign nodeIn_r_bits_echo_tl_state_source = _GEN_1[nodeOut_r_bits_id]; // @[UserYanker.scala:73:22] wire _r_bits_WIRE_0_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_1_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_2_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_3_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_4_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_5_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_6_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_7_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_8_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_9_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_10_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_11_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_12_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_13_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_14_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_15_extra_id; // @[UserYanker.scala:68:27] wire [15:0] _GEN_2 = {{_r_bits_WIRE_15_extra_id}, {_r_bits_WIRE_14_extra_id}, {_r_bits_WIRE_13_extra_id}, {_r_bits_WIRE_12_extra_id}, {_r_bits_WIRE_11_extra_id}, {_r_bits_WIRE_10_extra_id}, {_r_bits_WIRE_9_extra_id}, {_r_bits_WIRE_8_extra_id}, {_r_bits_WIRE_7_extra_id}, {_r_bits_WIRE_6_extra_id}, {_r_bits_WIRE_5_extra_id}, {_r_bits_WIRE_4_extra_id}, {_r_bits_WIRE_3_extra_id}, {_r_bits_WIRE_2_extra_id}, {_r_bits_WIRE_1_extra_id}, {_r_bits_WIRE_0_extra_id}}; // @[UserYanker.scala:68:27, :73:22] assign nodeIn_r_bits_echo_extra_id = _GEN_2[nodeOut_r_bits_id]; // @[UserYanker.scala:73:22] wire [15:0] _arsel_T = 16'h1 << arsel_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [15:0] _arsel_T_1 = _arsel_T; // @[OneHot.scala:65:{12,27}] wire arsel_0 = _arsel_T_1[0]; // @[OneHot.scala:65:27] wire arsel_1 = _arsel_T_1[1]; // @[OneHot.scala:65:27] wire arsel_2 = _arsel_T_1[2]; // @[OneHot.scala:65:27] wire arsel_3 = _arsel_T_1[3]; // @[OneHot.scala:65:27] wire arsel_4 = _arsel_T_1[4]; // @[OneHot.scala:65:27] wire arsel_5 = _arsel_T_1[5]; // @[OneHot.scala:65:27] wire arsel_6 = _arsel_T_1[6]; // @[OneHot.scala:65:27] wire arsel_7 = _arsel_T_1[7]; // @[OneHot.scala:65:27] wire arsel_8 = _arsel_T_1[8]; // @[OneHot.scala:65:27] wire arsel_9 = _arsel_T_1[9]; // @[OneHot.scala:65:27] wire arsel_10 = _arsel_T_1[10]; // @[OneHot.scala:65:27] wire arsel_11 = _arsel_T_1[11]; // @[OneHot.scala:65:27] wire arsel_12 = _arsel_T_1[12]; // @[OneHot.scala:65:27] wire arsel_13 = _arsel_T_1[13]; // @[OneHot.scala:65:27] wire arsel_14 = _arsel_T_1[14]; // @[OneHot.scala:65:27] wire arsel_15 = _arsel_T_1[15]; // @[OneHot.scala:65:27] wire [15:0] _rsel_T = 16'h1 << rsel_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [15:0] _rsel_T_1 = _rsel_T; // @[OneHot.scala:65:{12,27}] wire rsel_0 = _rsel_T_1[0]; // @[OneHot.scala:65:27] wire rsel_1 = _rsel_T_1[1]; // @[OneHot.scala:65:27] wire rsel_2 = _rsel_T_1[2]; // @[OneHot.scala:65:27] wire rsel_3 = _rsel_T_1[3]; // @[OneHot.scala:65:27] wire rsel_4 = _rsel_T_1[4]; // @[OneHot.scala:65:27] wire rsel_5 = _rsel_T_1[5]; // @[OneHot.scala:65:27] wire rsel_6 = _rsel_T_1[6]; // @[OneHot.scala:65:27] wire rsel_7 = _rsel_T_1[7]; // @[OneHot.scala:65:27] wire rsel_8 = _rsel_T_1[8]; // @[OneHot.scala:65:27] wire rsel_9 = _rsel_T_1[9]; // @[OneHot.scala:65:27] wire rsel_10 = _rsel_T_1[10]; // @[OneHot.scala:65:27] wire rsel_11 = _rsel_T_1[11]; // @[OneHot.scala:65:27] wire rsel_12 = _rsel_T_1[12]; // @[OneHot.scala:65:27] wire rsel_13 = _rsel_T_1[13]; // @[OneHot.scala:65:27] wire rsel_14 = _rsel_T_1[14]; // @[OneHot.scala:65:27] wire rsel_15 = _rsel_T_1[15]; // @[OneHot.scala:65:27] wire _T_80 = nodeOut_r_valid & nodeIn_r_ready; // @[UserYanker.scala:78:37] wire _T_83 = nodeIn_ar_valid & nodeOut_ar_ready; // @[UserYanker.scala:81:37] wire _aw_ready_WIRE_0; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_1; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_2; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_3; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_4; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_5; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_6; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_7; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_8; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_9; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_10; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_11; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_12; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_13; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_14; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_15; // @[UserYanker.scala:88:29] wire [15:0] _GEN_3 = {{_aw_ready_WIRE_15}, {_aw_ready_WIRE_14}, {_aw_ready_WIRE_13}, {_aw_ready_WIRE_12}, {_aw_ready_WIRE_11}, {_aw_ready_WIRE_10}, {_aw_ready_WIRE_9}, {_aw_ready_WIRE_8}, {_aw_ready_WIRE_7}, {_aw_ready_WIRE_6}, {_aw_ready_WIRE_5}, {_aw_ready_WIRE_4}, {_aw_ready_WIRE_3}, {_aw_ready_WIRE_2}, {_aw_ready_WIRE_1}, {_aw_ready_WIRE_0}}; // @[UserYanker.scala:88:29, :89:36] assign _nodeIn_aw_ready_T = nodeOut_aw_ready & _GEN_3[nodeIn_aw_bits_id]; // @[UserYanker.scala:89:36] assign nodeIn_aw_ready = _nodeIn_aw_ready_T; // @[UserYanker.scala:89:36] assign _nodeOut_aw_valid_T = nodeIn_aw_valid & _GEN_3[nodeIn_aw_bits_id]; // @[UserYanker.scala:89:36, :90:36] assign nodeOut_aw_valid = _nodeOut_aw_valid_T; // @[UserYanker.scala:90:36] wire _r_valid_WIRE_0; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_1; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_2; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_3; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_4; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_5; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_6; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_7; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_8; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_9; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_10; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_11; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_12; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_13; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_14; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_15; // @[UserYanker.scala:67:28] wire _b_valid_WIRE_0; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_1; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_2; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_3; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_4; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_5; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_6; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_7; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_8; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_9; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_10; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_11; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_12; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_13; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_14; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_15; // @[UserYanker.scala:96:28]
Generate the Verilog code corresponding to the following Chisel files. File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }
module AsyncResetRegVec_w1_i0_29( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset // @[AsyncResetReg.scala:56:7] ); wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_d = 1'h0; // @[AsyncResetReg.scala:56:7] wire io_q = 1'h0; // @[AsyncResetReg.scala:56:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module RecFNToRecFN_179( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module RecFNToRecFN_127( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLBuffer_a26d64s11k1z2u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [10:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [10:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [25:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [10:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [10:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [10:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_24 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a26d64s11k1z2u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a26d64s11k1z2u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File recFNFromFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ object recFNFromFN { def apply(expWidth: Int, sigWidth: Int, in: Bits) = { val rawIn = rawFloatFromFN(expWidth, sigWidth, in) rawIn.sign ## (Mux(rawIn.isZero, 0.U(3.W), rawIn.sExp(expWidth, expWidth - 2)) | Mux(rawIn.isNaN, 1.U, 0.U)) ## rawIn.sExp(expWidth - 3, 0) ## rawIn.sig(sigWidth - 2, 0) } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } } File fNFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ object fNFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits) = { val minNormExp = (BigInt(1)<<(expWidth - 1)) + 2 val rawIn = rawFloatFromRecFN(expWidth, sigWidth, in) val isSubnormal = rawIn.sExp < minNormExp.S val denormShiftDist = 1.U - rawIn.sExp(log2Up(sigWidth - 1) - 1, 0) val denormFract = ((rawIn.sig>>1)>>denormShiftDist)(sigWidth - 2, 0) val expOut = Mux(isSubnormal, 0.U, rawIn.sExp(expWidth - 1, 0) - ((BigInt(1)<<(expWidth - 1)) + 1).U ) | Fill(expWidth, rawIn.isNaN || rawIn.isInf) val fractOut = Mux(isSubnormal, denormFract, Mux(rawIn.isInf, 0.U, rawIn.sig(sigWidth - 2, 0)) ) Cat(rawIn.sign, expOut, fractOut) } } File rawFloatFromFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ object rawFloatFromFN { def apply(expWidth: Int, sigWidth: Int, in: Bits) = { val sign = in(expWidth + sigWidth - 1) val expIn = in(expWidth + sigWidth - 2, sigWidth - 1) val fractIn = in(sigWidth - 2, 0) val isZeroExpIn = (expIn === 0.U) val isZeroFractIn = (fractIn === 0.U) val normDist = countLeadingZeros(fractIn) val subnormFract = (fractIn << normDist) (sigWidth - 3, 0) << 1 val adjustedExp = Mux(isZeroExpIn, normDist ^ ((BigInt(1) << (expWidth + 1)) - 1).U, expIn ) + ((BigInt(1) << (expWidth - 1)).U | Mux(isZeroExpIn, 2.U, 1.U)) val isZero = isZeroExpIn && isZeroFractIn val isSpecial = adjustedExp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && !isZeroFractIn out.isInf := isSpecial && isZeroFractIn out.isZero := isZero out.sign := sign out.sExp := adjustedExp(expWidth, 0).zext out.sig := 0.U(1.W) ## !isZero ## Mux(isZeroExpIn, subnormFract, fractIn) out } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module PE_30( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [31:0] io_in_a_bits, // @[PE.scala:35:14] input [31:0] io_in_b_bits, // @[PE.scala:35:14] input [31:0] io_in_d_bits, // @[PE.scala:35:14] output [31:0] io_out_a_bits, // @[PE.scala:35:14] output [31:0] io_out_b_bits, // @[PE.scala:35:14] output [31:0] io_out_c_bits, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [3:0] io_in_id, // @[PE.scala:35:14] output [3:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire c2_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_shift_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire c1_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_shift_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [32:0] _c2_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _io_out_c_resizer_1_io_out; // @[Arithmetic.scala:500:29] wire [32:0] _io_out_c_muladder_1_io_out; // @[Arithmetic.scala:450:30] wire [32:0] _c1_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _io_out_c_resizer_io_out; // @[Arithmetic.scala:500:29] wire [32:0] _io_out_c_muladder_io_out; // @[Arithmetic.scala:450:30] wire [31:0] _mac_unit_io_out_d_bits; // @[PE.scala:64:24] wire [31:0] io_in_a_bits_0 = io_in_a_bits; // @[PE.scala:31:7] wire [31:0] io_in_b_bits_0 = io_in_b_bits; // @[PE.scala:31:7] wire [31:0] io_in_d_bits_0 = io_in_d_bits; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [3:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire _io_out_c_T_1 = reset; // @[Arithmetic.scala:447:15] wire _io_out_c_T_5 = reset; // @[Arithmetic.scala:447:15] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [31:0] io_out_a_bits_0 = io_in_a_bits_0; // @[PE.scala:31:7] wire [31:0] _mac_unit_io_in_b_WIRE_1 = io_in_b_bits_0; // @[PE.scala:31:7, :106:37] wire [31:0] _mac_unit_io_in_b_WIRE_3 = io_in_b_bits_0; // @[PE.scala:31:7, :113:37] wire [31:0] _mac_unit_io_in_b_WIRE_9 = io_in_b_bits_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [3:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [31:0] io_out_b_bits_0; // @[PE.scala:31:7] wire [31:0] io_out_c_bits_0; // @[PE.scala:31:7] reg [31:0] c1_bits; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_WIRE_7 = c1_bits; // @[PE.scala:70:15, :127:38] reg [31:0] c2_bits; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_WIRE_5 = c2_bits; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire io_out_c_self_rec_rawIn_sign = c1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_sign_0 = io_out_c_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn = c1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn = c1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn = io_out_c_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn = io_out_c_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T = io_out_c_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_1 = io_out_c_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_2 = io_out_c_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_3 = io_out_c_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_4 = io_out_c_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_5 = io_out_c_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_6 = io_out_c_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_7 = io_out_c_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_8 = io_out_c_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_9 = io_out_c_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_10 = io_out_c_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_11 = io_out_c_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_12 = io_out_c_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_13 = io_out_c_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_14 = io_out_c_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_15 = io_out_c_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_16 = io_out_c_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_17 = io_out_c_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_18 = io_out_c_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_19 = io_out_c_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_20 = io_out_c_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_21 = io_out_c_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_22 = io_out_c_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_23 = _io_out_c_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_24 = _io_out_c_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_25 = _io_out_c_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_26 = _io_out_c_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_27 = _io_out_c_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_28 = _io_out_c_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_29 = _io_out_c_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_30 = _io_out_c_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_31 = _io_out_c_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_32 = _io_out_c_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_33 = _io_out_c_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_34 = _io_out_c_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_35 = _io_out_c_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_36 = _io_out_c_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_37 = _io_out_c_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_38 = _io_out_c_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_39 = _io_out_c_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_40 = _io_out_c_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_41 = _io_out_c_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_42 = _io_out_c_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_43 = _io_out_c_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist = _io_out_c_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T = {31'h0, io_out_c_self_rec_rawIn_fractIn} << io_out_c_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_1 = _io_out_c_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract = {_io_out_c_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_c_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_1 = io_out_c_self_rec_rawIn_isZeroExpIn ? _io_out_c_self_rec_rawIn_adjustedExp_T : {1'h0, io_out_c_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_2 = io_out_c_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp = _io_out_c_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T = io_out_c_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero = io_out_c_self_rec_rawIn_isZeroExpIn & io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_isZero_0 = io_out_c_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T = io_out_c_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial = &_io_out_c_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_2 = io_out_c_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T = ~io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_1 = io_out_c_self_rec_rawIn_isSpecial & _io_out_c_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T = io_out_c_self_rec_rawIn_isSpecial & io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_isInf = _io_out_c_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T = ~io_out_c_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_2 = io_out_c_self_rec_rawIn_isZeroExpIn ? io_out_c_self_rec_rawIn_subnormFract : io_out_c_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_3 = {_io_out_c_self_rec_rawIn_out_sig_T_1, _io_out_c_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_sig = _io_out_c_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T = io_out_c_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_1 = io_out_c_self_rec_rawIn_isZero_0 ? 3'h0 : _io_out_c_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_3 = {_io_out_c_self_rec_T_1[2:1], _io_out_c_self_rec_T_1[0] | _io_out_c_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_4 = {io_out_c_self_rec_rawIn_sign_0, _io_out_c_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_5 = io_out_c_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_6 = {_io_out_c_self_rec_T_4, _io_out_c_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_7 = io_out_c_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec = {_io_out_c_self_rec_T_6, _io_out_c_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [7:0] io_out_c_shift_exp; // @[Arithmetic.scala:442:29] wire [7:0] _GEN = 8'h7F - {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _io_out_c_shift_exp_T; // @[Arithmetic.scala:443:34] assign _io_out_c_shift_exp_T = _GEN; // @[Arithmetic.scala:443:34] wire [7:0] _io_out_c_shift_exp_T_2; // @[Arithmetic.scala:443:34] assign _io_out_c_shift_exp_T_2 = _GEN; // @[Arithmetic.scala:443:34] wire [6:0] _io_out_c_shift_exp_T_1 = _io_out_c_shift_exp_T[6:0]; // @[Arithmetic.scala:443:34] assign io_out_c_shift_exp = {1'h0, _io_out_c_shift_exp_T_1}; // @[Arithmetic.scala:442:29, :443:{19,34}] wire [8:0] io_out_c_shift_fn_hi = {1'h0, io_out_c_shift_exp}; // @[Arithmetic.scala:442:29, :444:27] wire [31:0] io_out_c_shift_fn = {io_out_c_shift_fn_hi, 23'h0}; // @[Arithmetic.scala:444:27] wire io_out_c_shift_rec_rawIn_sign = io_out_c_shift_fn[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_shift_rec_rawIn_sign_0 = io_out_c_shift_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_shift_rec_rawIn_expIn = io_out_c_shift_fn[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_shift_rec_rawIn_fractIn = io_out_c_shift_fn[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_shift_rec_rawIn_isZeroExpIn = io_out_c_shift_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_shift_rec_rawIn_isZeroFractIn = io_out_c_shift_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_shift_rec_rawIn_normDist_T = io_out_c_shift_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_1 = io_out_c_shift_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_2 = io_out_c_shift_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_3 = io_out_c_shift_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_4 = io_out_c_shift_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_5 = io_out_c_shift_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_6 = io_out_c_shift_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_7 = io_out_c_shift_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_8 = io_out_c_shift_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_9 = io_out_c_shift_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_10 = io_out_c_shift_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_11 = io_out_c_shift_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_12 = io_out_c_shift_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_13 = io_out_c_shift_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_14 = io_out_c_shift_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_15 = io_out_c_shift_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_16 = io_out_c_shift_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_17 = io_out_c_shift_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_18 = io_out_c_shift_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_19 = io_out_c_shift_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_20 = io_out_c_shift_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_21 = io_out_c_shift_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_22 = io_out_c_shift_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_23 = _io_out_c_shift_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_24 = _io_out_c_shift_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_c_shift_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_25 = _io_out_c_shift_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_c_shift_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_26 = _io_out_c_shift_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_c_shift_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_27 = _io_out_c_shift_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_c_shift_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_28 = _io_out_c_shift_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_c_shift_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_29 = _io_out_c_shift_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_c_shift_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_30 = _io_out_c_shift_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_c_shift_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_31 = _io_out_c_shift_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_c_shift_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_32 = _io_out_c_shift_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_c_shift_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_33 = _io_out_c_shift_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_c_shift_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_34 = _io_out_c_shift_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_c_shift_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_35 = _io_out_c_shift_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_c_shift_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_36 = _io_out_c_shift_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_c_shift_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_37 = _io_out_c_shift_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_c_shift_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_38 = _io_out_c_shift_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_c_shift_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_39 = _io_out_c_shift_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_c_shift_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_40 = _io_out_c_shift_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_c_shift_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_41 = _io_out_c_shift_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_c_shift_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_42 = _io_out_c_shift_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_c_shift_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_43 = _io_out_c_shift_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_c_shift_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_c_shift_rec_rawIn_normDist = _io_out_c_shift_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_c_shift_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_c_shift_rec_rawIn_subnormFract_T = {31'h0, io_out_c_shift_rec_rawIn_fractIn} << io_out_c_shift_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_c_shift_rec_rawIn_subnormFract_T_1 = _io_out_c_shift_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_shift_rec_rawIn_subnormFract = {_io_out_c_shift_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_c_shift_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_1 = io_out_c_shift_rec_rawIn_isZeroExpIn ? _io_out_c_shift_rec_rawIn_adjustedExp_T : {1'h0, io_out_c_shift_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_2 = io_out_c_shift_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_c_shift_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_shift_rec_rawIn_adjustedExp = _io_out_c_shift_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_shift_rec_rawIn_out_sExp_T = io_out_c_shift_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_shift_rec_rawIn_isZero = io_out_c_shift_rec_rawIn_isZeroExpIn & io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_shift_rec_rawIn_isZero_0 = io_out_c_shift_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_shift_rec_rawIn_isSpecial_T = io_out_c_shift_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_shift_rec_rawIn_isSpecial = &_io_out_c_shift_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_shift_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_shift_rec_T_2 = io_out_c_shift_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_shift_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_shift_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_c_shift_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_shift_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_shift_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_shift_rec_rawIn_out_isNaN_T = ~io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_shift_rec_rawIn_out_isNaN_T_1 = io_out_c_shift_rec_rawIn_isSpecial & _io_out_c_shift_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_shift_rec_rawIn_isNaN = _io_out_c_shift_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_shift_rec_rawIn_out_isInf_T = io_out_c_shift_rec_rawIn_isSpecial & io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_shift_rec_rawIn_isInf = _io_out_c_shift_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_shift_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_c_shift_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_shift_rec_rawIn_sExp = _io_out_c_shift_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_shift_rec_rawIn_out_sig_T = ~io_out_c_shift_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_shift_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_c_shift_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_shift_rec_rawIn_out_sig_T_2 = io_out_c_shift_rec_rawIn_isZeroExpIn ? io_out_c_shift_rec_rawIn_subnormFract : io_out_c_shift_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_shift_rec_rawIn_out_sig_T_3 = {_io_out_c_shift_rec_rawIn_out_sig_T_1, _io_out_c_shift_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_shift_rec_rawIn_sig = _io_out_c_shift_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_shift_rec_T = io_out_c_shift_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_shift_rec_T_1 = io_out_c_shift_rec_rawIn_isZero_0 ? 3'h0 : _io_out_c_shift_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_shift_rec_T_3 = {_io_out_c_shift_rec_T_1[2:1], _io_out_c_shift_rec_T_1[0] | _io_out_c_shift_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_shift_rec_T_4 = {io_out_c_shift_rec_rawIn_sign_0, _io_out_c_shift_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_shift_rec_T_5 = io_out_c_shift_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_shift_rec_T_6 = {_io_out_c_shift_rec_T_4, _io_out_c_shift_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_shift_rec_T_7 = io_out_c_shift_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_shift_rec = {_io_out_c_shift_rec_T_6, _io_out_c_shift_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _io_out_c_T = |io_out_c_shift_exp; // @[Arithmetic.scala:442:29, :447:26] wire _io_out_c_T_2 = ~_io_out_c_T_1; // @[Arithmetic.scala:447:15] wire _io_out_c_T_3 = ~_io_out_c_T; // @[Arithmetic.scala:447:{15,26}] wire [31:0] _io_out_c_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] io_out_c_result_bits; // @[Arithmetic.scala:458:26] wire [8:0] io_out_c_result_bits_rawIn_exp = _io_out_c_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _io_out_c_result_bits_rawIn_isZero_T = io_out_c_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_c_result_bits_rawIn_isZero = _io_out_c_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_c_result_bits_rawIn_isZero_0 = io_out_c_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_c_result_bits_rawIn_isSpecial_T = io_out_c_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_c_result_bits_rawIn_isSpecial = &_io_out_c_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_c_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_c_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_c_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_c_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_c_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_c_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_c_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_c_result_bits_rawIn_out_isNaN_T = io_out_c_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_c_result_bits_rawIn_out_isInf_T = io_out_c_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_c_result_bits_rawIn_out_isNaN_T_1 = io_out_c_result_bits_rawIn_isSpecial & _io_out_c_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_c_result_bits_rawIn_isNaN = _io_out_c_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_1 = ~_io_out_c_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_c_result_bits_rawIn_out_isInf_T_2 = io_out_c_result_bits_rawIn_isSpecial & _io_out_c_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_c_result_bits_rawIn_isInf = _io_out_c_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_c_result_bits_rawIn_out_sign_T = _io_out_c_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign io_out_c_result_bits_rawIn_sign = _io_out_c_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_c_result_bits_rawIn_out_sExp_T = {1'h0, io_out_c_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_c_result_bits_rawIn_sExp = _io_out_c_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_c_result_bits_rawIn_out_sig_T = ~io_out_c_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_c_result_bits_rawIn_out_sig_T_1 = {1'h0, _io_out_c_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_c_result_bits_rawIn_out_sig_T_2 = _io_out_c_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _io_out_c_result_bits_rawIn_out_sig_T_3 = {_io_out_c_result_bits_rawIn_out_sig_T_1, _io_out_c_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_c_result_bits_rawIn_sig = _io_out_c_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_c_result_bits_isSubnormal = $signed(io_out_c_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_c_result_bits_denormShiftDist_T = io_out_c_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_c_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_c_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_c_result_bits_denormShiftDist = _io_out_c_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_c_result_bits_denormFract_T = io_out_c_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_c_result_bits_denormFract_T_1 = _io_out_c_result_bits_denormFract_T >> io_out_c_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_c_result_bits_denormFract = _io_out_c_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_c_result_bits_expOut_T = io_out_c_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_c_result_bits_expOut_T_1 = {1'h0, _io_out_c_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_c_result_bits_expOut_T_2 = _io_out_c_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_c_result_bits_expOut_T_3 = io_out_c_result_bits_isSubnormal ? 8'h0 : _io_out_c_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_c_result_bits_expOut_T_4 = io_out_c_result_bits_rawIn_isNaN | io_out_c_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_c_result_bits_expOut_T_5 = {8{_io_out_c_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_c_result_bits_expOut = _io_out_c_result_bits_expOut_T_3 | _io_out_c_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_c_result_bits_fractOut_T = io_out_c_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_c_result_bits_fractOut_T_1 = io_out_c_result_bits_rawIn_isInf ? 23'h0 : _io_out_c_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_c_result_bits_fractOut = io_out_c_result_bits_isSubnormal ? io_out_c_result_bits_denormFract : _io_out_c_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_c_result_bits_hi = {io_out_c_result_bits_rawIn_sign, io_out_c_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _io_out_c_result_bits_T = {io_out_c_result_bits_hi, io_out_c_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign io_out_c_result_bits = _io_out_c_result_bits_T; // @[fNFromRecFN.scala:66:12] wire io_out_c_self_rec_rawIn_sign_1 = io_out_c_result_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_1_sign = io_out_c_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn_1 = io_out_c_result_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn_1 = io_out_c_result_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn_1 = io_out_c_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn_1 = io_out_c_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T_44 = io_out_c_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_45 = io_out_c_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_46 = io_out_c_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_47 = io_out_c_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_48 = io_out_c_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_49 = io_out_c_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_50 = io_out_c_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_51 = io_out_c_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_52 = io_out_c_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_53 = io_out_c_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_54 = io_out_c_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_55 = io_out_c_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_56 = io_out_c_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_57 = io_out_c_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_58 = io_out_c_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_59 = io_out_c_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_60 = io_out_c_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_61 = io_out_c_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_62 = io_out_c_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_63 = io_out_c_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_64 = io_out_c_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_65 = io_out_c_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_66 = io_out_c_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_67 = _io_out_c_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_68 = _io_out_c_self_rec_rawIn_normDist_T_46 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_69 = _io_out_c_self_rec_rawIn_normDist_T_47 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_70 = _io_out_c_self_rec_rawIn_normDist_T_48 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_71 = _io_out_c_self_rec_rawIn_normDist_T_49 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_72 = _io_out_c_self_rec_rawIn_normDist_T_50 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_73 = _io_out_c_self_rec_rawIn_normDist_T_51 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_74 = _io_out_c_self_rec_rawIn_normDist_T_52 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_75 = _io_out_c_self_rec_rawIn_normDist_T_53 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_76 = _io_out_c_self_rec_rawIn_normDist_T_54 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_77 = _io_out_c_self_rec_rawIn_normDist_T_55 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_78 = _io_out_c_self_rec_rawIn_normDist_T_56 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_79 = _io_out_c_self_rec_rawIn_normDist_T_57 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_80 = _io_out_c_self_rec_rawIn_normDist_T_58 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_81 = _io_out_c_self_rec_rawIn_normDist_T_59 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_82 = _io_out_c_self_rec_rawIn_normDist_T_60 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_83 = _io_out_c_self_rec_rawIn_normDist_T_61 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_84 = _io_out_c_self_rec_rawIn_normDist_T_62 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_85 = _io_out_c_self_rec_rawIn_normDist_T_63 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_86 = _io_out_c_self_rec_rawIn_normDist_T_64 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_87 = _io_out_c_self_rec_rawIn_normDist_T_65 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist_1 = _io_out_c_self_rec_rawIn_normDist_T_66 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T_2 = {31'h0, io_out_c_self_rec_rawIn_fractIn_1} << io_out_c_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_3 = _io_out_c_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract_1 = {_io_out_c_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~io_out_c_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_6 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? _io_out_c_self_rec_rawIn_adjustedExp_T_5 : {1'h0, io_out_c_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_7 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp_1 = _io_out_c_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T_2 = io_out_c_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero_1 = io_out_c_self_rec_rawIn_isZeroExpIn_1 & io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_1_isZero = io_out_c_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T_1 = io_out_c_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial_1 = &_io_out_c_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_10 = io_out_c_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T_2 = ~io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_3 = io_out_c_self_rec_rawIn_isSpecial_1 & _io_out_c_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_1_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T_1 = io_out_c_self_rec_rawIn_isSpecial_1 & io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_1_isInf = _io_out_c_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_3 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_1_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T_4 = ~io_out_c_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_5 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_6 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? io_out_c_self_rec_rawIn_subnormFract_1 : io_out_c_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_7 = {_io_out_c_self_rec_rawIn_out_sig_T_5, _io_out_c_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_1_sig = _io_out_c_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T_8 = io_out_c_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_9 = io_out_c_self_rec_rawIn_1_isZero ? 3'h0 : _io_out_c_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_11 = {_io_out_c_self_rec_T_9[2:1], _io_out_c_self_rec_T_9[0] | _io_out_c_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_12 = {io_out_c_self_rec_rawIn_1_sign, _io_out_c_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_13 = io_out_c_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_14 = {_io_out_c_self_rec_T_12, _io_out_c_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_15 = io_out_c_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec_1 = {_io_out_c_self_rec_T_14, _io_out_c_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _io_out_c_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] io_out_c_result_1_bits; // @[Arithmetic.scala:505:26] wire [8:0] io_out_c_result_bits_rawIn_exp_1 = _io_out_c_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _io_out_c_result_bits_rawIn_isZero_T_1 = io_out_c_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_c_result_bits_rawIn_isZero_1 = _io_out_c_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_c_result_bits_rawIn_1_isZero = io_out_c_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_c_result_bits_rawIn_isSpecial_T_1 = io_out_c_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_c_result_bits_rawIn_isSpecial_1 = &_io_out_c_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_c_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_c_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_c_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_c_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_c_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_c_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_c_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_c_result_bits_rawIn_out_isNaN_T_2 = io_out_c_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_c_result_bits_rawIn_out_isInf_T_3 = io_out_c_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_c_result_bits_rawIn_out_isNaN_T_3 = io_out_c_result_bits_rawIn_isSpecial_1 & _io_out_c_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_c_result_bits_rawIn_1_isNaN = _io_out_c_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_4 = ~_io_out_c_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_c_result_bits_rawIn_out_isInf_T_5 = io_out_c_result_bits_rawIn_isSpecial_1 & _io_out_c_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_c_result_bits_rawIn_1_isInf = _io_out_c_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_c_result_bits_rawIn_out_sign_T_1 = _io_out_c_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign io_out_c_result_bits_rawIn_1_sign = _io_out_c_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_c_result_bits_rawIn_out_sExp_T_1 = {1'h0, io_out_c_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_c_result_bits_rawIn_1_sExp = _io_out_c_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_c_result_bits_rawIn_out_sig_T_4 = ~io_out_c_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_c_result_bits_rawIn_out_sig_T_5 = {1'h0, _io_out_c_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_c_result_bits_rawIn_out_sig_T_6 = _io_out_c_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _io_out_c_result_bits_rawIn_out_sig_T_7 = {_io_out_c_result_bits_rawIn_out_sig_T_5, _io_out_c_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_c_result_bits_rawIn_1_sig = _io_out_c_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_c_result_bits_isSubnormal_1 = $signed(io_out_c_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_c_result_bits_denormShiftDist_T_2 = io_out_c_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_c_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _io_out_c_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_c_result_bits_denormShiftDist_1 = _io_out_c_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_c_result_bits_denormFract_T_2 = io_out_c_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_c_result_bits_denormFract_T_3 = _io_out_c_result_bits_denormFract_T_2 >> io_out_c_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_c_result_bits_denormFract_1 = _io_out_c_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_c_result_bits_expOut_T_6 = io_out_c_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_c_result_bits_expOut_T_7 = {1'h0, _io_out_c_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_c_result_bits_expOut_T_8 = _io_out_c_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_c_result_bits_expOut_T_9 = io_out_c_result_bits_isSubnormal_1 ? 8'h0 : _io_out_c_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_c_result_bits_expOut_T_10 = io_out_c_result_bits_rawIn_1_isNaN | io_out_c_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_c_result_bits_expOut_T_11 = {8{_io_out_c_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_c_result_bits_expOut_1 = _io_out_c_result_bits_expOut_T_9 | _io_out_c_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_c_result_bits_fractOut_T_2 = io_out_c_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_c_result_bits_fractOut_T_3 = io_out_c_result_bits_rawIn_1_isInf ? 23'h0 : _io_out_c_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_c_result_bits_fractOut_1 = io_out_c_result_bits_isSubnormal_1 ? io_out_c_result_bits_denormFract_1 : _io_out_c_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_c_result_bits_hi_1 = {io_out_c_result_bits_rawIn_1_sign, io_out_c_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _io_out_c_result_bits_T_1 = {io_out_c_result_bits_hi_1, io_out_c_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign io_out_c_result_1_bits = _io_out_c_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] _mac_unit_io_in_b_T; // @[PE.scala:106:37] assign _mac_unit_io_in_b_T = _mac_unit_io_in_b_WIRE_1; // @[PE.scala:106:37] wire [31:0] _mac_unit_io_in_b_WIRE_bits = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire c1_self_rec_rawIn_sign = io_in_d_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire c2_self_rec_rawIn_sign = io_in_d_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire c1_self_rec_rawIn_sign_0 = c1_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] c1_self_rec_rawIn_expIn = io_in_d_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] c2_self_rec_rawIn_expIn = io_in_d_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] c1_self_rec_rawIn_fractIn = io_in_d_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] c2_self_rec_rawIn_fractIn = io_in_d_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire c1_self_rec_rawIn_isZeroExpIn = c1_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire c1_self_rec_rawIn_isZeroFractIn = c1_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _c1_self_rec_rawIn_normDist_T = c1_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_1 = c1_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_2 = c1_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_3 = c1_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_4 = c1_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_5 = c1_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_6 = c1_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_7 = c1_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_8 = c1_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_9 = c1_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_10 = c1_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_11 = c1_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_12 = c1_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_13 = c1_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_14 = c1_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_15 = c1_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_16 = c1_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_17 = c1_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_18 = c1_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_19 = c1_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_20 = c1_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_21 = c1_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_22 = c1_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _c1_self_rec_rawIn_normDist_T_23 = _c1_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_24 = _c1_self_rec_rawIn_normDist_T_2 ? 5'h14 : _c1_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_25 = _c1_self_rec_rawIn_normDist_T_3 ? 5'h13 : _c1_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_26 = _c1_self_rec_rawIn_normDist_T_4 ? 5'h12 : _c1_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_27 = _c1_self_rec_rawIn_normDist_T_5 ? 5'h11 : _c1_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_28 = _c1_self_rec_rawIn_normDist_T_6 ? 5'h10 : _c1_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_29 = _c1_self_rec_rawIn_normDist_T_7 ? 5'hF : _c1_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_30 = _c1_self_rec_rawIn_normDist_T_8 ? 5'hE : _c1_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_31 = _c1_self_rec_rawIn_normDist_T_9 ? 5'hD : _c1_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_32 = _c1_self_rec_rawIn_normDist_T_10 ? 5'hC : _c1_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_33 = _c1_self_rec_rawIn_normDist_T_11 ? 5'hB : _c1_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_34 = _c1_self_rec_rawIn_normDist_T_12 ? 5'hA : _c1_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_35 = _c1_self_rec_rawIn_normDist_T_13 ? 5'h9 : _c1_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_36 = _c1_self_rec_rawIn_normDist_T_14 ? 5'h8 : _c1_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_37 = _c1_self_rec_rawIn_normDist_T_15 ? 5'h7 : _c1_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_38 = _c1_self_rec_rawIn_normDist_T_16 ? 5'h6 : _c1_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_39 = _c1_self_rec_rawIn_normDist_T_17 ? 5'h5 : _c1_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_40 = _c1_self_rec_rawIn_normDist_T_18 ? 5'h4 : _c1_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_41 = _c1_self_rec_rawIn_normDist_T_19 ? 5'h3 : _c1_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_42 = _c1_self_rec_rawIn_normDist_T_20 ? 5'h2 : _c1_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_43 = _c1_self_rec_rawIn_normDist_T_21 ? 5'h1 : _c1_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] c1_self_rec_rawIn_normDist = _c1_self_rec_rawIn_normDist_T_22 ? 5'h0 : _c1_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _c1_self_rec_rawIn_subnormFract_T = {31'h0, c1_self_rec_rawIn_fractIn} << c1_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _c1_self_rec_rawIn_subnormFract_T_1 = _c1_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] c1_self_rec_rawIn_subnormFract = {_c1_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _c1_self_rec_rawIn_adjustedExp_T = {4'hF, ~c1_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _c1_self_rec_rawIn_adjustedExp_T_1 = c1_self_rec_rawIn_isZeroExpIn ? _c1_self_rec_rawIn_adjustedExp_T : {1'h0, c1_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _c1_self_rec_rawIn_adjustedExp_T_2 = c1_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _c1_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _c1_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _c1_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _c1_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _c1_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] c1_self_rec_rawIn_adjustedExp = _c1_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _c1_self_rec_rawIn_out_sExp_T = c1_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire c1_self_rec_rawIn_isZero = c1_self_rec_rawIn_isZeroExpIn & c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire c1_self_rec_rawIn_isZero_0 = c1_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _c1_self_rec_rawIn_isSpecial_T = c1_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire c1_self_rec_rawIn_isSpecial = &_c1_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _c1_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _c1_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _c1_self_rec_T_2 = c1_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _c1_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _c1_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire c1_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] c1_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] c1_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _c1_self_rec_rawIn_out_isNaN_T = ~c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _c1_self_rec_rawIn_out_isNaN_T_1 = c1_self_rec_rawIn_isSpecial & _c1_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign c1_self_rec_rawIn_isNaN = _c1_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _c1_self_rec_rawIn_out_isInf_T = c1_self_rec_rawIn_isSpecial & c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign c1_self_rec_rawIn_isInf = _c1_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _c1_self_rec_rawIn_out_sExp_T_1 = {1'h0, _c1_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign c1_self_rec_rawIn_sExp = _c1_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _c1_self_rec_rawIn_out_sig_T = ~c1_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _c1_self_rec_rawIn_out_sig_T_1 = {1'h0, _c1_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _c1_self_rec_rawIn_out_sig_T_2 = c1_self_rec_rawIn_isZeroExpIn ? c1_self_rec_rawIn_subnormFract : c1_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _c1_self_rec_rawIn_out_sig_T_3 = {_c1_self_rec_rawIn_out_sig_T_1, _c1_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign c1_self_rec_rawIn_sig = _c1_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _c1_self_rec_T = c1_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _c1_self_rec_T_1 = c1_self_rec_rawIn_isZero_0 ? 3'h0 : _c1_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _c1_self_rec_T_3 = {_c1_self_rec_T_1[2:1], _c1_self_rec_T_1[0] | _c1_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _c1_self_rec_T_4 = {c1_self_rec_rawIn_sign_0, _c1_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _c1_self_rec_T_5 = c1_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _c1_self_rec_T_6 = {_c1_self_rec_T_4, _c1_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _c1_self_rec_T_7 = c1_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] c1_self_rec = {_c1_self_rec_T_6, _c1_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _c1_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] c1_result_bits; // @[Arithmetic.scala:491:26] wire [8:0] c1_result_bits_rawIn_exp = _c1_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _c1_result_bits_rawIn_isZero_T = c1_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire c1_result_bits_rawIn_isZero = _c1_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire c1_result_bits_rawIn_isZero_0 = c1_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _c1_result_bits_rawIn_isSpecial_T = c1_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire c1_result_bits_rawIn_isSpecial = &_c1_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _c1_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _c1_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _c1_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _c1_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _c1_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire c1_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire c1_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire c1_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] c1_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] c1_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _c1_result_bits_rawIn_out_isNaN_T = c1_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _c1_result_bits_rawIn_out_isInf_T = c1_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _c1_result_bits_rawIn_out_isNaN_T_1 = c1_result_bits_rawIn_isSpecial & _c1_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign c1_result_bits_rawIn_isNaN = _c1_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _c1_result_bits_rawIn_out_isInf_T_1 = ~_c1_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _c1_result_bits_rawIn_out_isInf_T_2 = c1_result_bits_rawIn_isSpecial & _c1_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign c1_result_bits_rawIn_isInf = _c1_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _c1_result_bits_rawIn_out_sign_T = _c1_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign c1_result_bits_rawIn_sign = _c1_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _c1_result_bits_rawIn_out_sExp_T = {1'h0, c1_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign c1_result_bits_rawIn_sExp = _c1_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _c1_result_bits_rawIn_out_sig_T = ~c1_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _c1_result_bits_rawIn_out_sig_T_1 = {1'h0, _c1_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _c1_result_bits_rawIn_out_sig_T_2 = _c1_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _c1_result_bits_rawIn_out_sig_T_3 = {_c1_result_bits_rawIn_out_sig_T_1, _c1_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign c1_result_bits_rawIn_sig = _c1_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire c1_result_bits_isSubnormal = $signed(c1_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _c1_result_bits_denormShiftDist_T = c1_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _c1_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _c1_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] c1_result_bits_denormShiftDist = _c1_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _c1_result_bits_denormFract_T = c1_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _c1_result_bits_denormFract_T_1 = _c1_result_bits_denormFract_T >> c1_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] c1_result_bits_denormFract = _c1_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _c1_result_bits_expOut_T = c1_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _c1_result_bits_expOut_T_1 = {1'h0, _c1_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _c1_result_bits_expOut_T_2 = _c1_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _c1_result_bits_expOut_T_3 = c1_result_bits_isSubnormal ? 8'h0 : _c1_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _c1_result_bits_expOut_T_4 = c1_result_bits_rawIn_isNaN | c1_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _c1_result_bits_expOut_T_5 = {8{_c1_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] c1_result_bits_expOut = _c1_result_bits_expOut_T_3 | _c1_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _c1_result_bits_fractOut_T = c1_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _c1_result_bits_fractOut_T_1 = c1_result_bits_rawIn_isInf ? 23'h0 : _c1_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] c1_result_bits_fractOut = c1_result_bits_isSubnormal ? c1_result_bits_denormFract : _c1_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] c1_result_bits_hi = {c1_result_bits_rawIn_sign, c1_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _c1_result_bits_T = {c1_result_bits_hi, c1_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign c1_result_bits = _c1_result_bits_T; // @[fNFromRecFN.scala:66:12] wire io_out_c_self_rec_rawIn_sign_2 = c2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_2_sign = io_out_c_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn_2 = c2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn_2 = c2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn_2 = io_out_c_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn_2 = io_out_c_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T_88 = io_out_c_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_89 = io_out_c_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_90 = io_out_c_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_91 = io_out_c_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_92 = io_out_c_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_93 = io_out_c_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_94 = io_out_c_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_95 = io_out_c_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_96 = io_out_c_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_97 = io_out_c_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_98 = io_out_c_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_99 = io_out_c_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_100 = io_out_c_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_101 = io_out_c_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_102 = io_out_c_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_103 = io_out_c_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_104 = io_out_c_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_105 = io_out_c_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_106 = io_out_c_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_107 = io_out_c_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_108 = io_out_c_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_109 = io_out_c_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_110 = io_out_c_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_111 = _io_out_c_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_112 = _io_out_c_self_rec_rawIn_normDist_T_90 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_113 = _io_out_c_self_rec_rawIn_normDist_T_91 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_114 = _io_out_c_self_rec_rawIn_normDist_T_92 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_115 = _io_out_c_self_rec_rawIn_normDist_T_93 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_116 = _io_out_c_self_rec_rawIn_normDist_T_94 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_117 = _io_out_c_self_rec_rawIn_normDist_T_95 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_118 = _io_out_c_self_rec_rawIn_normDist_T_96 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_119 = _io_out_c_self_rec_rawIn_normDist_T_97 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_120 = _io_out_c_self_rec_rawIn_normDist_T_98 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_121 = _io_out_c_self_rec_rawIn_normDist_T_99 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_122 = _io_out_c_self_rec_rawIn_normDist_T_100 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_123 = _io_out_c_self_rec_rawIn_normDist_T_101 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_124 = _io_out_c_self_rec_rawIn_normDist_T_102 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_125 = _io_out_c_self_rec_rawIn_normDist_T_103 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_126 = _io_out_c_self_rec_rawIn_normDist_T_104 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_127 = _io_out_c_self_rec_rawIn_normDist_T_105 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_128 = _io_out_c_self_rec_rawIn_normDist_T_106 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_129 = _io_out_c_self_rec_rawIn_normDist_T_107 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_130 = _io_out_c_self_rec_rawIn_normDist_T_108 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_131 = _io_out_c_self_rec_rawIn_normDist_T_109 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist_2 = _io_out_c_self_rec_rawIn_normDist_T_110 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T_4 = {31'h0, io_out_c_self_rec_rawIn_fractIn_2} << io_out_c_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_5 = _io_out_c_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract_2 = {_io_out_c_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~io_out_c_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_11 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? _io_out_c_self_rec_rawIn_adjustedExp_T_10 : {1'h0, io_out_c_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_12 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp_2 = _io_out_c_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T_4 = io_out_c_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero_2 = io_out_c_self_rec_rawIn_isZeroExpIn_2 & io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_2_isZero = io_out_c_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T_2 = io_out_c_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial_2 = &_io_out_c_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_18 = io_out_c_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T_4 = ~io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_5 = io_out_c_self_rec_rawIn_isSpecial_2 & _io_out_c_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_2_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T_2 = io_out_c_self_rec_rawIn_isSpecial_2 & io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_2_isInf = _io_out_c_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_5 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_2_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T_8 = ~io_out_c_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_9 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_10 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? io_out_c_self_rec_rawIn_subnormFract_2 : io_out_c_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_11 = {_io_out_c_self_rec_rawIn_out_sig_T_9, _io_out_c_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_2_sig = _io_out_c_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T_16 = io_out_c_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_17 = io_out_c_self_rec_rawIn_2_isZero ? 3'h0 : _io_out_c_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_19 = {_io_out_c_self_rec_T_17[2:1], _io_out_c_self_rec_T_17[0] | _io_out_c_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_20 = {io_out_c_self_rec_rawIn_2_sign, _io_out_c_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_21 = io_out_c_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_22 = {_io_out_c_self_rec_T_20, _io_out_c_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_23 = io_out_c_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec_2 = {_io_out_c_self_rec_T_22, _io_out_c_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [7:0] io_out_c_shift_exp_1; // @[Arithmetic.scala:442:29] wire [6:0] _io_out_c_shift_exp_T_3 = _io_out_c_shift_exp_T_2[6:0]; // @[Arithmetic.scala:443:34] assign io_out_c_shift_exp_1 = {1'h0, _io_out_c_shift_exp_T_3}; // @[Arithmetic.scala:442:29, :443:{19,34}] wire [8:0] io_out_c_shift_fn_hi_1 = {1'h0, io_out_c_shift_exp_1}; // @[Arithmetic.scala:442:29, :444:27] wire [31:0] io_out_c_shift_fn_1 = {io_out_c_shift_fn_hi_1, 23'h0}; // @[Arithmetic.scala:444:27] wire io_out_c_shift_rec_rawIn_sign_1 = io_out_c_shift_fn_1[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_shift_rec_rawIn_1_sign = io_out_c_shift_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_shift_rec_rawIn_expIn_1 = io_out_c_shift_fn_1[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_shift_rec_rawIn_fractIn_1 = io_out_c_shift_fn_1[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_shift_rec_rawIn_isZeroExpIn_1 = io_out_c_shift_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_shift_rec_rawIn_isZeroFractIn_1 = io_out_c_shift_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_shift_rec_rawIn_normDist_T_44 = io_out_c_shift_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_45 = io_out_c_shift_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_46 = io_out_c_shift_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_47 = io_out_c_shift_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_48 = io_out_c_shift_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_49 = io_out_c_shift_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_50 = io_out_c_shift_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_51 = io_out_c_shift_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_52 = io_out_c_shift_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_53 = io_out_c_shift_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_54 = io_out_c_shift_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_55 = io_out_c_shift_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_56 = io_out_c_shift_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_57 = io_out_c_shift_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_58 = io_out_c_shift_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_59 = io_out_c_shift_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_60 = io_out_c_shift_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_61 = io_out_c_shift_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_62 = io_out_c_shift_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_63 = io_out_c_shift_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_64 = io_out_c_shift_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_65 = io_out_c_shift_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_66 = io_out_c_shift_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_67 = _io_out_c_shift_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_68 = _io_out_c_shift_rec_rawIn_normDist_T_46 ? 5'h14 : _io_out_c_shift_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_69 = _io_out_c_shift_rec_rawIn_normDist_T_47 ? 5'h13 : _io_out_c_shift_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_70 = _io_out_c_shift_rec_rawIn_normDist_T_48 ? 5'h12 : _io_out_c_shift_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_71 = _io_out_c_shift_rec_rawIn_normDist_T_49 ? 5'h11 : _io_out_c_shift_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_72 = _io_out_c_shift_rec_rawIn_normDist_T_50 ? 5'h10 : _io_out_c_shift_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_73 = _io_out_c_shift_rec_rawIn_normDist_T_51 ? 5'hF : _io_out_c_shift_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_74 = _io_out_c_shift_rec_rawIn_normDist_T_52 ? 5'hE : _io_out_c_shift_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_75 = _io_out_c_shift_rec_rawIn_normDist_T_53 ? 5'hD : _io_out_c_shift_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_76 = _io_out_c_shift_rec_rawIn_normDist_T_54 ? 5'hC : _io_out_c_shift_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_77 = _io_out_c_shift_rec_rawIn_normDist_T_55 ? 5'hB : _io_out_c_shift_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_78 = _io_out_c_shift_rec_rawIn_normDist_T_56 ? 5'hA : _io_out_c_shift_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_79 = _io_out_c_shift_rec_rawIn_normDist_T_57 ? 5'h9 : _io_out_c_shift_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_80 = _io_out_c_shift_rec_rawIn_normDist_T_58 ? 5'h8 : _io_out_c_shift_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_81 = _io_out_c_shift_rec_rawIn_normDist_T_59 ? 5'h7 : _io_out_c_shift_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_82 = _io_out_c_shift_rec_rawIn_normDist_T_60 ? 5'h6 : _io_out_c_shift_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_83 = _io_out_c_shift_rec_rawIn_normDist_T_61 ? 5'h5 : _io_out_c_shift_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_84 = _io_out_c_shift_rec_rawIn_normDist_T_62 ? 5'h4 : _io_out_c_shift_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_85 = _io_out_c_shift_rec_rawIn_normDist_T_63 ? 5'h3 : _io_out_c_shift_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_86 = _io_out_c_shift_rec_rawIn_normDist_T_64 ? 5'h2 : _io_out_c_shift_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_87 = _io_out_c_shift_rec_rawIn_normDist_T_65 ? 5'h1 : _io_out_c_shift_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] io_out_c_shift_rec_rawIn_normDist_1 = _io_out_c_shift_rec_rawIn_normDist_T_66 ? 5'h0 : _io_out_c_shift_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _io_out_c_shift_rec_rawIn_subnormFract_T_2 = {31'h0, io_out_c_shift_rec_rawIn_fractIn_1} << io_out_c_shift_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _io_out_c_shift_rec_rawIn_subnormFract_T_3 = _io_out_c_shift_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_shift_rec_rawIn_subnormFract_1 = {_io_out_c_shift_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_5 = {4'hF, ~io_out_c_shift_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_6 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? _io_out_c_shift_rec_rawIn_adjustedExp_T_5 : {1'h0, io_out_c_shift_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_7 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_8 = {6'h20, _io_out_c_shift_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_9 = {1'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_6} + {2'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_shift_rec_rawIn_adjustedExp_1 = _io_out_c_shift_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_shift_rec_rawIn_out_sExp_T_2 = io_out_c_shift_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_shift_rec_rawIn_isZero_1 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 & io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_shift_rec_rawIn_1_isZero = io_out_c_shift_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_shift_rec_rawIn_isSpecial_T_1 = io_out_c_shift_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_shift_rec_rawIn_isSpecial_1 = &_io_out_c_shift_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_shift_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_shift_rec_T_10 = io_out_c_shift_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_shift_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_shift_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire io_out_c_shift_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_shift_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_shift_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_2 = ~io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_shift_rec_rawIn_out_isNaN_T_3 = io_out_c_shift_rec_rawIn_isSpecial_1 & _io_out_c_shift_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_shift_rec_rawIn_1_isNaN = _io_out_c_shift_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_shift_rec_rawIn_out_isInf_T_1 = io_out_c_shift_rec_rawIn_isSpecial_1 & io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_shift_rec_rawIn_1_isInf = _io_out_c_shift_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_shift_rec_rawIn_out_sExp_T_3 = {1'h0, _io_out_c_shift_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_shift_rec_rawIn_1_sExp = _io_out_c_shift_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_shift_rec_rawIn_out_sig_T_4 = ~io_out_c_shift_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_shift_rec_rawIn_out_sig_T_5 = {1'h0, _io_out_c_shift_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_shift_rec_rawIn_out_sig_T_6 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? io_out_c_shift_rec_rawIn_subnormFract_1 : io_out_c_shift_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_shift_rec_rawIn_out_sig_T_7 = {_io_out_c_shift_rec_rawIn_out_sig_T_5, _io_out_c_shift_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_shift_rec_rawIn_1_sig = _io_out_c_shift_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_shift_rec_T_8 = io_out_c_shift_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_shift_rec_T_9 = io_out_c_shift_rec_rawIn_1_isZero ? 3'h0 : _io_out_c_shift_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_shift_rec_T_11 = {_io_out_c_shift_rec_T_9[2:1], _io_out_c_shift_rec_T_9[0] | _io_out_c_shift_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_shift_rec_T_12 = {io_out_c_shift_rec_rawIn_1_sign, _io_out_c_shift_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_shift_rec_T_13 = io_out_c_shift_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_shift_rec_T_14 = {_io_out_c_shift_rec_T_12, _io_out_c_shift_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_shift_rec_T_15 = io_out_c_shift_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_shift_rec_1 = {_io_out_c_shift_rec_T_14, _io_out_c_shift_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _io_out_c_T_4 = |io_out_c_shift_exp_1; // @[Arithmetic.scala:442:29, :447:26] wire _io_out_c_T_6 = ~_io_out_c_T_5; // @[Arithmetic.scala:447:15] wire _io_out_c_T_7 = ~_io_out_c_T_4; // @[Arithmetic.scala:447:{15,26}]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_15( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [28:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire _GEN = io_in_d_valid & d_first_1; // @[Monitor.scala:674:26] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] wire d_clr = _GEN & _GEN_0; // @[Monitor.scala:673:46, :674:{26,71,74}] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire d_clr_1 = io_in_d_valid & d_first_2 & io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46, :784:26, :788:70] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File IngressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class IngressUnit( ingressNodeId: Int, cParam: IngressChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean, ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits))) } val io = IO(new IngressUnitIO) val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2, flow=combineRCVA)) assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR)) route_buffer.io.enq.bits.head := io.in.bits.head route_buffer.io.enq.bits.tail := io.in.bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { route_buffer.io.enq.bits.flow := DontCare } else { route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U route_buffer.io.enq.bits.flow.egress_node := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNode.U) ) route_buffer.io.enq.bits.flow.egress_node_id := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNodeId.U) ) } route_buffer.io.enq.bits.payload := io.in.bits.payload route_buffer.io.enq.bits.virt_channel_id := DontCare io.router_req.bits.src_virt_id := 0.U io.router_req.bits.flow := route_buffer.io.enq.bits.flow val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U route_buffer.io.enq.valid := io.in.valid && ( io.router_req.ready || !io.in.bits.head || at_dest) io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest io.in.ready := route_buffer.io.enq.ready && ( io.router_req.ready || !io.in.bits.head || at_dest) route_q.io.enq.valid := io.router_req.fire route_q.io.enq.bits := io.router_resp when (io.in.fire && io.in.bits.head && at_dest) { route_q.io.enq.valid := true.B route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (egressParams(o).egressId.U === io.in.bits.egress_id) { route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B } } } assert(!(route_q.io.enq.valid && !route_q.io.enq.ready)) val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams), 1, pipe=true)) vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow io.vcalloc_req.bits.in_vc := 0.U val head = route_buffer.io.deq.bits.head val tail = route_buffer.io.deq.bits.tail vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid && (route_q.io.deq.valid || !head) && (io.vcalloc_req.ready || !head) ) io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid && head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready) route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready && (route_q.io.deq.valid || !head) && (io.vcalloc_req.ready || !head) && (vcalloc_q.io.enq.ready || !head)) route_q.io.deq.ready := (route_buffer.io.deq.fire && tail) vcalloc_q.io.enq.valid := io.vcalloc_req.fire vcalloc_q.io.enq.bits := io.vcalloc_resp assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready)) io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire val out_bundle = if (combineSAST) { Wire(Valid(new SwitchBundle(outParams, egressParams))) } else { Reg(Valid(new SwitchBundle(outParams, egressParams))) } io.out(0) := out_bundle out_bundle.valid := vcalloc_buffer.io.deq.fire out_bundle.bits.flit := vcalloc_buffer.io.deq.bits out_bundle.bits.flit.virt_channel_id := 0.U val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh, vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq) io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready // TODO: We should not generate input/ingress/output/egress units for untraversable channels if (!cParam.traversable) { io.in.ready := false.B io.router_req.valid := false.B io.router_req.bits := DontCare io.vcalloc_req.valid := false.B io.vcalloc_req.bits := DontCare io.salloc_req.foreach(_.valid := false.B) io.salloc_req.foreach(_.bits := DontCare) io.out.foreach(_.valid := false.B) io.out.foreach(_.bits := DontCare) } }
module IngressUnit_29( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [144:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [144:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [144:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h13; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h15; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'hD; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_11 = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T ? 3'h5 : 3'h0} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'hA : 4'h0); // @[Mux.scala:30:73] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_13 = {_route_buffer_io_enq_bits_flow_egress_node_T_11[3], _route_buffer_io_enq_bits_flow_egress_node_T_11[2:0] | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 3'h6 : 3'h0)}; // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & (&_route_buffer_io_enq_bits_flow_egress_node_T_13); // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & ~(&_route_buffer_io_enq_bits_flow_egress_node_T_13); // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_64( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1148 = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1148 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1148 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1148 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1148 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_1148 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1194 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1163 = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1163 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1163 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1163 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1248 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1248 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1248 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1248 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }
module IntSyncCrossingSource_n1x1_44( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9] wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] AsyncResetRegVec_w1_i0_44 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d (nodeIn_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_sync_0) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_430( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_174 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File cpath.scala: //************************************************************************** // RISCV Processor Control Path //-------------------------------------------------------------------------- // // Christopher Celio package sodor.stage2 import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.{CSR, Causes} import sodor.common._ import sodor.common.Instructions._ import sodor.stage2.Constants._ class CtlToDatIo extends Bundle() { val stall = Output(Bool()) val if_kill = Output(Bool()) val pc_sel = Output(UInt(3.W)) val op1_sel = Output(UInt(2.W)) val op2_sel = Output(UInt(3.W)) val alu_fun = Output(UInt(5.W)) val wb_sel = Output(UInt(2.W)) val rf_wen = Output(Bool()) val csr_cmd = Output(UInt(CSR.SZ.W)) val mem_val = Output(Bool()) val mem_fcn = Output(UInt(2.W)) val mem_typ = Output(UInt(3.W)) val exception = Output(Bool()) val exception_cause = Output(UInt(32.W)) val pc_sel_no_xept = Output(UInt(PC_4.getWidth.W)) // Use only for instuction misalignment detection } class CpathIo(implicit val conf: SodorCoreParams) extends Bundle() { val dcpath = Flipped(new DebugCPath()) val imem = new MemPortIo(conf.xprlen) val dmem = new MemPortIo(conf.xprlen) val dat = Flipped(new DatToCtlIo()) val ctl = new CtlToDatIo() } class CtlPath(implicit val conf: SodorCoreParams) extends Module { val io = IO(new CpathIo()) io := DontCare val csignals = ListLookup(io.dat.inst, List(N, BR_N , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X ,MT_X, CSR.N), Array( /* val | BR | op1 | op2 | ALU | wb | rf | mem | mem | mask | csr */ /* inst | type | sel | sel | fcn | sel | wen | en | wr | type | cmd */ LW -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_ADD , WB_MEM, REN_1, MEN_1, M_XRD, MT_W, CSR.N), LB -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_ADD , WB_MEM, REN_1, MEN_1, M_XRD, MT_B, CSR.N), LBU -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_ADD , WB_MEM, REN_1, MEN_1, M_XRD, MT_BU, CSR.N), LH -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_ADD , WB_MEM, REN_1, MEN_1, M_XRD, MT_H, CSR.N), LHU -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_ADD , WB_MEM, REN_1, MEN_1, M_XRD, MT_HU, CSR.N), SW -> List(Y, BR_N , OP1_RS1, OP2_IMS , ALU_ADD , WB_X , REN_0, MEN_1, M_XWR, MT_W, CSR.N), SB -> List(Y, BR_N , OP1_RS1, OP2_IMS , ALU_ADD , WB_X , REN_0, MEN_1, M_XWR, MT_B, CSR.N), SH -> List(Y, BR_N , OP1_RS1, OP2_IMS , ALU_ADD , WB_X , REN_0, MEN_1, M_XWR, MT_H, CSR.N), AUIPC -> List(Y, BR_N , OP1_IMU, OP2_PC , ALU_ADD ,WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), LUI -> List(Y, BR_N , OP1_IMU, OP2_X , ALU_COPY1,WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), ADDI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_ADD , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), ANDI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_AND , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), ORI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_OR , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), XORI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_XOR , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), SLTI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SLT , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), SLTIU -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SLTU, WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), SLLI_RV32->List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), SRAI_RV32->List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SRA , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), SRLI_RV32->List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SRL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), SLL -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), ADD -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_ADD , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), SUB -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_SUB , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), SLT -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_SLT , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), SLTU -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_SLTU, WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), AND -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_AND , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), OR -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_OR , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), XOR -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_XOR , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), SRA -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_SRA , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), SRL -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_SRL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N), JAL -> List(Y, BR_J , OP1_X , OP2_X , ALU_X , WB_PC4, REN_1, MEN_0, M_X , MT_X, CSR.N), JALR -> List(Y, BR_JR , OP1_RS1, OP2_IMI , ALU_X , WB_PC4, REN_1, MEN_0, M_X , MT_X, CSR.N), BEQ -> List(Y, BR_EQ , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.N), BNE -> List(Y, BR_NE , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.N), BGE -> List(Y, BR_GE , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.N), BGEU -> List(Y, BR_GEU, OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.N), BLT -> List(Y, BR_LT , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.N), BLTU -> List(Y, BR_LTU, OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.N), CSRRWI -> List(Y, BR_N , OP1_IMZ, OP2_X , ALU_COPY1,WB_CSR, REN_1, MEN_0, M_X , MT_X, CSR.W), CSRRSI -> List(Y, BR_N , OP1_IMZ, OP2_X , ALU_COPY1,WB_CSR, REN_1, MEN_0, M_X , MT_X, CSR.S), CSRRW -> List(Y, BR_N , OP1_RS1, OP2_X , ALU_COPY1,WB_CSR, REN_1, MEN_0, M_X , MT_X, CSR.W), CSRRS -> List(Y, BR_N , OP1_RS1, OP2_X , ALU_COPY1,WB_CSR, REN_1, MEN_0, M_X , MT_X, CSR.S), CSRRC -> List(Y, BR_N , OP1_RS1, OP2_X , ALU_COPY1,WB_CSR, REN_1, MEN_0, M_X , MT_X, CSR.C), CSRRCI -> List(Y, BR_N , OP1_IMZ, OP2_X , ALU_COPY1,WB_CSR, REN_1, MEN_0, M_X , MT_X, CSR.C), ECALL -> List(Y, BR_N , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.I), MRET -> List(Y, BR_N , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.I), DRET -> List(Y, BR_N , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.I), EBREAK -> List(Y, BR_N , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.I), WFI -> List(Y, BR_N , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.N), // implemented as a NOP FENCE_I-> List(Y, BR_N , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.N), FENCE -> List(Y, BR_N , OP1_X , OP2_X , ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, CSR.N) // we are already sequentially consistent, so no need to honor the fence instruction )) // Put these control signals in variables val (cs_val_inst: Bool) :: cs_br_type :: cs_op1_sel :: cs_op2_sel :: cs_alu_fun :: cs_wb_sel :: cs0 = csignals val (cs_rf_wen: Bool) :: (cs_mem_en: Bool) :: cs_mem_fcn :: cs_msk_sel :: cs_csr_cmd :: Nil = cs0 // Branch Logic val ctrl_pc_sel_no_xept = Mux(io.dat.csr_interrupt , PC_EXC, Mux(cs_br_type === BR_N , PC_4, Mux(cs_br_type === BR_NE , Mux(!io.dat.br_eq, PC_BR, PC_4), Mux(cs_br_type === BR_EQ , Mux( io.dat.br_eq, PC_BR, PC_4), Mux(cs_br_type === BR_GE , Mux(!io.dat.br_lt, PC_BR, PC_4), Mux(cs_br_type === BR_GEU, Mux(!io.dat.br_ltu, PC_BR, PC_4), Mux(cs_br_type === BR_LT , Mux( io.dat.br_lt, PC_BR, PC_4), Mux(cs_br_type === BR_LTU, Mux( io.dat.br_ltu, PC_BR, PC_4), Mux(cs_br_type === BR_J , PC_J, Mux(cs_br_type === BR_JR , PC_JR, PC_4)))))))))) val ctrl_pc_sel = Mux(io.ctl.exception || io.dat.csr_eret, PC_EXC, ctrl_pc_sel_no_xept) // stall entire pipeline on I$ or D$ miss val stall = !io.dat.if_valid_resp || !((cs_mem_en && (io.dmem.resp.valid || io.dat.data_misaligned)) || !cs_mem_en) val ifkill = !(ctrl_pc_sel === PC_4) io.ctl.stall := stall io.ctl.if_kill := ifkill io.ctl.pc_sel := ctrl_pc_sel io.ctl.op1_sel := cs_op1_sel io.ctl.op2_sel := cs_op2_sel io.ctl.alu_fun := cs_alu_fun io.ctl.wb_sel := cs_wb_sel io.ctl.rf_wen := Mux(stall, false.B, cs_rf_wen) // convert CSR instructions with raddr1 == 0 to read-only CSR commands val rs1_addr = io.dat.inst(RS1_MSB, RS1_LSB) val csr_ren = (cs_csr_cmd === CSR.S || cs_csr_cmd === CSR.C) && rs1_addr === 0.U val csr_cmd = Mux(csr_ren, CSR.R, cs_csr_cmd) io.ctl.csr_cmd := Mux(stall, CSR.N, csr_cmd) io.dmem.req.valid := cs_mem_en && !io.dat.data_misaligned io.dmem.req.bits.fcn := cs_mem_fcn io.dmem.req.bits.typ := cs_msk_sel io.ctl.mem_val := cs_mem_en io.ctl.mem_fcn := cs_mem_fcn io.ctl.mem_typ := cs_msk_sel // Exception Handling --------------------- io.ctl.pc_sel_no_xept := ctrl_pc_sel_no_xept val illegal = (!cs_val_inst && io.imem.resp.valid) // Exception priority matters! io.ctl.exception := (illegal || io.dat.inst_misaligned || io.dat.data_misaligned) && !io.dat.csr_eret io.ctl.exception_cause := Mux(illegal, Causes.illegal_instruction.U, Mux(io.dat.inst_misaligned, Causes.misaligned_fetch.U, Mux(io.dat.mem_store, Causes.misaligned_store.U, Causes.misaligned_load.U ))) }
module CtlPath( // @[cpath.scala:47:7] input clock, // @[cpath.scala:47:7] input reset, // @[cpath.scala:47:7] input io_imem_req_ready, // @[cpath.scala:49:14] input io_imem_resp_valid, // @[cpath.scala:49:14] input [31:0] io_imem_resp_bits_data, // @[cpath.scala:49:14] input io_dmem_req_ready, // @[cpath.scala:49:14] output io_dmem_req_valid, // @[cpath.scala:49:14] output io_dmem_req_bits_fcn, // @[cpath.scala:49:14] output [2:0] io_dmem_req_bits_typ, // @[cpath.scala:49:14] input io_dmem_resp_valid, // @[cpath.scala:49:14] input [31:0] io_dmem_resp_bits_data, // @[cpath.scala:49:14] input io_dat_if_valid_resp, // @[cpath.scala:49:14] input [31:0] io_dat_inst, // @[cpath.scala:49:14] input io_dat_br_eq, // @[cpath.scala:49:14] input io_dat_br_lt, // @[cpath.scala:49:14] input io_dat_br_ltu, // @[cpath.scala:49:14] input io_dat_inst_misaligned, // @[cpath.scala:49:14] input io_dat_data_misaligned, // @[cpath.scala:49:14] input io_dat_mem_store, // @[cpath.scala:49:14] input io_dat_csr_eret, // @[cpath.scala:49:14] input io_dat_csr_interrupt, // @[cpath.scala:49:14] output io_ctl_stall, // @[cpath.scala:49:14] output io_ctl_if_kill, // @[cpath.scala:49:14] output [2:0] io_ctl_pc_sel, // @[cpath.scala:49:14] output [1:0] io_ctl_op1_sel, // @[cpath.scala:49:14] output [2:0] io_ctl_op2_sel, // @[cpath.scala:49:14] output [4:0] io_ctl_alu_fun, // @[cpath.scala:49:14] output [1:0] io_ctl_wb_sel, // @[cpath.scala:49:14] output io_ctl_rf_wen, // @[cpath.scala:49:14] output [2:0] io_ctl_csr_cmd, // @[cpath.scala:49:14] output io_ctl_mem_val, // @[cpath.scala:49:14] output [1:0] io_ctl_mem_fcn, // @[cpath.scala:49:14] output [2:0] io_ctl_mem_typ, // @[cpath.scala:49:14] output io_ctl_exception, // @[cpath.scala:49:14] output [31:0] io_ctl_exception_cause, // @[cpath.scala:49:14] output [2:0] io_ctl_pc_sel_no_xept // @[cpath.scala:49:14] ); wire io_imem_req_ready_0 = io_imem_req_ready; // @[cpath.scala:47:7] wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[cpath.scala:47:7] wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[cpath.scala:47:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[cpath.scala:47:7] wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[cpath.scala:47:7] wire [31:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[cpath.scala:47:7] wire io_dat_if_valid_resp_0 = io_dat_if_valid_resp; // @[cpath.scala:47:7] wire [31:0] io_dat_inst_0 = io_dat_inst; // @[cpath.scala:47:7] wire io_dat_br_eq_0 = io_dat_br_eq; // @[cpath.scala:47:7] wire io_dat_br_lt_0 = io_dat_br_lt; // @[cpath.scala:47:7] wire io_dat_br_ltu_0 = io_dat_br_ltu; // @[cpath.scala:47:7] wire io_dat_inst_misaligned_0 = io_dat_inst_misaligned; // @[cpath.scala:47:7] wire io_dat_data_misaligned_0 = io_dat_data_misaligned; // @[cpath.scala:47:7] wire io_dat_mem_store_0 = io_dat_mem_store; // @[cpath.scala:47:7] wire io_dat_csr_eret_0 = io_dat_csr_eret; // @[cpath.scala:47:7] wire io_dat_csr_interrupt_0 = io_dat_csr_interrupt; // @[cpath.scala:47:7] wire [3:0] _csignals_T_149 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_150 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_151 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_152 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_153 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_154 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_155 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_156 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_157 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_158 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_159 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_160 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_161 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_296 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_297 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_298 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_299 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_300 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_301 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_302 = 4'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_198 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_199 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_200 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_201 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_202 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_203 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_204 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_345 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_346 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_347 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_348 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_349 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_350 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_351 = 2'h0; // @[Lookup.scala:34:39] wire [2:0] io_imem_req_bits_typ = 3'h0; // @[cpath.scala:47:7] wire [2:0] _csignals_T_247 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_248 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_249 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_250 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_251 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_252 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_253 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_254 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_255 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_256 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_257 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_258 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_259 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_260 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_261 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_262 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_263 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_264 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_265 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_541 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_542 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_543 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_544 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_545 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_546 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_547 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_548 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_549 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_550 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_551 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_552 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_553 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_554 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_555 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_556 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_557 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_558 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_559 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_560 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_561 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_562 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_563 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_564 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_565 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_566 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_567 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_568 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_569 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_570 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_571 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_572 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_573 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_574 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_575 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_576 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_577 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_578 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_579 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_580 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_581 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_582 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_590 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_591 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_592 = 3'h0; // @[Lookup.scala:34:39] wire [31:0] io_imem_req_bits_addr = 32'h0; // @[cpath.scala:47:7] wire [31:0] io_imem_req_bits_data = 32'h0; // @[cpath.scala:47:7] wire [31:0] io_dmem_req_bits_addr = 32'h0; // @[cpath.scala:47:7] wire [31:0] io_dmem_req_bits_data = 32'h0; // @[cpath.scala:47:7] wire io_dcpath_halt = 1'h0; // @[cpath.scala:47:7] wire io_imem_req_valid = 1'h0; // @[cpath.scala:47:7] wire io_imem_req_bits_fcn = 1'h0; // @[cpath.scala:47:7] wire _csignals_T_394 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_395 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_396 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_397 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_398 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_399 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_400 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_443 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_444 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_445 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_446 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_447 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_448 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_449 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_450 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_451 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_452 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_453 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_454 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_455 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_456 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_457 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_458 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_459 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_460 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_461 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_462 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_463 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_464 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_465 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_466 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_467 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_468 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_469 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_470 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_471 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_472 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_473 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_474 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_475 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_476 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_477 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_478 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_479 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_480 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_481 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_482 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_483 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_484 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_492 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_493 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_494 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_495 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_496 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_497 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_498 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_499 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_500 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_501 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_502 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_503 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_504 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_505 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_506 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_507 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_508 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_509 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_510 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_511 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_512 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_513 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_514 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_515 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_516 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_517 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_518 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_519 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_520 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_521 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_522 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_523 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_524 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_525 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_526 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_527 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_528 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_529 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_530 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_531 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_532 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_533 = 1'h0; // @[Lookup.scala:34:39] wire _io_dmem_req_valid_T_1; // @[cpath.scala:159:38] wire csignals_8; // @[Lookup.scala:34:39] wire [2:0] csignals_9; // @[Lookup.scala:34:39] wire [31:0] _csignals_T_86 = io_dat_inst_0; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_88 = io_dat_inst_0; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_90 = io_dat_inst_0; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_92 = io_dat_inst_0; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_94 = io_dat_inst_0; // @[Lookup.scala:31:38] wire stall; // @[cpath.scala:138:38] wire ifkill; // @[cpath.scala:140:17] wire [2:0] ctrl_pc_sel; // @[cpath.scala:135:25] wire [1:0] csignals_2; // @[Lookup.scala:34:39] wire [2:0] csignals_3; // @[Lookup.scala:34:39] wire [1:0] csignals_5; // @[Lookup.scala:34:39] wire _io_ctl_rf_wen_T; // @[cpath.scala:149:28] wire [2:0] _io_ctl_csr_cmd_T; // @[cpath.scala:157:28] wire csignals_7; // @[Lookup.scala:34:39] wire _io_ctl_exception_T_3; // @[cpath.scala:171:86] wire [2:0] ctrl_pc_sel_no_xept; // @[cpath.scala:124:34] wire io_dmem_req_bits_fcn_0; // @[cpath.scala:47:7] wire [2:0] io_dmem_req_bits_typ_0; // @[cpath.scala:47:7] wire io_dmem_req_valid_0; // @[cpath.scala:47:7] wire io_ctl_stall_0; // @[cpath.scala:47:7] wire io_ctl_if_kill_0; // @[cpath.scala:47:7] wire [2:0] io_ctl_pc_sel_0; // @[cpath.scala:47:7] wire [1:0] io_ctl_op1_sel_0; // @[cpath.scala:47:7] wire [2:0] io_ctl_op2_sel_0; // @[cpath.scala:47:7] wire [4:0] io_ctl_alu_fun_0; // @[cpath.scala:47:7] wire [1:0] io_ctl_wb_sel_0; // @[cpath.scala:47:7] wire io_ctl_rf_wen_0; // @[cpath.scala:47:7] wire [2:0] io_ctl_csr_cmd_0; // @[cpath.scala:47:7] wire io_ctl_mem_val_0; // @[cpath.scala:47:7] wire [1:0] io_ctl_mem_fcn_0; // @[cpath.scala:47:7] wire [2:0] io_ctl_mem_typ_0; // @[cpath.scala:47:7] wire io_ctl_exception_0; // @[cpath.scala:47:7] wire [31:0] io_ctl_exception_cause_0; // @[cpath.scala:47:7] wire [2:0] io_ctl_pc_sel_no_xept_0; // @[cpath.scala:47:7] wire [31:0] _GEN = {17'h0, io_dat_inst_0[14:0] & 15'h707F}; // @[Lookup.scala:31:38] wire [31:0] _csignals_T; // @[Lookup.scala:31:38] assign _csignals_T = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_2; // @[Lookup.scala:31:38] assign _csignals_T_2 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_4; // @[Lookup.scala:31:38] assign _csignals_T_4 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_6; // @[Lookup.scala:31:38] assign _csignals_T_6 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_8; // @[Lookup.scala:31:38] assign _csignals_T_8 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_10; // @[Lookup.scala:31:38] assign _csignals_T_10 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_12; // @[Lookup.scala:31:38] assign _csignals_T_12 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_14; // @[Lookup.scala:31:38] assign _csignals_T_14 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_20; // @[Lookup.scala:31:38] assign _csignals_T_20 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_22; // @[Lookup.scala:31:38] assign _csignals_T_22 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_24; // @[Lookup.scala:31:38] assign _csignals_T_24 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_26; // @[Lookup.scala:31:38] assign _csignals_T_26 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_28; // @[Lookup.scala:31:38] assign _csignals_T_28 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_30; // @[Lookup.scala:31:38] assign _csignals_T_30 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_60; // @[Lookup.scala:31:38] assign _csignals_T_60 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_62; // @[Lookup.scala:31:38] assign _csignals_T_62 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_64; // @[Lookup.scala:31:38] assign _csignals_T_64 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_66; // @[Lookup.scala:31:38] assign _csignals_T_66 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_68; // @[Lookup.scala:31:38] assign _csignals_T_68 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_70; // @[Lookup.scala:31:38] assign _csignals_T_70 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_72; // @[Lookup.scala:31:38] assign _csignals_T_72 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_74; // @[Lookup.scala:31:38] assign _csignals_T_74 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_76; // @[Lookup.scala:31:38] assign _csignals_T_76 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_78; // @[Lookup.scala:31:38] assign _csignals_T_78 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_80; // @[Lookup.scala:31:38] assign _csignals_T_80 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_82; // @[Lookup.scala:31:38] assign _csignals_T_82 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_84; // @[Lookup.scala:31:38] assign _csignals_T_84 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_96; // @[Lookup.scala:31:38] assign _csignals_T_96 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_98; // @[Lookup.scala:31:38] assign _csignals_T_98 = _GEN; // @[Lookup.scala:31:38] wire _csignals_T_1 = _csignals_T == 32'h2003; // @[Lookup.scala:31:38] wire _csignals_T_3 = _csignals_T_2 == 32'h3; // @[Lookup.scala:31:38] wire _csignals_T_5 = _csignals_T_4 == 32'h4003; // @[Lookup.scala:31:38] wire _csignals_T_7 = _csignals_T_6 == 32'h1003; // @[Lookup.scala:31:38] wire _csignals_T_9 = _csignals_T_8 == 32'h5003; // @[Lookup.scala:31:38] wire _csignals_T_11 = _csignals_T_10 == 32'h2023; // @[Lookup.scala:31:38] wire _csignals_T_13 = _csignals_T_12 == 32'h23; // @[Lookup.scala:31:38] wire _csignals_T_15 = _csignals_T_14 == 32'h1023; // @[Lookup.scala:31:38] wire _csignals_T_485 = _csignals_T_15; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_534 = _csignals_T_15; // @[Lookup.scala:31:38, :34:39] wire [31:0] _GEN_0 = {25'h0, io_dat_inst_0[6:0]}; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_16; // @[Lookup.scala:31:38] assign _csignals_T_16 = _GEN_0; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_18; // @[Lookup.scala:31:38] assign _csignals_T_18 = _GEN_0; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_58; // @[Lookup.scala:31:38] assign _csignals_T_58 = _GEN_0; // @[Lookup.scala:31:38] wire _csignals_T_17 = _csignals_T_16 == 32'h17; // @[Lookup.scala:31:38] wire _csignals_T_19 = _csignals_T_18 == 32'h37; // @[Lookup.scala:31:38] wire _csignals_T_21 = _csignals_T_20 == 32'h13; // @[Lookup.scala:31:38] wire _csignals_T_23 = _csignals_T_22 == 32'h7013; // @[Lookup.scala:31:38] wire _csignals_T_25 = _csignals_T_24 == 32'h6013; // @[Lookup.scala:31:38] wire _csignals_T_27 = _csignals_T_26 == 32'h4013; // @[Lookup.scala:31:38] wire _csignals_T_29 = _csignals_T_28 == 32'h2013; // @[Lookup.scala:31:38] wire _csignals_T_31 = _csignals_T_30 == 32'h3013; // @[Lookup.scala:31:38] wire [31:0] _GEN_1 = io_dat_inst_0 & 32'hFE00707F; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_32; // @[Lookup.scala:31:38] assign _csignals_T_32 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_34; // @[Lookup.scala:31:38] assign _csignals_T_34 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_36; // @[Lookup.scala:31:38] assign _csignals_T_36 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_38; // @[Lookup.scala:31:38] assign _csignals_T_38 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_40; // @[Lookup.scala:31:38] assign _csignals_T_40 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_42; // @[Lookup.scala:31:38] assign _csignals_T_42 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_44; // @[Lookup.scala:31:38] assign _csignals_T_44 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_46; // @[Lookup.scala:31:38] assign _csignals_T_46 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_48; // @[Lookup.scala:31:38] assign _csignals_T_48 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_50; // @[Lookup.scala:31:38] assign _csignals_T_50 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_52; // @[Lookup.scala:31:38] assign _csignals_T_52 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_54; // @[Lookup.scala:31:38] assign _csignals_T_54 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_56; // @[Lookup.scala:31:38] assign _csignals_T_56 = _GEN_1; // @[Lookup.scala:31:38] wire _csignals_T_33 = _csignals_T_32 == 32'h1013; // @[Lookup.scala:31:38] wire _csignals_T_35 = _csignals_T_34 == 32'h40005013; // @[Lookup.scala:31:38] wire _csignals_T_37 = _csignals_T_36 == 32'h5013; // @[Lookup.scala:31:38] wire _csignals_T_39 = _csignals_T_38 == 32'h1033; // @[Lookup.scala:31:38] wire _csignals_T_41 = _csignals_T_40 == 32'h33; // @[Lookup.scala:31:38] wire _csignals_T_43 = _csignals_T_42 == 32'h40000033; // @[Lookup.scala:31:38] wire _csignals_T_45 = _csignals_T_44 == 32'h2033; // @[Lookup.scala:31:38] wire _csignals_T_47 = _csignals_T_46 == 32'h3033; // @[Lookup.scala:31:38] wire _csignals_T_49 = _csignals_T_48 == 32'h7033; // @[Lookup.scala:31:38] wire _csignals_T_51 = _csignals_T_50 == 32'h6033; // @[Lookup.scala:31:38] wire _csignals_T_53 = _csignals_T_52 == 32'h4033; // @[Lookup.scala:31:38] wire _csignals_T_55 = _csignals_T_54 == 32'h40005033; // @[Lookup.scala:31:38] wire _csignals_T_57 = _csignals_T_56 == 32'h5033; // @[Lookup.scala:31:38] wire _csignals_T_59 = _csignals_T_58 == 32'h6F; // @[Lookup.scala:31:38] wire _csignals_T_61 = _csignals_T_60 == 32'h67; // @[Lookup.scala:31:38] wire _csignals_T_63 = _csignals_T_62 == 32'h63; // @[Lookup.scala:31:38] wire _csignals_T_65 = _csignals_T_64 == 32'h1063; // @[Lookup.scala:31:38] wire _csignals_T_67 = _csignals_T_66 == 32'h5063; // @[Lookup.scala:31:38] wire _csignals_T_69 = _csignals_T_68 == 32'h7063; // @[Lookup.scala:31:38] wire _csignals_T_71 = _csignals_T_70 == 32'h4063; // @[Lookup.scala:31:38] wire _csignals_T_73 = _csignals_T_72 == 32'h6063; // @[Lookup.scala:31:38] wire _csignals_T_75 = _csignals_T_74 == 32'h5073; // @[Lookup.scala:31:38] wire _csignals_T_77 = _csignals_T_76 == 32'h6073; // @[Lookup.scala:31:38] wire _csignals_T_79 = _csignals_T_78 == 32'h1073; // @[Lookup.scala:31:38] wire _csignals_T_81 = _csignals_T_80 == 32'h2073; // @[Lookup.scala:31:38] wire _csignals_T_83 = _csignals_T_82 == 32'h3073; // @[Lookup.scala:31:38] wire _csignals_T_85 = _csignals_T_84 == 32'h7073; // @[Lookup.scala:31:38] wire _csignals_T_401 = _csignals_T_85; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_87 = _csignals_T_86 == 32'h73; // @[Lookup.scala:31:38] wire _csignals_T_89 = _csignals_T_88 == 32'h30200073; // @[Lookup.scala:31:38] wire _csignals_T_91 = _csignals_T_90 == 32'h7B200073; // @[Lookup.scala:31:38] wire _csignals_T_93 = _csignals_T_92 == 32'h100073; // @[Lookup.scala:31:38] wire _csignals_T_95 = _csignals_T_94 == 32'h10500073; // @[Lookup.scala:31:38] wire _csignals_T_97 = _csignals_T_96 == 32'h100F; // @[Lookup.scala:31:38] wire _csignals_T_99 = _csignals_T_98 == 32'hF; // @[Lookup.scala:31:38] wire _csignals_T_100 = _csignals_T_99; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_101 = _csignals_T_97 | _csignals_T_100; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_102 = _csignals_T_95 | _csignals_T_101; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_103 = _csignals_T_93 | _csignals_T_102; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_104 = _csignals_T_91 | _csignals_T_103; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_105 = _csignals_T_89 | _csignals_T_104; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_106 = _csignals_T_87 | _csignals_T_105; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_107 = _csignals_T_85 | _csignals_T_106; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_108 = _csignals_T_83 | _csignals_T_107; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_109 = _csignals_T_81 | _csignals_T_108; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_110 = _csignals_T_79 | _csignals_T_109; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_111 = _csignals_T_77 | _csignals_T_110; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_112 = _csignals_T_75 | _csignals_T_111; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_113 = _csignals_T_73 | _csignals_T_112; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_114 = _csignals_T_71 | _csignals_T_113; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_115 = _csignals_T_69 | _csignals_T_114; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_116 = _csignals_T_67 | _csignals_T_115; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_117 = _csignals_T_65 | _csignals_T_116; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_118 = _csignals_T_63 | _csignals_T_117; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_119 = _csignals_T_61 | _csignals_T_118; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_120 = _csignals_T_59 | _csignals_T_119; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_121 = _csignals_T_57 | _csignals_T_120; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_122 = _csignals_T_55 | _csignals_T_121; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_123 = _csignals_T_53 | _csignals_T_122; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_124 = _csignals_T_51 | _csignals_T_123; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_125 = _csignals_T_49 | _csignals_T_124; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_126 = _csignals_T_47 | _csignals_T_125; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_127 = _csignals_T_45 | _csignals_T_126; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_128 = _csignals_T_43 | _csignals_T_127; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_129 = _csignals_T_41 | _csignals_T_128; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_130 = _csignals_T_39 | _csignals_T_129; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_131 = _csignals_T_37 | _csignals_T_130; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_132 = _csignals_T_35 | _csignals_T_131; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_133 = _csignals_T_33 | _csignals_T_132; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_134 = _csignals_T_31 | _csignals_T_133; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_135 = _csignals_T_29 | _csignals_T_134; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_136 = _csignals_T_27 | _csignals_T_135; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_137 = _csignals_T_25 | _csignals_T_136; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_138 = _csignals_T_23 | _csignals_T_137; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_139 = _csignals_T_21 | _csignals_T_138; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_140 = _csignals_T_19 | _csignals_T_139; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_141 = _csignals_T_17 | _csignals_T_140; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_142 = _csignals_T_15 | _csignals_T_141; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_143 = _csignals_T_13 | _csignals_T_142; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_144 = _csignals_T_11 | _csignals_T_143; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_145 = _csignals_T_9 | _csignals_T_144; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_146 = _csignals_T_7 | _csignals_T_145; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_147 = _csignals_T_5 | _csignals_T_146; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_148 = _csignals_T_3 | _csignals_T_147; // @[Lookup.scala:31:38, :34:39] wire csignals_0 = _csignals_T_1 | _csignals_T_148; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_162 = _csignals_T_73 ? 4'h6 : 4'h0; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_163 = _csignals_T_71 ? 4'h5 : _csignals_T_162; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_164 = _csignals_T_69 ? 4'h4 : _csignals_T_163; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_165 = _csignals_T_67 ? 4'h3 : _csignals_T_164; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_166 = _csignals_T_65 ? 4'h1 : _csignals_T_165; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_167 = _csignals_T_63 ? 4'h2 : _csignals_T_166; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_168 = _csignals_T_61 ? 4'h8 : _csignals_T_167; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_169 = _csignals_T_59 ? 4'h7 : _csignals_T_168; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_170 = _csignals_T_57 ? 4'h0 : _csignals_T_169; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_171 = _csignals_T_55 ? 4'h0 : _csignals_T_170; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_172 = _csignals_T_53 ? 4'h0 : _csignals_T_171; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_173 = _csignals_T_51 ? 4'h0 : _csignals_T_172; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_174 = _csignals_T_49 ? 4'h0 : _csignals_T_173; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_175 = _csignals_T_47 ? 4'h0 : _csignals_T_174; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_176 = _csignals_T_45 ? 4'h0 : _csignals_T_175; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_177 = _csignals_T_43 ? 4'h0 : _csignals_T_176; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_178 = _csignals_T_41 ? 4'h0 : _csignals_T_177; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_179 = _csignals_T_39 ? 4'h0 : _csignals_T_178; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_180 = _csignals_T_37 ? 4'h0 : _csignals_T_179; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_181 = _csignals_T_35 ? 4'h0 : _csignals_T_180; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_182 = _csignals_T_33 ? 4'h0 : _csignals_T_181; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_183 = _csignals_T_31 ? 4'h0 : _csignals_T_182; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_184 = _csignals_T_29 ? 4'h0 : _csignals_T_183; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_185 = _csignals_T_27 ? 4'h0 : _csignals_T_184; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_186 = _csignals_T_25 ? 4'h0 : _csignals_T_185; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_187 = _csignals_T_23 ? 4'h0 : _csignals_T_186; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_188 = _csignals_T_21 ? 4'h0 : _csignals_T_187; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_189 = _csignals_T_19 ? 4'h0 : _csignals_T_188; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_190 = _csignals_T_17 ? 4'h0 : _csignals_T_189; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_191 = _csignals_T_15 ? 4'h0 : _csignals_T_190; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_192 = _csignals_T_13 ? 4'h0 : _csignals_T_191; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_193 = _csignals_T_11 ? 4'h0 : _csignals_T_192; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_194 = _csignals_T_9 ? 4'h0 : _csignals_T_193; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_195 = _csignals_T_7 ? 4'h0 : _csignals_T_194; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_196 = _csignals_T_5 ? 4'h0 : _csignals_T_195; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_197 = _csignals_T_3 ? 4'h0 : _csignals_T_196; // @[Lookup.scala:31:38, :34:39] wire [3:0] csignals_1 = _csignals_T_1 ? 4'h0 : _csignals_T_197; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_205 = {_csignals_T_85, 1'h0}; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_206 = _csignals_T_83 ? 2'h0 : _csignals_T_205; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_207 = _csignals_T_81 ? 2'h0 : _csignals_T_206; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_208 = _csignals_T_79 ? 2'h0 : _csignals_T_207; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_209 = _csignals_T_77 ? 2'h2 : _csignals_T_208; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_210 = _csignals_T_75 ? 2'h2 : _csignals_T_209; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_211 = _csignals_T_73 ? 2'h0 : _csignals_T_210; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_212 = _csignals_T_71 ? 2'h0 : _csignals_T_211; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_213 = _csignals_T_69 ? 2'h0 : _csignals_T_212; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_214 = _csignals_T_67 ? 2'h0 : _csignals_T_213; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_215 = _csignals_T_65 ? 2'h0 : _csignals_T_214; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_216 = _csignals_T_63 ? 2'h0 : _csignals_T_215; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_217 = _csignals_T_61 ? 2'h0 : _csignals_T_216; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_218 = _csignals_T_59 ? 2'h0 : _csignals_T_217; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_219 = _csignals_T_57 ? 2'h0 : _csignals_T_218; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_220 = _csignals_T_55 ? 2'h0 : _csignals_T_219; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_221 = _csignals_T_53 ? 2'h0 : _csignals_T_220; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_222 = _csignals_T_51 ? 2'h0 : _csignals_T_221; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_223 = _csignals_T_49 ? 2'h0 : _csignals_T_222; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_224 = _csignals_T_47 ? 2'h0 : _csignals_T_223; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_225 = _csignals_T_45 ? 2'h0 : _csignals_T_224; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_226 = _csignals_T_43 ? 2'h0 : _csignals_T_225; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_227 = _csignals_T_41 ? 2'h0 : _csignals_T_226; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_228 = _csignals_T_39 ? 2'h0 : _csignals_T_227; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_229 = _csignals_T_37 ? 2'h0 : _csignals_T_228; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_230 = _csignals_T_35 ? 2'h0 : _csignals_T_229; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_231 = _csignals_T_33 ? 2'h0 : _csignals_T_230; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_232 = _csignals_T_31 ? 2'h0 : _csignals_T_231; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_233 = _csignals_T_29 ? 2'h0 : _csignals_T_232; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_234 = _csignals_T_27 ? 2'h0 : _csignals_T_233; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_235 = _csignals_T_25 ? 2'h0 : _csignals_T_234; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_236 = _csignals_T_23 ? 2'h0 : _csignals_T_235; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_237 = _csignals_T_21 ? 2'h0 : _csignals_T_236; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_238 = _csignals_T_19 ? 2'h1 : _csignals_T_237; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_239 = _csignals_T_17 ? 2'h1 : _csignals_T_238; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_240 = _csignals_T_15 ? 2'h0 : _csignals_T_239; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_241 = _csignals_T_13 ? 2'h0 : _csignals_T_240; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_242 = _csignals_T_11 ? 2'h0 : _csignals_T_241; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_243 = _csignals_T_9 ? 2'h0 : _csignals_T_242; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_244 = _csignals_T_7 ? 2'h0 : _csignals_T_243; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_245 = _csignals_T_5 ? 2'h0 : _csignals_T_244; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_246 = _csignals_T_3 ? 2'h0 : _csignals_T_245; // @[Lookup.scala:31:38, :34:39] assign csignals_2 = _csignals_T_1 ? 2'h0 : _csignals_T_246; // @[Lookup.scala:31:38, :34:39] assign io_ctl_op1_sel_0 = csignals_2; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_266 = {1'h0, _csignals_T_61, 1'h0}; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_267 = _csignals_T_59 ? 3'h0 : _csignals_T_266; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_268 = _csignals_T_57 ? 3'h0 : _csignals_T_267; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_269 = _csignals_T_55 ? 3'h0 : _csignals_T_268; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_270 = _csignals_T_53 ? 3'h0 : _csignals_T_269; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_271 = _csignals_T_51 ? 3'h0 : _csignals_T_270; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_272 = _csignals_T_49 ? 3'h0 : _csignals_T_271; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_273 = _csignals_T_47 ? 3'h0 : _csignals_T_272; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_274 = _csignals_T_45 ? 3'h0 : _csignals_T_273; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_275 = _csignals_T_43 ? 3'h0 : _csignals_T_274; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_276 = _csignals_T_41 ? 3'h0 : _csignals_T_275; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_277 = _csignals_T_39 ? 3'h0 : _csignals_T_276; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_278 = _csignals_T_37 ? 3'h2 : _csignals_T_277; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_279 = _csignals_T_35 ? 3'h2 : _csignals_T_278; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_280 = _csignals_T_33 ? 3'h2 : _csignals_T_279; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_281 = _csignals_T_31 ? 3'h2 : _csignals_T_280; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_282 = _csignals_T_29 ? 3'h2 : _csignals_T_281; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_283 = _csignals_T_27 ? 3'h2 : _csignals_T_282; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_284 = _csignals_T_25 ? 3'h2 : _csignals_T_283; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_285 = _csignals_T_23 ? 3'h2 : _csignals_T_284; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_286 = _csignals_T_21 ? 3'h2 : _csignals_T_285; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_287 = _csignals_T_19 ? 3'h0 : _csignals_T_286; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_288 = _csignals_T_17 ? 3'h1 : _csignals_T_287; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_289 = _csignals_T_15 ? 3'h3 : _csignals_T_288; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_290 = _csignals_T_13 ? 3'h3 : _csignals_T_289; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_291 = _csignals_T_11 ? 3'h3 : _csignals_T_290; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_292 = _csignals_T_9 ? 3'h2 : _csignals_T_291; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_293 = _csignals_T_7 ? 3'h2 : _csignals_T_292; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_294 = _csignals_T_5 ? 3'h2 : _csignals_T_293; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_295 = _csignals_T_3 ? 3'h2 : _csignals_T_294; // @[Lookup.scala:31:38, :34:39] assign csignals_3 = _csignals_T_1 ? 3'h2 : _csignals_T_295; // @[Lookup.scala:31:38, :34:39] assign io_ctl_op2_sel_0 = csignals_3; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_303 = _csignals_T_85 ? 4'hB : 4'h0; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_304 = _csignals_T_83 ? 4'hB : _csignals_T_303; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_305 = _csignals_T_81 ? 4'hB : _csignals_T_304; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_306 = _csignals_T_79 ? 4'hB : _csignals_T_305; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_307 = _csignals_T_77 ? 4'hB : _csignals_T_306; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_308 = _csignals_T_75 ? 4'hB : _csignals_T_307; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_309 = _csignals_T_73 ? 4'h0 : _csignals_T_308; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_310 = _csignals_T_71 ? 4'h0 : _csignals_T_309; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_311 = _csignals_T_69 ? 4'h0 : _csignals_T_310; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_312 = _csignals_T_67 ? 4'h0 : _csignals_T_311; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_313 = _csignals_T_65 ? 4'h0 : _csignals_T_312; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_314 = _csignals_T_63 ? 4'h0 : _csignals_T_313; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_315 = _csignals_T_61 ? 4'h0 : _csignals_T_314; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_316 = _csignals_T_59 ? 4'h0 : _csignals_T_315; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_317 = _csignals_T_57 ? 4'h4 : _csignals_T_316; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_318 = _csignals_T_55 ? 4'h5 : _csignals_T_317; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_319 = _csignals_T_53 ? 4'h8 : _csignals_T_318; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_320 = _csignals_T_51 ? 4'h7 : _csignals_T_319; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_321 = _csignals_T_49 ? 4'h6 : _csignals_T_320; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_322 = _csignals_T_47 ? 4'hA : _csignals_T_321; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_323 = _csignals_T_45 ? 4'h9 : _csignals_T_322; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_324 = _csignals_T_43 ? 4'h2 : _csignals_T_323; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_325 = _csignals_T_41 ? 4'h1 : _csignals_T_324; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_326 = _csignals_T_39 ? 4'h3 : _csignals_T_325; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_327 = _csignals_T_37 ? 4'h4 : _csignals_T_326; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_328 = _csignals_T_35 ? 4'h5 : _csignals_T_327; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_329 = _csignals_T_33 ? 4'h3 : _csignals_T_328; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_330 = _csignals_T_31 ? 4'hA : _csignals_T_329; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_331 = _csignals_T_29 ? 4'h9 : _csignals_T_330; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_332 = _csignals_T_27 ? 4'h8 : _csignals_T_331; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_333 = _csignals_T_25 ? 4'h7 : _csignals_T_332; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_334 = _csignals_T_23 ? 4'h6 : _csignals_T_333; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_335 = _csignals_T_21 ? 4'h1 : _csignals_T_334; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_336 = _csignals_T_19 ? 4'hB : _csignals_T_335; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_337 = _csignals_T_17 ? 4'h1 : _csignals_T_336; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_338 = _csignals_T_15 ? 4'h1 : _csignals_T_337; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_339 = _csignals_T_13 ? 4'h1 : _csignals_T_338; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_340 = _csignals_T_11 ? 4'h1 : _csignals_T_339; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_341 = _csignals_T_9 ? 4'h1 : _csignals_T_340; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_342 = _csignals_T_7 ? 4'h1 : _csignals_T_341; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_343 = _csignals_T_5 ? 4'h1 : _csignals_T_342; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_344 = _csignals_T_3 ? 4'h1 : _csignals_T_343; // @[Lookup.scala:31:38, :34:39] wire [3:0] csignals_4 = _csignals_T_1 ? 4'h1 : _csignals_T_344; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_352 = {2{_csignals_T_85}}; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_353 = _csignals_T_83 ? 2'h3 : _csignals_T_352; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_354 = _csignals_T_81 ? 2'h3 : _csignals_T_353; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_355 = _csignals_T_79 ? 2'h3 : _csignals_T_354; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_356 = _csignals_T_77 ? 2'h3 : _csignals_T_355; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_357 = _csignals_T_75 ? 2'h3 : _csignals_T_356; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_358 = _csignals_T_73 ? 2'h0 : _csignals_T_357; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_359 = _csignals_T_71 ? 2'h0 : _csignals_T_358; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_360 = _csignals_T_69 ? 2'h0 : _csignals_T_359; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_361 = _csignals_T_67 ? 2'h0 : _csignals_T_360; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_362 = _csignals_T_65 ? 2'h0 : _csignals_T_361; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_363 = _csignals_T_63 ? 2'h0 : _csignals_T_362; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_364 = _csignals_T_61 ? 2'h2 : _csignals_T_363; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_365 = _csignals_T_59 ? 2'h2 : _csignals_T_364; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_366 = _csignals_T_57 ? 2'h0 : _csignals_T_365; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_367 = _csignals_T_55 ? 2'h0 : _csignals_T_366; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_368 = _csignals_T_53 ? 2'h0 : _csignals_T_367; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_369 = _csignals_T_51 ? 2'h0 : _csignals_T_368; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_370 = _csignals_T_49 ? 2'h0 : _csignals_T_369; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_371 = _csignals_T_47 ? 2'h0 : _csignals_T_370; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_372 = _csignals_T_45 ? 2'h0 : _csignals_T_371; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_373 = _csignals_T_43 ? 2'h0 : _csignals_T_372; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_374 = _csignals_T_41 ? 2'h0 : _csignals_T_373; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_375 = _csignals_T_39 ? 2'h0 : _csignals_T_374; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_376 = _csignals_T_37 ? 2'h0 : _csignals_T_375; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_377 = _csignals_T_35 ? 2'h0 : _csignals_T_376; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_378 = _csignals_T_33 ? 2'h0 : _csignals_T_377; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_379 = _csignals_T_31 ? 2'h0 : _csignals_T_378; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_380 = _csignals_T_29 ? 2'h0 : _csignals_T_379; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_381 = _csignals_T_27 ? 2'h0 : _csignals_T_380; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_382 = _csignals_T_25 ? 2'h0 : _csignals_T_381; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_383 = _csignals_T_23 ? 2'h0 : _csignals_T_382; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_384 = _csignals_T_21 ? 2'h0 : _csignals_T_383; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_385 = _csignals_T_19 ? 2'h0 : _csignals_T_384; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_386 = _csignals_T_17 ? 2'h0 : _csignals_T_385; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_387 = _csignals_T_15 ? 2'h0 : _csignals_T_386; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_388 = _csignals_T_13 ? 2'h0 : _csignals_T_387; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_389 = _csignals_T_11 ? 2'h0 : _csignals_T_388; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_390 = _csignals_T_9 ? 2'h1 : _csignals_T_389; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_391 = _csignals_T_7 ? 2'h1 : _csignals_T_390; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_392 = _csignals_T_5 ? 2'h1 : _csignals_T_391; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_393 = _csignals_T_3 ? 2'h1 : _csignals_T_392; // @[Lookup.scala:31:38, :34:39] assign csignals_5 = _csignals_T_1 ? 2'h1 : _csignals_T_393; // @[Lookup.scala:31:38, :34:39] assign io_ctl_wb_sel_0 = csignals_5; // @[Lookup.scala:34:39] wire _csignals_T_402 = _csignals_T_83 | _csignals_T_401; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_403 = _csignals_T_81 | _csignals_T_402; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_404 = _csignals_T_79 | _csignals_T_403; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_405 = _csignals_T_77 | _csignals_T_404; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_406 = _csignals_T_75 | _csignals_T_405; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_407 = ~_csignals_T_73 & _csignals_T_406; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_408 = ~_csignals_T_71 & _csignals_T_407; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_409 = ~_csignals_T_69 & _csignals_T_408; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_410 = ~_csignals_T_67 & _csignals_T_409; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_411 = ~_csignals_T_65 & _csignals_T_410; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_412 = ~_csignals_T_63 & _csignals_T_411; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_413 = _csignals_T_61 | _csignals_T_412; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_414 = _csignals_T_59 | _csignals_T_413; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_415 = _csignals_T_57 | _csignals_T_414; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_416 = _csignals_T_55 | _csignals_T_415; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_417 = _csignals_T_53 | _csignals_T_416; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_418 = _csignals_T_51 | _csignals_T_417; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_419 = _csignals_T_49 | _csignals_T_418; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_420 = _csignals_T_47 | _csignals_T_419; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_421 = _csignals_T_45 | _csignals_T_420; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_422 = _csignals_T_43 | _csignals_T_421; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_423 = _csignals_T_41 | _csignals_T_422; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_424 = _csignals_T_39 | _csignals_T_423; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_425 = _csignals_T_37 | _csignals_T_424; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_426 = _csignals_T_35 | _csignals_T_425; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_427 = _csignals_T_33 | _csignals_T_426; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_428 = _csignals_T_31 | _csignals_T_427; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_429 = _csignals_T_29 | _csignals_T_428; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_430 = _csignals_T_27 | _csignals_T_429; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_431 = _csignals_T_25 | _csignals_T_430; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_432 = _csignals_T_23 | _csignals_T_431; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_433 = _csignals_T_21 | _csignals_T_432; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_434 = _csignals_T_19 | _csignals_T_433; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_435 = _csignals_T_17 | _csignals_T_434; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_436 = ~_csignals_T_15 & _csignals_T_435; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_437 = ~_csignals_T_13 & _csignals_T_436; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_438 = ~_csignals_T_11 & _csignals_T_437; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_439 = _csignals_T_9 | _csignals_T_438; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_440 = _csignals_T_7 | _csignals_T_439; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_441 = _csignals_T_5 | _csignals_T_440; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_442 = _csignals_T_3 | _csignals_T_441; // @[Lookup.scala:31:38, :34:39] wire csignals_6 = _csignals_T_1 | _csignals_T_442; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_486 = _csignals_T_13 | _csignals_T_485; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_487 = _csignals_T_11 | _csignals_T_486; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_488 = _csignals_T_9 | _csignals_T_487; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_489 = _csignals_T_7 | _csignals_T_488; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_490 = _csignals_T_5 | _csignals_T_489; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_491 = _csignals_T_3 | _csignals_T_490; // @[Lookup.scala:31:38, :34:39] assign csignals_7 = _csignals_T_1 | _csignals_T_491; // @[Lookup.scala:31:38, :34:39] assign io_ctl_mem_val_0 = csignals_7; // @[Lookup.scala:34:39] wire _csignals_T_535 = _csignals_T_13 | _csignals_T_534; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_536 = _csignals_T_11 | _csignals_T_535; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_537 = ~_csignals_T_9 & _csignals_T_536; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_538 = ~_csignals_T_7 & _csignals_T_537; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_539 = ~_csignals_T_5 & _csignals_T_538; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_540 = ~_csignals_T_3 & _csignals_T_539; // @[Lookup.scala:31:38, :34:39] assign csignals_8 = ~_csignals_T_1 & _csignals_T_540; // @[Lookup.scala:31:38, :34:39] assign io_dmem_req_bits_fcn_0 = csignals_8; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_583 = {1'h0, _csignals_T_15, 1'h0}; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_584 = _csignals_T_13 ? 3'h1 : _csignals_T_583; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_585 = _csignals_T_11 ? 3'h3 : _csignals_T_584; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_586 = _csignals_T_9 ? 3'h6 : _csignals_T_585; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_587 = _csignals_T_7 ? 3'h2 : _csignals_T_586; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_588 = _csignals_T_5 ? 3'h5 : _csignals_T_587; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_589 = _csignals_T_3 ? 3'h1 : _csignals_T_588; // @[Lookup.scala:31:38, :34:39] assign csignals_9 = _csignals_T_1 ? 3'h3 : _csignals_T_589; // @[Lookup.scala:31:38, :34:39] assign io_dmem_req_bits_typ_0 = csignals_9; // @[Lookup.scala:34:39] assign io_ctl_mem_typ_0 = csignals_9; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_593 = {_csignals_T_93, 2'h0}; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_594 = _csignals_T_91 ? 3'h4 : _csignals_T_593; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_595 = _csignals_T_89 ? 3'h4 : _csignals_T_594; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_596 = _csignals_T_87 ? 3'h4 : _csignals_T_595; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_597 = _csignals_T_85 ? 3'h7 : _csignals_T_596; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_598 = _csignals_T_83 ? 3'h7 : _csignals_T_597; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_599 = _csignals_T_81 ? 3'h6 : _csignals_T_598; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_600 = _csignals_T_79 ? 3'h5 : _csignals_T_599; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_601 = _csignals_T_77 ? 3'h6 : _csignals_T_600; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_602 = _csignals_T_75 ? 3'h5 : _csignals_T_601; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_603 = _csignals_T_73 ? 3'h0 : _csignals_T_602; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_604 = _csignals_T_71 ? 3'h0 : _csignals_T_603; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_605 = _csignals_T_69 ? 3'h0 : _csignals_T_604; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_606 = _csignals_T_67 ? 3'h0 : _csignals_T_605; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_607 = _csignals_T_65 ? 3'h0 : _csignals_T_606; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_608 = _csignals_T_63 ? 3'h0 : _csignals_T_607; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_609 = _csignals_T_61 ? 3'h0 : _csignals_T_608; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_610 = _csignals_T_59 ? 3'h0 : _csignals_T_609; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_611 = _csignals_T_57 ? 3'h0 : _csignals_T_610; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_612 = _csignals_T_55 ? 3'h0 : _csignals_T_611; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_613 = _csignals_T_53 ? 3'h0 : _csignals_T_612; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_614 = _csignals_T_51 ? 3'h0 : _csignals_T_613; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_615 = _csignals_T_49 ? 3'h0 : _csignals_T_614; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_616 = _csignals_T_47 ? 3'h0 : _csignals_T_615; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_617 = _csignals_T_45 ? 3'h0 : _csignals_T_616; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_618 = _csignals_T_43 ? 3'h0 : _csignals_T_617; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_619 = _csignals_T_41 ? 3'h0 : _csignals_T_618; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_620 = _csignals_T_39 ? 3'h0 : _csignals_T_619; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_621 = _csignals_T_37 ? 3'h0 : _csignals_T_620; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_622 = _csignals_T_35 ? 3'h0 : _csignals_T_621; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_623 = _csignals_T_33 ? 3'h0 : _csignals_T_622; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_624 = _csignals_T_31 ? 3'h0 : _csignals_T_623; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_625 = _csignals_T_29 ? 3'h0 : _csignals_T_624; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_626 = _csignals_T_27 ? 3'h0 : _csignals_T_625; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_627 = _csignals_T_25 ? 3'h0 : _csignals_T_626; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_628 = _csignals_T_23 ? 3'h0 : _csignals_T_627; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_629 = _csignals_T_21 ? 3'h0 : _csignals_T_628; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_630 = _csignals_T_19 ? 3'h0 : _csignals_T_629; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_631 = _csignals_T_17 ? 3'h0 : _csignals_T_630; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_632 = _csignals_T_15 ? 3'h0 : _csignals_T_631; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_633 = _csignals_T_13 ? 3'h0 : _csignals_T_632; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_634 = _csignals_T_11 ? 3'h0 : _csignals_T_633; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_635 = _csignals_T_9 ? 3'h0 : _csignals_T_634; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_636 = _csignals_T_7 ? 3'h0 : _csignals_T_635; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_637 = _csignals_T_5 ? 3'h0 : _csignals_T_636; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_638 = _csignals_T_3 ? 3'h0 : _csignals_T_637; // @[Lookup.scala:31:38, :34:39] wire [2:0] csignals_10 = _csignals_T_1 ? 3'h0 : _csignals_T_638; // @[Lookup.scala:31:38, :34:39] wire _ctrl_pc_sel_no_xept_T = csignals_1 == 4'h0; // @[Lookup.scala:34:39] wire _ctrl_pc_sel_no_xept_T_1 = csignals_1 == 4'h1; // @[Lookup.scala:34:39] wire _ctrl_pc_sel_no_xept_T_2 = ~io_dat_br_eq_0; // @[cpath.scala:47:7, :126:62] wire [2:0] _ctrl_pc_sel_no_xept_T_3 = {2'h0, _ctrl_pc_sel_no_xept_T_2}; // @[cpath.scala:126:{61,62}] wire _ctrl_pc_sel_no_xept_T_4 = csignals_1 == 4'h2; // @[Lookup.scala:34:39] wire [2:0] _ctrl_pc_sel_no_xept_T_5 = {2'h0, io_dat_br_eq_0}; // @[cpath.scala:47:7, :127:61] wire _ctrl_pc_sel_no_xept_T_6 = csignals_1 == 4'h3; // @[Lookup.scala:34:39] wire _ctrl_pc_sel_no_xept_T_7 = ~io_dat_br_lt_0; // @[cpath.scala:47:7, :128:62] wire [2:0] _ctrl_pc_sel_no_xept_T_8 = {2'h0, _ctrl_pc_sel_no_xept_T_7}; // @[cpath.scala:128:{61,62}] wire _ctrl_pc_sel_no_xept_T_9 = csignals_1 == 4'h4; // @[Lookup.scala:34:39] wire _ctrl_pc_sel_no_xept_T_10 = ~io_dat_br_ltu_0; // @[cpath.scala:47:7, :129:62] wire [2:0] _ctrl_pc_sel_no_xept_T_11 = {2'h0, _ctrl_pc_sel_no_xept_T_10}; // @[cpath.scala:129:{61,62}] wire _ctrl_pc_sel_no_xept_T_12 = csignals_1 == 4'h5; // @[Lookup.scala:34:39] wire [2:0] _ctrl_pc_sel_no_xept_T_13 = {2'h0, io_dat_br_lt_0}; // @[cpath.scala:47:7, :130:61] wire _ctrl_pc_sel_no_xept_T_14 = csignals_1 == 4'h6; // @[Lookup.scala:34:39] wire [2:0] _ctrl_pc_sel_no_xept_T_15 = {2'h0, io_dat_br_ltu_0}; // @[cpath.scala:47:7, :131:61] wire _ctrl_pc_sel_no_xept_T_16 = csignals_1 == 4'h7; // @[Lookup.scala:34:39] wire _ctrl_pc_sel_no_xept_T_17 = csignals_1 == 4'h8; // @[Lookup.scala:34:39] wire [2:0] _ctrl_pc_sel_no_xept_T_18 = _ctrl_pc_sel_no_xept_T_17 ? 3'h3 : 3'h0; // @[cpath.scala:133:{34,46}] wire [2:0] _ctrl_pc_sel_no_xept_T_19 = _ctrl_pc_sel_no_xept_T_16 ? 3'h2 : _ctrl_pc_sel_no_xept_T_18; // @[cpath.scala:132:{34,46}, :133:34] wire [2:0] _ctrl_pc_sel_no_xept_T_20 = _ctrl_pc_sel_no_xept_T_14 ? _ctrl_pc_sel_no_xept_T_15 : _ctrl_pc_sel_no_xept_T_19; // @[cpath.scala:131:{34,46,61}, :132:34] wire [2:0] _ctrl_pc_sel_no_xept_T_21 = _ctrl_pc_sel_no_xept_T_12 ? _ctrl_pc_sel_no_xept_T_13 : _ctrl_pc_sel_no_xept_T_20; // @[cpath.scala:130:{34,46,61}, :131:34] wire [2:0] _ctrl_pc_sel_no_xept_T_22 = _ctrl_pc_sel_no_xept_T_9 ? _ctrl_pc_sel_no_xept_T_11 : _ctrl_pc_sel_no_xept_T_21; // @[cpath.scala:129:{34,46,61}, :130:34] wire [2:0] _ctrl_pc_sel_no_xept_T_23 = _ctrl_pc_sel_no_xept_T_6 ? _ctrl_pc_sel_no_xept_T_8 : _ctrl_pc_sel_no_xept_T_22; // @[cpath.scala:128:{34,46,61}, :129:34] wire [2:0] _ctrl_pc_sel_no_xept_T_24 = _ctrl_pc_sel_no_xept_T_4 ? _ctrl_pc_sel_no_xept_T_5 : _ctrl_pc_sel_no_xept_T_23; // @[cpath.scala:127:{34,46,61}, :128:34] wire [2:0] _ctrl_pc_sel_no_xept_T_25 = _ctrl_pc_sel_no_xept_T_1 ? _ctrl_pc_sel_no_xept_T_3 : _ctrl_pc_sel_no_xept_T_24; // @[cpath.scala:126:{34,46,61}, :127:34] wire [2:0] _ctrl_pc_sel_no_xept_T_26 = _ctrl_pc_sel_no_xept_T ? 3'h0 : _ctrl_pc_sel_no_xept_T_25; // @[cpath.scala:125:{34,46}, :126:34] assign ctrl_pc_sel_no_xept = io_dat_csr_interrupt_0 ? 3'h4 : _ctrl_pc_sel_no_xept_T_26; // @[cpath.scala:47:7, :124:34, :125:34] assign io_ctl_pc_sel_no_xept_0 = ctrl_pc_sel_no_xept; // @[cpath.scala:47:7, :124:34] wire _ctrl_pc_sel_T = io_ctl_exception_0 | io_dat_csr_eret_0; // @[cpath.scala:47:7, :135:43] assign ctrl_pc_sel = _ctrl_pc_sel_T ? 3'h4 : ctrl_pc_sel_no_xept; // @[cpath.scala:124:34, :135:{25,43}] assign io_ctl_pc_sel_0 = ctrl_pc_sel; // @[cpath.scala:47:7, :135:25] wire _stall_T = ~io_dat_if_valid_resp_0; // @[cpath.scala:47:7, :138:16] wire _stall_T_1 = io_dmem_resp_valid_0 | io_dat_data_misaligned_0; // @[cpath.scala:47:7, :138:77] wire _stall_T_2 = csignals_7 & _stall_T_1; // @[Lookup.scala:34:39] wire _stall_T_3 = ~csignals_7; // @[Lookup.scala:34:39] wire _stall_T_4 = _stall_T_2 | _stall_T_3; // @[cpath.scala:138:{54,105,108}] wire _stall_T_5 = ~_stall_T_4; // @[cpath.scala:138:{41,105}] assign stall = _stall_T | _stall_T_5; // @[cpath.scala:138:{16,38,41}] assign io_ctl_stall_0 = stall; // @[cpath.scala:47:7, :138:38] wire _ifkill_T = ctrl_pc_sel == 3'h0; // @[cpath.scala:135:25, :140:31] assign ifkill = ~_ifkill_T; // @[cpath.scala:140:{17,31}] assign io_ctl_if_kill_0 = ifkill; // @[cpath.scala:47:7, :140:17] assign io_ctl_alu_fun_0 = {1'h0, csignals_4}; // @[Lookup.scala:34:39] assign _io_ctl_rf_wen_T = ~stall & csignals_6; // @[Lookup.scala:34:39] assign io_ctl_rf_wen_0 = _io_ctl_rf_wen_T; // @[cpath.scala:47:7, :149:28] wire [4:0] rs1_addr = io_dat_inst_0[19:15]; // @[cpath.scala:47:7, :153:30] wire _csr_ren_T = csignals_10 == 3'h6; // @[Lookup.scala:34:39] wire _csr_ren_T_1 = &csignals_10; // @[Lookup.scala:34:39] wire _csr_ren_T_2 = _csr_ren_T | _csr_ren_T_1; // @[cpath.scala:154:{30,40,54}] wire _csr_ren_T_3 = rs1_addr == 5'h0; // @[cpath.scala:153:30, :154:77] wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[cpath.scala:154:{40,65,77}] wire [2:0] csr_cmd = csr_ren ? 3'h2 : csignals_10; // @[Lookup.scala:34:39] assign _io_ctl_csr_cmd_T = stall ? 3'h0 : csr_cmd; // @[cpath.scala:138:38, :155:21, :157:28] assign io_ctl_csr_cmd_0 = _io_ctl_csr_cmd_T; // @[cpath.scala:47:7, :157:28] wire _io_dmem_req_valid_T = ~io_dat_data_misaligned_0; // @[cpath.scala:47:7, :159:41] assign _io_dmem_req_valid_T_1 = csignals_7 & _io_dmem_req_valid_T; // @[Lookup.scala:34:39] assign io_dmem_req_valid_0 = _io_dmem_req_valid_T_1; // @[cpath.scala:47:7, :159:38] assign io_ctl_mem_fcn_0 = {1'h0, csignals_8}; // @[Lookup.scala:34:39] wire _illegal_T = ~csignals_0; // @[Lookup.scala:34:39] wire illegal = _illegal_T & io_imem_resp_valid_0; // @[cpath.scala:47:7, :169:{19,32}] wire _io_ctl_exception_T = illegal | io_dat_inst_misaligned_0; // @[cpath.scala:47:7, :169:32, :171:33] wire _io_ctl_exception_T_1 = _io_ctl_exception_T | io_dat_data_misaligned_0; // @[cpath.scala:47:7, :171:{33,59}] wire _io_ctl_exception_T_2 = ~io_dat_csr_eret_0; // @[cpath.scala:47:7, :171:89] assign _io_ctl_exception_T_3 = _io_ctl_exception_T_1 & _io_ctl_exception_T_2; // @[cpath.scala:171:{59,86,89}] assign io_ctl_exception_0 = _io_ctl_exception_T_3; // @[cpath.scala:47:7, :171:86] wire [2:0] _io_ctl_exception_cause_T = {1'h1, io_dat_mem_store_0, 1'h0}; // @[cpath.scala:47:7, :174:34] wire [2:0] _io_ctl_exception_cause_T_1 = io_dat_inst_misaligned_0 ? 3'h0 : _io_ctl_exception_cause_T; // @[cpath.scala:47:7, :173:34, :174:34] wire [2:0] _io_ctl_exception_cause_T_2 = illegal ? 3'h2 : _io_ctl_exception_cause_T_1; // @[cpath.scala:169:32, :172:34, :173:34] assign io_ctl_exception_cause_0 = {29'h0, _io_ctl_exception_cause_T_2}; // @[cpath.scala:47:7, :172:{27,34}] assign io_dmem_req_valid = io_dmem_req_valid_0; // @[cpath.scala:47:7] assign io_dmem_req_bits_fcn = io_dmem_req_bits_fcn_0; // @[cpath.scala:47:7] assign io_dmem_req_bits_typ = io_dmem_req_bits_typ_0; // @[cpath.scala:47:7] assign io_ctl_stall = io_ctl_stall_0; // @[cpath.scala:47:7] assign io_ctl_if_kill = io_ctl_if_kill_0; // @[cpath.scala:47:7] assign io_ctl_pc_sel = io_ctl_pc_sel_0; // @[cpath.scala:47:7] assign io_ctl_op1_sel = io_ctl_op1_sel_0; // @[cpath.scala:47:7] assign io_ctl_op2_sel = io_ctl_op2_sel_0; // @[cpath.scala:47:7] assign io_ctl_alu_fun = io_ctl_alu_fun_0; // @[cpath.scala:47:7] assign io_ctl_wb_sel = io_ctl_wb_sel_0; // @[cpath.scala:47:7] assign io_ctl_rf_wen = io_ctl_rf_wen_0; // @[cpath.scala:47:7] assign io_ctl_csr_cmd = io_ctl_csr_cmd_0; // @[cpath.scala:47:7] assign io_ctl_mem_val = io_ctl_mem_val_0; // @[cpath.scala:47:7] assign io_ctl_mem_fcn = io_ctl_mem_fcn_0; // @[cpath.scala:47:7] assign io_ctl_mem_typ = io_ctl_mem_typ_0; // @[cpath.scala:47:7] assign io_ctl_exception = io_ctl_exception_0; // @[cpath.scala:47:7] assign io_ctl_exception_cause = io_ctl_exception_cause_0; // @[cpath.scala:47:7] assign io_ctl_pc_sel_no_xept = io_ctl_pc_sel_no_xept_0; // @[cpath.scala:47:7] endmodule